Datasheet Am79C978VCW, Am79C978KCW Datasheet (AMD Advanced Micro Devices)

Page 1

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Publication# 22206 Rev: B Amendment/0 Issue Date: November 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

Am79C978

PCnet™- Home Single-Chip 1/10 Mbps PCI Home Networking Controller

DISTINCTIVE CHARACTERISTICS

■

Fully integrated 1 Mbps HomePNA Physical Layer (PHY) as deﬁned by Home Phoneline Networking Alliance (HomePNA) speciﬁcation

1.0 — Optimized for home networking applications

over ordinary copper telephone wire

— In-band control features:

Adjustable power and speed levels 32 bits of reserved in-band messaging piggy-

backed on Ethernet packet

— Register programmable features:

Power control Performance registers Speed control Major frame timing parameters programma-

ble: ISBI, AID ISBI, pulse width, inter-symbol time

■

Fully integrated 10 Mbps PHY interface — Comprehensive Auto-Negotiation

implementation — Full-duplex capability — Optimized for 10BASE-T applications

■

Integrated Fast Ethernet controller for the Peripheral Component Interconnect (PCI) bus

— 32-bit glueless PCI host interface — Supports PCI clock frequency from DC to

33 MHz independent of network clock — Supports network operation with PCI clock

from 15 MHz to 33 MHz — High performance bus mastering

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization — PCI draft speciﬁcation revision 2.2 compliant — Supports PCI Subsystem/Subvendor ID/

Vendor ID pr ogramming through the

EEPROM interface — Supports both PCI 5.0-V and 3.3-V signaling

environments

— Plug and Play compatible — Supports an unlimited PCI burst length — Big endian and little endian byte alignments

supported

— Implements optional PCI power management

event (PME) pin

■

Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 Ethernet standard

■

Compliant with HomePNA speciﬁcation 1.0

■

Media Independent Interface (MII) for connecting external 10/100 Mbps transceivers

— IEEE 802.3u compliant MII — Intelligent Auto-Poll™ external PHY status

monitor and interrupt

— Supports both auto-negotiable and non-

auto-negotiable external PHYs

— Supports 10BASE-T, 100BASETX/FX,

100BASET4, and 100BASET2 IEEE 802.3 compliant MII PHYs at full-duplex or halfduplex

■

Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels

■

Supports PC98/PC99 and Net PC speciﬁcations — Implements full OnNow features including

pattern matching and link status wake-up

events — Implements Magic Packet™ mode — Magic Packet mode and the physical address

loaded from EEPROM at power up without

requiring PCI clock — Supports PCI Bus Power Management

Interface speciﬁcation revision 1.1 — Supports Advanced Conﬁguration and

Power Interface (ACPI) speciﬁcation version

1.0

— Supports Network Device Class Power

Management speciﬁcation version 1.0a

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2 Am79C978

PRELIMINARY

■

Independent internal TX and RX FIFOs — Programmable FIFO watermarks for both TX

and RX operations

— RX frame queuing for high latency PCI bus

host operation

— Programmable allocation of buffer space

between RX and TX queues

■

Extensive programmable internal/external loopback capabilities

■

EEPROM interface supports jumperless design and provides through-chip programming

— Supports full programmability of half-/full-

duplex operation through EEPROM mapping

— Programmable PHY reset output pin capable

of resetting external PHY without the need for buffering

■

Extensive programmable LED status support

■

Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead

by allowing protocol analysis to begin before the end of a receive frame

■

Includes Programmable Inter Packet Gap (IPG) to address less network aggressive MAC controllers

■

Offers the Modiﬁed Back-Off algorithm to address the

Ethernet Capture Effect

■

IEEE 1149.1-compliant JTAG Boundary Scan test access port interface and NAND tree test mode for board-level production connectivity test

■

Software compatible with AMD’s PCnet™ Family and LANCE/C-LANCE register and descriptor architecture

■

Very low power consumption

■

+3.3 V power supply along with 5 V tolerant I/Os enable broad system compatibility

■

Available in 144-pin TQFP and 160-pin PQFP packages

GENERAL DESCRIPTION

The Am79C978 controller is the ﬁrst in a series of home networking products from AMD. The Am79C978 controller is fabricated in an advanced low po wer 3.3 V CMOS process to provide low operating current for power sensitive applications.

The Am79C978 controller contains an Ethernet Controller based on the Am79C971 Fast Ethernet controller, a physical layer device for supporting the 802.3 standard for 10BASE-T, and a physical layer device f or data networking at speeds up to 1 Mbps over ordinary residential telephone wiring.

The integrated PCI Ethernet controller is a highly integrated 32-bit full-duplex, 10/100 Mbps Ethernet controller solution designed to address high-performance system application requirements. It is a ﬂexible busmastering device that can be used in any application, including network ready PCs. The bus master architecture provides high data throughput and low CPU and system bus utilization.

The integrated Ethernet transceiver is a physical layer device supporting the IEEE 802.3 standards for 10BASE-T. It provides all of the PHY la yer functions required to support 10 Mbps data transfer speeds.

The integrated HomePNA transceiver is a physical layer de vice that enables data netw orking at speeds up to 1 Mbps over common residential phone wiring regardless of topology and without disrupting telephone (POTS) service.

The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus, simplifying the design of an Ethernet or home network node in a PC

system. The device has built-in support for both little and big endian byte alignment. The integrated home networking controller’s adv anced CMOS design allo ws the bus interface to be connected to either a +5.0 V or a +3.3 V signaling environment. A compliant IEEE

1149.1 JT A G test interface f or board level testing is also provided, as well as a NAND tree test structure for those systems that do not support the JTAG interface.

The integrated Am79C978 home networking controller is also compliant with the PC98, PC99, and Net PC speciﬁcations. It includes the full implementation of the Microsoft OnNow and ACPI speciﬁcations, which are backward compatible with Magic Packet technology, and is compliant with the PCI Bus Pow er Management Interface speciﬁcation by supporting the four power management states (D0, D1, D2, and D3), the optional PME

pin, and the necessary conﬁguration and data

registers. The integrated Am79C978 home networking controller

is a complete Ethernet or home network node integrated into a single VLSI de vice. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 88023 (IEEE 802.3) compliant Media Access Controller (MAC), a Transmit FIFO and a large Receive FIFO, and an IEEE 802.3u compliant MII. Both IEEE 802.3 compliant full-duplex and half-duplex operations are supported on the MII interface. 10/100 Mbps operation is suppor ted through the MII interface.

The integrated Am79C978 home networking controller is register compatible with the LANCE (Am7990) and C-LANCE (Am79C90) Ethernet controllers and all

Page 3

Am79C978 3

PRELIMINARY

Ethernet controllers in the PCnet Family (

except

ILACC™ (Am79C900)), including PCnet-ISA (Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA II (Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI (Am79C970), PCnet-PCI II (Am79C970A), PCnet-

FAST

(Am79C971), and PCnet-

FAST+

(Am79C972). The Buffer Management Unit supports the LANCE and PCnet descriptor software models.

The integrated Am79C978 controller supports autoconﬁguration in the PCI conﬁguration space. Additional integrated controller conﬁguration parameters, includ-

ing the unique IEEE physical address, can be read from an external non-volatile memory (EEPROM) immediately following system reset.

In addition, the Am79C978 controller provides programmable on-chip LED drivers for transmit, receive, collision, link integrity, Magic Packet status, speed, activity, power output, address match, full-duplex, or 100 Mbps status.

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4 Am79C978

PRELIMINARY

BLOCK DIAGRAM

CLK RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT PERR SERR

INTA

PCI Bus

Interface

Unit

Buffer

Management

Unit

Bus Rcv

FIFO

Bus Xmt

FIFO

Control

Network

Port

Manager

MAC

Rcv

FIFO

12K

SRAM

MAC

Xmt

FIFO

JTAG

Port

Control

OnNow

Power

Management

Unit

802.3 MAC Core

93C46

EEPROM

Interface

LED

Control

PME

TCK

TMS

TDI

TDO

Transmit

State

Machine

MII

Interface

MII

Management

MDIO

Receive

State

Machine

PHY Control

Link

Monitor

Auto

Negotiation

10 Mbps PHY

Transmit

State

Machine

MII

Interface

Receive

State

Machine

Drive

Control

Analog

Front

End

10 BASE-T

TX±

RX±

LED0 LED1 LED2 LED3 LED4

EECS EESK EEDI

EEDO

MII

Management

MDIO

RXD(3:0)/TXD(3:0)

PHY

Control

Link

Monitor

HRTXRXP/N

MDC

1Mbps HomePNA PHY

MDC

Clock

Reference

XTAL2

XTAL1

22206B-1

Page 5

Am79C978 5

PRELIMINARY

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

CONNECTION DIAGRAM (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

CONNECTION DIAGRAM (160 PQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Listed By Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Listed By Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Magic Packet Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Board Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

EEPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Ethernet Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

HomePNA PHY Network Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

MII Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

MII Network Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

MII Management Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Auto-Poll External PHY Status Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Network Port Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

PCI and JTAG Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Disconnect When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Disconnect Of Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Master Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Bus Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Basic Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

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6 Am79C978

PRELIMINARY

Basic Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Disconnect With Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Master Initiated Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Preemption During Non-Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Master Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Advanced Parity Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Non-Burst FIFO DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Burst FIFO DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Re-Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Descriptor Rings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Transmit Descriptor Table Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Receive Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Receive Frame Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Software Interrupt Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

10/100 Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Transmit and Receive Message Data Encapsulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Media Access Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Medium Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Transmit Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Late Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

SQE Test Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Receive Function Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Address Matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Automatic Pad Stripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Miscellaneous Loopback Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Full-Duplex Link Status LED Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

10BASE-T Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Twisted Pair Receive Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Page 7

Am79C978 7

PRELIMINARY

Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Collision Detect Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Jabber Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Reverse Polarity Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Soft Reset Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

1 Mbps HomePNA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

HomePNA PHY Medium Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

HomePNA Symbol Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Time Interval Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

ACCESS ID Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Symbol 0 (SYNC interval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

SYNC Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

SYNC Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

AID Symbols 1 through 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

AID Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

AID Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Collisions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

JAM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

ACCESS ID Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Silence Interval (AID symbol 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Data Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Data Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Data Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Data Symbol RLL25 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Management Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Header AID Remote Control Word Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

PHY Control and Management Block (PCM Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Description of the Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Direct SRAM Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Automatic EEPROM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

EEPROM Auto-Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Direct Access to the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

EEPROM-Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

EEPROM MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Power Savings Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Power Management Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

OnNow Wake-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Link Change Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

OnNow Pattern Match Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Pattern Match RAM (PMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Magic Packet Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Boundary Scan Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

TAP Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Instruction Register and Decoding Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Other Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

NAND Tree Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Page 8

8 Am79C978

PRELIMINARY

H_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

S_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Address PROM Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Word I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Double Word I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

PCI Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

PCI Programming Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

PCI Sub-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

PCI Base-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

PCI Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

PCI Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

PCI I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

PCI Memory Mapped I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

PCI Capabilities Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

PCI Interrupt Line Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI MIN_GNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Capability Identifier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Power Management Capabilities Register (PMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Power Management Control/Status Register (PMCSR) . . . . . . . . . . . . . . . . . . . . . . . . . .112

PCI PMCSR Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

RAP: Register Address Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Control and Status Registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

CSR0: Controller Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

CSR1: Initialization Block Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

CSR2: Initialization Block Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

CSR5: Extended Control and Interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

CSR6: RX/TX Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

CSR7: Extended Control and Interrupt 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

CSR12: Physical Address Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

CSR13: Physical Address Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

CSR14: Physical Address Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

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CSR15: Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

CSR18: Current Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

CSR19: Current Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CSR20: Current Transmit Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CSR21: Current Transmit Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CSR22: Next Receive Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CSR23: Next Receive Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CSR26: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CSR27: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CSR28: Current Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CSR29: Current Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CSR30: Base Address of Transmit Ring Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CSR31: Base Address of Transmit Ring Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CSR32: Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

CSR33: Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

CSR34: Current Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

CSR35: Current Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

CSR36: Next Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

CSR37: Next Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

CSR38: Next Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

CSR39: Next Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

CSR40: Current Receive Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

CSR41: Current Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

CSR42: Current Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

CSR43: Current Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

CSR44: Next Receive Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

CSR45: Next Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

CSR46: Transmit Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

CSR47: Transmit Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

CSR48: Receive Poll Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

CSR49: Receive Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

CSR58: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

CSR60: Previous Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

CSR61: Previous Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

CSR62: Previous Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

CSR63: Previous Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

CSR64: Next Transmit Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

CSR65: Next Transmit Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

CSR66: Next Transmit Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

CSR67: Next Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

CSR72: Receive Ring Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . .140

CSR82: Transmit Descriptor Address Pointer Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

CSR84: DMA Address Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

CSR85: DMA Address Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

CSR88: Chip ID Register Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

CSR89: Chip ID Register Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

CSR92: Ring Length Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

CSR100: Bus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

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CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

CSR122: Advanced Feature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

CSR124: Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

CSR125: MAC Enhanced Configuration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Bus Configuration Registers (BCRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

BCR1: Master Mode Write Active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

BCR2: Miscellaneous Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

BCR4: LED 0 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

BCR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

BCR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

BCR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

BCR9: Full-Duplex Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

BCR16: I/O Base Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

BCR17: I/O Base Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

BCR19: EEPROM Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

BCR20: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

BCR22: PCI Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

BCR23: PCI Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

BCR24: PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

BCR25: SRAM Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

BCR26: SRAM Boundary Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

BCR27: SRAM Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

BCR28: Expansion Bus Port Address Lower (Used for Flash/EPROM and SRAM Accesses)169

BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses). . . . . . . . . . . . .169

BCR30: Expansion Bus Data Port Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

BCR31: Software Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

BCR32: PHY Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

BCR33: PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

BCR34: PHY Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

BCR36: PCI Power Management Capabilities (PMC) Alias Register . . . . . . . . . . . . . . . . . . .174

BCR37: PCI DATA Register 0 (DATA0) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

BCR38: PCI DATA Register 1 (DATA1) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

BCR39: PCI DATA Register 2 (DATA2) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

BCR40: PCI DATA Register 3 (DATA3) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

BCR41: PCI DATA Register 4 (DATA4) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

BCR42: PCI DATA Register 5 (DATA5) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

BCR43: PCI DATA Register 6 (DATA6) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

BCR44: PCI DATA Register 7 (DATA7) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

BCR48: LED4 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

BCR49: PHY Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

BCR50-BCR55: Reserved Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

10BASE-T PHY Management Registers (TBRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

TBR1: 10BASE-T Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

TBR2 and TBR3: 10BASE-T PHY Identifier (Registers 2 and 3). . . . . . . . . . . . . . . . . . . . . . .184

TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4). . . . . . . . . . . . . . . .185

TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . .186

TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . .187

TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . . . . . . .187

Reserved Registers (Registers 8-15, 18, 20-23, and 25-31) . . . . . . . . . . . . . . . . . . . . . . . . . .187

TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16). . . . . . . . . . . . . .188

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Am79C978 11

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TBR17: 10BASE-T PHY Control/Status Register (Register 17). . . . . . . . . . . . . . . . . . . . . . . .189

TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . . . . . . .190

Reserved Register: 10BASE-T Configuration Register (Register 22) . . . . . . . . . . . . . . . . . . .190

Reserved Register: 10BASE-T Carrier Status Register (Register 23). . . . . . . . . . . . . . . . . . .190

TBR24: 10BASE-T Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . .190

1 Mbps HomePNA PHY Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

HPR0: HomePNA PHY MII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

HPR1: HomePNA PHY MII Status (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

HPR2 and HPR3: HomePNA PHY MII PHY ID (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . .193

HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7). . . . . . . . . . . . . . . . . . . . . .193

Reserved Registers: HPR8 - HPR15, HPR17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

HPR16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19). . . . . . . . . . . . . . . . . .194

HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21) . . . . . . . . . . . . . . . . .195

HPR22: HomePNA PHY AID (Register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

HPR23: HomePNA PHY Noise Control (Register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

HPR24: HomePNA PHY Noise Control 2 (Register 24). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

HPR25: HomePNA PHY Noise Statistics (Register 25). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

HPR26: HomePNA PHY Event Status (Register 26). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

HPR27: HomePNA PHY Event Status (Register 27). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

HPR28: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

HPR29: HomePNA PHY Tx Control (Register 29). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Initialization Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

RLEN and TLEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

RMD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

RMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

RMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

RMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

TMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

TMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

TMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

TMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Bus Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

10BASE-T PHY Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

1 Mbps HomePNA PHY Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Am79C978 Programmable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES . . . . . . . . . . . . . . . . . . . .221

SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Analog I/O - PECL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

10BASE-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

PECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

10BASE-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE. . . . . . . . . . . . . . . . . . .228

Page 12

12 Am79C978

PRELIMINARY

SWITCHING WAVEFORMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . .234

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

PQL144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

APPENDIX A - ALTERNATIVE METHOD FOR INITIALIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . A-1

APPENDIX B - LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT . . . . . . . . . . . . . . . . B-1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

LAPP Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

An Alternative LAPP Flow: Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

LIST OF FIGURES

Figure 1. Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 2. Frame Format at the MII Interface Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 3. Slave Configuration Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 4. Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 5. Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 6. Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 7. Expansion ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 8. Disconnect of Slave Cycle When Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 9. Disconnect of Slave Burst Transfer - No Host Wait States. . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 10. Disconnect of Slave Burst Transfer - Host Inserts Wait States. . . . . . . . . . . . . . . . . . . . . 42

Figure 11. Address Parity Error Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 12. Slave Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13. Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 14. Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 15. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16. Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 17. Burst Write Transfer (EXTREQ = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 18. Disconnect With Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 19. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 20. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21. Preemption During Non-Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 22. Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 23. Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 24. Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 25. Initialization Block Read In Non-Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 26. Initialization Block Read In Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 27. Descriptor Ring Read In Non-Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 28. Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 29. Descriptor Ring Write In Non-Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 30. Descriptor Ring Write In Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 31. FIFO Burst Write at Start of Unaligned Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 32. FIFO Burst Write at End of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 33. 16-Bit Software Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 34. 32-Bit Software Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 36. IEEE 802.3 Frame and Length Field Transmission Order . . . . . . . . . . . . . . . . . . . . . . . . 75

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Am79C978 13

PRELIMINARY

Figure 37. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 38. HomePNA PHY Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 39. AID Symbol Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 40. AID Symbol Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 41. Transmit Data Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 42. Receive Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 43. RLL 25 Coding Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 44. Block Diagram No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 45. Block Diagram Low Latency Receive Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 46. LED Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47. OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 48. Pattern Match RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 49. NAND Tree Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 50. NAND Tree Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 51. Address Match Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 52. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 56. Normal and Tri-State Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 57. CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 58. CLK Waveform for 3.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 59. Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 60. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 61. Output Tri-State Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 62. EEPROM Read Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 63. Automatic PREAD EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 64. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 65. JTAG (IEEE 1149.1) Test Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 66. Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 67. Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 68. MDC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 69. Management Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 70. Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure B-1. LAPP Timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4

Figure B-2. LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5

Figure B-3. LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-9

Figure B-4. LAPP 3 Buffer Grouping for Two-Interrupt Methods . . . . . . . . . . . . . . . . . . . . . . . . . . .B-10

LIST OF TABLES

Table 1. Interrupt Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 2. External Clock/Crystal Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 3. PCI Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 4. PCI Software Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 5. Slave Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 6. Slave Configuration Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 7. Master Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 8. Descriptor Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 9. Descriptor Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 10. Receive Address Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 11. Auto-Negotiation Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 12. HomePNA PHY Pulse Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 13. Access ID Symbol Pulse Positions and Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 14. Blanking Interval Speed Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 15. Master Station Control Word Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 16. Slave Station Control Word Status Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 17. MII Control Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 18. EEPROM Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 19. LED Default Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 20. IEEE 1149.1 Supported Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Page 14

14 Am79C978

PRELIMINARY

Table 21. BSR Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 22. Device ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 23. NAND Tree Pin Sequence (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 24. NAND Tree Pin Sequence (144 TQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 25. PCI Configuration Space Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 26. I/O Map in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 27. Legal I/O Accesses in Word I/O Mode (DWIO = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 28. I/O Map in DWord I/O Mode (DWIO = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 29. Legal I/O Accesses in Double Word I/O Mode (DWIO =1) . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 30. Loopback Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 31. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 32. Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 33. Transmit Start Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 34. Transmit Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 35. BCR Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 36. ROMTNG Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 37. PHY Select Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 38. EEDET Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 39. Interface Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 40. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 41. SRAM_BND Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 42. EBCS Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 43. CLK_FAC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 44. FMDC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 45. APDW Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 46. Am79C978 10BASE-T PHY Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 47. TBR0: 10BASE-T PHY Control Register (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 48. TBR1: 10BASE-T PHY Status Register (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 49. TBR2: 10BASE-T PHY Identifier (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 50. TBR3: 10BASE-T PHY Identifier (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 51. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . 185

Table 52. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 53. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 54. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6). . . . . . . . . . . . . . . . . 187

Table 55. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7). . . . . . . . . . . . . . . . . 187

Table 56. TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16) . . . . . . . . . . . 188

Table 57. TBR17: 10BASE-T PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . . . . 189

Table 58. TBR19: 10BASE-T PHY Management Extension Register (Register 19). . . . . . . . . . . . . . 190

Table 59. TBR24: 10BASE-T Summary Status Register (Register 24). . . . . . . . . . . . . . . . . . . . . . . . 190

Table 60. HPR0: HomePNA PHY MII Control (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 61. HPR1: HomePNA PHY MII Status (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 62. HPR2 and HPR3: HomePNA PHY MII ID (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . 193

Table 63. HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7) . . . . . . . . . . . . . . . . . . . 193

Table 64. HPR 16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 65. HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19) . . . . . . . . . . . . . . . 195

Table 66. HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21) . . . . . . . . . . . . . . . 195

Table 67. HPR22: HomePNA PHY AID (Register 22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 68. HPR23: HomePNA PHY Noise Control (Register 23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 69. HPR24: HomePNA PHY Noise Control 2 (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 70. HPR25: HomePNA PHY Noise Statistics (Register 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 71. HPR26: HomePNA PHY Event Status (Register 26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 72. HPR27: HomePNA PHY Event Status (Register 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 73. HPR28: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 74. HPR29: HomePNA PHY TX Control (Register 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 75. Initialization Block (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 76. Initialization Block (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Page 15

Am79C978 15

PRELIMINARY

Table 77. R/TLEN Decoding (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 78. R/TLEN Decoding (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 79. Receive Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 80. Receive Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 81. Receive Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 82. Transmit Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 83. Transmit Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 84. Transmit Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 85. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 86. Control and Status Registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 87. Bus Configuration Registers (BCRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 88. 10BASE-T PHY Management Registers (TBRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 89. 1 Mbps HomePNA PHY Management Registers (HPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 90. Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 91. Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table A-1. Registers for Alternative Initialization Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1

Page 16

16 Am79C978

PRELIMINARY

RELATED AMD PRODUCTS

Part No. Description Controllers

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)

Integrated Controllers

Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller Am79C940B Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus Am79C965A PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus Am79C971 PCnet-

FAST

Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

Am79C972 PCnet-

FAST

+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

Manchester Encoder/Decoder

Am7992B Serial Interface Adapter (SIA)

Physical Layer Devices (Single-Port)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver (TAP) Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79C873 10/100 Mbps Ethernet Physical Layer Transceiver (NetPHY™-1)

Physical Layer Devices (Multi-Port)

Am79C871 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™) Am79C988B Quad Integrated Ethernet Transceiver (QuIET™) Am79C989 Quad Ethernet Switching Transceiver (QuEST™)

Integrated Repeater/Hub Devices

Am79C981 Integrated Multiport Repeater Plus (IMR+) Am79C982 Basic Integrated Multiport Repeater (bIMR) Am79C983A Integrated Multiport Repeater 2 (IMR2™) Am79C984A Enhanced Integrated Multiport Repeater (eIMR™) Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™) Am79C987 Hardware Implemented Management Information Base (HIMIB™)

Page 17

Am79C978 17

PRELIMINARY

CONNECTION DIAGRAM (144 TQFP)

100

101

102

103

104

108 107 106 105

4 5 6 7 8 9 10 11

1 2 3

28 29 30

12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27

32 33 34

35 36

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21 AD20

VDD AD19 AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY VSSB TRDY

VDD_PCI

DEVSEL

STOP

VDD PERR SERR VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS AD14 AD13

VSSB

AD12

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

PCI_CLK

RST

INTAPGVDD

TDI

VSSB

TDO

VDDB

TMS

TCK

PME

VSS

EECS

VSSB

EESK/LED1

LED2

VDDB

EEDI/LED0

EEDO/LED3

RXDVDDRX RX+ DVSSX TXDVDDTX TX+ DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 VSS VDD XCLK/XTAL LED4 MDIO VSSB MDC RXD3 RXD2 VDDB RXD1 RXD0 VSS

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

VDD

CRS

VSSB

COL

TXD3

TXD2

TXD1

VDD

VDDB

TXD0

TX_EN

TX_CLK

VSSB

RX_ER

RX_CLK

RX_DV

132

131

130

129

128

127

126

125

124

123

122

144

143

142

141

140

139

138

137

136

135

134

133

121

120

119

118

117

116

115

114

113

112

111

110

109

4243444546474849505152

373839

Am79C978

22206B-2

Page 18

18 Am79C978

PRELIMINARY

CONNECTION DIAGRAM (160 PQFP)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

NC NC

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21 AD20

VDD AD19 AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS AD14 AD13

VSSB

AD12

NC NC

414243444546474849505152535455565758596061626364656667686970717273747576777879

AD11

VDD_PCI

AD10

AD9

AD8

C/BE0

VSSB

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

VSSB

AD2

VDD_PCI

AD1

AD0

VSS

VDD

CRS

VSSB

COL

TXD3

TXD2

TXD1

VDD

VDDB

TXD0

TX_EN

TX_CLK

VSSB

RX_ER

RX_CLK

RX_DV

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

NCNCC/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

PCI_CLK

RST

INTAPGVDD

TDI

VSSB

TDO

VDDB

TMS

TCK

PME

VSS

EECS

VSSB

EESK/LED1

LED2

VDDB

EEDI/LED0

EEDO/LED3NCNC

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

RXDVDDRX RX+ DVSSX TXDVDDTX TX+ DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 VSS VDD XCLK/XTAL LED4 MDIO VSSB MDC RXD3 RXD2 VDDB RXD1 RXD0 VSS NC NC NC NC

Am79C978

22206B-3

Page 19

Am79C978 19

PRELIMINARY

PIN DESIGNATIONS (PQL144) Listed By Pin Number

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

IDSEL 37 AD11 73 VSS 109 EEDO/LED3 2 AD23 38 VDD_PCI 74 RXD0 110 EEDI/LED0 3 VSSB 39 AD10 75 RXD1 111 VDDB 4 AD22 40 AD9 76 VDDB 112 LED2 5 VDD_PCI 41 AD8 77 RXD2 113 EESK/LED1 6 AD21 42 C/BE0 78 RXD3 114 VSSB 7 AD20 43 VSSB 79 MDC 115 EECS 8 VDD 44 AD7 80 VSSB 116 VSS 9 AD19 45 VDD_PCI 81 MDIO 117 PME 10 AD18 46 AD6 82 LED4 118 TCK 11 VSSB 47 AD5 83 XCLK/XTAL 119 TMS 12 AD17 48 VDD 84 VDD 120 VDDB 13 VDD_PCI 49 AD4 85 VSS 121 TDO 14 AD16 50 AD3 86 XTAL2 122 VSSB 15 C/BE2 51 VSSB 87 XTAL1 123 TDI 16 VSS 52 AD2 88 VDDCO 124 VDD 17 FRAME 53 VDD_PCI 89 VSSHR 125 PG 18 IRDY 54 AD1 90 HRTRXN 126 INTA 19 VSSB 55 AD0 91 VDDHR 127 RST 20 TRDY 56 VSS 92 HRTRXP 128 PCI_CLK 21 VDD_PCI 57 VDD 93 VDDB 129 GNT 22 DEVSEL 58 CRS 94 VSSB 130 REQ 23 STOP 59 VSSB 95 DVDDA_HR 131 VDD_PCI 24 VDD 60 COL 96 PHY_RST 132 AD31 25 PERR 61 TXD3 97 DVDDA 133 VSSB 26 SERR 62 TXD2 98 DVSSA 134 VSS 27 VSSB 63 TXD1 99 DVSSD 135 AD30 28 PAR 64 VDD 100 IREF 136 AD29 29 VDD_PCI 65 VDDB 101 DVDDD 137 AD28 30 C/BE1 66 TXD0 102 TX+ 138 AD27 31 AD15 67 TX_EN 103 DVDDTX 139 VDD_PCI 32 VSS 68 TX_CLK 104 TX- 140 AD26 33 AD14 69 VSSB 105 DVSSX 141 VSSB 34 AD13 70 RX_ER 106 RX+ 142 AD25 35 VSSB 71 RX_CLK 107 DVDDRX 143 AD24 36 AD12 72 RX_DV 108 RX- 144 C/BE3

Page 20

20 Am79C978

PRELIMINARY

PIN DESIGNATIONS (PQR160) Listed By Pin Number

Pin No.

Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

NC 41 NC 81 NC 121 NC 2 NC 42 NC 82 NC 122 NC 3 IDSEL 43 AD11 83 NC 123 EEDO/LED3 4 AD23 44 VDD_PCI 84 NC 124 EEDI/LED0 5 VSSB 45 AD10 85 VSS 125 VDDB 6 AD22 46 AD9 86 RXD0 126 LED2 7 VDD_PCI 47 AD8 87 RXD1 127 EESK/LED1 8 AD21 48 C/BE0 88 VDDB 128 VSSB 9 AD20 49 VSSB 89 RXD2 129 EECS 10 VDD 50 AD7 90 RXD3 130 VSS 11 AD19 51 VDD_PCI 91 MDC 131 PME 12 AD18 52 AD6 92 VSSB 132 TCK 13 VSSB 53 AD5 93 MDIO 133 TMS 14 AD17 54 VDD 94 LED4 134 VDDB 15 VDD_PCI 55 AD4 95 XCLK/XTAL 135 TDO 16 AD16 56 AD3 96 VDD 136 VSSB 17 C/BE2 57 VSSB 97 VSS 137 TDI 18 VSS 58 AD2 98 XTAL2 138 VDD 19 FRAME 59 VDD_PCI 99 XTAL1 139 PG 20 IRDY 60 AD1 100 VDDCO 140 INTA 21 VSSB 61 AD0 101 VSSHR 141 RST 22 TRDY 62 VSS 102 HRTRXN 142 PCI_CLK 23 VDD_PCI 63 VDD 103 VDDHR 143 GNT 24 DEVSEL 64 CRS 104 HRTRXP 144 REQ 25 STOP 65 VSSB 105 VDDB 145 VDD_PCI 26 VDD 66 COL 106 VSSB 146 AD31 27 PERR 67 TXD3 107 DVDDA_HR 147 VSSB 28 SERR 68 TXD2 108 PHY_RST 148 VSS 29 VSSB 69 TXD1 109 DVDDA 149 AD30 30 PAR 70 VDD 110 DVSSA 150 AD29 31 VDD_PCI 71 VDDB 111 DVSSD 151 AD28 32 C/BE1 72 TXD0 112 IREF 152 AD27 33 AD15 73 TX_EN 113 DVDDD 153 VDD_PCI 34 VSS 74 TX_CLK 114 TX+ 154 AD26 35 AD14 75 VSSB 115 DVDDTX 155 VSSB 36 AD13 76 RX_ER 116 TX- 156 AD25 37 VSSB 77 RX_CLK 117 DVSSX 157 AD24 38 AD12 78 RX_DV 118 RX+ 158 C/BE3 39 NC 79 NC 119 DVDDRX 159 NC 40 NC 80 NC 120 RX- 160 NC

Page 21

Am79C978 21

PRELIMINARY

PIN DESIGNATIONS (PQL144) Listed By Group

Pin Name

Pin Function Type Voltage Driver

No. of

Pins

HomePNA PHY Network Ports

HRTXRXP/N

Receive/Transmit Data I/O 3.3 NA 2 XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I 3.3 - 1 XTAL2 Crystal Output (20 MHz XTAL) O 3.3 XTAL 1 XCLK/XTAL Oscillator/Crystal Select I 3.3 - 1

10BASE-T Network Ports

TX±

Serial T ransmit Data O 3.3 NA 2 RX± Serial Receive Data I 3.3 - 2 IREF Tied to GND via a 12 k Ω 1% resistor I 3.3 - 1 PHY_RST Buffered PCI RST signal O 3.3 OMII1 1

MII

TX_CLK

MII T r ansmit Clock I 3.3 - 1 TXD[3:0] MII Tr ansmit Data O 3.3 OMII1 4 TX_EN MII Transmit Enable O 3.3 OMII1 1 RX_CLK MII Receive Clock I 3.3 - 1 RXD[3:0] MII Receive Data I 3.3 - 4 RX_ER MII Receive Error I 3.3 - 1 RX_DV MII Receive Data Valid I 3.3 - 1 MDC MII Management Data Clock O 3.3 OMII2 1 MDIO MII Management Data I/O I/O 3.3 TSMII 1 CRS Carrier Sense I 3.3 - 1 COL Collision I 3.3 - 1

Magic Packet

PME

Power Management Event O 3.3 OD6 1 PG Power Good I 3.3 - 1

Host CPU Interface

PCI_CLK

CPU Clock I 3.3/5 - 1 C/BE[3:0] Bus Command Byte Enable I/O 3.3/5 TS3 4 AD[31:0] Address/Data I/O 3.3/5 TS3 32 DEVSEL Device Select I/O 3.3/5 STS6 1 FRAME Cycle Frame I/O 3.3/5 STS6 1 GNT Bus Grant I 3.3/5 - 1 IDSEL Initialization Device Select I 3.3/5 - 1 INTA Interrupt O 3.3/5 OD6 1 IRDY Initiator Ready I/O 3.3/5 STS6 1 PAR Parity I/O 3.3/5 STS6 1 PERR Parity Error I/O 3.3/5 STS6 1 REQ Bus Request O 3.3/5 TS3 1 RST Reset I 3.3/5 - 1 SERR System Error I/O 3.3/5 OD6 1

Page 22

22 Am79C978

PRELIMINARY

Pin Name

Pin Function Type Voltage Driver

No. of

Pins

OP Stop I/O 3.3/5 STS6 1

TRDY Target Ready I/O 3.3/5 STS6 1

EEPROM/LED Interface

EECS

Chip Select O 3.3 O6 1 EEDI/LED0 Data In/LED0 I/O 3.3 LED 1 EESK/LED1 Serial Clock/LED1 O 3.3 LED 1 LED2 LED2 O 3.3 LED 1 EEDO/LED3 Data Out/LED3 O 3.3 LED 1 LED4 LED4 O 3.3 LED 1

Test Access Port Interface (JTAG)

TCLK

Test Clock I 3.3 - 1 TMS Test Mode Select I 3.3 - 1 TDI Test Data In I 3.3 - 1 TDO Test Data Out O 3.3 TS6 1

Power/Ground

DVDDTX

Transceiver Digital Power P 3.3 - 1 DVDDRX Transceiver Digital Power P 3.3 - 1 VDD_PCI Digital power for the PCI bus P 3.3 - 9 VDDB Digital power for the PCI bus P 3.3 - 5 VDD Digital power P 3.3 - 7 VDDHR Digital power for HomePNA PHY P 3.3 - 1 DVDDA Transceiver Analog Power P 3.3 - 1 DVDDD Transceiver Digital Power P 3.3 - 1 VDDCO Crystal Oscillator Power P 3.3 - 1 DVDDA_HR Transceiver Analog Power P 3.3 - 1 DVSSD Transceiver Digital Ground G 0 - 1 DVSSA Transceiver Analog Ground G 0 - 1 DVSSX Transceiver Ground G 0 - 1 VSSB Digital I/O Ground G 0 - 15 VSS Digital Ground G 0 - 7 VSSHR HomePNA PHY Analog Ground G 0 - 1

Page 23

Am79C978 23

PRELIMINARY

PIN DESIGNATIONS (PQR160) Listed By Group

Pin Name

Pin Function Type Voltage Driver

No. of

Pins

HomePNA PHY Network Ports

HRTXRXP/N

Receive/Transmit Data I/O 3.3 NA 2 XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I 3.3 - 1 XTAL2 Crystal Output (20 MHz XTAL) O 3.3 XTAL 1 XCLK/XTAL Oscillator/Crystal Select I 3.3 - 1

10BASE-T Network Ports

TX±

Serial T ransmit Data O 3.3 NA 2 RX± Serial Receive Data I 3.3 - 2 IREF Tied to GND via a 12 k Ω 1% resistor I 3.3 - 1 PHY_RST Buffered PCI RST signal O 3.3 OMII1 1

MII

TX_CLK

Magic Packet

PME

Power Management Event O 3.3 OD6 1 PG Power Good I 3.3 - 1

Host CPU Interface

PCI_CLK CPU Clock I 3.3/5 - 1 C/BE[3:0] Bus Command Byte Enable I/O 3.3/5 TS3 4 AD[31:0] Address/Data I/O 3.3/5 TS3 32 DEVSEL Device Select I/O 3.3/5 STS6 1 FRAME Cycle Frame I/O 3.3/5 STS6 1 GNT Bus Grant I 3.3/5 - 1 IDSEL Initialization Device Select I 3.3/5 - 1 INTA Interrupt O 3.3/5 OD6 1 IRDY Initiator Ready I/O 3.3/5 STS6 1 PAR Parity I/O 3.3/5 STS6 1 PERR Parity Error I/O 3.3/5 STS6 1 REQ Bus Request O 3.3/5 TS3 1 RST Reset I 3.3/5 - 1 SERR System Error I/O 3.3/5 OD6 1

Page 24

24 Am79C978

PRELIMINARY

Pin Name Pin Function Type Voltage Driver

No. of

Pins

STOP Stop I/O 3.3/5 STS6 1 TRDY Target Ready I/O 3.3/5 STS6 1

EEPROM/LED Interface

EECS Chip Select O 3.3 O6 1 EEDI/LED0 Data In/LED0 I/O 3.3 LED 1 EESK/LED1 Serial Clock/LED1 O 3.3 LED 1 LED2 LED2 O 3.3 LED 1 EEDO/LED3 Data Out/LED3 O 3.3 LED 1 LED4 LED4 O 3.3 LED 1

Test Access Port Interface (JTAG)

TCLK Test Clock I 3.3 - 1 TMS Test Mode Select I 3.3 - 1 TDI Test Data In I 3.3 - 1 TDO Test Data Out O 3.3 TS6 1

Power/Ground

DVDDTX Transceiver Digital Power P 3.3 - 1 DVDDRX Transceiver Digital Power P 3.3 - 1 VDD_PCI Digital power for the PCI bus P 3.3 - 9 VDDB Digital power for the PCI bus P 3.3 - 5 VDD Digital power P 3.3 - 7 VDDHR Digital power for HomePNA PHY P 3.3 - 1 DVDDA Transceiver Analog Power P 3.3 - 1 DVDDD Transceiver Digital Power P 3.3 - 1 VDDCO Crystal Oscillator Power P 3.3 - 1 DVDDA_HR Transceiver Analog Power P 3.3 - 1 DVSSD Transceiver Digital Ground G 0 - 1 DVSSA Transceiver Analog Ground G 0 - 1 DVSSX Transceiver Ground G 0 - 1 VSSB Digital I/O Ground G 0 - 15 VSS Digital Ground G 0 - 7 VSSHR HomePNA PHY Analog Ground G 0 - 1

Page 25

Am79C978 25

PRELIMINARY

PIN DESIGNATIONS Listed By Driver Type

The following table describes the various types of output drivers used in the Am79C978 controller. All I

and

values shown in the table apply to 3.3 V signaling.

A sustained tri-state signal is a low active signal that is driven high for one clock period bef ore it is left ﬂoating.

TX is a differential output driver. Its characteristics and those of XTAL2 output are described in the

DC CHAR-

ACTERISTICS

section.

Driver Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 0.4 50 O6 Totem Pole 6 0.4 50 OD6 Open Drain 6 NA 50 TS3 Tri-State 3 2 50 TS6 Tri-State 6 2 50 STS6 Sustained Tri-State 6 2 50 OMII1 T ri-State 4 4 50 OMII2 T ri-State 4 4 390 TSMII Tri-State 4 4 470

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26 Am79C978

PRELIMINARY

ORDERING INFORMATION Standard Products

AMD standard products are available in se veral pac kages and operating ranges. The order number (V alid Combination) is formed by a combination of the elements below.

Am79C978

TEMPERATURE RANGE

C = Commercial (0° C to +70° C)

SPEED OPTION

PACKAGE TYPE

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Not applicable

K = Plastic Quad Flat Pack (PQR160) V = Thin Quad Flat Pack (PQL144)

Am79C978 PCnet-Home Single-Chip 1/10 Mbps PCI Home Networking Controller

Valid Combinations

Am79C978

KC\W VC\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

K\V

Page 27

Am79C978 27

PRELIMINARY

PIN DESCRIPTIONS PCI Interface AD[31:0]

Address and Data Input/Output

Address and data are multiplexed on the same bus interface pins. During the ﬁrst clock of a transaction, AD[31:0] contain a physical address (32 bits). Dur ing the subsequent clocks, AD[31:0] contain data. Byte ordering is little endian by default. AD[7:0] are deﬁned as the least signiﬁcant byte (LSB) and AD[31:24] are deﬁned as the most signiﬁcant byte (MSB). F or FIFO data transfers, the Am79C978 controller can be programmed for big endian b yte ordering. See CSR3, bit 2 (BSWP) for more details.

During the address phase of the transaction, when the Am79C978 controller is a bus master , AD[31:2] will address the active Double Word (DWord). The Am79C978 controller always drives AD[1:0] to '00' during the address phase indicating linear burst order. When the Am79C978 controller is not a bus master , the AD[31:0] lines are continuously monitored to determine if an address match exists for slave transfers.

During the data phase of the transaction, AD[31:0] are driven by the Am79C978 controller when performing bus master write and slave read operations. Data on AD[31:0] is latched by the Am79C978 controller when performing bus master read and slav e write operations.

When RST is active, AD[31:0] are inputs f or NAND tree testing.

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiple x ed on the same bus interface pins. During the address phase of the transaction, C/BE[3:0] deﬁne the bus command. During the data phase, C/BE[3:0] are used as byte enables. The byte enables deﬁne which physical byte lanes carry meaningful data. C/BE0 applies to byte 0 (AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The function of the byte enables is independent of the byte ordering mode (BSWP, CSR3, bit 2).

When RST is active, C/BE[3:0] are inputs for NAND tree testing

PCI_CLK

Clock Input

This clock is used to drive the system bus interf ace and the internal buffer management unit. All bus signals are sampled on the rising edge of PCI_CLK and all parameters are deﬁned with respect to this edge. The Am79C978 controller normally operates over a frequency range of 10 to 33 MHz on the PCI bus due to networking demands. The Am79C978 controller will

support a clock frequency of 0 MHz after certain precautions are taken to ensure data integrity. This clock or a derivation is not used to drive any network functions.

When RST is active, PCI_CLK is an input for NAND tree testing

DEVSEL

Device Select Input/Output

The Am79C978 controller drives DEVSEL LOW when it detects a transaction that selects the device as a target. The device samples DEVSEL to detect if a target claims a transaction that the Am79C978 controller has initiated.

When RST is active, DEVSEL is an input f or NAND tree testing

FRAME

Cycle Frame Input/Output

FRAME is driven by the Am79C978 controller when it is the bus master to indicate the beginning and duration of a transaction. FRAME is asserted to indicate a bus transaction is beginning. FRAME is asserted while data transfers continue. FRAME is deasserted before the ﬁnal data phase of a transaction. When the Am79C978 controller is in slave mode, it samples FRAME to determine the address phase of a transaction.

When RST is active, FRAME is an input f or NAND tree testing

GNT

Bus Grant Input

This signal indicates that the access to the bus has been granted to the Am79C978 controller.

The Am79C978 controller supports bus parking. When the PCI bus is idle and the system arbiter asserts GNT without an active REQ from the Am79C978 controller, the device will drive the AD[31:0], C/BE[3:0], and PAR lines.

When RST is active, GNT is an input for NAND tree testing

IDSEL

Initialization Device Select Input

This signal is used as a chip select for the Am79C978 controller during conﬁguration read and write transactions.

When RST is active, IDSEL is an input for NAND tree testing

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28 Am79C978

PRELIMINARY

INTA

Interrupt Request Output

An attention signal which indicates that one or more of the following status ﬂags is set: EXDINT, IDON, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MREINT, and STINT. Each status ﬂag has either a mask or an enable bit which allows for suppression of INTA assertion. Table 1 shows the ﬂag descriptions. By default INTA is an open-drain output. For applications that need a high-active edge-sensitive interrupt signal, the INT

A pin can be conﬁgured for this mode by setting IN-

TLEVEL (BCR2, bit 7) to Table 1.

When RST is active, INTA is the output for NAND tree testing.

IRDY

Initiator Ready Input/Output

IRD Y indicates the ability of the initiator of the transaction to complete the current data phase. IRDY is used in conjunction with TRDY. Wait states are inserted until both IRDY and TRDY are asserted simultaneously. A data phase is completed on any clock when both IRDY and TRD Y are asserted.

When the Am79C978 controller is a bus master, it asserts IRDY during all write data phases to indicate that valid data is present on AD[31:0]. Dur ing all read data phases, the device asserts IRD

Y to indicate that it is

ready to accept the data. When the Am79C978 controller is the target of a trans-

action, it checks IRDY during all write data phases to determine if valid data is present on AD[31:0]. During all read data phases, the device checks IRDY to determine if the initiator is ready to accept the data.

When RST is active, IRDY is an input for NAND tree testing

PAR

Parity Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0]. When the Am79C978 controller is a bus master , it generates parity during the address and write data phases. It checks parity during read data phases. When the Am79C978 controller operates in slave mode , it checks parity during every address phase. When it is the target of a cycle, it checks parity during write data phases and it generates parity during read data phases.

When RST is active, PAR is an input for NAND tree testing

PERR

Parity Error Input/Output

During any slave write transaction and any master read transaction, the Am79C978 controller asserts PERR when it detects a data parity error and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) to 1. During any master write transaction, the Am79C978 controller monitors PERR to see if the target reports a data parity error.

When RST is active, PERR is an input for NAND tree testing

REQ

Bus Request Input/Output

The Am79C978 controller asserts REQ pin as a signal that it wishes to become a bus master. REQ is driven high when the Am79C978 controller does not request the bus. In Power Management mode, the REQ pin will not be driven.

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

EXDINT

Excessive Deferral

CSR5, bit 6 CSR5, bit 7

IDON

Initialization Done

CSR3, bit 8 CSR0, bit 8

MERR Memory Error CSR3, bit 11 CSR0, bit 11 MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO

Missed Frame Count Overﬂow

CSR4, bit 8 CSR4, bit 9

MPINT

Magic Packet Interrupt

CSR5, bit 3 CSR5, bit 4

RCVCCO

Receive Collision Count Overﬂow

CSR4, bit 4 CSR4, bit 5

RINT

Receive Interrupt

CSR3, bit 10 CSR0, bit 10 SINT System Error CSR5, bit 10 CSR5, bit 11 TINT

Transmit Interrupt

CSR3, bit 9 CSR0, bit 9 TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCINT

MII Management Command Complete Interrupt

CSR7, bit 4 CSR7, bit 5

MPDTINT

MII PHY Detect T ransition Interrupt

CSR7, bit 0 CSR7, bit 1

MAPINT

MII Auto-Poll Interrupt

CSR7, bit 6 CSR7, bit 7

MREINT

MII Management Frame Read Error Interrupt

CSR7, bit 8 CSR7, bit 9

STINT

Software Timer Interrupt

CSR7, bit 10 CSR7, bit 11

Page 29

Am79C978 29

PRELIMINARY

When RST is active, REQ is an input for NAND tree testing

RST

Reset Input

When RST is asserted LOW and the PG pin is HIGH, then the Am79C978 controller performs an internal system reset of the type H_RESET (HARDWARE_RESET, see section on RESET). RST must be held for a minimum of 30 clock periods. While in the H_RESET state, the Am79C978 controller will disable or deassert all outputs. RST may be asynchronous to clock when asserted or deasserted.

When the PG pin is LOW, RST

disables all of the PCI

pins except the PME pin.

When RST is LOW and PG is HIGH, NAND tree testing is enabled.

SERR

System Error Output

During any slave transaction, the Am79C978 controller asserts SERR when it detects an address parity error, and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to 1.

By default SERR is an open-drain output. For component test, it can be programmed to be an active-high totem-pole output.

When RST is active, SERR is an input for NAND tree testing

STOP

Stop Input/Output

In slave mode, the Am79C978 controller drives the STOP signal to inform the bus master to stop the current transaction. In bus master mode, the Am79C978 controller checks STOP to determine if the target wants to disconnect the current transaction.

When RST is active, STOP is an input for NAND tree testing

TRDY

Target Ready Input/Output

TRDY indicates the ability of the target of the transaction to complete the current data phase. W ait states are inserted until both IRDY and TRDY are asserted simultaneously. A data phase is completed on any clock when both IRDY and TRDY are asserted.

When the Am79C978 controller is a bus master, it checks TRD Y during all read data phases to determine if valid data is present on AD[31:0]. During all write data phases, the device checks TRDY to determine if the target is ready to accept the data.

When the Am79C978 controller is the target of a transaction, it asserts TRD

Y during all read data phases to indicate that valid data is present on AD[31:0]. Dur ing all write data phases, the device asserts TRDY to indicate that it is ready to accept the data.

When RST is active, TRDY is an input for NAND tree testing

Magic Packet Interface PME

Power Management Event Output, Open Drain

PME is an output that can be used to indicate that a power management ev ent (a Magic Packet, an OnNow pattern match, or a change in link state) has been detected. The PME

pin is asserted when either

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1. The PME signal is asynchronous with respect to the

PCI clock. See the

Power Saving Mode

section for de-

tailed description.

Power Good Input

The PG pin has two functions: (1) it puts the de vice into Magic Packet mode, and (2) it blocks any resets when the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is set to 1, the device enters Magic Packet mode.

When PG is LOW, a LOW assertion of the PCI RST pin will only cause the PCI interface pins (except for PME) to be put in the high impedance state. The internal logic will ignore the assertion of RST.

When PG is HIGH, assertion of the PCI RST pin causes the controller logic to be reset and the conﬁguration information to be loaded from the EEPROM.

Note: PG input should be k ept high during NAND tree testing.

Board Interface

Note: Before programming the LED pins, see the

description of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED . By default, LED0 indicates an active link connection. This pin can also be programmed to indicate other network status (see BCR4). The LED0 pin polarity is programmable, but by default it is active LOW. When the LED0 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED0 pin polarity is pro-

Page 30

30 Am79C978

PRELIMINARY

grammed to active HIGH, the output is a totem pole driver.

Note: The LED0 pin is multiplexed with the EEDI pin.

LED1

LED1 Output

This output is designed to directly drive an LED . By default, LED1 indicates receive activity on the network. This pin can also be programmed to indicate other network status (see BCR5). The LED1 pin polarity is programmable, but by default, it is active LOW. When the LED1 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED1

pin polarity is programmed to active HIGH, the output is a totem pole driver.

Note: The LED1 pin is multiplexed with the EESK pin.

The LED1 pin is also used during EEPROM AutoDetection to determine whether or not an EEPROM is present at the Am79C978 controller interface. At the last rising edge of CLK while RST is active LOW, LED1 is sampled to determine the value of the EEDET bit in BCR19. It is important to maintain adequate hold time around the rising edge of the CLK at this time to ensure a correctly sampled value. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EEPROM is not present, and EEDET will be set to 0. See the

EEPROM Auto-Detection

section for more details.

If no LED circuit is to be attached to this pin, then a pullup or pull-down resistor must be attached instead in order to ground the EEDET setting.

WARNING: The input signal level of LED1 must be insured for correct EEPROM detection before the deassertion of RST.

LED2

LED2 Output

This output is designed to directly drive an LED. This pin can be programmed to indicate various network status (see BCR6). The LED2 pin polarity is programmable, but by default it is active LOW. When the LED2 pin polarity is programmed to active LOW, the output is an open drain driver . When the LED2 pin polarity is programmed to active HIGH, the output is a totem pole driver.

LED3

LED3 Output

This output is designed to directly drive an LED . By default, LED3 indicates transmit activity on the network. This pin can also be programmed to indicate other network status (see BCR7). The LED3 pin polarity is programmable, but by default it is active LOW. When the LED3 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED3 pin po-

larity is programmed to active HIGH, the output is a totem pole driver.

Special attention must be given to the external circuitry attached to this pin. When this pin is used to drive an LED while an EEPROM is used in the system, then buffering may be required between the LED3

pin and the LED circuit. If an LED circuit w ere directly attached to this pin, it may create an IOL requirement that could not be met by the serial EEPROM attached to this pin. If no EEPROM is included in the system design or low current LEDs are used, then the LED3

signal may be directly connected to an LED without buffering. For more details regarding LED connection, see the section on

LED Support

Note: The LED3 pin is multiple x ed with the EEDO pin.

LED4

LED4 Output

This output is designed to directly drive an LED. This pin can be programmed to indicate various network status (see BCR48). The LED4 pin polarity is programmable, but by default it is active LOW. When the LED4 pin polarity is programmed to active LOW, the output is an open drain driver . When the LED4 pin polarity is programmed to active HIGH, the output is a totem pole driver.

EEPROM Interface EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EECS is connected to the EEPROM’s chip select pin. It is controlled by either the Am79C978 controller during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 2.

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interf ace protocol. EEDI is connected to the EEPROM’s data input pin. It is controlled by either the Am79C978 controller during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0 pin.

EEDO

EEPROM Data Out Input

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interf ace protocol. EEDO is connected to the EEPROM’s data output pin. It is controlled by either the Am79C978

Page 31

Am79C978 31

PRELIMINARY

controller during command portions of a read of the entire EEPROM, or indirectly by the host system by reading from BCR19, bit 0.

Note: The EEDO pin is multiple x ed with the LED3 pin.

EESK

EEPROM Serial Clock Output

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interf ace protocol. EESK is connected to the EEPROM’s clock pin. It is controlled by either the Am79C978 controller directly during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1 pin.

The EESK pin is also used during EEPROM AutoDetection to determine whether or not an EEPROM is present at the Am79C978 controller interface. At the rising edge of the last CLK edge while RST is asserted, EESK is sampled to determine the value of the EEDET bit in BCR19. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EEPROM is not present, and EEDET will be set to 0. See the

EEPROM

Auto-Detection

section for more details.

If no LED circuit is to be attached to this pin, then a pullup or pull-down resistor must be attached instead to resolve the EEDET setting.

WARNING: The input signal level of EESK must be valid for correct EEPROM detection before the deassertion of RST.

MII Interface RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing reference for the transfer of the RX_DV, RXD[3:0], and RX_ER signals into the Am79C978 device. RX_CLK must provide a nibble rate clock (25% of the networ k data rate). Hence, when the Am79C978 de vice is operating at 10 Mbps, it provides an RX_CLK frequency of

2.5 MHz, and at 100 Mbps it provides an RX_CLK frequency of 25 MHz.

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII-compatible receive data bus. Data on RXD[3:0] is sampled on every rising edge of RX_CLK while RX_D V is asserted. RXD[3:0] is ignored while RX_DV is de-asserted.

RX_DV

Receive Data Valid Input

RX_DV is an input used to indicate that valid received data is being presented on the RXD[3:0] pins and

RX_CLK is synchronous to the receive data. In order for a frame to be fully received by the Am79C978 device, RX_D V must be asserted prior to the RX_CLK rising edge, when the ﬁrst nibble of the Start of Frame Delimiter is driven on RXD[3:0], and must remain asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV must then be deasserted prior to the RX_CLK rising edge which follows this ﬁnal nibble. RX_DV transitions are synchronous to RX_CLK rising edges.

CRS

Receive Carrier Sense Input

CRS is an input that indicates that a non-idle medium, due either to transmit or receive activity, has been detected.

COL

Collision Input

COL is an input that indicates that a collision has been detected on the network medium.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII transceiver device has detected a coding error in the receiv e data frame currently being transferred on the RXD[3:0] pins. If RX_ER is asserted while RX_DV is asserted, a CRC error will be indicated in the receive descriptor for the incoming receive frame. RX_ER is ignored while RX_DV is deasserted. Special code groups generated on RXD while RX_DV is deasserted are ignored (e.g., bad SSD in TX and idle in T4). RX_ER transitions are synchronous to RX_CLK.

TX_CLK

T ransmit Clock Input

TX_CLK is a clock input that provides the timing reference for the transfer of the TXD[3:0] and TX_ER signals into the Am79C978 device. TX_CLK must provide a nibble rate clock (25% of the network data rate). Hence, when the Am79C978 device is operating at 10 Mbps, it provides an TX_CLK frequency of 2.5 MHz, and at 100 Mbps it provides an RX_CLK frequency of 25 MHz.

TXD[3:0]

T ransmit Data Output

TXD[3:0] is the nibble-wide MII-compatible transmit data bus. Valid data is gener ated on TXD[3:0] on every rising edge of TX_CLK while TX_EN is asserted. While TX_EN is deasserted, TXD[3:0] values are driven to 0. TXD[3:0] transitions are synchronous to rising edges of TX_CLK.

Page 32

32 Am79C978

PRELIMINARY

TX_EN

T ransmit Enable Output

TX_EN indicates when the Am79C978 device is presenting valid transmit nibbles on the MII TXD[3:0] bus. While TX_EN is asserted, the Am79C978 device generates TXD[3:0] and TX_ER on TX_CLK rising edges. TX_EN is asserted with the ﬁrst nibble of preamble and remains asserted throughout the duration of the packet until it is deasserted prior to the ﬁrst TX_CLK following the ﬁnal nibble of the frame. TX_EN transitions are synchronous to TX_CLK.

MDC

Management Data Clock Output

MDC is the non-continuous clock output that provides a timing reference for bits on the MDIO pin. During MII management port operations, MDC runs at a nominal frequency of 2.5 MHz. When no management operations are in progress, MDC is driven LOW.

If the MII port is not selected, the MDC pin may be left ﬂoating.

MDIO

Management Data Input/Output Input/ Output

MDIO is a bidirectional MII management port data pin. MDIO is an output during the header portion of the management frame transfers and during the data portion of write operations. MDIO is an input during the data portion of read operations.

If a PHY is attached to the MII port via a MII physical connector then the MDIO pin should be externally pulled down to Vss with a 10 k Ω ±5% resistor. If a PHY is directly attached to the MII pins then the MDIO pin should be externally pulled up to Vcc with a 10 kΩ ±5% resistor.

IEEE 1149.1 (1990) T est Access P ort Interface

TCK

Test Clock Input

TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency of up to 10 MHz. TCK has an internal pull-up resistor.

TDI

Test Data In Input

TDI is the test data input path to the Am79C978 controller. The pin has an internal pull-up resistor.

TDO

Test Data Out Output

TDO is the test data output path from the Am79C978 controller. The pin is tri-stated when the JTAG port is inactive.

TMS

Test Mode Select Input

A serial input bit stream on the TMS pin is used to deﬁne the speciﬁc boundary scan test to be executed. The pin has an internal pull-up resistor.

Ethernet Network Interfaces TX±

Serial Transmit Data Output

These pins carry the transmit output data and are connected to the transmit side of the magnetics module.

RX±

Serial Receive Data Input

These pins accept the receive input data from the magnetics module.

IREF

Internal Current Reference Input

This pin serves as a current reference for the integr ated 1/10 PHY. It must be connected to VSS through a 12KΩ resistor (1%).

PHY_RST

PHY Reset Output

This output is used to reset the external PHY. This output eliminates the need for a fanout buffer on the PCI reset (RST) signal, provided polarity control for the speciﬁc PHY used, and prevents the resetting of the PHY when the PG input is LOW. The output polarity is determined by the RST_POL (CRS116, bit0).

HomePNA PHY Network Interface HRTXRXP/HRTXRXN

Serial Receive Data Input/Output

These pins accept the receive input data from the magnetics module and carry the transmit output data. A 100-Ω resistor should be placed between these pins.

Clock Interface XCLK/XTAL

External Clock/Crystal Select Input

When HIGH, an external 60-MHz clock source is selected bypassing the crystal circuit and clock trippler. When LOW, a 20-MHz cr ystal is used instead. The following table illustrates how this pin works.

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Am79C978 33

PRELIMINARY

Table 2. External Clock/Crystal Select

XTAL1

Crystal Oscillator In Input

The internal clock generator utilizes either a 20-MHz crystal that is attached to pins XTAL1 and XTAL2 or a 60-MHz clock source connected to XTAL1. This pin is not 5 V tolerant, and the 60 MHz clock source should be from a 3.3 V source, not a 5 V clock source.

XTAL2

Crystal Oscillator Out Output

The internal clock generator utilizes either a 20-MHz crystal that is attached to pins XTAL1 and XTAL2 or a 60-MHz clock source connected to XTAL1.

Power Supply VDDB

I/O Buffer Power (5 Pins) +3.3 V Power

These pins are the power supply pins that are used by the input/output buffer drivers. All VDDB pins must be connected to a +3.3 V supply.

VDD_PCI

PCI I/O Buffer Power (9 Pins) +3.3 V Power

These pins are the power supply pins that are used by the PCI input/output buffer drivers (e xcept PME driv er). All VDD_PCI pins must be connected to a +3.3 V supply.

VSSB

I/O Buffer Ground (15 Pins) Ground

These pins are the ground pins that are used by the input/output buffer drivers.

VDD

Digital Power (7 Pins) +3.3 V Power

These pins are the power supply pins that are used by the internal digital circuitry. All VDD pins must be connected to a +3.3 V supply.

VSS

Digital Ground (7 Pins) Ground

There are seven ground pins that are used b y the internal digital circuitry.

DVDDD

10BASE-T PDX Block Power +3.3 V Power

This pin supplies power to the 10 Mbps Transceiver block. It must be connected to a +3.3 V ±5% source. This pin requires careful decoupling to ensure proper device performance.

DVDDRX, DVDDTX

10BASE-T I/O Buffer Power +3.3 V Power

These pins supply power to the 10BASE-T input/output buffers. They must be connected to a +3.3 V ±5% source. These pins require careful decoupling to ensure proper device performance.

DVDDA

Analog PLL Power +3.3 V Power

This pin supplies power to the IREF current reference circuit and the 10BASE-T analog PLL. They must be connected to a +3.3 V ±5% source. These pins require careful decoupling to ensure proper device performance.

DVSSX, DVSSA

10BASE-T PDX Analog Ground Ground

These pins are the ground connection for the analog section within the Physical Data Transceiver (PDX) block.

DVSSD

10BASE-T PDX Digital Ground Ground

This pin is the ground connection for the digital logic within the PDX block.

VDDCO

Crystal +3.3 V Power

This pin supplies power to the crystal circuit.

VDDHR

HomePNA Digital Power +3.3 V Power

These pins are the digital power supply pins that are used by the internal digital circuitry for the HomePNA block. They must be connected to a +3.3 V source.

VSSHR

HomePNA Analog Ground Ground

This pin is the ground connection for the analog section within the HomePNA block.

DVDDA_HR

HomePNA Analog Power +3.3 V Power

This pin supplies power to the analog section of the HomePNA block. It must be connected to a +3.3 V ±5% source. This pin requires careful decoupling to ensure proper device performance.

Input Pin

Output

Pin XCLK/XTAL Clock Source

XTAL1 XTAL2 0 20-MHz Crystal

XTAL1 Don’t Care 1

60-MHz Oscillator/

External CLK

Source

Page 34

34 Am79C978

PRELIMINARY

BASIC FUNCTIONS System Bus Interface

The Am79C978 controller is designed to operate as a bus master during normal operations. Some slave I/O accesses to the Am79C978 controller are required in normal operations as well. Initialization of the Am79C978 controller is achieved through a combination of PCI Conﬁguration Space accesses, bus slave accesses, bus master accesses, and an optional read of a serial EEPROM that is performed by the Am79C978 controller. The EEPROM read operation is performed through the 93C46 EEPROM interface. The ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address may reside within the serial EEPROM. Some controller conﬁguration registers may also be programmed by the EEPROM read operation.

The Address PROM, on-chip board-conﬁguration registers, and the Ethernet controller registers occupy 32 bytes of address space. I/O and memor y mapped I/O accesses are supported. Base Address registers in the PCI conﬁguration space allow locating the address space on a wide variety of starting addresses.

Software Interface

The software interface to the Am79C978 controller is divided into three parts. One part is the PCI conﬁguration registers used to identify the Am79C978 controller and to setup the conﬁguration of the device. The setup information includes the I/O or memory mapped I/O base address, mapping of the Expansion ROM, and the routing of the Am79C978 controller interrupt channel. This allows for a jumperless implementation.

The second portion of the software interface is the direct access to the I/O resources of the Am79C978 controller. The Am79C978 controller occupies 32 bytes of address space that must begin on a 32-byte block boundary. The address space can be mapped into I/O or memory space (memory mapped I/O). The I/O Base Address Register in the PCI Conﬁguration Space controls the start address of the address space if it is mapped to I/O space. The Memory Mapped I/O Base Address Register controls the start address of the address space if it is mapped to memory space. The 32byte address space is used by the software to progr am the Am79C978 controller operating mode, to enable and disable various features, to monitor operating status, and to request particular functions to be executed by the Am79C978 controller.

The third portion of the software interface is the descriptor and buffer areas that are shared between the software and the Am79C978 controller during normal network operations. The descriptor area boundaries

are set by the software and do not change during normal network operations. There is one descriptor area for receive activity, and there is a separate area for transmit activity. The descriptor space contains relocatable pointers to the network frame data, and it is used to transfer frame status from the Am79C978 controller to the software. The b uff er areas are locations that hold frame data for transmission or that accept frame data that has been received.

Network Interfaces

The Am79C978 controller provides all of the PHY layer functions for 10 Mbps (10BASE-T) or 1 Mbps. The Am79C978 controller supports both half-duplex and full-duplex operation on the network MII interface.

Media Independent Interface

The Am79C978 controller fully supports the MII according to the IEEE 802.3 standard. This Reconciliation Sublay er interface allo ws a variety of PHYs (100BASETX, 100BASE-FX, 100BASE-T4, 100BASE-T2, 10BASE-T, etc.) to be attached to the Am79C978 device without future upgrade problems. The MII interface is a 4-bit (nibble) wide data path interface that runs at 25 MHz for 100-Mbps networks or 2.5 MHz for 10Mbps networks. The interface consists of two independent data paths, receive (RXD(3:0)) and transmit (TXD(3:0)), control signals for each data path (RX_ER, RX_DV, TX_EN), network status signals (COL, CRS), clocks (RX_CLK, TX_CLK) for each data path, and a two-wire management interface (MDC and MDIO). See Figure 1.

MII T ransmit Interface

The MII transmit clock is generated by the exter nal PHY and is sent to the Am79C978 controller on the TX_CLK input pin. The clock can run at 25 MHz or 2.5 MHz, depending on the speed of the network to which the external PHY is attached. The data is a nibble-wide (4 bits) data path, TXD(3:0), from the Am79C978 controller to the external PHY and is synchronous to the rising edge of TX_CLK. The transmit process starts when the Am79C978 controller asserts the TX_EN, which indicates to the external PHY that the data on TXD(3:0) is valid.

Normally, unrecoverable errors are signaled through the MII to the external PHY with the TX_ER output pin. The external PHY will respond to this error by generating a TX coding error on the current transmitted fr ame. The Am79C978 controller does not use this method of signaling errors on the transmit side. The Am79C978 controller will invert the FCS on the last byte generating an invalid FCS. The TX_ER pin should be tied to GND.

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Am79C978 35

PRELIMINARY

Figure 1. Media Independent Interface

MII Receive Interface

The MII receive clock is also generated b y the external PHY and is sent to the Am79C978 controller on the RX_CLK input pin. The clock will be the same frequency as the TX_CLK but will be out of phase and can run at 25 MHz or 2.5 MHz, depending on the speed of the network to which the external PHY is attached.

The RX_CLK is a continuous clock during the reception of the frame, but can be stopped f or up to two RX_CLK periods at the beginning and the end of frames, so that the external PHY can sync up to the network data trafﬁc necessary to recover the receive clock. During this time, the external PHY may switch to the TX_CLK to maintain a stable clock on the receive interface. The Am79C978 controller will handle this situation with no loss of data. The data is a nibble-wide (4 bits) data path, RXD(3:0), from the external PHY to the Am79C978 controller and is synchronous to the rising edge of RX_CLK.

The receive process starts when RX_DV is asserted. RX_DV will remain asserted until the end of the receive frame. The Am79C978 controller requires CRS (Carrier Sense) to toggle in between frames in order to receive them properly. Errors in the currently received frame are signaled across the MII by the RX_ER pin. RX_ER can be used to signal special conditions

out of band

when RX_DV is not asserted. Two deﬁned out-of-band conditions for this are the 100BASE-TX signaling of

bad

Start of Frame Delimiter and the 100BASE-T4 in-

dication of illegal code group before the receiver has

synched

to the incoming data. The Am79C978 control-

ler will not respond to these conditions. All

out of band

conditions are currently treated as NULL events. Certain

in band

non-IEEE 802.3u-compliant ﬂow control sequences may cause erratic behavior for the Am79C978 controller.

MII Network Status Interface

The MII also provides signals that are consistent and necessary for IEEE 802.3 and IEEE 802.3u operation. These signals are CRS (Carrier Sense) and COL (Collision Sense). Carrier Sense is used to detect non-idle activity on the network. Collision Sense is used to indicate that simultaneous transmission has occurred in a half-duplex network.

MII Management Interface

The MII provides a two-wire management interface so that the Am79C978 controller can control and receive status from external PHY devices.

The Network Port Manager copies the PHY AD after the Am79C978 controller reads the EEPROM and uses it to communicate with the external PHY. The PHY address must be programmed into the EEPROM prior to starting the Am79C978 controller. This is necessary so that the internal management controller can work autonomously from the software driver and can always know where to access the external PHY. The Am79C978 controller is unique by offering direct hardware support of the external PHY device without software support. The PHY address of 1Fh is reserved and should not be used. To access the external PHYs, the software driver must have knowledge of the external PHY’s address when multiple PHYs are present bef ore attempting to address it.

The MII Management Interface uses the MII Control, Address, and Data registers (BCR32, 33, 34) to control and communicate to the external PHYs. The Am79C978 controller generates MII management frames to the external PHY through the MDIO pin synchronous to the rising edge of the Management Data Clock (MDC) based on a combination of writes and reads to these registers.

RXD(3:0) RX_DV RX_ER RX_CLK

TXD(3:0) TX_EN

Am79C978

MII Interface

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

TX_CLK

MDIO

MDC

22206B-4

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36 Am79C978

PRELIMINARY

MII Management Frames

MII management frames are automatically generated by the Am79C978 controller and conform to the MII clause in the IEEE 802.3u standard.

The start of the frame is a preamble of 32 ones and guarantees that all of the external PHYs are synchronized on the same interface. See Figure 2. Loss of synchronization is possible due to the

hot-plugging

capability of the exposed MII.

The IEEE 802.3 speciﬁcation allows you to drop the preamble, if after reading the MII Status Register from the external PHY you can determine that the external PHY will support Preamble Suppression (BCR34, bit

6). After having a valid MII Status Register read, the Am79C978 controller will then drop the creation of the preamble stream until a reset occurs, receives a read error, or the external PHY is disconnected.

Figure 2. Frame Format at the MII Interface Connection

This is followed by a start ﬁeld (ST) and an operation ﬁeld (OP). The operation ﬁeld (OP) indicates whether the Am79C978 controller is initiating a read or write operation. This is followed by the external PHY address (PHYAD) and the register address (REGAD) programmed in BCR33. The PHY address of 1Fh is reserved and should not be used. The external PHY may have a larger address space starting at 10h - 1Fh. This is the address range set aside by the IEEE as vendor usable address space and will vary from vendor to vendor. This ﬁeld is f ollow ed by a b us turnaround ﬁeld. During a read operation, the bus turnaround ﬁeld is used to determine if the external PHY is responding correctly to the read request or not. The Am79C978 controller will tri-state the MDIO for both MDC cycles.

During the second cycle, if the external PHY is synchronized to the Am79C978 controller, the exter nal PHY will drive a 0. If the external PHY does not drive a 0, the Am79C978 controller will signal a MREINT (CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set to a 1, indicating the Am79C978 controller had an MII management frame read error and that the data in BCR34 is not valid. The data ﬁeld to/from the external PHY is read or written into the BCR34 register. The last ﬁeld is an IDLE ﬁeld that is necessary to give ample time for drivers to turn off before the next access. The Am79C978 controller will drive the MDC to 0 and tristate the MDIO anytime the MII Management Port is not active.

To help to speed up the reading and of writing the MII management frames to the external PHY, the MDC can be sped up to 10 MHz by setting the FMDC bits in BCR32. The IEEE 802.3 speciﬁcation requires use of

the 2.5-MHz clock rate, but 5 MHz and 10 MHz are available for the user. The intended applications are that the 10-MHz clock rate can be used for a single external PHY on an adapter card or motherboard. The 5MHz clock rate can be used for an exposed MII with one external PHY attached. The 2.5-MHz clock rate is intended to be used when multiple external PHYs are connected to the MII Management Port or if compliance to the IEEE 802.3u standard is required.

Auto-Poll External PHY Status Polling

As deﬁned in the IEEE 802.3 standard, the external PHY attached to the Am79C978 controller’s MII has no way of communicating important timely status information back to Am79C978 controller. The Am79C978 controller has no way of knowing that an e xternal PHY has undergone a change in status without polling the MII status register. To prevent prob lems from occurring with inadequate host or software polling, the Am79C978 controller will Auto-Poll when APEP (BCR32, bit 11) is set to 1 to insure that the most current information is available . See

10BASE-T PHY Management Registers

for the bit descriptions of the MII Status Register. The contents of the latest read from the external PHY will be stored in a shadow register in the Auto-Poll block. The ﬁrst read of the MII Status Register will just be stored, but subsequent reads will be compared to the contents already stored in the shadow register. If there has been a change in the contents of the MII Status Register, a MAPINT (CSR7, bit 5) interrupt will be generated on INT

A if the MAPINTE (CSR7, bit 4) is set to 1. The A utoPoll features can be disabled if software driver polling is required.

Preamble

1111....1111

OP 10 Rd 01 Wr

PHY

Address

TA Z0 Rd 10 Wr

Data

Bits

ST 01

Bits

Bit

Idle

22206B-5

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Am79C978 37

PRELIMINARY

The Auto-Poll’s frequency of generating MII management frames can be adjusted by setting of the APDW bits (BCR32, bits 10-8). The dela y can be adjusted from 0 MDC periods to 2048 MDC periods. Auto-Poll by default will only read the MII Status register in the external PHY.

Network Port Manager

If the external PHY is present and is active, the Network Port Manager will request status from the external PHY by generating MII management frames. These frames will be sent roughly every 900 ms. These frames are necessary so that the Network Port Manager can monitor the current active link and can select a different network port if the current link goes down.

10BASE-T PHY

The 10BASE-T transceiver incorporates the physical layer function, including both clock recovery (ENDEC) and transceiver function. Data transmission over the 10BASE-T medium requires an integrated 10BASE-T MAU. The transceiver will meet the electr ical requirements for 10BASE-T as speciﬁed in IEEE 802.3i. The transmit signal is ﬁltered on the transceiver to reduce harmonic content per IEEE 802.3i. Since ﬁltering is performed in silicon, external ﬁltering modules are not needed. The 10BASE-T PHY transceiver receives 10 Mbps data from the MAC across the internal MII at 2.5 million nibbles per second (parallel), or 10 million bits per second (serial) for 10BASE-T. It then Manchester encodes the data before transmission to the network.

The RX+ pins are differential twisted-pair receivers. When properly terminated, each receiver will meet the electrical requirements for 10BASE-T as speciﬁed in IEEE 802.3i. Each receiver has inter nal ﬁltering and does not require external ﬁlter modules. The 10BASE-T PHY transceiver receives a Manchester coded 10BASE-T data stream from the medium. It then recovers the clock and decodes the data. The data stream is presented at the internal MII interface in either parallel or serial format.

PCI and JTAG Conﬁguration Information

The PCI device ID and software conﬁguration information is as follows in Table 3 and Table 4.

Table 3. PCI Device ID

Table 4. PCI Software Conﬁguration

Slave Bus Interface Unit

The slave Bus Interface Unit (BIU) controls all accesses to the PCI conﬁguration space, the Control and Status Registers (CSR), the Bus Conﬁguration Registers (BCR), the Address PROM (APROM) locations, and the Expansion ROM. Table 5 shows the response of the Am79C978 controller to each of the PCI commands in slave mode.

Table 5. Slave Commands

Slave Conﬁguration Transfers

The host can access the PCI conﬁguration space with a conﬁguration read or write command. The Am79C978 controller will assert DEVSEL during the address phase when IDSEL is asserted, AD[1:0] are both 0, and the access is a conﬁguration cycle. AD[7:2] select the DWord location in the conﬁguration space. The Am79C978 controller ignores AD[10:8], because it

Vendor ID Device ID Rev ID (offset 0x08)

1022 2001 50

CSR89 CSR88 JTAG

00000262h 00006003h 0262 6003h

C[3:0] Command Use

0000

Interrupt Acknowledge

Not used

0001 Special Cycle Not used

0010 I/O Read

Read of CSR, BCR, APROM, and Reset registers

0011 I/O Write

Write to CSR, BCR, and

APROM 0100 Reserved 0101 Reserved

0110 Memory Read

Memory mapped I/O read of

CSR, BCR, APROM, and

Reset registers. Read of the

Expansion Bus

0111 Memory Write

Memory mapped I/O write of

CSR, BCR, and APROM 1000 Reserved 1001 Reserved

1010

Conﬁguration Read

Read of the Conﬁguration

Space

1011

Conﬁguration Write

Write to the Conﬁguration

Space

1100

Memory Read Multiple

Aliased to Memory Read

1101

Dual Address Cycle

Not used

1110

Memory Read Line

Aliased to Memory Read

1111

Memory Write Invalidate

Aliased to Memory Write

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38 Am79C978

PRELIMINARY

is a single function device. AD[31:11] are “don't cares.” See Table 6.

Table 6. Slave Conﬁguration Transfers

The active bytes within a D W ord are determined by the byte enable signals. Eight-bit, 16-bit, and 32-bit transfers are supported. DEVSEL is asserted two clock cycles after the host has asserted FRAME

. All conﬁguration cycles are of ﬁxed length. The Am79C978 controller will assert TRDY on the third clock of the data phase.

The Am79C978 controller does not support burst transfers for access to conﬁguration space. When the host keeps FRAME

asserted for a second data phase, the

Am79C978 controller will disconnect the transfer. When the host tries to access the PCI conﬁguration

space while the automatic read of the EEPROM after H_RESET (see section on RESET) is on-going, the Am79C978 controller will terminate the access on the PCI bus with a disconnect/retry response.

The Am79C978 controller supports fast back-to-back transactions to different targets. This is indicated by the Fast Bac k-To-Back Capable bit (PCI Status register, bit

7), which is hardwired to 1. The Am79C978 controller is capable of detecting a conﬁguration cycle ev en when its address phase immediately follows the data phase of a transaction to a different target without any idle state in-between. There will be no contention on the DEVSEL, TRDY, and STOP signals, since the Am79C978 controller asserts DEVSEL on the second clock after FRAME is asserted (medium timing).

Slave I/O Transfers

After the Am79C978 controller is conﬁgured as an I/O device by setting IOEN (for regular I/O mode) or MEMEN (for memory mapped I/O mode) in the PCI Command register, it starts monitoring the PCI bus for access to its CSR, BCR, or EEPROM locations. If conﬁgured for regular I/O mode, the Am79C978 controller will look for an address that falls within its 32 b ytes of I/ O address space (starting from the I/O base address).

The Am79C978 controller asserts DEVSEL

if it detects an address match and the access is an I/O cycle. If conﬁgured for memory mapped I/O mode, the Am79C978 controller will look for an address that falls within its 32 bytes of memory address space (starting from the memory mapped I/O base address). The Am79C978 controller asserts DEVSEL if it detects an address match and the access is a memory cycle. DEVSEL is asserted two clock cycles after the host has asserted FRAME. See Figure 3 and Figure 4.

The Am79C978 controller will not assert DEVSEL

if it detects an address match and the PCI command is not of the correct type. In memory mapped I/O mode, the Am79C978 controller aliases all accesses to the I/O resources of the command types

Memory Read Multiple

and

Memory Read Line

to the basic Memory Read com-

mand. All accesses of the type

Memory Write and In-

validate

are aliased to the basic Memory Write command. Eight-bit, 16-bit, and 32-bit non-burst transactions are supported. The Am79C978 controller decodes all 32 address lines to determine which I/O resource is accessed.

The typical number of wait states added to a slave I/O or memory mapped I/O read or write access on the part of the Am79C978 controller is six to seven cloc k cycles, depending upon the relative phases of the internal Buffer Management Unit clock and the CLK signal, since the internal Buffer Management Unit clock is a divideby-two version of the CLK signal.

The Am79C978 controller does not support burst transfers for access to its I/O resources . When the host keeps FRAME asserted for a second data phase, the Am79C978 controller will disconnect the transfer.

The Am79C978 controller supports fast back-to-back transactions to different targets. This is indicated by the Fast Bac k-To-Back Capable bit (PCI Status register, bit

7), which is hardwired to 1. The Am79C978 controller is capable of detecting an I/O or a memory-mapped I/ O cycle even when its address phase immediately follows the data phase of a transaction to a different target, without any idle state in-between. There will be no contention on the DEVSEL, TRD Y, and STOP signals, since the Am79C978 controller asserts DEVSEL on the second clock after FRAME is asserted (medium timing). See Figure 5 and Figure 6.

AD31 AD11

AD10

AD8

AD7 AD2 AD1 AD0

Don't care Don't care

DWord

Index

Page 39

Am79C978 39

PRELIMINARY

Figure 3. Slave Conﬁguration Read

Figure 4. Slave Conﬁguration Write

Figure 5. Slave Read Using I/O Command

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1010

PAR

PAR PAR

DEVSEL is sampled

DATA

ADDR

22206B-6

22206B-7

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1011

PAR

DATA

ADDR

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0010

PAR

1 2345678

109

DATA

PAR

22206B-8

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40 Am79C978

PRELIMINARY

Figure 6. Slave Write Using Memory Command

Expansion ROM Transfers

The host must initialize the Expansion ROM Base Address register at offset 30H in the PCI conﬁguration space with a valid address before enabling access to the device. The Am79C978 controller will not react to any access to the Expansion ROM until both MEMEN (PCI Command register, bit 1) and ROMEN (PCI Expansion ROM Base Address register , bit 0) are set to 1. After the Expansion ROM is enabled, the Am79C978 controller will assert DEVSEL

on all memory read accesses with an address between ROMBASE and ROMBASE + 1M - 4. The Am79C978 controller aliases all accesses to the Expansion ROM of the command types

Memory Read Multiple

and

Memory Read Line

to the basic Memory Read command. Eight-bit, 16-bit, and 32-bit read transfers are supported.

Since setting MEMEN also enables memory mapped access to the I/O resources, attention must be given the PCI Memory Mapped I/O Base Address register before enabling access to the Expansion ROM. The host must set the PCI Memory Mapped I/O Base Address register to a value that prevents the Am79C978 controller from claiming any memory cycles not intended for it.

The Am79C978 controller will always read four bytes for every host Expansion ROM read access. TRDY will not be asserted until all four bytes are loaded into an internal scratch register. The cycle TRDY is asserted depends on the programming of the Expansion ROM interface timing. Figure 7 assumes that ROMTMG (BCR18, bits 15-12) is at its default value.

Note: The Expansion R OM should be read only during PCI conﬁguration time for the PCI system.

When the host tries to write to the Expansion ROM, the Am79C978 controller will claim the cycle by asserting DEVSEL. TRDY will be asserted one clock cycle later. The write operation will have no eff ect. Writes to the Expansion ROM are done through the BCR30 Expansion Bus Data Port. See the section on the

Expansion Bus

Interface

for more details.

During the boot procedure, the system will try to ﬁnd an Expansion ROM. A PCI system assumes that an Expansion ROM is present when it reads the ROM signature 55H (byte 0) and AAH (byte 1).

Slave Cycle Termination

There are three scenarios besides normal completion of a transaction where the Am79C978 controller is the target of a slave cycle and it will terminate the access.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0111

PAR

1 2345678

109

DATA

PAR

22206B-9

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Am79C978 41

PRELIMINARY

Figure 7. Expansion ROM Read

Disconnect When Busy

The Am79C978 controller cannot service any slave access while it is reading the contents of the EEPROM. Simultaneous access is not allowed in order to avoid conﬂicts, since the EEPROM is used to initialize some of the PCI conﬁguration space locations and most of the BCRs and CSR116. The EEPROM read operation will always happen automatically after the deassertion of the RST

pin. In addition, the host can start the read operation by setting the PREAD bit (BCR19, bit 14). While the EEPROM read is on-going, the Am79C978 controller will disconnect any slave access where it is the target by asserting STOP together with DEVSEL, while driving TRDY high. STOP will stay asserted until the end of the cycle.

Note that I/O and memory slave accesses will only be disconnected if they are enabled by setting the IOEN or MEMEN bit in the PCI Command register. Without the enable bit set, the cycles will not be claimed at all. Since H_RESET clears the IOEN and MEMEN bits for the automatic EEPROM read after H_RESET, the disconnect only applies to conﬁguration cycles.

A second situation where the Am79C978 controller will generate a PCI disconnect/retry cycle is when the host tries to access any of the I/O resources right after hav-

ing read the Reset register. Since the access generates an internal reset pulse of about 1 ms in length, all further slave accesses will be deferred until the internal reset operation is completed. See Figure 8.

Disconnect Of Burst Transfer

The Am79C978 controller does not support burst access to the conﬁguration space, the I/O resources, or to the Expansion Bus. The host indicates a burst transaction by keeping FRAME asserted during the data phase. When the Am79C978 controller sees FRAME and IRDY asserted in the clock cycle before it wants to assert TRD Y, it also asserts STOP at the same time. The transfer of the ﬁrst data phase is still successful, since IRDY and TRDY are both asserted. See Figure 9.

If the host is not yet ready when the Am79C978 controller asserts TRDY, the device will wait for the host to assert IRDY. When the host asserts IRDY and FRAME is still asserted, the Am79C978 controller will ﬁnish the ﬁrst data phase by deasserting TRDY one clock later. At the same time, it will assert STOP to signal a disconnect to the host. STOP will stay asserted until the host removes FRAME. See Figure 10.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

CMD

PAR

1 2345 484950

DATA

PAR

DEVSEL is sampled

22206B-10

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42 Am79C978

PRELIMINARY

Figure 8. Disconnect of Slave Cycle When Busy

Figure 9. Disconnect of Slave Burst Transfer - No

Host Wait States

Figure 10. Disconnect of Slave Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am79C978 controller is not the current bus master, it samples the AD[31:0], C/BE[3:0], and the PAR lines during the address phase of any PCI command for a parity error. When it detects an address parity error, the Am79C978 controller sets PERR (PCI Status register, bit 15) to 1. When reporting of that error is enabled by setting SERREN (PCI Command register, bit 8) and PERREN (PCI Command register, bit 6) to 1, the Am79C978 controller also drives the SERR signal low for one clock cycle and sets SERR (PCI Status register, bit 14) to 1. The assertion of SERR follows the address phase by two clock cycles. The Am79C978 controller will not assert DEVSEL for a PCI transaction that has an address parity error when PERREN and SERREN are set to 1. See Figure 11.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

CMD

PAR

PAR PAR

DATA

ADDR

22206B-11

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

PAR

DATA

1st DATA

22206B-12

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 23456

PAR

DATA

1st DATA

22206B-13

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Am79C978 43

PRELIMINARY

Figure 11. Address Parity Error Response

During the data phase of an I/O write, memory-mapped I/O write, or conﬁguration write command that selects the Am79C978 controller as target, the device samples the AD[31:0] and C/BE[3:0] lines for parity on the clock edge, and data is transferred as indicated b y the assertion of IRD Y and TRDY. P AR is sampled in the f ollowing clock cycle. If a parity error is detected and reporting of that error is enabled by setting PERREN (PCI Command register, bit 6) to 1, PERR is asserted one clock later. The parity error will always set PERR (PCI Status register, bit 15) to 1 even when PERREN is cleared to

0. The Am79C978 controller will ﬁnish a transaction that has a data parity error in the normal way by asserting TRD

Y. The corrupted data will be wr itten to the ad-

dressed location. Figure 12 shows a transaction that suffered a parity

error at the time data was transferred (clock 7, IRDY and TRDY are both asser ted). PERR is driven high at the beginning of the data phase and then drops low due to the parity error on clock 9, two clock cycles after the data was transferred. After PERR is driven low, the Am79C978 controller drives PERR high for one clock cycle, since PERR is a sustained tri-state signal.

Figure 12. Slave Cycle Data Parity Error Response

FRAME

CLK

SERR

C/BE

DEVSEL

1 2345

PAR

ADDR

1st DATA

CMD

PAR

22206B-14

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

1 2345678

109

DATA

PAR

PERR

22206B-15

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44 Am79C978

PRELIMINARY

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Am79C978 45

PRELIMINARY

Am79C978 controller supports zero wait state read cycles. It asserts IRDY immediately after the address phase and at the same time starts sampling DEVSEL. Figure 14 shows two non-burst read transactions. The ﬁrst transaction has zero wait states. In the second transaction, the target extends the cycle by asserting TRDY one clock later.

Basic Burst Read Transfer

The Am79C978 controller supports burst mode for all bus master read operations. The burst mode must be enabled by setting BREADE (BCR18, bit 6). To allow burst transfers in descriptor read operations, the Am79C978 controller must also be programmed to use SWSTYLE 3 (BCR20, bits 7-0). All b urst read accesses to the initialization block and descriptor ring are of the PCI command type Memory Read (type 6). Burst read accesses to the transmit buffer typically are longer than two data phases. When MEMCMD (BCR18, bit 9) is cleared to 0, all burst read accesses to the transmit buffer are of the PCI command type Memory Read Line (type 14). When MEMCMD (BCR18, bit 9) is set to 1, all burst read accesses to the transmit buff er are of the PCI command type Memory Read Multiple (type 12).

AD[1:0] will both be 0 during the address phase indicating a linear burst order. Note that during a burst read operation, all byte lanes will always be active. The Am79C978 controller will internally discard unneeded bytes.

The Am79C978 controller will always perform only a single burst read transaction per bus mastership period, where

transaction

is deﬁned as one address phase and one or multiple data phases. The Am79C978 controller supports zero wait state read cycles. It asserts IRD

Y immediately after the address phase and at the same time starts sampling DEVSEL. FRAME is deasserted when the next to last data phase is completed.

Figure 15 shows a typical burst read access. The Am79C978 controller arbitrates for the bus, is granted access, reads three 32-bit words (DW ord) from the system memory, and then releases the bus. In the example, the memory system extends the data phase of each access by one wait state. The example assumes that EXTREQ (BCR18, bit 8) is cleared to 0, therefore, REQ is deasserted in the same cycle as FRAME is asserted.

Figure 14. Non-Burst Read Transfer

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0110

PAR

1 2345678

109

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46 Am79C978

PRELIMINARY

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Am79C978 47

PRELIMINARY

Figure 16. Non-Burst Write Transfer

Figure 17 shows a typical burst write access. The Am79C978 controller arbitrates for the bus, is granted access, and writes four 32-bit words (DWords) to the system memory and then releases the bus. In this example, the memory system extends the data phase of the ﬁrst access by one wait state. The following three data phases take one clock cycle each, which is determined by the timing of TRD

Y. The example assumes that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ is not deasserted until the next to last data phase is ﬁnished.

Target Initiated Termination

When the Am79C978 controller is a bus master , the cycles it produces on the PCI bus may be terminated by the target in one of three different ways: disconnect

with data transfer , disconnect without data transf er, and target abort.

Disconnect With Data T ransfer

Figure 18 shows a disconnection in which one last data transfer occurs after the target asserted STOP. ST OP is asserted on clock 4 to start the ter mination sequence. Data is still transferred during this cycle, since both IRDY and TRDY are asser ted. The Am79C978 controller terminates the current transfer with the deassertion of FRAME on clock 5 and of IRDY one clock later. It ﬁnally releases the bus on clock 7. If it wants to transfer more data, the Am79C978 controller will again request the bus after two clock cycles. The starting address of the new transfer will be the address of the ne xt non-transferred data.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 2345678

109

DATA

ADDR

DATA

PAR

0111

22206B-19

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48 Am79C978

PRELIMINARY

Figure 17. Burst Write Transfer (EXTREQ = 1)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

12345678

ADDR

DATA

DATA DATA

0111

PAR

PAR PAR

DATA

PAR

DEVSEL is sampled

22206B-20

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Am79C978 49

PRELIMINARY

Figure 18. Disconnect With Data Transfer

Disconnect Without Data T ransfer

Figure 19 shows a target disconnect sequence during which no data is transferred. ST OP is asserted on clock 4 without TRDY being asserted at the same time. The Am79C978 controller terminates the access with the deassertion of FRAME on clock 5 and of IRDY one clock cycle later. It ﬁnally releases the bus on clock 7. The Am79C978 controller will again request the bus after two clock cycles to retry the last transfer. The starting address of the new transfer will be the address of the last non-transferred data.

Target Abort

Figure 20 shows a target abort sequence. The target asserts DEVSEL for one clock. It then deasserts DEVSEL and asserts STOP on clock 4. A target can use the target abort sequence to indicate that it cannot service the data transfer and that it does not want the transaction to be retried. Additionally, the Am79C978 controller cannot make any assumption

about the success of the previous data transf ers in the current transaction. The Am79C978 controller terminates the current transfer with the deassertion of FRAME on clock 5 and of IRDY one clock cycle later. It ﬁnally releases the bus on clock 6.

Since data integrity is not guaranteed, the Am79C978 controller cannot recover from a target abort event. TheAm79C978 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI conﬁguration registers will not be cleared. Any on-going network transmission is terminated in an orderly sequence. If less than 512 bits have been transmitted onto the network, the transmission will be terminated immediately, generating a runt packet. If 512 bits or more have been transmitted, the message will ha ve the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is detected at the receiving station.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

00000111

PAR

0111

23456789

PAR

DATA

STOP

ADDRi+8

DATA

22206B-21

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50 Am79C978

PRELIMINARY

Figure 19. Disconnect Without Data Transfer

RTABORT (PCI Status register, bit 12) will be set to indicate that the Am79C978 controller has received a target abort. In addition, SINT (CSR5, bit 11) will be set to 1. When SINT is set, INT

A is asserted if the enable bit SINTE (CSR5, bit 10) is set to 1. This mechanism can be used to inform the driver of the system error. The host can read the PCI Status register to determine the exact cause of the interrupt.

Master Initiated Termination

There are three scenarios besides normal completion of a transaction where the Am79C978 controller will terminate the cycles it produces on the PCI bus.

Preemption During Non-Burst Transaction

When the Am79C978 controller performs multiple nonburst transactions, it keeps REQ asserted until the assertion of FRAME for the last transaction. When GNT is removed, the Am79C978 controller will ﬁnish the current transaction and then release the bus. If it is not the

last transaction, REQ

will remain asserted to regain

bus ownership as soon as possible. See Figure 21.

Preemption During Burst Transaction

When the Am79C978 controller operates in burst mode, it only performs a single transaction per bus mastership period, where

transaction

is deﬁned as one address phase and one or multiple data phases. The central arbiter can remove GNT at any time during the transaction. TheAm79C978 controller will ignore the deassertion of GNT

and continue with data transfers, as long as the PCI Latency Timer is not expired. When the Latency Timer is 0 and GNT is deasserted, the Am79C978 controller will ﬁnish the current data phase, deassert FRAME, ﬁnish the last data phase, and release the bus. If EXTREQ (BCR18, bit 8) is cleared to 0, it will immediately assert REQ to regain bus ownership as soon as possible. If EXTREQ is set to 1, REQ will stay asserted.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

STOP

ADDR

00000111

PAR

0111

23456789

ADDR

DATA

PAR

22206B-22

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Am79C978 51

PRELIMINARY

Figure 20. Target Abort

When the preemption occurs after the counter has counted down to 0, the Am79C978 controller will ﬁnish the current data phase, deassert FRAME, ﬁnish the last data phase, and release the bus. Note that it is important for the host to program the PCI Latency Timer according to the bus bandwidth requirement of the Am79C978 controller. The host can determine this bus bandwidth requirement by reading the PCI MAX_LAT and MIN_GNT registers.

Figure 22 assumes that the PCI Latency Timer has counted down to 0 on clock 7.

Master Abort

TheAm79C978 controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asser ted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the Am79C978 controller.

TheAm79C978 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI conﬁguration registers will not be cleared. Any on-going network transmission is terminated in an orderly sequence. If less than 512 bits have been transmitted onto the network, the transmission will be terminated immediately, generating a runt packet. If 512 bits or more have been transmitted, the message will ha ve the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is detected at the receiving station.

RMABORT (in the PCI Status register , bit 13) will be set to indicate that the Am79C978 controller has terminated its transaction with a master abort. In addition, SINT (CSR5, bit 11) will be set to 1. When SINT is set, INT

Parity Error Response

During every data phase of a DMA read operation, when the target indicates that the data is valid by asserting TRDY, the Am79C978 controller samples the AD[31:0], C/BE[3:0], and the PAR lines for a data parity error. When it detects a data parity error, the Am79C978 controller sets PERR (PCI Status register, bit 15) to 1. When repor ting of that error is enabled by setting PERREN (PCI Command register, bit 6) to 1, the Am79C978 controller also drives the PERR signal low and sets DATAPERR (PCI Status register, bit 8) to

1. The asser tion of PERR follows the corrupted data/ byte enables by tw o clock cycles and PAR by one clock cycle.

Figure 24 shows a transaction that has a parity error in the data phase. TheAm79C978 controller asserts PERR on clock 8, two clock cycles after data is valid. The data on clock 5 is not checked for par ity, because on a read access, PAR is only required to be valid one clock after the target has asserted TRDY. TheAm79C978 controller then drives PERR high for one clock cycle, since PERR is a sustained tri-state signal.

During every data phase of a DMA write operation, the Am79C978 controller checks the PERR input to see if the target reports a parity error. When it sees the PERR input asserted, the Am79C978 controller sets PERR (PCI Status register, bit 15) to 1. When PERREN (PCI Command register, bit 6) is set to 1, the Am79C978 controller also sets DATAPERR (PCI Status register, bit

8) to 1.

Page 52

52 Am79C978

PRELIMINARY

Figure 21. Preemption During Non-Burst Transaction

Figure 22. Preemption During Burst Transaction

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

BE0111

PAR

DEVSEL is sampled

PAR

DATA

ADDR

22206B-24

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

BE0111

PAR

1 234

DATA

PAR

REQ

DATA

PAR PAR PAR

PAR

GNT

22206B-25

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Am79C978 53

PRELIMINARY

Figure 23. Master Abort

Figure 24. Master Cycle Data Parity Error Response

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

Page 54

54 Am79C978

PRELIMINARY

Whenever the Am79C978 controller is the current bus master and a data parity error occurs, SINT (CSR5, bit

11) will be set to 1. When SINT is set, INT A is asserted if the enable bit SINTE (CSR5, bit 10) is set to 1. This mechanism can be used to inform the driver of the system error. The host can read the PCI Status register to determine the exact cause of the interrupt. The setting of SINT due to a data parity error is not dependent on the setting of PERREN (PCI Command register, bit 6).

By default, a data parity error does not affect the state of the MAC engine. TheAm79C978 controller treats the data in all bus master transfers that have a parity error as if nothing has happened. All netw ork activity continues.

Advanced Parity Error Handling

For all DMA cycles, the Am79C978 controller provides a second, more advanced lev el of parity error handling. This mode is enabled by setting APERREN (BCR20, bit

10) to 1. When APERREN is set to 1, the BPE bits (RMD1 and TMD1, bit 23) are used to indicate parity error in data transfers to the receive and transmit buffers. Note that since the advanced parity error handling uses an additional bit in the descriptor, SWSTYLE (BCR20, bits 7-0) must be set to 2 or 3 to program the Am79C978 controller to use 32-bit software structures. TheAm79C978 controller will react in the following wa y when a data parity error occurs:

■ Initialization block read: STOP (CSR0, bit 2) is set to 1 and causes a STOP_RESET of the device.

■ Descriptor ring read: Any on-going network activity is terminated in an orderly sequence and then STOP (CSR0, bit 2) is set to 1 to cause a STOP_RESET of the device.

■ Descriptor ring write: Any on-going network activity is terminated in an orderly sequence and then STOP (CSR0, bit 2) is set to 1 to cause a STOP_RESET of the device.

■ Transmit buffer read: BPE (TMD1, bit 23) is set in the current transmit descriptor. Any on-going network transmission is terminated in an orderly sequence.

■ Receive buffer write: BPE (RMD1, bit 23) is set in the last receive descriptor associated with the frame.

Terminating on-going network transmission in an orderly sequence means that if less than 512 bits have been transmitted onto the network, the transmission

will be terminated immediately, generating a runt packet.

If 512 bits or more have been transmitted, the message will have the current FCS inv erted and appended at the next byte boundary to guarantee an FCS error is detected at the receiving station.

APERREN does not affect the reporting of address parity errors or data parity errors that occur when the Am79C978 controller is the target of the transfer.

Initialization Block DMA Transfers

During execution of the Am79C978 controller bus master initialization procedure, the microcode will repeatedly request DMA transfers from the BIU. During each of these initialization block DMA transfers, the BIU will perform two data transfer cycles reading one DWord per transfer and then it will relinquish the bus. When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the initialization block is organized as 32-bit software structures), there are seven D W ords to transfer during the bus master initialization procedure, so four bus mastership periods are needed in order to complete the initialization sequence. Note that the last DWord transfer of the last bus mastership period of the initialization sequence accesses an unneeded location. Data from this tr ansfer is discarded internally. When SSIZE32 is cleared to 0 (i.e., the initialization block is organized as 16-bit software structures), then three bus mastership periods are needed to complete the initialization sequence.

The Am79C978 device supports two transfer modes f or reading the initialization block: non-burst and burst mode, with burst mode being the preferred mode when the Am79C978 controller is used in a PCI bus application. See Figure 25 and Figure 26.

When BREADE is cleared to 0 (BCR18, bit 6), all initialization block read transfers will be executed in nonburst mode. There is a new address phase for every data phase. FRAME

will be dropped between the two transfers. The two phases within a bus mastership period will have addresses of ascending contiguous order.

When BREADE is set to 1 (BCR18, bit 6), all initialization block read transf ers will be ex ecuted in burst mode. AD[1:0] will be 0 during the address phase indicating a linear burst order.

Page 55

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PRELIMINARY

Figure 25. Initialization Block Read In Non-Burst Mode

Figure 26. Initialization Block Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

IADD

00000110

PAR

DATA

IADDi+4

0000

0110

PAR

1 2345678

109

22206B-28

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000110

PAR

PAR PAR

PAR

DEVSEL is sampled

DATA DATA

IADD

22206B-29

Page 56

56 Am79C978

PRELIMINARY

Descriptor DMA Transfers

The Am79C978 microcode will determine when a descriptor access is required. A descriptor DMA read will consist of two data transfers. A descriptor DMA write will consist of one or two data transfers. The descriptor DMA transfers within a single bus mastership period will always be of the same type (either all read or all write).

During descriptor read accesses, the byte enable signals will indicate that all byte lanes are active. Should some of the bytes not be needed, then the Am79C978 controller will internally discard the extraneous information that was gathered during such a read.

The settings of SWSTYLE (BCR20, bits 7-0) and BREADE (BCR18, bit 6) affect the wa y the Am79C978 controller performs descriptor read operations.

When SWSTYLE is set to 0 or 2, all descriptor read operations are performed in non-burst mode. The setting of BREADE has no effect in this conﬁguration. See Figure 27.

When SWSTYLE is set to 3, the descriptor entries are ordered to allow burst transfers. TheAm79C978 controller will perform all descriptor read operations in burst mode, if BREADE is set to 1. See Figure 28.

Table 8 shows the descriptor read sequence. During descriptor write accesses, only the byte lanes

which need to be written are enabled. If buffer chaining is used, accesses to the descriptors

of all intermediate buffers consist of only one data transfer to return ownership of the buff er to the system. When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e., the descriptor entries are organized as 16-bit software structures), the descriptor access will write a single byte. When SWSTYLE (BCR20, bits 7-0) is set to 2 or 3 (i.e., the descriptor entries are organized as 32-bit software structures), the descriptor access will write a single word. On all single buffer transmit or receive descriptors, as well as on the last buffer in chain, writes to the descriptor consist of two data transfers.

The ﬁrst data transfer writes a DW ord containing status information. The second data transfer writes a byte (SWSTYLE cleared to 0), or otherwise a word containing additional status and the ownership bit (i.e., MD1[31]).

The settings of SWSTYLE (BCR20, bits 7-0) and BWRITE (BCR18, bit 5) affect the way the Am79C978 controller performs descriptor write operations.

When SWSTYLE is set to 0 or 2, all descriptor write operations are performed in non-burst mode. The setting

of BWRITE has no effect in this conﬁguration. See Figure 29.

When SWSTYLE is set to 3, the descriptor entries are ordered to allow burst transfers. TheAm79C978 controller will perform all descriptor write operations in burst mode, if BWRITE is set to 1. See Figure 30 and Table 9 for the descriptor write sequence.

A write transaction to the descriptor ring entries is the only case where the Am79C978 controller inserts a wait state when being the bus master. Every data phase in non-burst and burst mode is e xtended b y one clock cycle, during which IRD

Y is deasserted.

Note that Figure 28 assumes that the Am79C978 controller is programmed to use 32-bit software structures (SWSTYLE = 2 or 3). The byte enable signals for the second data transfer would be 0111b , if the de vice w as programmed to use 16-bit software structures (SWSTYLE = 0).

Table 8. Descriptor Read Sequence

SWSTYLE

BCR20[7:0]

BREADE

BCR18[6] AD Bus Sequence

Address = XXXX XX00h Turn around cycle Data = MD1[31:24], MD0[23:0] Idle Address = XXXX XX04h Turn around cycle Data = MD2[15:0], MD1[15:0]

Address = XXXX XX04h Turn around cycle Data = MD1[31:0] Idle Address = XXXX XX00h Turn around cycle Data = MD0[31:0]

Address = XXXX XX04h Turn around cycle Data = MD1[31:0] Idle Address = XXXX XX08h Turn around cycle Data = MD0[31:0]

Address = XXXX XX04h Turn around cycle Data = MD1[31:0] Data = MD0[31:0]

Page 57

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PRELIMINARY

Figure 27. Descriptor Ring Read In Non-Burst Mode

Figure 28. Descriptor Ring Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD1

00000110

PAR

DATA DATA

MD0

00000110

PAR PAR

1 2345678

109

22206B-30

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

MD1

00000110

PAR

PAR PAR

DATA

PAR

DEVSEL is sampled

22206B-31

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58 Am79C978

PRELIMINARY

Figure 29. Descriptor Ring Write In Non-Burst Mode

Figure 30. Descriptor Ring Write In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD2

00000111

PAR

MD1

00110111

PAR

1 2345678

109

DATA

PAR

DATA

22206B-32

GNT

REQ

DEVSEL

TRDY

PAR

C/BE

FRAME

CLK

PAR

IRDY

DEVSEL is sampled

DATA

1 2 4 6 7 8

0110

0000 0011

MD2

PAR

DATA

PAR

22206B-33

Page 59

Am79C978 59

PRELIMINARY

Table 9. Descriptor Write Sequence

FIFO DMA Transfers

The Am79C978 microcode will determine when a FIFO DMA transfer is required. This transfer mode will be used for transfers of data to and from the FIFOs. Once the BIU has been granted bus mastership, it will perform a series of consecutive transfer cycles before relinquishing the bus. All transf ers within the master cycle will be either read or write cycles, and all transfers will be to contiguous, ascending addresses. Both nonburst and burst cycles are used, with burst mode being the preferred mode when the device is used in a PCI bus application.

Non-Burst FIFO DMA Transfers

In the default mode, the Am79C978 controller uses non-burst transfers to read and write data when accessing the FIFOs. Each non-b urst tr ansfer will be performed sequentially with the issue of an address and the transfer of the corresponding data with appropriate output signals to indicate selection of the active data bytes during the transfer.

FRAME will be deasserted after every address phase. Several factors will affect the length of the bus mastership period. The possibilities are as follows:

Bus cycles will continue until the transmit FIFO is ﬁlled to its high threshold (read transfers) or the receive FIFO is emptied to its low threshold (write transfers). The exact number of total transfer cycles in the bus

mastership period is dependent on all of the following variables: the settings of the FIFO watermarks, the conditions of the FIFOs, the latency of the system bus to the Am79C978 controller's bus request, the speed of bus operation and bus preemption events. The TRD

Y response time of the memory device will also affect the number of transfers, since the speed of the accesses will affect the state of the FIFO. During accesses, the FIFO may be ﬁlling or emptying on the network end. For example, on a receive operation, a slower TRDY response will allow additional data to accumulate inside of the FIFO. If the accesses are slow enough, a complete DWord may become available before the end of the bus mastership period and, thereby, increase the number of transfers in that period. The general rule is that the longer the Bus Grant latency, the slower the bus transfer oper ations; the slower the cloc k speed, the higher the transmit watermark; or the higher the receive watermark, the longer the bus mastership period will be.

Note: The PCI Latency Timer is not signiﬁcant during non-burst transfers.

Burst FIFO DMA Transfers

Bursting is only performed by the Am79C978 controller if the BREADE and/or BWRITE bits of BCR18 are set. These bits individually enable/disable the ability of the Am79C978 controller to perform burst accesses during master read operations and master write operations, respectively.

A burst transaction will start with an address phase, followed by one or more data phases. AD[1:0] will always be 0 during the address phase indicating a linear burst order.

During FIFO DMA read operations, all byte lanes will always be active. TheAm79C978 controller will internally discard unused bytes. During the ﬁrst and the last data phases of a FIFO DMA burst write operation, one or more of the byte enable signals may be inactive. All other data phases will always write a complete D W ord.

Figure 31 shows the beginning of a FIFO DMA write with the beginning of the buffer not aligned to a DWord boundary . TheAm79C978 controller starts off by writing only three bytes during the ﬁrst data phase. This operation aligns the address for all other data transf ers to a 32-bit boundary so that the Am79C978 controller can continue bursting full DWords.

If a receive buffer does not end on a DWord boundary, the Am79C978 controller will perform a non-DWord write on the last transfer to the buffer. Figure 32 shows the ﬁnal three FIFO DMA transfers to a receive buffer. Since there were only nine bytes of space left in the receive buff er, the Am79C978 controller b ursts three data phases. The ﬁrst two data phases write a full DWord, the last one only writes a single byte.

SWSTYLE

BCR20[7:0]

BWRITE

BCR18[5] AD Bus Sequence

Address = XXXX XX04h Data = MD2[15:0],

MD1[15:0] Idle Address = XXXX XX00h Data = MD1[31:24]

Address = XXXX XX08h Data = MD2[31:0] Idle Address = XXXX XX04h Data = MD1[31:16]

Address = XXXX XX00h Data = MD2[31:0] Idle Address = XXXX XX04h Data = MD1[31:16]

Address = XXXX XX00h Data = MD2[31:0] Data = MD1[31:16]

Page 60

60 Am79C978

PRELIMINARY

Note that the Am79C978 controller will always perf orm a DWord transfer as long as it owns the buffer space, even when there are less than four bytes to write. For example, if there is only one byte left for the current receive frame, the Am79C978 controller will write a full DWord, containing the last byte of the receive frame in the least signiﬁcant byte position (BSWP is cleared to 0, CSR3, bit 2). The content of the other three bytes is undeﬁned. The message byte count in the receive descriptor always reﬂects the exact length of the receiv ed frame.

Figure 31. FIFO Burst Write at Start of Unaligned

Buffer

TheAm79C978 controller will continue transferring FIFO data until the transmit FIFO is ﬁlled to its high threshold (read transfers) or the receive FIFO is emptied to its low threshold (write transfers), or the Am79C978 controller is preempted and the PCI Latency Timer is expired. The host should use the values in the PCI MIN_GNT and MAX_LAT registers to determine the value for the PCI Latency Timer.

Figure 32. FIFO Burst Write at End of Unaligned

Buffer

The exact number of total transfer cycles in the bus mastership period is dependent on all of the following variables: the settings of the FIFO watermarks, the conditions of the FIFOs, the latency of the system bus to the Am79C978 controller's bus request, and the speed of bus operation. The TRD

Y response time of the memory device will also affect the number of transf ers, since the speed of the accesses will affect the state of the FIFO. During accesses, the FIFO may be ﬁlling or emptying on the network end. For example, on a receive operation, a slower TRDY response will allow additional data to accumulate inside of the FIFO. If the accesses are slow enough, a complete DW ord may become available before the end of the bus mastership period and, thereby , increase the number of transf ers in that period. The general rule is that the longer the Bus Grant latency, the slower the bus transfer operations; the slower the clock speed, the higher the transmit w atermark; or the lower the receive w atermark, the longer the total burst length will be.

When a FIFO DMA burst operation is preempted, the Am79C978 controller will not relinquish bus ownership until the PCI Latency Timer expires.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 23456

00000111

PAR

PAR PAR

DEVSEL is sampled

0001

PAR

DATA DATA

DATA

ADD

22206B-34

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000111

PAR

PAR PAR

PAR

DEVSEL is sampled

1110

PAR

DATA DATA

DATA

ADD

22206B-35

Page 61

Am79C978 61

PRELIMINARY

Buffer Management Unit

The Buffer Management Unit (BMU) is a microcoded state machine which implements the initialization procedure and manages the descriptors and buffers. The buffer management unit operates at half the speed of the CLK input.

Initialization

Initialization includes the reading of the initialization block in memory to obtain the operating parameters. The initialization block can be organized in two ways. When SSIZE32 (BCR20, bit 8) is at its default value of 0, all initialization block entries are logically 16-bits wide to be backwards compatible with the Am79C90 CLANCE and Am79C96x PCnet-ISA family. When SSIZE32 (BCR20, bit 8) is set to 1, all initialization block entries are logically 32-bits wide. Note that the Am79C978 controller always perf orms 32-bit bus transfers to read the initialization bloc k entries. The initialization block is read when the INIT bit in CSR0 is set. The INIT bit should be set before or concurrent with the STRT bit to insure correct operation. Once the initialization block has been completely read in and internal registers have been updated, IDON will be set in CSR0, generating an interrupt (if IENA is set).

TheAm79C978 controller obtains the start address of the initialization block from the contents of CSR1 (least signiﬁcant 16 bits of address) and CSR2 (most signiﬁcant 16 bits of address). The host m ust write CSR1 and CSR2 before setting the INIT bit. The initialization b lock contains the user deﬁned conditions for operation, together with the base addresses and length information of the transmit and receive descriptor rings.

There is an alternate method to initialize the Am79C978 controller. Instead of initialization via the initialization block in memory, data can be written directly into the appropriate registers. Either method or a combination of the two may be used at the discretion of the programmer. Please refer to

Appendix A, Alterna-

tive Method for Initialization

for details on this alternate

method.

Re-Initialization

The transmitter and receiver sections of the Am79C978 controller can be turned on via the initialization block (DTX, DRX, CSR15, bits 1-0). The states of the transmitter and receiver are monitored by the host through CSR0 (RXON, TXON bits). TheAm79C978 controller should be re-initialized if the transmitter and/or the receiver were not turned on during the original initialization and it was subsequently required to activate them, or if either section was shut off due to the detection of an error condition (MERR, UFLO, TX BUFF error).

Re-initialization may be done via the initialization bloc k or by setting the STOP bit in CSR0, followed by writing

to CSR15, and then setting the START bit in CSR0. Note that this form of restart will not perform the same in the Am79C978 controller as in the C-LANCE device. In particular, upon restart, the Am79C978 controller reloads the transmit and receive descriptor pointers with their respective base addresses. This means that the software must clear the descriptor OWN bits and reset its descriptor ring pointers before restarting the Am79C978 controller. The reload of descriptor base addresses is performed in the C-LANCE device only after initialization, so that a restart of the C-LANCE without initialization leaves the C-LANCE pointing at the same descriptor locations as before the restart.

Suspend

TheAm79C978 controller offers two suspend modes that allow easy updating of the CSR registers without going through a full re-initialization of the device. The suspend modes also allow stopping the device with orderly termination of all network activity.

The host requests the Am79C978 controller to enter the suspend mode by setting SPND (CSR5, bit 0) to 1. The host must poll SPND until it reads back 1 to determine that the Am79C978 controller has entered the suspend mode. When the host sets SPND to 1, the procedure taken by the Am79C978 controller to enter the suspend mode depends on the setting of the fast suspend enable bit (FASTSPND, CSR7, bit 15).

When a fast suspend is requested (FASTSPND is set to 1), the Am79C978 controller performs a quick entry into the suspend mode. At the time the SPND bit is set, the Am79C978 controller will continue the DMA process of any transmit and/or receive packets that have already begun DMA activity until the network activity has been completed. In addition, any transmit packet that had started transmission will be fully transmitted and any receive pack et that had begun reception will be fully received. However, no additional packets will be transmitted or received and no additional transmit or receive DMA activity will begin after network activity has ceased. Hence, the Am79C978 controller may enter the suspend mode with transmit and/or receive pack ets still in the FIFOs or the SRAM. This offers a worst case suspend time of a maximum length packet over the possibility of completely emptying the SRAM. Care must be exercised in this mode, because the entire memory subsystem of the Am79C978 controller is suspended. Any changes to either the descriptor rings or the SRAM can cause the Am79C978 controller to start up in an unknown condition and could cause data corruption.

When FASTSPNDE is 0 and the SPND bit is set, the Am79C978 controller may take longer before entering the suspend mode. At the time the SPND bit is set, the Am79C978 controller will complete the DMA process of a transmit packet if it had already begun, and the

Page 62

62 Am79C978

PRELIMINARY

Am79C978 controller will completely receive a receive packet if it had already begun. TheAm79C978 controller will not receive any new packets after the completion of the current reception. Additionally, all transmit packets stored in the transmit FIFOs and the transmit buffer area in the SRAM (if one is present) will be transmitted, and all receive packets stored in the receive FIFOs and the receive buffer area in the SRAM (if selected) will be transferred into system memory. Since the FIFO and the SRAM contents are ﬂushed, it may take much longer before the Am79C978 controller enters the suspend mode. The amount of time that it tak es depends on many factors including the size of the SRAM, bus latency, and network trafﬁc level.

Upon completion of the described operations, the Am79C978 controller sets the read-version of SPND to 1 and enters the suspend mode. In suspend mode, all of the CSR and BCR registers are accessible. As long as the Am79C978 controller is not reset while in suspend mode (by H_RESET, S_RESET, or by setting the STOP bit), no re-initialization of the device is required after the device comes out of suspend mode. When SPND is set to 0, the Am79C978 controller will leave the suspend mode and will continue at the transmit and receive descriptor ring locations where it was when it entered the suspend mode.

See the section on

Magic Pack et

technology for details on how that affects suspension of the integrated Ethernet controller.

Buffer Management

Buffer management is accomplished through message descriptor entries organized as ring structures in memory . There are two descriptor rings, one for transmit and one for receive. Each descriptor describes a single buffer. A frame may occup y one or more b uff ers . If multiple buffers are used, this is ref erred to as buff er chaining.

Descriptor Rings

Each descriptor ring must occupy a contiguous area of memory. During initialization, the user-deﬁned base address for the transmit and receive descriptor rings, as well as the number of entries contained in the descriptor rings are set up. The programming of the software style (SWSTYLE, BCR20, bits 7-0) affects the way the descriptor rings and their entries are arranged.

When SWSTYLE is at its default value of 0, the descriptor rings are backwards compatible with the Am79C90 C-LANCE and the Am79C96x PCnet-ISA family. The descr iptor ring base addresses must be aligned to an 8-byte boundary and a maximum of 128 ring entries is allowed when the ring length is set through the TLEN and RLEN ﬁelds of the initialization block. Each ring entr y contains a subset of the three

32-bit transmit or receive message descriptors (TMD, RMD) that are organized as four 16-bit structures (SSIZE32 (BCR20, bit 8) is set to 0). Note that even though the Am79C978 controller treats the descriptor entries as 16-bit structures, it will always perform 32-bit bus transfers to access the descriptor entries. The value of CSR2, bits 15-8, is used as the upper 8-bits for all memory addresses during bus master transfers.

When SWSTYLE is set to 2 or 3, the descriptor ring base addresses must be aligned to a 16-byte boundary , and a maximum of 512 ring entries is allowed when the ring length is set through the TLEN and RLEN ﬁelds of the initialization block. Each ring entr y is organized as three 32-bit message descriptors (SSIZE32 (BCR20, bit 8) is set to 1). The fourth DWord is reserved. When SWSTYLE is set to 3, the order of the message descriptors is optimized to allow read and write access in burst mode.

For any software style, the ring lengths can be set beyond this range (up to 65535) by writing the transmit and receive ring length registers (CSR76, CSR78) directly.

Each ring entry contains the following information:

■ The address of the actual message data buffer in user or host memory

■ The length of the message buffer

■ Status information indicating the condition of the

buffer

To permit the queuing and de-queuing of message buffers, ownership of each buffer is allocated to either the Am79C978 controller or the host. The OWN bit within the descriptor status information, either TMD or RMD, is used for this purpose.

When OWN is set to 1, it signiﬁes that the Am79C978 controller currently has ownership of this ring descriptor and its associated buffer. Only the owner is permitted to relinquish ownership or to write to any ﬁeld in the descriptor entry. A device that is not the current owner of a descriptor entry cannot assume ownership or change any ﬁeld in the entry. A device may, however, read from a descriptor that it does not currently own. Software should always read descriptor entries in sequential order. When software ﬁnds that the current descriptor is owned by the Am79C978 controller , then the software must not read ahead to the next descriptor. The software should wait at a descriptor it does not own until the Am79C978 controller sets OWN to 0 to release ownership to the software. When LAPPEN (CSR3, bit

5) is set to 1, this rule is modiﬁed. See the LAPPEN de-

scription. At initialization, the Am79C978 controller reads the base address of both the transmit and receive descriptor rings into CSRs for use by the Am79C978 controller during subsequent operations.

Page 63

Am79C978 63

PRELIMINARY

Figure 33 illustrates the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base addresses, the receive and transmit descriptors, and the receive and transmit data buffers, when SSIZE32 is cleared to 0.

Note that the value of CSR2, bits 15-8, is used as the upper 8-bits for all memory addresses during bus master transfers.

Figure 34 illustrates when SSIZE32 is set to 1, the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base addresses, the receive and transmit descriptors, and the receive and transmit data buffers.

Figure 33. 16-Bit Software Model

22206B-36

Initialization

Block

IADR[15:0]IADR[31:16]

CSR1

CSR2

TDRA[15:0]

MOD

PADR[15:0]

PADR[31:16] PADR[47:32] LADRF[15:0]

LADRF[31:16] LADRF[47:32] LADRF[63:48]

RDRA[15:0]

RLE

RES

RDRA[23:16]

TLE RES

TDRA[23:16]

Rcv

Buffers

RMD

Rcv Descriptor

Ring

•

1st desc. start

2nd desc.

RMD0

Xmt

Buffers

TMD

Xmt Descriptor

Ring

•

1st desc. start

2nd desc.

TMD

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Page 64

64 Am79C978

PRELIMINARY

Figure 34. 32-Bit Software Model

Polling

If there is no network channel activity and there is no pre- or post-receive or pre- or post-transmit activity being performed by the Am79C978 controller , then the Am79C978 controller will periodically poll the current receive and transmit descriptor entries in order to ascertain their ownership. If the DPOLL bit in CSR4 is set, then the transmit polling function is disabled.

A typical polling operation consists of the following sequence. TheAm79C978 controller will use the current receive descriptor address stored internally to vector to the appropriate Receive Descriptor Table Entry (RDTE). It will then use the current transmit descriptor address (stored internally) to vector to the appropriate Transmit Descriptor Table Entry (TDTE). The accesses will be made in the following order: RMD1, then RMD0 of the current RDTE during one bus arbitration, and after that, TMD1, then TMD0 of the current TDTE during a second bus arbitration. All information collected during polling activity will be stored internally in the appropriate CSRs, if the OWN bit is set (i.e., CSR18,

CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52).

A typical receive poll is the product of the follo wing conditions:

1. The controller does not own the current RDTE

and

the poll time has elapsed

and

RXON = 1 (CSR0,

bit 5),

2. The controller does not own the next RDTE

and

there

is more than one receive descriptor in the ring

and

the poll time has elapsed

and

RXON = 1.

If RXON is cleared to 0, the Am79C978 controller will never poll RDTE locations.

In order to avoid missing frames, the system should have at least one RDTE available. To minimize poll activity, two RDTEs should be available. In this case, the poll operation will only consist of the check of the status of the current TDTE.

A typical transmit poll is the product of the following conditions:

Initialization

Block

CSR1CSR2

RMD

Rcv Descriptor

Ring

•

1st desc.

start

2nd desc. start

RMD

TMD0

TMD1

TMD2

TMD3

Xmt Descriptor

Ring

•

1st desc.

start

2nd desc. start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16] IADR[15:0]

TLE

RES

RLE

RES

MODE

PADR[47:32]

RES

LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

22206B-37

Page 65

Am79C978 65

PRELIMINARY

1. The controller does not own the current TDTE

and

TXDPOLL = 0 (CSR4, bit 12)

and

TXON = 1 (CSR0,

bit 4)

and

the poll time has elapsed,

2. The controller does not own the current TDTE

and

TXDPOLL = 0

and

TXON = 1

and

a frame has just

been received, or

3. The controller does not own the current TDTE

and

TXDPOLL = 0

and

TXON = 1

and

a frame has just

been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode controller to exit the poll counting code and immediately perform a polling operation. If RDTE ownership has not been previously established, then an RDTE poll will be performed ahead of the TDTE poll. If the microcode is not executing the poll counting code when the TDMD bit is set, then the demanded poll of the TDTE will be delayed until the microcode returns to the poll counting code.

The user may change the poll time value from the default of 65,536 clock periods by modifying the value in the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) access, the Am79C978 controller ﬁnds that the OWN bit of that TDTE is not set, the Am79C978 controller resumes the poll time count and re-examines the same TDTE at the next expiration of the poll time count.

If the OWN bit of the TDTE is set, but the Start of Pack et (STP) bit is not set, the Am79C978 controller will immediately request the bus in order to clear the OWN bit of this descriptor. (This condition would normally be found following a late collision (LCOL) or retry (RTRY) error that occurred in the middle of a transmit frame chain of buffers.) After resetting the OWN bit of this descr iptor, the Am79C978 controller will again immediately request the bus in order to access the next TDTE location in the ring.

If the OWN bit is set and the buff er length is 0, the OWN bit will be cleared. In the C-LANCE device, the buffer length of 0 is interpreted as a 4096-byte buffer. A zero length buffer is acceptable as long as it is not the last buffer in a chain (STP = 0 and ENP = 1).

If the OWN bit and STP are set, then microcode control proceeds to a routine that will enable transmit data transfers to the FIFO. TheAm79C978 controller will look ahead to the next transmit descriptor after it has performed at least one transmit data transfer from the ﬁrst buffer.

If the Am79C978 controller does not own the next TDTE (i.e., the second TDTE f or this frame), it will complete transmission of the current buffer and update the status of the current (ﬁrst) TDTE with the BUFF and UFLO bits being set. If DXSUFLO (CSR3, bit 6) is

cleared to 0, the underﬂow error will cause the transmitter to be disabled (CSR0, TXON = 0). TheAm79C978 controller will have to be re-initialized to restore the transmit function. Setting DXSUFLO to 1 enables the Am79C978 controller to gracefully recover from an underﬂow error. The device will scan the transmit descriptor ring until it ﬁnds either the start of a new frame or a TDTE it does not o wn. To avoid an underﬂo w situation in a chained buffer transmission, the system should always set the transmit chain descriptor own bits in reverse order.

If the Am79C978 controller does own the second TDTE in a chain, it will gradually empty the contents of the ﬁrst buffer (as the bytes are needed by the transmit operation), perform a single-cycle DMA transfer to update the status of the ﬁrst descriptor (clear the OWN bit in TMD1), and then it may perform one data DMA access on the second buffer in the chain before executing another lookahead operation. (i.e., a lookahead to the third descriptor.)

It is imperative that the host system never reads the TDTE OWN bits out of order. TheAm79C978 controller normally clears OWN bits in strict FIFO order. Howe ver , the Am79C978 controller can queue up to two frames in the transmit FIFO. When the second frame uses buffer chaining, the Am79C978 controller might return ownership out of normal FIFO order. The OWN bit for the last (and maybe only) buff er of the ﬁrst fr ame is not cleared until transmission is completed. During the transmission the Am79C978 controller will read in buffers for the next frame and clear their OWN bits for all but the last one. The ﬁrst and all intermediate buffers of the second frame can have their OWN bits cleared before the Am79C978 controller returns ownership for the last buffer of the ﬁrst frame.

If an error occurs in the transmission before all of the bytes of the current buff er have been tr ansferred, transmit status of the current buffer will be immediately updated. If the buffer does not contain the end of packet, the Am79C978 controller will skip over the rest of the frame which experienced the error. This is done by returning to the polling microcode where the Am79C978 controller will clear the OWN bit for all descriptors with OWN = 1 and STP = 0 and continue in like manner until a descriptor with OWN = 0 (no more transmit frames in the ring) or OWN = 1 and STP = 1 (the ﬁrst buffer of a new frame) is reached.

At the end of any transmit operation, whether successful or with errors, immediately following the completion of the descriptor updates, the Am79C978 controller will always perf orm another polling operation. As described earlier, this polling operation will begin with a check of the current RDTE, unless the Am79C978 controller already owns that descriptor. Then the Am79C978 controller will poll the next TDTE. If the transmit descriptor OWN bit has a 0 value, the Am79C978 controller will

Page 66

66 Am79C978

PRELIMINARY

resume incrementing the poll time counter. If the transmit descriptor OWN bit has a value of 1, the Am79C978 controller will begin ﬁlling the FIFO with transmit data and initiate a transmission. This end-of-operation poll coupled with the TDTE lookahead operation allo ws the Am79C978 controller to avoid inserting poll time counts between successive transmit frames.

By default, whenever the Am79C978 controller completes a transmit frame (either with or without error) and writes the status information to the current descriptor, then the TINT bit of CSR0 is set to indicate the completion of a transmission. This causes an interrupt signal if the IENA bit of CSR0 has been set and the TINTM bit of CSR3 is cleared. TheAm79C978 controller provides two modes to reduce the number of transmit interrupts. The interrupt of a successfully transmitted frame can be suppressed by setting TINTOKD (CSR5, bit 15) to 1. Another mode, which is enabled by setting LTINTEN (CSR5, bit 14) to 1, allows suppression of interrupts for successful transmissions for all but the last frame in a sequence.

Receive Descriptor Table Entry

If the Am79C978 controller does not own both the current and the next Receive Descriptor Table Entry (RDTE), then the Am79C978 controller will continue to poll according to the polling sequence described above. If the receive descriptor ring length is one, then there is no next descriptor to be polled.

If a poll operation has revealed that the current and the next RDTE belong to the Am79C978 controller, then additional poll accesses are not necessary. Future poll operations will not include RDTE accesses as long as the Am79C978 controller retains ownership of the current and the next RDTE.

When receive activity is present on the channel, the Am79C978 controller waits for the complete address of the message to arrive. It then decides whether to accept or reject the frame based on all active addressing schemes. If the frame is accepted, the Am79C978 controller checks the current receive buffer status register CRST (CSR41) to determine the ownership of the current buffer.

If ownership is lacking, the Am79C978 controller will immediately perform a ﬁnal poll of the current RDTE. If ownership is still denied, the Am79C978 controller has no buffer in which to store the incoming message. The MISS bit will be set in CSR0 and the Missed Frame Counter (CSR112) will be incremented. Another poll of the current RDTE will not occur until the frame has ﬁnished.

If the Am79C978 controller sees that the last poll (either a normal poll, or the ﬁnal effort described in the above paragraph) of the current RDTE shows valid ownership, it proceeds to a poll of the next RDTE. Fol-

lowing this poll, and regardless of the outcome of this poll, transfers of receive data from the FIFO ma y begin.

Regardless of ownership of the second receive descriptor, the Am79C978 controller will continue to perform receive data DMA transf ers to the ﬁrst buff er . If the frame length exceeds the length of the ﬁrst buffer, and the Am79C978 controller does not own the second buffer, ownership of the current descriptor will be passed back to the system by writing a 0 to the OWN bit of RMD1. Status will be written indicating buffer (BUFF = 1) and possibly overﬂow (OFLO = 1) errors.

If the frame length exceeds the length of the ﬁrst (current) buffer, and the Am79C978 controller does own the second (next) buff er , ownership will be passed back to the system by writing a 0 to the OWN bit of RMD1 when the ﬁrst buffer is full. The OWN bit is the only bit modiﬁed in the descriptor. Receiv e data transfers to the second buffer may occur before the Am79C978 controller proceeds to look ahead to the ownership of the third buffer. Such action will depend upon the state of the FIFO when the OWN bit has been updated in the ﬁrst descriptor. In any case, lookahead will be performed to the third buffer and the information gathered will be stored in the chip, regardless of the state of the ownership bit.

This activity continues until the Am79C978 controller recognizes the completion of the frame (the last byte of this receive message has been removed from the FIFO). TheAm79C978 controller will subsequently update the current RDTE status with the end of frame (ENP) indication set, write the message byte count (MCNT) for the entire frame into RMD2, and overwrite the “current” entries in the CSRs with the “ne xt” entries.

Receive Frame Queuing

TheAm79C978 controller supports the lack of RDTEs when SRAM (SRAM SIZE in BCR 25, bits 7-0) is enabled through the Receive Frame Queuing mechanism. When the SRAM SIZE = 0, then the Am79C978 controller reverts back to the PCnet-PCI II mode of operation. This operation is automatic and does not require any programming by the host. When SRAM is enabled, the Receive Frame Queuing mechanism allows a slow protocol to manage more frames without the high frame loss rate normally attributed to FIFObased network controllers.

TheAm79C978 controller will store the incoming frames in the extended FIFOs until polling takes place , if enabled and it discovers it o wns an RDTE. The stored frames are not altered in any way until written out into system buffers. When the receive FIFO overﬂows, further incoming receive frames will be missed during that time. As soon as the network receive FIFO is empty, incoming frames are processed as normal. Status on a per frame basis is not kept during the overﬂo w process.

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Statistic counters are maintained and accurate during that time.

During the time that the Receive Frame Queuing mechanism is in operation, the Am79C978 controller relies on the Receive Poll Time Counter (CSR 48) to control the worst case access to the RDTE. The Receive Poll Time Counter is programmed through the Receive P olling Interval (CSR49) register. The Received Polling Interval defaults to approximately 2 ms. TheAm79C978 controller will also try to access the RDTE during normal descriptor accesses whether they are transmit or receive accesses. The host can force the Am79C978 controller to immediately access the RDTE by setting the RDMD (CSR 7, bit 13) to 1. Its operation is similar to the transmit one. The polling process can be disabled by setting the RXDPOLL (CSR7, bit 12) bit. This will stop the automatic polling process and the host must set the RDMD bit to initiate the receive process into host memory. Receive frames are still stored even when the receive polling process is disabled.

Software Interrupt Timer

TheAm79C978 controller is equipped with a software programmable free-running interrupt timer. The timer is constantly running and will generate an interrupt STINT (CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to 1. After generating the interrupt, the software timer will load the value stored in STVAL and restar t. The timer value STVAL (BCR31, bits 15-0) is interpreted as an unsigned number with a resolution of 256 Time Base Clock periods. For instance, a value of 122 ms would be programmed with a value of 9531 (253Bh), if the Time Base Clock is running at 20 MHz. The default value of STVAL is FFFFh which yields the approximate maximum 838 ms timer duration. A write to STVAL restarts the timer with the new contents of STVAL.

10/100 Media Access Controller

The Media Access Controller (MAC) engine incorporates the essential protocol requirements for operation of an Ethernet/IEEE 802.3-compliant node and provides the interface between the FIFO subsystem and the internal PHY.

This section describes operation of the MAC engine when operating in half-duplex mode. When operating in half-duplex mode, the MA C engine is fully compliant to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard 1990 Second Edition) and ANSI/IEEE 802.3 (1985). When operating in full-duplex mode, the MAC engine behavior changes as described in the section

Full-

Duplex Operation

The MAC engine provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. These features include the ability to disable retries after

a collision, dynamic FCS generation on a frame-byframe basis, automatic pad ﬁeld insertion and deletion to enforce minimum frame size attrib utes, automatic retransmission without reloading the FIFO, and automatic deletion of collision fragments.

The two primary attributes of the MAC engine are:

■ Transmit and receive message data encapsulation — Framing (frame boundary delimitation, frame

synchronization)

— Addressing (source and destination address

handling)

— Error detection (physical medium transmission

errors)

■ Media access management — Medium allocation (collision avoidance, except

in full-duplex operation)

— Contention resolution (collision handling, except

in full-duplex operation)

T ransmit and Receive Message Data Encapsulation

The MAC engine provides minimum frame size enforcement for transmit and receive frames. When APAD_XMT (CSR, bit 11) is set to 1, transmit messages will be padded with sufﬁcient bytes (containing 00h) to ensure that the receiving station will observe an information ﬁeld (destination address, source address, length/type, data, and FCS) of 64 bytes. When ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will automatically strip pad bytes from the received message by observing the value in the length ﬁeld and by stripping excess bytes if this value is below the minimum data size (46 bytes). Both features can be independently over-ridden to allow illegally short (less than 64 bytes of frame data) messages to be transmitted and/or received. The use of this feature reduces bus utilization because the pad bytes are not transferred into or out of main memory.

Framing

The MAC engine will autonomously handle the construction of the transmit frame. Once the tr ansmit FIFO has been ﬁlled to the predetermined threshold (set by XMTSP in CSR80) and access to the channel is currently permitted, the MAC engine will commence the 7byte preamble sequence (10101010b, where ﬁrst bit transmitted is a 1). The MAC engine will subsequently append the Start Frame Delimiter (SFD) byte (10101011b) followed by the serialized data from the transmit FIFO. Once the data has been completed, the MAC engine will append the FCS (most signiﬁcant bit ﬁrst), which was computed on the entire data portion of the frame. The data portion of the frame consists of destination address, source address, length/type, and frame data. The user is responsible for the correct ordering and content in each of these ﬁelds in the frame.

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The MAC does not use the content in the length/type ﬁeld unless APAD_XMT (CSR4, bit 11) is set and the data portion of the frame is shorter than 60 bytes.

The MAC engine will detect the incoming preamble sequence when the RX_DV signal is activated by the internal PHY. The MAC will discard the preamble and begin searching for the SFD. Once the SFD is detected, all subsequent nibbles are treated as part of the frame. The MAC engine will inspect the length ﬁeld to ensure minimum frame size, strip unnecessary pad characters (if enabled), and pass the remaining bytes through the receive FIFO to the host. If pad stripping is performed, the MAC engine will also strip the received FCS bytes, although normal FCS computation and checking will occur. Note that apart from pad stripping, the frame will be passed unmodiﬁed to the host. If the length ﬁeld has a value of 46 or greater , all frame b ytes including FCS will be passed unmodiﬁed to the receive buffer, regardless of the actual frame length.

If the frame terminates or suffers a collision before 64 bytes of information (after SFD) have been received, the MAC engine will automatically delete the frame from the receive FIFO, without host intervention. TheAm79C978 controller has the ability to accept runt packets for diagnostic purposes and proprietar y networks.

Destination Address Handling

The ﬁrst 6 bytes of information after SFD will be interpreted as the destination address ﬁeld. The MAC engine provides facilities for physical (unicast), logical (multicast), and broadcast address reception.

Error Detection

The MAC engine provides several facilities which report and recover from errors on the medium. In addition, it protects the network from gross errors due to inability of the host to keep pace with the MAC engine activity.

On completion of transmission, the following transmit status is available in the appropriate Transmit Message Descriptor (TMD) and Control and Status Register (CSR) areas:

■ The number of transmission retry attempts (ONE, MORE, RTRY, and TRC).

■ Whether the MAC engine had to Defer (DEF) due to channel activity.

■ Excessive deferral (EXDEF), indicating that the transmitter experienced Excessive Deferral on this transmit frame, where Excessive Def erral is deﬁned in the ISO 8802-3 (IEEE/ANSI 802.3) standard.

■ Loss of Carrier (LCAR), indicating that there was an interruption in the ability of the MAC engine to monitor its own transmission. Repeated LCAR errors in-

dicate a potentially faulty transceiver or network connection.

■ Late Collision (LCOL) indicates that the transmission suffered a collision after the slot time. This is indicative of a badly conﬁgured network. Late collisions should not occur in a normal operating network.

■ Collision Error (CERR) indicates that the transceiver did not respond with an SQE Test message within the ﬁrst 4 ms after a transmission was completed. This may be due to a failed transceiver, disconnected or faulty transceiver drop cable, or because the transceiver does not support this feature (or it is disabled). SQE Test is only valid for 10Mbps networks.

In addition to the reporting of network errors, the MAC engine will also attempt to prevent the creation of any network error due to the inability of the host to service the MAC engine. During transmission, if the host fails to keep the transmit FIFO ﬁlled sufﬁciently, causing an underﬂow , the MAC engine will guarantee the message is either sent as a runt packet (which will be deleted by the receiving station) or as an invalid FCS (which will also cause the receiver to reject the message).

The status of each receive message is available in the appropriate Receive Message Descriptor (RMD) and CSR areas. All received frames are passed to the host regardless of any error. The FRAM error will only be reported if an FCS error is detected and there is a nonintegral number of bytes in the message.

During the reception, the FCS is generated on every nibble (including the dribbling bits) coming from the cable, although the internally saved FCS v alue is only updated on the eighth bit (on each byte boundary). The MAC engine will ignore up to 7 additional bits at the end of a message (dribbling bits), which can occur under normal network operating conditions. The fr aming error is reported to the user as follows:

■ If the number of dribbling bits are 1 to 7 and there is no FCS error, then there is no Framing error (FRAM = 0).

■ If the number of dribbling bits are 1 to 7 and there is a FCS error, then there is also a Framing error (FRAM = 1).

■ If the number of dribbling bits is 0, then there is no Framing error. There may or may not be a FCS error.

■ If the number of dribbling bits is 8, then there is no Framing error. FCS error will be reported, and the receive message count will indicate one extra byte.

Counters are provided to report the Receive Collision Count and Runt Pack et Count for network statistics and utilization calculations.

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Media Access Management

The basic requirement for all stations on the network is to provide fairness of channel allocation. The IEEE

802.3/Ethernet protocols deﬁne a media access mechanism which permits all stations to access the channel with equality. Any node can attempt to contend for the channel by waiting for a predetermined time (Inter Packet Gap) after the last activity, before transmitting on the media. The channel is a multidrop communications media (with various topological conﬁgurations permitted), which allows a single station to transmit and all other stations to receive. If two nodes simultaneously contend for the channel, their signals will interact causing loss of data, deﬁned as a collision. It is the responsibility of the MAC to attempt to avoid and recover from a collision and to guarantee data integrity for the end-to-end transmission to the receiving station.

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990) requires that the CSMA/CD MAC monitor the medium for trafﬁc by w atching for carrier activity. When carrier is detected, the media is considered busy, and the MAC should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard also allows optionally a two-part deferral after a receive message.

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: “It is possible for the PLS carrier sense indication to fail to be asserted during a collision on the media. If the deference process simply times the interframe gap based on this indication, it is possible for a short interframe gap to be generated, leading to a potential reception failure of a subsequent frame. To enhance system robustness, the following optional measures (as speciﬁed in 4.2.8) are recommended when InterFrameSpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the interrupted gap as soon as transmitting and carrier sense are both false.

2. When timing an inter-frame gap following reception, reset the inter-frame gap timing if carrier sense becomes true during the ﬁrst 2/3 of the inter-frame gap timing interval. During the ﬁnal 1/3 of the interval, the timer shall not be reset to ensure fair access to the medium. An initial period shorter than 2/3 of the interval is permissible including 0.”

The MAC engine implements the optional receive twopart deferral algorithm, with an InterFrameSpacingPart1 time of 6.0 ms. The InterFrameSpacingPart 2 interval is, therefore, 3.4 ms.

TheAm79C978 controller will perform the two-part deferral algorithm as speciﬁed in the

Process Deference

section. The Inter Packet Gap (IPG) timer will start timing the 9.6 ms InterFrameSpacing after the receiv e car-

rier is deasserted. During the ﬁrst part deferral (InterFrameSpacingPart1 - IFS1), the Am79C978 controller will defer any pending transmit frame and respond to the receive message. The IPG counter will be cleared to 0 continuously until the carrier deasserts, at which point the IPG counter will resume the 9.6 ms count once again. Once the IFS1 period of 6.0 ms has elapsed, the Am79C978 controller will begin timing the second part deferral (InterFrameSpacingPar t2 - IFS2) of 3.4 ms. Once IFS1 has completed and IFS2 has commenced, the Am79C978 controller will not defer to a receive frame if a transmit frame is pending. This means that the Am79C978 controller will not attempt to receive the receive frame, since it will start to transmit and generate a collision at 9.6 ms. TheAm79C978 controller will complete the preamble (64-bit) and jam (32bit) sequence before ceasing transmission and invoking the random backoff algorithm.

TheAm79C978 controller allows the user to program the IPG and the ﬁrst-part deferral (InterFrameSpacingPart1 - IFS1) through CSR125. By changing the IPG default value of 96 bit times (60h), the user can adjust the fairness or aggressiveness of the MAC on the network. By programming a low er number of bit times than the ISO/IEC 8802-3 standard requires, the MAC engine will become more aggressive on the network. This aggressive nature will give rise to the Am79C978 controller possibly capturing the network at times by forcing other less aggressive compliant nodes to defer . By programming a larger number of bit times, the MAC will become less aggressive on the network and may defer more often than normal. The performance of the Am79C978 controller may decrease as the IPG value is increased from the default value, but the resulting behavior may improve network performance by reducing collisions. TheAm79C978 controller uses the same IPG for back-to-back transmits and receive-to-transmit accesses. Changing IFS1 will alter the period for which the MAC engine will def er to incoming receive frames.

CAUTION: Care must be exercised when altering these parameters. Adverse network activity could result!

This transmit two-part deferral algorithm is implemented as an option which can be disabled using the DXMT2PD bit in CSR3. The IFS1 programming will have no eff ect when DXMT2PD is set to 1, but the IPG programming value is still valid. Two part deferral after transmission is useful for ensuring that severe IPG shrinkage cannot occur in speciﬁc circumstances, causing a transmit message to follow a receive message so closely as to make them indistinguishable.

During the time period immediately after a transmission has been completed, the external transceiver should generate the SQE Test message within 0.6 to

1.6 ms after the transmission ceases. Dur ing the time

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period in which the SQE Test message is expected, the Am79C978 controller will not respond to receive carrier sense.

See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):

“At the conclusion of the output function, the DTE opens a time window during which it expects to see the signal_quality_error signal asserted on the Control In circuit. The time window begins when the CARRIER_STATUS becomes CARRIER_OFF. If execution of the output function does not cause CARRIER_ON to occur, no SQE test occurs in the DTE. The duration of the window shall be at least 4.0

s but no more than 8.0 µs. During the time window the Carrier Sense Function is inhibited.”

TheAm79C978 controller implements a carrier sense “blinding” period of 4.0 µs length starting from the deassertion of carrier sense after transmission. This effectively means that when transmit two-part deferral is enabled (DXMT2PD is cleared), the IFS1 time is from 4 ms to 6 ms after a transmission. However, since IPG shrinkage below 4 ms will rarely be encountered on a correctly conﬁgured network, and since the fragment size will be larger than the 4 ms blinding window, the IPG counter will be reset by a worst case IPG shrinkage/fragment scenario and the Am79C978 controller will defer its transmission. If carrier is detected within the 4.0 to 6.0 ms IFS1 period, the Am79C978 controller will not restart the “blinding” period, but only restart IFS1.

Collision Handling

Collision detection is performed and reported to the MAC engine via the COL input pin.

If a collision is detected before the complete preamble/ SFD sequence has been transmitted, the MAC engine will complete the preamble/SFD before appending the jam sequence. If a collision is detected after the preamble/SFD has been completed, but prior to 512 bits being transmitted, the MAC engine will abort the transmission and append the jam sequence immediately. The jam sequence is a 32-bit all zeros pattern.

The MAC engine will attempt to transmit a frame a total of 16 times (initial attempt plus 15 retries) due to normal collisions (those within the slot time). Detection of collision will cause the transmission to be rescheduled to a time determined by the random backoff algorithm. If a single retry was required, the 1 bit will be set in the transmit frame status. If more than one retr y was required, the MORE bit will be set. If all 16 attempts experienced collisions, the RTRY bit will be set (1 and MORE will be clear), and the transmit message will be ﬂushed from the FIFO. If retries have been disabled by setting the DRTY bit in CSR15, the MAC engine will abandon transmission of the frame on detection of the

ﬁrst collision. In this case , only the R TRY bit will be set, and the transmit message will be ﬂushed from the FIFO.

If a collision is detected after 512 bit times have been transmitted, the collision is termed a late collision. The MAC engine will abort the transmission, append the jam sequence, and set the LCOL bit. No retry attempt will be scheduled on detection of a late collision, and the transmit message will be ﬂushed from the FIFO.

The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires use of a “truncated binary exponential backoff” algorithm, which provides a controlled pseudo random mechanism to enforce the collision backoff interval, before retransmission is attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), the CSMA/CD sublayer delays before attempting to retransmit the frame. The delay is an integer multiple of slot time. The number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer r in the range:

0 ≤ r < 2k Where k = Min (N,10).”

TheAm79C978 controller provides an alternative algorithm, which suspends the counting of the slot time/IPG during the time that receive carrier sense is detected. This aids in networks where large numbers of nodes are present, and numerous nodes can be in collision. It effectively accelerates the increase in the backoff time in busy networks and allows nodes not involved in the collision to access the channel, while the colliding nodes await a reduction in channel activity. Once channel activity is reduced, the nodes resolving the collision time-out their slot time counters as normal.

This modiﬁed backoff algorithm is enabled when EMBA (CSR3, bit 3) is set to 1.

Transmit Operation

The transmit operation and features of the Am79C978 controller are controlled by programmable options. TheAm79C978 controller offers a large transmit FIFO to provide frame buff ering for increased system latency , automatic retransmission with no FIFO reload, and automatic transmit padding.

Transmit Function Programming

Automatic transmit features such as retry on collision, FCS generation/transmission, and pad ﬁeld insertion can all be programmed to provide ﬂexibility in the (re-) transmission of messages.

Disable retry on collision (DRTY) is controlled by the DRTY bit of the Mode register (CSR15) in the initialization block.

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Automatic pad ﬁeld insertion is controlled by the APAD_XMT bit in CSR4.

The disable FCS generation/transmission feature can be programmed as a static feature or dynamically on a frame-by-frame basis.

T r ansmit FIFO W atermark (XMTFW) in CSR80 sets the point at which the BMU requests more data from the transmit buffers for the FIFO. A minimum of XMTFW empty spaces must be available in the transmit FIFO before the BMU will request the system bus in order to transfer transmit frame data into the transmit FIFO.

Transmit Start Point (XMTSP) in CSR80 sets the point when the transmitter actually attempts to transmit a frame onto the media. A minimum of XMTSP bytes must be written to the transmit FIFO for the current frame before transmission of the current frame will begin. (When automatically padded packets are being sent, it is conceivable that the XMTSP is not reached when all of the data has been transferred to the FIFO. In this case, the transmission will begin when all of the frame data has been placed into the transmit FIFO.) The default value of XMTSP is 01b, meaning there has to be 64 bytes in the transmit FIFO to start a transmission.

Automatic Pad Generation

T ransmit fr ames can be automatically padded to extend them to 64 data bytes (excluding preamble). This allows the minimum frame size of 64 bytes (512 bits) for IEEE 802.3/Ethernet to be guaranteed with no software intervention from the host/controlling process. Setting the APAD_XMT bit in CSR4 enables the automatic padding feature. The pad is placed between the LLC data ﬁeld and FCS ﬁeld in the IEEE 802.3 frame. FCS is always added if the frame is padded, regardless of the state of DXMTFCS (CSR15, bit 3) or ADD_FCS (TMD1, bit 29). The transmit frame will be padded by bytes with the value of 00h. The default value of

APAD_XMT is 0, which will disable automatic pad generation after H_RESET.

It is the responsibility of upper layer software to correctly deﬁne the actual length ﬁeld contained in the message to correspond to the total number of LLC data bytes encapsulated in the frame (length ﬁeld as deﬁned in the ISO 8802-3 (IEEE/ANSI 802.3) standard). The length value contained in the message is not used by the Am79C978 controller to compute the actual number of pad bytes to be inserted. TheAm79C978 controller will append pad bytes dependent on the actual number of bits transmitted onto the network. Once the last data byte of the frame has completed, prior to appending the FCS, the Am79C978 controller will check to ensure that 544 bits have been transmitted. If not, pad bytes are added to extend the frame size to this value, and the FCS is then added. See Figure 35.

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble/SFD, including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits FCS size 4 bytes 32 bits

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble/SFD, including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits FCS size 4 bytes 32 bits

At the point that FCS is to be appended, the transmitted frame should contain:

Preamble/SFD + (Min Frame Size - FCS) 64 + (512-32) = 544 bits

A minimum length transmit frame from theAm79C978 controller, theref ore, will be 576 bits after the FCS is appended.

Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

Preamble

1010....1010

SFD

10101011

Destination

Address

Source

Address

Length

LLC

Data

Pad FCS

Bytes

46 – 1500

Bytes

Bits

22206B-38

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Transmit FCS Generation

Automatic generation and transmission of FCS for a transmit frame depends on the value of DXMTFCS (CSR15, bit 3). If DXMTFCS is cleared to 0, the transmitter will generate and append the FCS to the transmitted frame. If the automatic padding feature is invoked (APAD_XMT is set in CSR4), the FCS will be appended by theAm79C978 controller regardless of the state of DXMTFCS or ADD_FCS (TMD1, bit 29). Note that the calculated FCS is transmitted most significant bit ﬁrst. The default value of DXMTFCS is 0 after H_RESET.

ADD_FCS (TMD1, bit 29) allows the automatic generation and transmission of FCS on a frame-by-frame basis. DXMTFCS should be cleared to 0 in this mode. To generate FCS for a frame, ADD_FCS must be set in all descriptors of a frame (STP is set to 1). Note that bit 29 of TMD1 has the function of ADD_FCS if SWSTYLE (BCR20, bits 7-0) is programmed to 0, 2, or 3.

Transmit Exception Conditions

Exception conditions for frame transmission fall into two distinct categories: those conditions which are the result of normal network operation, and those which occur due to abnormal network and/or host related events.

Normal events which may occur and which are handled autonomously by theAm79C978 controller include collisions within the slot time with automatic retry. TheAm79C978 controller will ensure that collisions which occur within 512 bit times from the start of transmission (including preamble) will be automatically retried with no host intervention. The transmit FIFO ensures this by guaranteeing that data contained within the FIFO will not be overwritten until at least 64 bytes (512 bits) of preamble plus address, length, and data ﬁelds have been transmitted onto the network without encountering a collision. Note that if DR TY (CSR15, bit

5) is set to 1 or if the network interface is operating in full-duplex mode, no collision handling is required, and any byte of frame data in the FIFO can be overwr itten as soon as it is transmitted.

If 16 total attempts (initial attempt plus 15 retries) fail, theAm79C978 controller sets the RTRY bit in the current transmit TDTE in host memory (TMD2), gives up ownership (resets the OWN bit to 0) f or this fr ame , and processes the next frame in the transmit ring for transmission.

Abnormal network conditions include:

■ Loss of carrier

■ Late collision

■ SQE Test Error (does not apply to 100 Mbps net-

works.)

These conditions should not occur on a correctly conﬁgured IEEE 802.3 network operating in half-duplex mode. If they do, they will be repor ted. None of these conditions will occur on a network operating in fullduplex mode. (See the section

Full-Duplex Operation

for more detail.) When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in the current descriptor. The OWN bit(s) in the subsequent descriptor(s) will be cleared until the STP (the next frame) is found.

Loss of Carrier

LCAR will be reported for every frame transmitted if theAm79C978 controller detects a loss of carrier.

Late Collision

A late collision will be reported if a collision condition occurs after one slot time (512 bit times) after the transmit process was initiated (ﬁrst bit of preamble commenced). TheAm79C978 controller will abandon the transmit process for that frame, set Late Collision (LCOL) in the associated TMD2, and process the next transmit frame in the ring. Frames experiencing a late collision will not be retried. Recover y from this condition must be performed by upper layer software.

SQE Test Error

If the network port is in Link Fail state, CERR will be asserted in the 10BASE-T mode after transmit. CERR will never cause INTA to be activated. It will, however, set the ERR bit CSR0.

Receive Operation

The receive operation and features of theAm79C978 controller are controlled by programmable options. TheAm79C978 controller offers a large receive FIFO to provide frame buffering for increased system latency, automatic ﬂushing of collision fragments (runt packets), automatic receive pad stripping, and a variety of address match options.

Receive Function Programming

Automatic pad ﬁeld stripping is enabled by setting the ASTRP_RCV bit in CSR4. This can provide ﬂexibility in the reception of messages using the IEEE 802.3 frame format.

All receive frames can be accepted by setting the PROM bit in CSR15. Acceptance of unicast and broadcast frames can be individually turned off by setting the DRCVPA or DRCVBC bits in CSR15. The Physical Address register (CSR12 to CSR14) stores the address that theAm79C978 controller compares to the destination address of the incoming frame for a unicast address match. The Logical Address Filter register (CSR8 to CSR11) serves as a hash ﬁlter for multicast address match.

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The point at which the BMU will start to transfer data from the receive FIFO to buff er memory is controlled by the RCVFW bits in CSR80. The default established during H_RESET is 01b, which sets the watermark ﬂag at 64 bytes ﬁlled.

For test purposes, theAm79C978 controller can be programmed to accept runt packets by setting RPA in CSR124.

Address Matching

TheAm79C978 controller supports three types of address matching: unicast, multicast, and broadcast. The normal address matching procedure can be modiﬁed by programming three bits in CSR15, the mode register (PROM, DRCVPA, and DRCVBC).

If the ﬁrst bit received after the SFD (the least signiﬁcant bit of the ﬁrst byte of the destination address ﬁeld) is 0, the frame is unicast, which indicates that the frame is meant to be received by a single node. If the ﬁrst bit received is 1, the frame is multicast, which indicates that the frame is meant to be received by a group of nodes. If the destination address ﬁeld contains all 1s, the frame is broadcast, which is a special type of multicast. F rames with the broadcast address in the destination address ﬁeld are meant to be received by all nodes on the local area network.

When a unicast frame arrives at theAm79C978 controller, the Am79C978 controller will accept the frame if the destination address ﬁeld of the incoming frame exactly matches the 6-byte station address stored in the Physical Address registers (PADR, CSR12 to CSR14). The byte ordering is such that the ﬁrst byte received from the network (after the SFD) must match the least significant byte of CSR12 (PADR[7:0]), and the sixth byte received must match the most signiﬁcant byte of CSR14 (PADR[47:40]).

When DRCVPA (CSR15, bit 13) is set to 1,the Am79C978 controller will not accept unicast frames.

If the incoming frame is multicast, the Am79C978 controller performs a calculation on the contents of the destination address ﬁeld to determine whether or not to accept the frame. This calculation is explained in the section that describes the Logical Address Filter (LADRF).

When all bits of the LADRF registers are 0, no multicast frames are accepted, except for broadcast frames.

Although broadcast frames are classiﬁed as special multicast frames, they are treated differently by the Am79C978 controller hardware. Broadcast frames are always accepted, except when DRCVBC (CSR15, bit

14) is set and there is no Logical Address match.

None of the address ﬁltering described above applies when the Am79C978 controller is operating in the promiscuous mode. In the promiscuous mode, all properly formed packets are received, regardless of the contents of their destination address ﬁelds. The promiscuous mode overrides the Disable Receiv e Broadcast bit (DRCVBC bit l4 in the MODE register) and the Disable Receive Physical Address bit (DRCVPA, CSR15, bit

13). TheAm79C978 controller operates in promiscuous

mode when PROM (CSR15, bit 15) is set. The receive descriptor entry RMD1 contains three bits

that indicate which method of address matching caused the Am79C978 controller to accept the frame. Note that these indicator bits are only available when the Am79C978 controller is programmed to use 32-bit structures for the descriptor entries (BCR20, bit 7-0, SWSTYLE is set to 2 or 3).

Physical Address Match (PAM) (RMD1, bit 22) is set by the Am79C978 controller when it accepts the received frame due to a match of the frame's destination address with the content of the physical address register.

Logical Address Filter Match (LAFM) (RMD1, bit 21) is set by the Am79C978 controller when it accepts the received frame based on the value in the logical address ﬁlter register.

Broadcast Address Match (BAM) (RMD1, bit 20) is set by the Am79C978 controller when it accepts the received frame because the frame's destination address is of the type 'Broadcast.’

If DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, but not LAFM will be set when a Broadcast frame is received, even if the Logical Address Filter is programmed in such a way that a Broadcast frame would pass the hash ﬁlter. If DRCVBC is set to 1 and the Logical Address Filter is programmed in such a way that a Broadcast frame would pass the hash ﬁlter, LAFM will be set on the reception of a Broadcast frame.

When the Am79C978 controller operates in promiscuous mode and none of the three match bits is set, it is an indication that the Am79C978 controller has only accepted the frame because it was in promiscuous mode.

When the Am79C978 controller is not programmed to be in promiscuous mode, then when none of the three match bits is set, it is an indication that the Am79C978 controller only accepted the frame because it was not rejected. See Table 10 for receive address matches.

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74 Am79C978

PRELIMINARY

Table 10. Receive Address Match

Automatic Pad Stripping

During reception of an IEEE 802.3 frame, the pad ﬁeld can be stripped automatically. Setting ASTRP_RCV (CSR4, bit 0) to 1 enables the automatic pad stripping feature. The pad ﬁeld will be stripped before the frame is passed to the FIFO, thus preserving FIFO space for additional frames. The FCS ﬁeld will also be stripped, since it is computed at the transmitting station based on the data and pad ﬁeld characters, and will be inv alid for a receive frame that has had the pad characters stripped.

The number of bytes to be stripped is calculated from the embedded length ﬁeld (as deﬁned in the ISO 88023 (IEEE/ANSI 802.3) deﬁnition) contained in the frame. The length indicates the actual number of LLC data bytes contained in the message. Any received frame which contains a length ﬁeld less than 46 bytes will have the pad ﬁeld stripped (if ASTRP_RCV is set). Receive frames which have a length ﬁeld of 46 bytes or greater will be passed to the host unmodiﬁed.

Figure 36 shows the byte/bit ordering of the received length ﬁeld for an IEEE 802.3-compatible frame f ormat.

Since any valid Ethernet Type ﬁeld value will always be greater than a normal IEEE 802.3 Length ﬁeld (≥46), the Am79C978 controller will not attempt to strip valid Ethernet frames.

Note that for some network protocols,

the value passed in the Ethernet Type and/or IEEE

802.3 Length ﬁeld is not compliant with either standard and may cause problems if pad stripping is enabled

Receive FCS Checking

Reception and checking of the received FCS is performed automatically by the Am79C978 controller. Note that if the Automatic Pad Stripping feature is enabled, the FCS for padded frames will be ver iﬁed against the value computed for the incoming bit stream including pad characters, but the FCS value for a padded frame will not be passed to the host. If an FCS error is detected in any frame, the error will be reported in the CRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two distinct categories, i.e., those conditions which are the result of normal network operation, and those which occur due to abnormal network and/or host related events.

Normal events which may occur and which are handled autonomously by the Am79C978 controller are basically collisions within the slot time and automatic runt packet rejection. The Am79C978 controller will ensure that collisions that occur within 512 bit times from the start of reception (excluding preamble) will be automatically deleted from the receive FIFO with no host intervention.

PAM LAFM BAM DRCVBC Comment

000 X

Frame accepted due to PROM = 1

100 X

Physical address match

010 0

Logical address ﬁlter match; frame is not of type broadcast

010 1

Logical address ﬁlter match; frame can be of type broadcast

0 0 1 0 Broadcast frame

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Am79C978 75

PRELIMINARY

Figure 36. IEEE 802.3 Frame and Length Field Transmission Order

The receive FIFO will delete any frame that is composed of fewer than 64 bytes provided that the Runt Packet Accept (RPA bit in CSR124) feature has not been enabled and the network interface is operating in half-duplex mode, or the full-duplex Runt Packet Accept Disable bit (FDRPAD, BCR9, bit 2) is set. This criterion will be met regardless of whether the receive frame was the ﬁrst (or only) frame in the FIFO or if the receive frame was queued behind a previously received message.

Abnormal network conditions include:

■ FCS errors

■ Late collision

Host related receive exception conditions include MISS, BUFF, and OFLO. These are descr ibed in the

Buffer Management Unit

section.

Loopback Operation

Loopback is a mode of operation intended for system diagnostics. In this mode, the transmitter and receiver are both operating at the same time so that the Am79C978 controller receives its own transmissions. The Am79C978 controller provides two basic types of loopback. In internal loopback mode, the transmitted data is looped back to the receiver inside the Am79C978 controller without actually transmitting any data to the external network. The receiver will move the received data to the next receiv e buff er , where it can be examined by software. Alternatively, in external loop-

back mode, data can be transmitted to and received from the external network.

Refer to Table 30 for various bit settings required for Loopback modes.

The external loopback requires a two-step operation. The internal PHY must be placed into a loopback mode by writing to the PHY Control Register (BCR33, BCR34). Then, the Am79C978 controller must be placed into an external loopback mode by setting the Loop bits.

Miscellaneous Loopback Features

All transmit and receive function programming, such as automatic transmit padding and receive pad stripping, operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled (RPA bit in CSR124 is not affected) when any loopback mode is invoked. This is to be backwards compatible to the C-LANCE (Am79C90) software.

Since the Am79C978 controller has two FCS generators, there are no more restrictions on FCS generation or checking, or on testing multicast address detection as they exist in the half-duplex PCnet family devices and in the C-LANCE. On receive, the Am79C978 controller now provides true FCS status. The descriptor for a frame with an FCS error will have the FCS bit (RMD1, bit 27) set to 1. The FCS generator on the transmit side can still be disabled by setting DXMTFCS (CSR15, bit

3) to 1.

Preamble

1010....1010

SFD

10101011

Destination

Address

Source

Address

Length

LLC

Data

Pad FCS

Bytes

46 – 1500

Bytes

Bits

Start of Frame

at Time = 0

Increasing Time

Bit

Bit 7Bit

Bit

Most

Significant

Byte

Least

Significant

Byte

1 – 1500

Bytes

45 – 0 Bytes

22206B-39

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76 Am79C978

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In internal loopback operation, the Am79C978 controller provides a special mode to test the collision logic. When FCOLL (CSR15, bit 4) is set to 1, a collision is forced during every transmission attempt. This will result in a Retry error.

Full-Duplex Operation

TheAm79C978 controller supports full-duplex operation on the 10BASE-T and MII interfaces. Full-duplex operation allows simultaneous transmit and receiv e activity. Full-duplex operation is enabled by the FDEN bit located in BCR9. Full-duplex operation is also enabled through Auto-Negotiation when D ANAS (BCR 32, bit 7) is not enabled and the ASEL bit is set, and its link partner is capable of Auto-Negotiation and full-duplex operation.

When operating in full-duplex mode, the following changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

■ The ﬁrst 64 bytes of every transmit frame are not preserved in the Transmit FIFO during transmission of the ﬁrst 512 bits as described in the

Transmit Ex-

ception Conditions

section. Instead, when full-duplex mode is active and a frame is being tr ansmitted, the XMTFW bits (CSR80, bits 9-8) always govern when transmit DMA is requested.

■ Successful reception of the ﬁrst 64 bytes of every receive frame is not a requirement for Receiv e DMA to begin as described in the

Receive Exception Con-

ditions

section. Instead, receive DMA will be requested as soon as either the RCVFW threshold (CSR80, bits 12-13) is reached or a complete valid receive frame is detected, regardless of length. This Receive FIFO operation is identical to when the RPA bit (CSR124, bit 3) is set during half-duplex mode operation.

The MAC engine changes for full-duplex operation are as follows:

■ Changes to the transmit deferral mechanism: — Transmission is not deferred while receive is

active.

— The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits is started when transmit activity for the ﬁrst packet ends, instead of when transmit and carrier activity ends.

■ The 4.0 µs carrier sense blinding period after a transmission during which the SQE test normally occurs is disabled.

■ The collision indication input to the MAC engine is ignored.

The internal PHY changes for full-duplex operation are as follows:

■ The collision detect (COL) pin is disabled.

■ The SQE test function is disabled.

■ Loss of Carrier (LCAR) reporting is disabled.

■ PHY Control Register (TBR0) bit 8 is set to 1 if Auto-

Negotiation is disabled.

Full-Duplex Link Status LED Support

TheAm79C978 controller provides bits in each of the LED Status registers (BCR4, BCR5, BCR6, BCR7, and BCR48) to display the Full-Duplex Link Status. If the FDLSE bit (bit 8) is set, a value of 1 will be sent to the associated LEDOUT bit when in Full-Duplex.

PHY/MAC Interface

The internal MII-compatible interface provides the data path connection between the 10BASE-T PHY, the 1 Mbps HomePNA PHY, and the 10/100 Media Access Controller (MAC). The interface is compatible with Clause 22 of the IEEE 802.3 standard speciﬁcation.

10BASE-T Physical Layer

The 10BASE-T block consists of the following subblocks:

— Transmit Process — Receive Process — Interface Status — Collision Detect Function — Jabber Function — Reverse Polarity Detect

Refer to Figure 37 for the 10BASE-T block diagram.

Twisted Pair Transmit Function

Data transmission over the 10BASE-T medium requires use of the integrated 10BASE-T MAU and uses the differential driver circuitry on the TX± pins.

TX± is a differential twisted-pair driver. When properly terminated, TX± will meet the transmitter electrical requirements for 10BASE-T transmitters as speciﬁed in IEEE 802.3, Section 14.3.1.2. The load is a twisted pair cable that meets IEEE 802.3, Section 14.4.

The TX± signal is ﬁltered on the chip to reduce harmonic content per Section 14.3.2.1 (10BASE-T). Since ﬁltering is performed in silicon, TX± can be connected directly to a standard transformer. External ﬁltering modules are not needed.

Twisted Pair Receive Function

The RX+ port is a differential twisted-pair receiver. When properly terminated, the RX+ por t will meet the electrical requirements for 10BASE-T receivers as speciﬁed in IEEE 802.3, Section 14.3.1.3. The receiver has internal ﬁltering and does not require external ﬁlter modules or common mode chokes.

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Am79C978 77

PRELIMINARY

Signals appearing at the RX± differential input pair are routed to the internal decoder. The receiver function meets the propagation delays and jitter requirements speciﬁed by the 10BASE-T standard. The receiver squelch level drops to half its threshold value after unsquelch to allow reception of minimum amplitude signals and to mitigate carrier fade in the event of worst case signal attenuation and crosstalk noise conditions.

Figure 37. 10BASE-T Transmit and Receive Data

Paths

Twisted Pair Interface Status

The Am79C978 device will power up in the Link Fail state. The Auto-Negotiation algor ithm will apply to allow it to enter the Link Pass state.

In the Link Pass state, receiv e activity which passes the pulse width/amplitude requirements of the RX± inputs will cause the PCS Control block to assert Carrier Sense (CRS) signal at the internal MII interface. A collision would cause the PCS Control block to assert Carrier Sense (CRS) and Collision (COL) signals at the internal MII. In the Link Fail state, this block would cause the PCS Control block to de-assert Carrier Sense (CRS) and Collision (COL).

In jabber detect mode, this block w ould cause the PCS Control block to assert the COL signal at the internal MII and allow the PCS Control block to assert or de-assert the CRS pin to indicate the current state of the RX± pair. If there is no receive activity on RX±, this block would cause the PCS Control b lock to assert only the COL pin at the internal MII. If there is RX± activity,

this block would cause the PCS Control b lock to assert both COL and CRS at the internal MII.

Collision Detect Function

Simultaneous activity (presence of valid data signals) from both the internal encoder transmit function and the twisted pair RX± pins constitutes a collision, thereby causing the PCS Control block to assert the COL pin at the internal MII.

Jabber Function

The Jabber function inhibits the 10BASE-T twisted pair transmit function of the Am79C978 device if the TX± circuits are active for an e xcessive period (20-150 ms). This prevents one port from disrupting the network due to a

stuck-on

or faulty transmitter condition. If the maximum transmit time is exceeded, the data path through the 10BASE-T transmitter circuitry is disabled (although Link Test pulses will continue to be sent). The PCS Control block also asserts the COL signal at the internal MII and sets the Jabber Detect bit in Register 1 of the active PHY. Once the internal transmit data stream from the MENDEC stops, an

unjab

time of 250750 ms will elapse before this block causes the PCS Control block to de-assert the COL indication and reenable the transmit circuitry.

When jabber is detected, this block will cause the PCS Control block to assert the COL signal and allow the PCS Control block to assert or de-assert the CRS signal to indicate the current state of the RX± pair. If there is no receive activity on RX±, this block causes the PCS Control block to assert only the COL signal at the internal MII. If there is RX± activity, this block will cause the PCS Control block to assert both COL and CRS on the internal MII.

Reverse Polarity Detect

The polarity for 10BASE-T signals is set by reception of Normal Link Pulses (NLP) or packets. Polarity is locked, however, by incoming packets only. The ﬁrst NLP received when trying to bring the link up will be ignored, but it will set the polarity to the correct state. The reception of two consecutive pack ets will cause the polarity to be locked, based on the polarity of the ETD. In order to change the polarity once it has been locked, the link must be brought down and back up again.

Auto-Negotiation

The object of the Auto-Negotiation function is to determine the abilities of the devices sharing a link. After e xchanging abilities, the Am79C978 device and remote link partner device acknowledge each other and make a choice of which advertised abilities to support. The Auto-Negotiation function facilitates an ordered resolution between exchanged abilities. This exchange allows both devices at either end of the link to take

Clock Data

Manchester

Encoder

Clock Data

Manchester

Decoder

Squelch

Circuit

RX Driver

RX±TX±

TX Driver

22206B-40

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78 Am79C978

PRELIMINARY

maximum advantage of their respective shared abilities.

The Am79C978 device implements the transmit and receive Auto-Negotiation algorithm as deﬁned in IEEE

802.3u, Section 28. The Auto-Negotiation algorithm uses a burst of link pulses called Fast Link Pulses (FLPs). The b urst of link pulses are spaced between 55 and 140 µs so as to be ignored by the standard 10BASE-T algorithm. The FLP burst conveys information about the abilities of the sending device. The receiver can accept and decode an FLP burst to learn the abilities of the sending device. The link pulses transmitted conform to the standard 10BASE-T template. The device can perform auto-negotiation with rev erse polarity link pulses.

The Am79C978 device uses the Auto-Negotiation algorithm to select the type connection to be established according to the following priority: 10BASE-T full duplex, then 10BASE-T half-duplex. See Table 11.

The Auto-Negotiation algorithm is initiated by the following ev ents: Auto-Negotiation enable bit is set, hardware reset, soft reset, transition to link fail state (when Auto-Negotiation enable bit is set), or A uto-Negotiation restart bit is set. The result of the A uto-Negotiation process can be read from the status register (Summary Status Register, TBR24).

By default, the link partner must be at least 10BASE-T half-duplex capable. The Am79C978 controller can automatically negotiate with the network and yield the highest performance possible without software sup-

port. See the

Network Port Manager

section for more

details.

Auto-Negotiation goes further by providing a messagebased communication scheme called

be-

fore connecting to the Link Partner.

This feature is not supported in the Am79C978 device unless the DANAS (BCR32, bit 10) is selected.

Soft Reset Function

The PHY Control Register (TBR0) incorporates the soft reset function (bit 15). It is a read/write register and is self-clearing. Writing a 1 to this bit causes a soft reset. When read, the register returns a 1 if the soft reset is still being performed; otherwise, it is cleared to 0.

Note that the register can be polled to verify that the soft reset has terminated

. Under normal operating condi-

tions, soft reset will be ﬁnished in 150 clock cycles. Soft reset only resets the 10BASE-T PHY unit registers

to default values (some register bits retain their previous values). Refer to the individual registers for values after a soft reset. Soft reset does not reset the management interface.

Table 11. Auto-Negotiation Capabilities

Network Speed Physical Network Type

20 Mbps 10BASE-T, Full Duplex 10 Mbps 10BASE-T, Half Duplex

Page 79

Am79C978 79

PRELIMINARY

DETAILED FUNCTIONS 1 Mbps HomePNA PHY

The integrated HomePNA transceiver is a physical layer de vice supporting the HomePNA speciﬁcation 1.0 for home phoneline networking. It provides all of the PHY layer functions required to support 1 Mbps data transfer speeds ov er common residential phone wiring.

All data bits are encoded into the relative time position of a pulse with respect to the previous one, the waveform on the wire consists of a 7.5 MHz carrier sinusoid enclosed within an exponential (bell shaped) env elope. The waveform is produced by generating four 7.5 MHz square wave cycles and passing them through a bandpass ﬁlter.

The HomePNA PHY frame consists of a HomePNA header that replaces the normal Ethernet 64-bit preamble and delimiter and is prepended to a standard Ethernet packet starting with the source address and ending with the CRC.

Only the PHY layer and its parameters are modiﬁed from that of the standard Ethernet implementation. The HomePNA PHY layer is designed to operate with a standard Ethernet MAC layer controller implementing all the CSMA/CD protocol features.

The frame begins with a characteristic SYNC interval that delineates the beginning of a HomePNA frame followed by an Access ID (AID) which encodes 8 bits of Access ID and 4 bits of control word. The Access ID is used to detect collisions and is dynamically assigned, while the control word carries speed and power information.

The AID is followed b y a silence interval, then 32 bits of data reserved for PHY lay er communication. These bits are accessible via HPR20 and HPR21 and are for future use.

The data encoding consists of two symbol types: an AID symbol and a data symbol. The AID symbol is always transmitted at the same speed and encodes two bits that determine the pulse position (one of four) relative to the previous pulse . The access symbol interval is ﬁxed.

The data symbol interval is variable. The arriving bit stream is blocked into from 3 to 6 bit blocks according to a proprietary (RLL25™) algorithm. The bits in each block are then used to encode a data symbol. Each symbol consists of a Data Inter Symbol Blanking Interval (DISBI) and then a pulse at one of twenty-ﬁve possible positions. The bits in the data block determine the pulse position. Immediately after the pulse a new symbol interval begins. During the DISBI the receiver ignores all incoming pulses to allow network reﬂections to die out.

Any station may be programmed to assume the role of a PHY master and remotely command, via the control word, the rest of the units on the network to change their transmit speed or power level.

Many of the framing parameters are programmable in the HomePNA PHY and will allow future modiﬁcations to both transmission speed as well as noise and reﬂection rejection algorithms.

Two default speeds are provided, low at 0.7 Mbps and high at 1 Mbps. The center frequency is also programmable for future use.

HomePNA PHY Medium Interface

Framing

The HomePNA frame on the phone wire network consists of a header generated in the PHY prepended to an IEEE 802.3 Ethernet data packet received from the MAC layer. See Figure 38.

When transmitting on the phone wire pair, the HomePNA PHY ﬁrst receives an Ethernet MAC frame from the MAC. The 8 octets of preamble and delimiter are stripped off and replaced with the HomePNA PHY header described below, then tr ansmitted on the phone wire network.

During a receive operation, the rev erse process is e xecuted. When a HomePNA frame is received by the PHY, the header is stripped off and replaced with the four octets of preamble and delimiter of the IEEE 802.3 Ethernet MAC frame speciﬁcation and then passed on to the MAC layer.

Page 80

80 Am79C978

PRELIMINARY

Figure 38. HomePNA PHY Framing

HomePNA Symbol Waveform

All HomePNA symbols are composed at the transmitter of a silence interval, and a pulse formed of an integer number of cycles (TX_PULSE_CYCLES_P/N in HPR29) of a square wave of frequency (CENTER_FREQUENCY TX_PULSE_WIDTH in HPR29) that has been ﬁltered with a bandpass ﬁlter. Data is encoded in the time interval from the preceding pulse.

Table 12. HomePNA PHY Pulse Parameters

Time Interval Unit

HomePNA PHY time intervals are expressed in Time Interval Clock (TIC) units. One TIC is deﬁned as 7/60E6 seconds or approximately 116.7 ns.

ACCESS ID Intervals

A HomePNA frame begins with an Access ID (AID) interval which is composed of eight equally spaced subintervals termed AID symbols 0 through 7 as shown in Figure 38.

An AID symbol is 128 TICs long. Transmit timing is shown in Figure 39; receive timing in Figure 40. Timing starts at the beginning of each AID symbol at TIC = 0 and ends at TIC = 128.

These symbols are described in the following sections.

Symbol 0 (SYNC interval)

SYNC T ransmit Timing

The SYNC interval (AID symbol 0) delineates the beginning of a HomePNA frame and is composed of a SYNC_START pulse, follow ed b y a SYNC_END pulse , after a ﬁxed silence interval as shown in Figure 39. Timing for this (AID symbol 0) starts (TIC = 0) at the beginning of the SYNC_START pulse. The SYNC_END pulse starts at TIC = 126.

At TIC = 128, this AID symbol 0 ends and the next AID symbol begins, with the symbol timing reference reset to TIC = 0. No information bits are coded in the SYNC (AID symbol 0 interval).

SYNC Receive Timing

As soon as the SYNC_START pulse is detected the receiver disables (blanks) further detection until time TIC = 61, after which detection is re-enabled for the ne xt received pulse. The receiver allows for jitter by establishing a window around each legal pulse position. This window is two TICS wide on either side of the position.

A SYNC_END pulse that arrives outside the window of the legal TIC = 126 is considered a noise event which is used in setting the adaptive squelch lev el, aborts the packet, and sets the receiver in search of a new SYNC_START pulse and SYNC interval. If it is a transmitting station, the COLLISION event is asserted as described in the

Collisions

section.

SYNC

interval

Access ID Silence

PCOM

4 bytes

Source

destination

6 bytes

Length 2ETHERNET MAC and DATA

max 1500

CRC

32 bits PCOM

Ethernet Packet

Fixed

14.93 µs

AID blanking interval

01 11 10 00 01 00

60 tics

128 tics 128 tics 128 tics 128 tics 128 tics 128 tics 128 tics

Data

symbols

20 tics 66 tics

Silence interval

SYNC Symbol 0

ACCESS ID Symbol 1

ACCESS ID Symbol 2

ACCESS ID Symbol 3

ACCESS ID Symbol 4

ACCESS ID Symbol 5

ACCESS ID Symbol 6

ACCESS ID Symbol 7

30.75 µs @ 1 Mbps

ACCESS ID interval Example Access ID of 01110100 and control word 0100

Fixed 119.44 µs

HomePNA PHY Header

150.19 µs @ 1 Mbps 1 Tic = 116.6667 ns

HomePNA Header Ethernet Packet

pulse

128 tics

= receiver blanking interval

potential pulse position

22206B-41

Parameter Value Tolerance Unit

CENTER_FREQUENCY 7.5 500 PPM MHz CYCLES_PER_PULSE 4 -- Cycles

Page 81

Am79C978 81

PRELIMINARY

Figure 39. AID Symbol Transmit Timing

Figure 40. AID Symbol Receive Timing

AID Symbols 1 through 6

AID symbols 1 through 4 are used to identify individual stations to enable reliable collision detection as described in the

Collisions

section. Symbols 5 and 6 are used to transmit remote control management commands across the network. Coding and timing details are as follows.

The SYNC interval is followed by six AID symbols (symbols 1 through 6). Transmit timing is shown in Figure 39; receive timing in Figure 40. Data is encoded in

the relative position of each pulse with respect to the previous one. A pulse may occur at one, and only one, of the four possible positions within an AID symbol yielding two bits of data coded per AID symbol.

The decoded bits from the AID symbols 1 to 4 produce eight bits of Access ID which is used to identify individual HomePNA stations and to detect collisions. The MSB is encoded in AID Symbol 1 and is the leftmost bit in Table 13.

AID Symbol 0 AID Symbol 1 AID Symbol 2

pulse 2 shown in position 1

pulse 0

pulse 1

TIC=12 8 and TIC=0

SYNC_STAR T TIC=0

SYNC_END

TIC=126

AID_Position_0

TIC=66

AID_Position_1

TIC=86

AID_Position_2

TIC=106 AID_Position_3

TIC=126

Transmitter

22206B-42

AID Symbol 0 AID Symbol 1 AID Symbol 2

pulse 2 shown in position 1

pulse 0 pulse 1

TIC=128 and TIC=0

TIC=12 8 and TIC=0

SYNC_START TIC=0

SYNC_END

TIC=126

AID_Position_0

TIC=66

AID_Position_1

TIC=86

AID_Position_2

TIC=106 AID_Position_3

TIC=126

Receiver

AID slice threshold

END_RCV_BLANK

AID_GUARD_INTERVAL

Detected envelope

22206B-43

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82 Am79C978

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T ab le 13. Access ID Symbol Pulse Positions and

Encoding

The next two AID symbols (5 and 6) encode f our bits of control word information. The MSB is encoded in AID Symbol 5. Control word messages are described further in the

Management Interfaces

section.

AID T ransmit Timing

The transmitter encodes the Access ID in a pulse position in each 128 TIC interval. Each AID symbol interval must have only one pulse. Pulse transmission must start in only one of the four possible positions (measured from the beginning of the Access ID symbol) deﬁned in Table 13.

AID Receive Timing

The receiver allows for jitter by establishing a window around each legal pulse position. This window is two TICS wide on either side of the position. A pulse that arrives outside of the legal AID positions is considered a COLLISION event.

Collisions

A Collision is detected only during Access ID and silent intervals (AID symbols 0 through 7). In general during a collision, a transmitting station will read back an AID value that does not match its own and recognizes the event as a collision and alerts other stations with a JAM signal. Non-tr ansmitting stations ma y also detect some collisions by interpreting received non-conforming AID pulses as collisions.

With two transmitters colliding, each transmitter normally blanks its receive input immediately after transmitting (and simultaneously receiving) a pulse. Therefore, only when a transmitting station receives pulses in a position earlier than the position it transmitted will it recognize it as a pulse transmitted by another station and signal a collision.

For this reason, guaranteed collision detection is possible only as long as the spacing between successive possible pulse positions in an AID symbol (20 TICs or

2.3 µs) is greater than the round trip delay between the colliding nodes. At approximately 1.5 ns propagation delay per foot, the maximum distance between two HomePNA units must not be greater than 500 feet for collision detection purposes (1.5 µs round trip delay plus margin).

The following criteria must be met to guarantee reliable collision detection:

At least one HomePNA station of a colliding group must always detect a collision when the delay between the beginning of its transmitted packet and the beginning of the received colliding packet is between -1.5 µs and +1.5 µs.

In general, any received pulse at a HomePNA station that does not conform to the pulse position requirements of AID symbols 0 through 7 shall indicate a collision on the wire. When a transmitting station senses a collision, it emits a JAM signal to alert all other stations to the collision. The following conditions signify a COLLISION event:

1. A HomePNA station receives an AID that does not match the one being sent.

2. A HomePNA station receives a pulse outside the AID_GUARD INTERVAL in AID intervals 0 to 7.

3. A HomePNA station receives a pulse inside the SILENT_INTERVAL (AID symbol 7).

As in all cases, pulses received during a blanking interval are ignored.

Passive stations (stations not actively transmitting during the collision) cannot reliably detect collisions. Therefore, once a collision is detected by a tr ansmitting station, the station must inform the rest of the stations of the collision with a JAM pattern described below. Only a transmitting station emits a JAM signal.

Once a collision is detected, the COLLISION signal to the MAC interface is asserted and is not reset until the MAC deactivates the TXEN signal.

JAM Signal

A JAM pattern consists of 1 pulse every 32 TICs and continues until at least the end of the AID intervals. After the AID interval, the JAM pattern will continue until TXEN from the MAC is deactivated.

ACCESS ID Values

The access ID values for slave stations are picked by each individual station randomly from the set of AID slave numbers described in the management section. During operation, each HomePNA station monitors HomePNA frames received on the wire. If it detects another HomePNA station using the same AID, it will select a new random AID.

Silence Interval (AID symbol 7)

The Access ID symbols are followed by a ﬁxed silence interval of 128 TICs. The receive blanking interval is the same as that of the AID symbols (1 through 6).

Any pulses detected in the silence interval are considered a COLLISION event for transmitting stations and are handled as described in the

Collisions

section.

Pulse

Position

TICs from Beginning of AID

Symbol Bit Encoding

1 66 00 286 01 3 106 10 4 126 11

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Am79C978 83

PRELIMINARY

Data Symbols

Data symbols encode data for a much higher transmission rate, and they do not allow collision detection.

Data T ransmit Timing

A data symbol interval begins with the beginning of transmission of a pulse as shown in Figure 41. Transmit Symbol timing (in TICS) is measured from this point (TIC = 0).

Depending on the data code, the next pulse ma y begin at any PULSE_POSITION_N where N = 0 to 24. Each position is separated from the previous one by one TIC .

PULSE_POSITION_0 occurs at a value deﬁned in Table 14 which determines the transmission speed. When a pulse begins transmission, the previous symbol interval ends and a new one begins immediately.

Table 14. Blanking Interval Speed Settings

Figure 41. Transmit Data Symbol Timing

Data Receive Timing

The incoming waveform is formed from the transmitted pulse. The receiv er detects the point at which the env elope of the received waveform crosses a set threshold. See Figure 42.

Immediately after the threshold crossing, the receiver disables any further detection for a period ISBI-3 TICs (HPR28 ISBI_SLOW or ISBI_FAST) star ting with the detection of the pulse peak.

The receiver is then re-enabled for pulse detection. Upon reception of the next pulse, the receiver measures the elapsed time from the previous pulse. This value is then placed in the nearest pulse position bin (one of 25) where pulse position 0 is at PULSE_POSITION_0 and each subsequent position is spaced one TIC from the pre vious one as deﬁned in the

Data Transmit Timing

section. Data symbol intervals are therefore variable and depend on the encoded data.

Figure 42. Receive Symbol Timing

Speed Setting

Nominal Data

Rate

PULSE_POSITION_0

Value

(in TICs)

LOW_SPEED 0.7 Mbps 44

HIGH_SPEED 1.0 Mbps 28

Symbol 1 Symbol 2

Pulse 0 Data Blanking interval (DISBI) Pulse 1 Pulse 21 TIC

START_TX_PULSE TIC=0

END_TX_PULSE time

PULSE_POSITION_0 time

Position 1 Position n1 Position 0 Position 1 Position n2

n=0-24

Transmitter

22206B-44

Symbol 1 Symbol 2

Pulse 0

Detected Envelope

Pulse 1 Pulse 2

Begin of receive Blanking interval

END_DATA_BLANK

Position 1 Position n1 Position 0 Position 1 Position n2Position 0

Data slice threshold

Receiver

22206B-45

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84 Am79C978

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Data Symbol RLL25 Encoding

The RLL25 code is the version of TM32 that was de v eloped for the HomePNA PHY. It produces both the highest bit rate for a given value of ISBI and TIC size. In a manner similar to run length limited disk coding, RLL25 encodes data bits in groups of varying sizes, speciﬁcally: 4, 5, 6, and 7 bits. Pulse positions are assigned to the encoded bit groups in a manner, which causes more data bits to be encoded in positions that are farther apart. This keeps both the average and minimum bit rates higher.

Data symbol RLL25 codes data by trav ersing a tree as illustrated in Figure 43. Assume that successive data bits to be encoded are labeled A, B, C, D,…, etc. The encoding process begins at the root node and proceeds as follows:

1. If the ﬁrst bit (bit A) is a one, the next three bits (B, C, and D) select which one of the eight positions 18 is transmitted. The encoding process then continues at the root node.

2. If bit A is a zero and bit B is a one, the next three bits (C, D, and E) select which one of the eight positions 9-16 is transmitted. The encoding process then continues at the root node.

3. If bit A is a zero, bit B is a zero, and bit C is a one, the next three bits (D, E, and F) select which one of the eight positions 17-24 is transmitted. The encoding process then continues at the root node.

4. Finally, if bits A, B, and C are all zeros, position 0 is transmitted. The encoding process then continues at the root node.

As a result, Symbol 0 encodes the 3-bit data pattern 000, positions 1-8 encode the 4-bit data pattern 1BCD, positions 9-16 encode the 5-bit data pattern 01CDE, and positions 17-24 encode the 6-bit data pattern 001DEF. If the data encoded is r andom, 50% of the positions used will be for 4-bit patterns, 25% will be for 5bit patterns, 12.5% will be for 6-bit patterns, and 12.5% will be for 3-bit patterns.

Management Interfaces

The HomePNA PHY may be managed from either of two interfaces (the managed parameters vary depending on the interface):

1. Remote Control-Word management commands embedded in the HomePNA AID header on the wire network.

2. Management messages from a local management entity.

Figure 43. RLL 25 Coding Tree

C D

These select position 1 - 8

A B E F

Awaiting coding and transmissionEncoded and

Start: Examine the next bits to be encoded

C D1 B

These select position 9 - 16

C D0 1 E

These select position 17- 24

1 D0 0 E F

00 0

A = ?

B = ?

C = ?

Send symbol 1-8

Send symbol 9-16

Send symbol 17-24

Send symbol 0

Data stream from MAC controller

22206B-46

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Header AID Remote Control Word Commands

Stations may be conﬁgured either as master stations or as slave stations. Only one master may exist on a given HomePNA segment.

The master station may send commands embedded in the HomePNA header control word to remotely set various parameters of the remote slave stations. Stations are identiﬁed via the AID as follows:

1. The master station is identiﬁed on the HomePNA wire network with an AID of FFh.

2. A slave is identiﬁed with an AID of 00h to EFh.

3. AID values of F0h to FEh are reserved for future use.

Once a command has been transmitted, the master station will revert to a slave AID, so that subsequent control words are not interpreted as new commands.

Master mode is entered by writing to the PHY control register (HPR16) and is exited upon the completion of the command sequence.

A valid master remote command consists of three HomePNA frames with an AID of FFh. Since the HomePNA header is prepended to packets received from the MAC, pac kets from the master station may be separated by intervals during which other (slave) stations may transmit their frames.

A remote master Control Word command must be recognized and ex ecuted b y a HomePNA PHY when it receives three consecutive valid HomePNA frames with an AID of FFh.

If HPR16, bit 15 is not set to 0, valid commands are as follows:

1. SET_POWER: Commands slave stations to set their transmit level to a prescribed level.

2. SET_SPEED: Commands sla ve stations to set their transmit speed to a prescribed value.

The control word bit encoding and possible values are described in Table 15.

Table 15. Master Station Control Word Functions

All stations will transmit the following status messages in the HomePNA header control word of all outgoing frames:

1. VERSION_STATUS: The HomePNA PHY version of the slave station.

2. POWER_STATUS: The transmit power level of the transmitting slave station for the current frame. All HomePNA units support LOW_POWER and HIGH_POWER modes.

3. SPEED_STATUS: The transmit speed of the slave station for the current frame. Receiving stations will adjust their receiver parameters to correctly interpret this frame.

The slave control word bit encoding and possible values are described in Table 16.

Table 16. Slave Station Control Word Status

Conditions

PHY Control and Management Block (PCM Block)

The management interface speciﬁed in Clause 22 of the IEEE 802.3u standard provides for a simple two wire, serial interface to connect a management entity and a managed PHY for the purpose of controlling the PHY and gathering status information. The two lines are Management Data Input/Output (MDIO) and Management Data Clock (MDC). A station management entity which is attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for each PHY entity.

Description of the Methodology

The management interface physically transports management information across the internal MII. The information is encapsulated in a frame format as speciﬁed in Clause 22 of the IEEE 802.3u draft standard and is shown in Table 17.

Bit No. Command Function

0 = version 0 (All stations revert to version 0 HomePNA PHY mode of operation).

0 = Set transmit to low speed. 1 = Set transmit to high speed.

0 = Set to low power transmit mode. 1 = Set to high power transmit mode.

3 Reserved

Bit # Indicated Status

0 = This station is version 0. 1 = This station is not version 0.

0 = Frame transmitted at low speed. 1 = Frame transmitted at high speed.

0 = Frame transmitted at low power. 1 = Frame transmitted at high power.

3 Reserved

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Table 17. MII Control Frame Format

The start ﬁeld (ST) is followed by the operation ﬁeld (OP). The operation ﬁeld (OP) indicates whether the operation is a read or a write operation. This is followed by the PHY address (PHYAD) and the register address (REGAD) that was programed into BCR33 of the Fast Ethernet controller. This ﬁeld is followed by a bus turnaround ﬁeld (TA). During the read operation, the bus turnaround ﬁeld is used to determine if the PHY is responding properly to the read request. The data ﬁeld to/ from the MAC controller is then written to or read from BCR34. The ﬁnal ﬁeld is the idle ﬁeld, and it is required to allow the drivers to turn off.

The PHYADD ﬁeld, which is ﬁve bits wide, allows 32 unique PHY addresses. The managed PHY layer device that is connected to a station management entity via the MII interface has to respond to transactions addressed to the PHY's address. A station management entity attached to multiple PHYs is required to have prior knowledge of the appropriate PHY address.

No SRAM Conﬁguration

If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the SRAM size register, the controller will assume that there is no SRAM present and will reconﬁgure the four internal FIFOs into two FIFOs, one for transmit and one for receive. The FIFOs will operate the same as in the PCnet-PCI II controller. When the SRAM_SIZE (BCR25, bits 7-0) value is 0, the SRAM_BND (BCR26, bits 7-0) are ignored by the controller. See Figure 44.

Low Latency Receive Conﬁguration

If the LOLATRX (BCR27, bit 4) bit is set to 1, then the controller will conﬁgure itself for a low latency receive conﬁguration. In this mode, SRAM is required at all times. If the SRAM_SIZE (BCR25, bits 7-0) value is 0,

the controller will not conﬁgure for low latency receive mode. The controller will provide a fast path on the receive side bypassing the SRAM. All transmit trafﬁc will go to the SRAM, so SRAM_BND (BCR26, bits 7-0) has no meaning in low latency receive mode. When the controller has received 16 bytes from the network, it will start a DMA request to the PCI Bus Interface Unit. The controller will not wait for the ﬁrst 64 bytes to pass to check for collisions in Low Latency Receive mode. The controller must be in STOP before switching to this mode. See Figure 45.

CAUTION: To provide data integrity when switching into and out of the low latency mode, DO NO T SET the FASTSPNDE bit when setting the SPND bit. Receive frames WILL be overwritten and the controller may giv e erratic behavior when it is enabled again.

Direct SRAM Access

The SRAM can be accessed through the Expansion Bus Data port (BCR30). To access this data por t, the user must load the upper address EPADDRU (BCR29, bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the user will load the lower 16 bits of address EPADDRL (BCR28, bits 15-0). To initiate a read, the user reads the Expansion Bus Data Port (BCR30). This slave access from the PCI will result in a retry for the very ﬁrst access. Subsequent accesses may give a retry or not, depending on whether or not the data is present and valid. The direct SRAM access uses the same FLASH/ EPROM access except for accessing the SRAM in word format instead of byte format. This access is meant to be a diagnostic access only. The SRAM can only be accessed while the controller is in STOP or SPND (FASTSPNDE is set to 0) mode.

PRE ST OP PHYAD REGAD TA DATA IDLE

READ 1.1 01 10 AAAAA RRRRR Z0 D31………D0 Z

WRITE 1.1 01 01 AAAAA RRRRR 10 D31………D0 Z

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Figure 44. Block Diagram No SRAM Conﬁguration

Figure 45. Block Diagram Low Latency Receive Conﬁguration

PCI Bus

Interface

Unit

802.3 MAC Core

Bus Rcv

FIFO

MAC

Rcv

FIFO

Bus Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

and

10BASE-T

and

HomePNA

PHYs

22206B-47

PCI Bus

Interface

Unit

802.3 MAC Core

Bus Rcv

FIFO

MAC

Rcv

FIFO

Bus Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

SRAM

and

10BASE-T

and

HomePNA

PHYs

22206B-48

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EEPROM Interface

The controller contains a built-in capability for reading and writing to an external serial 93C46 EEPROM. This built-in capability consists of an interface f or direct connection to a 93C46 compatible EEPROM, an automatic EEPROM read feature, and a user-programmable register that allows direct access to the interface pins.

Automatic EEPROM Read Operation

Shortly after the deasser tion of the RST pin, the controller will read the contents of the EEPROM that is attached to the interface. Because of this automatic-read capability of the controller, an EEPR OM can be used to program many of the features of the controller at power-up, allo wing system-dependent conﬁguration information to be stored in the hardware instead of inside the device driver.

If an EEPROM exists on the interf ace, the controller will read the EEPROM contents at the end of the H_RESET operation. The EEPROM contents will be serially shifted into a temporary register and then sent to various register locations on board the controller. Access to the Am79C978 conﬁguration space, the Expansion ROM, or any I/O resource is not possible during the EEPROM read operation. The controller will terminate any access attempt with the assertion of DEVSEL and STOP while TRDY is not asserted, signaling to the initiator to disconnect and retry the access at a later time.

A checksum veriﬁcation is performed on the data that is read from the EEPROM. If the checksum veriﬁcation passes, PVALID (BCR19, bit 15) will be set to 1. If the checksum veriﬁcation of the EEPROM data fails, PV ALID will be cleared to 0, and the controller will force all EEPROM-programmable BCR registers back to their H_RESET default values . However , the content of the Address PROM locations (offsets 0h - Fh from the I/O or memory mapped I/O base address) will not be cleared. The 8-bit checksum for the entire 82 bytes of the EEPROM should be FFh.

If no EEPROM is present at the time of the automatic read operation, the controller will recognize this condition, abort the automatic read operation, and clear both the PREAD and PVALID bits in BCR19. All EEPROMprogrammable BCR registers will be assigned their default values after H_RESET. The content of the Address PROM locations (offsets 0h - Fh from the I/O or memory mapped I/O base address) will be undeﬁned.

EEPROM Auto-Detection

The controller uses the EESK/LED1 pin to determine if an EEPROM is present in the system. At the rising edge of CLK during the last clock during which RST is asserted, the controller will sample the value of the EESK/LED1 pin. If the sampled value is a 1, then the controller assumes that an EEPROM is present, and

the EEPROM read operation begins shortly after the RST

pin is deasserted. If the sampled value of EESK/ LED1 is a 0, the controller assumes that an external pull-down device is holding the EESK/LED1 pin low, indicating that there is no EEPROM in the system. Note that if the designer creates a system that contains an LED circuit on the EESK/LED1 pin, but has no EEPROM present, then the EEPROM auto-detection function will incorrectly conclude that an EEPROM is present in the system. However, this will not pose a problem for the controller, since the checksum veriﬁcation will fail.

Direct Access to the Interface

The user may directly access the port through the EEPROM register, BCR19. This register contains bits that can be used to control the interface pins. By performing an appropriate sequence of accesses to BCR19, the user can effectively write to and read from the EEPROM. This feature may be used by a system conﬁguration utility to program hardware conﬁguration information into the EEPROM.

EEPROM-Programmable Registers

The following registers contain conﬁguration infor mation that will be programmed automatically during the EEPROM read operation:

■ I/O offsets 0h-Fh Address PROM locations

■ BCR2 Miscellaneous Conﬁguration

■ BCR4 LED0 Status

■ BCR5 LED1 Status

■ BCR6 LED2 Status

■ BCR7 LED3 Status

■ BCR9 Full-Duplex Control

■ BCR18 Burst and Bus Control

■ BCR22 PCI Latency

■ BCR23 PCI Subsystem Vendor ID

■ BCR24 PCI Subsystem ID

■ BCR25 SRAM Size

■ BCR26 SRAM Boundary

■ BCR27 SRAM Interface Control

■ BCR32 PHY Control and Status

■ BCR33 PHY Address

■ BCR35 PCI Vendor ID

■ BCR36 PCI Power Management Capa-

bilities (PMC) Alias Register

■ BCR37 PCI DATA Register 0 (DATA0)

Alias Register

■ BCR38 PCI DATA Register 1 (DATA1)

Alias Register

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Am79C978 89

PRELIMINARY

■ BCR39 PCI DATA Register 2 (DATA2) Alias Register

■ BCR40 PCI DATA Register 3 (DATA3) Alias Register

■ BCR41 PCI DATA Register 4 (DATA4) Alias Register

■ BCR42 PCI DATA Register 5 (DATA5) Alias Register

■ BCR43 PCI DATA Register 6 (DATA6) Alias Register

■ BCR44 PCI DATA Register 7 (DATA7) Alias Register

■ BCR45 OnNow Pattern Matching Register 1

■ BCR46 OnNow Pattern Matching Register 2

■ BCR47 OnNow Pattern Matching Register 3

■ BCR48 LED4 Status

■ BCR49 PHY Select

■ CRS12 Physical Address Register 0

■ CRS13 Physical Address Register 1

■ CRS14 Physical Address Register 2

■ CSR116 OnNow Miscellaneous

If PREAD (BCR19, bit 14) and PV ALID (BCR19, bit 15) are cleared to 0, then the EEPROM read has experienced a failure and the contents of the EEPROM programmable BCR register will be set to default H_RESET values. The content of the Address PROM locations, however, will not be cleared.

EEPROM MAP

The automatic EEPROM read operation will access 41 words (i.e., 82 bytes) of the EEPROM. The format of the EEPROM contents is shown in Table 18, beginning with the byte that resides at the lowest EEPROM address.

Note: The ﬁrst bit out of any word location in the EEPROM is treated as the MSB of the register being programmed. For example, the ﬁrst bit out of EEPROM word location 09h will be written into BCR4, bit 15; the second bit out of EEPROM word location 09h will be written into BCR4, bit 14, etc.

There are two checksum locations within the EEPROM. The ﬁrst checksum will be used by AMD driver software to verify that the ISO 8802-3 (IEEE/ANSI

802.3) station address has not been corrupted. The value of bytes 0Ch and 0Dh should match the sum of bytes 00h through 0Bh and 0Eh and 0Fh. The second checksum location (byte 51h) is not a checksum total, but is, instead, a checksum adjustment. The value of this byte should be such that the total checksum f or the entire 82 bytes of EEPROM data equals the value FFh. The checksum adjust byte is needed by the controller in order to verify that the EEPROM content has not been corrupted.

LED Support

The controller can support up to ﬁve LEDs. LED outputs LED0, LED1, LED2, LED3, and LED4 allow for direct connection of an LED and its supporting pull-up device.

In applications that want to use the pin to drive an LED and also have an EEPROM, it might be necessary to buffer the LED3 circuit from the EEPROM connection. When an LED circuit is directly connected to the EEDO/LED3 pin, then it is not possible for most EEPROM devices to sink enough IOL to maintain a valid low level on the EEDO input to the controller. Use of buffering can be avoided if a low power LED is used.

Each LED can be programmed through a BCR register to indicate one or more of the following network status or activities: Collision Status, Full-Duplex Link Status, Half-Duplex Link Status, Receive Match, Receive Status, Magic Packet, Disable Transceiver, Transmit Status, Power, and Speed.

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Table 18. EEPROM Map

Note: *Lowest EEPROM address.

Word

Address

Byte

Addr. Most Signiﬁcant Byte

Byte

Addr. Least Signiﬁcant Byte

00h* 01h

2nd byte of the ISO 8802-3 (IEEE/ANSI

802.3) station physical address for this node

00h

First byte of the IS0 8802-3 (IEEE/ANSI 802.3) station physical address for this node, where “ﬁrst byte” refers to the ﬁrst byte to appear on

the 802.3 medium 01h 03h 4th byte of the node address 02h 3rd byte of the node address 02h 05h 6th byte of the node address 04h 5th byte of the node address 03h 07h CSR116[15:8] (OnNow Misc. Conﬁguration) 06h CSR116[7:0] (OnNow Misc. Conﬁguration)

04h 09h

Hardware ID: must be 11h if compatibility to AMD drivers is desired

08h Reserved location: must be 00h 05h 0Bh User programmable space 0Ah User programmable space 06h 0Dh

MSB of two-byte checksum, which is the sum of bytes 00h-0Bh and bytes 0Eh and 0Fh

0Ch

LSB of two-byte checksum, which is the sum of bytes 00h-0Bh and bytes 0Eh and 0Fh

07h 0Fh

Must be ASCII “W” (57h) if compatibility to AMD driver software is desired

0Eh

Must be ASCII “W” (57h) if compatibility to

AMD driver software is desired 08h 11h BCR2[15:8] (Miscellaneous Conﬁguration) 10h BCR2[7:0] (Miscellaneous Conﬁguration) 09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED)

0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status) 0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status) 0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status) 0Dh 1Bh BCR9[15:8] (Full-Duplex control) 1Ah BCR9[7:0] (Full-Duplex Control) 0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control)

0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Latency) 10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BCR23[7:0] (PCI Subsystem Vendor ID) 11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR24[7:0] (PCI Subsystem ID) 12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size) 13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary) 14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control) 15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status) 16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address) 17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID) 18h 31h BCR36[15:8] (Conf. Space. byte 43h alias) 30h BCR36[7:0] (Conf. Space byte 42h alias)

19h 33h BCR37[15:8] (DATA_SCALE alias 0) 32h BCR37[7:0] (Conf. Space byte 47h0alias) 1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Space byte 47h1alias) 1Bh 37h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Space byte 47h2alias) 1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Space byte 47h3alias) 1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Space byte 47h4alias) 1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 0) 3Ch BCR42[7:0] (Conf. Space byte 47h5alias)

1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 0) 3Eh BCR43[7:0] (Conf. Space byte 47h6alias)

20h 41h BCR44[15:8] (DATA_SCALE alias 0) 40h BCR44[7:0] (Conf. Space byte 47h7alias)

21h 43h BCR48[15:8] (LED4 Status) 42h BCR48[7:0] (LED4 Status)

22h 45h BCR49[15:8] (PHY Select) 44h BCR49[7:0] (PHY Select)

23h 47h BCR50[15:8]Reserved location: must be 00h 46h BCR50[7:0]Reserved location: must be 00h

24h 49h BCR51[15:8]Reserved location: must be 00h 48h BCR51[7:0]Reserved location: must be 00h

25h 4Bh BCR52[15:8]Reserved location: must be 00h 4Ah BCR52[7:0]Reserved location: must be 00h

26h 4Dh BCR53[15:8]Reserved location: must be 00h 4Ch BCR53[7:0]Reserved location: must be 00h

27h 4Fh BCR54[15:8]Reserved location: must be 00h 4Eh BCR54[7:0]Reserved location: must be 00h

28h 51h

Checksum adjust byte for the 82 b ytes of the EEPROM contents, checksum of the 82 bytes of the EEPROM should total to FFh

50h BCR54[7:0]Reserved location: must be 00h

Empty locations – Ignored by device

3Eh 7Dh Reserved 7Ch Reserved

3Fh 7Fh Reserved 7Eh Reserved

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The LED pins can be conﬁgured to operate in either open-drain mode (active low) or in totem-pole mode (active high). The output can be stretched to allow the human eye to recognize even shor t events that last only several microseconds. After H_RESET, the ﬁve LED outputs are conﬁgured as shown in Table 19.

Table 19. LED Default Conﬁguration

For each LED register, each of the status signals is AND’d with its enable signal, and these signals are all OR’d together to form a combined status signal. Each LED pin combined status signal can be programmed to run to a pulse stretcher, which consists of a 3-bit shift register clocked at 38 Hz (26 ms). The data input of each shift register is normally at logic 0. The OR gate output for each LED register asynchronously sets all three bits of its shift register when the output becomes asserted. The inverted output of each shift register is used to control an LED pin. Thus, the pulse stretcher provides 2 to 3 clocks of stretched LED output, or 52 ms to 78 ms. See Figure 46.

Power Savings Mode

Power Management Support

The controller supports power management as deﬁned in the PCI Bus Pow er Management Interface Speciﬁcation V1.1 and Network Device Class Power Management Reference Speciﬁcation V1.0a.These speciﬁcations deﬁne the network device power states, PCI power management interface including the Capabilities Data Structure and power management registers block deﬁnitions, power management events, and OnNow network wake-up events.

The general scheme for the Am79C978 power management is that when a PCI wake-up ev ent is detected, a signal is generated to cause hardware external to the Am79C978 device to put the computer into the working (S0) mode.

Figure 46. LED Control Logic

The Am79C978 device supports three types of wakeup events:

1. Magic Packet Detect

2. OnNow Pattern Match Detect

3. Link State Change Figure 47 shows the relationship between these wake-

up events and the v arious outputs used to signal to the external hardware.

OnNow Wake-Up Sequence

The system software enables the PME pin by setting the PME_EN bit in the PMCSR register (PCI conﬁguration registers, offset 44h, bit 8) to 1. When a wake-up event is detected, the controller sets the PME_STATUS bit in the PMCSR register (PCI conﬁguration registers, offset 44h, bit 15). Setting this bit causes the PME signal to be asserted. Assertion of the PME signal causes external hardware to wake up the CPU. The system software then reads the PMCSR register of every PCI device in the system to determine which device asserted the PME signal.

When the software determines that the signal came from the controller, it writes to the device's PMCSR to put the device into power state D0. The software then writes a 0 to the PME_STATUS bit to clear the bit and turn off the PME signal, and it calls the device's software driver to tell it that the device is now in state D0. The system software can clear the PME_STATUS bit either before, after, or at the same time that it puts the device back into the D0 state.

LED

Output Indication Driver Mode Pulse Stretch

LED0 Link Status

Open Drain -

Active Low

Enabled

LED1

Receive

Status

Open Drain -

Active Low

Enabled

LED2 Power

Open Drain -

Active Low

Enabled

LED3

Transmit

Status

Open Drain -

Active Low

Enabled

LED4 Speed

Open Drain -

Active Low

Enabled

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

Pulse Stretcher

MR_SPEED_SEL

100E

MPS

MPSE

POWER

POWERE

22206B-49

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Figure 47. OnNow Functional Diagram

Link Change Detect

Link change detect is one of wake-up ev ents deﬁned by the OnNow speciﬁcation. Link Change Detect mode is set when the LCMODE bit (CSR116, bit 8) is set either by software or loaded through the EEPROM.

When this bit is set, any change in the Link status will cause the LCDET bit (CSR116, bit 9) to be set. When the LCDET bit is set, the PME_STATUS bit (PMCSR register, bit 15) will be set. If either the PME_EN bit (PMCSR, bit 8) or the PME_EN_OVR bit (CSR116, bit

10) are set, then the PME will also be asserted.

OnNow Pattern Match Mode

In the OnNow Pattern Match Mode, the Am79C978 device compares the incoming packets with up to eight patterns stored in the Pattern Match RAM (PMR). The stored patterns can be compared with part or all of in-

coming packets, depending on the pattern length and the way the PMR is programmed. When a pattern match has been detected, then PMAT bit (CSR116, bit

7) is set. The setting of the PMAT bit causes the PME_STATUS bit (PMCSR, bit 15) to be set, which in turn will assert the PME pin if the PME_EN bit (PMCSR, bit 8) is set.

Pattern Match RAM (PMR)

PMR is organized as an array of 64 words b y 40 bits as shown in Figure 48. The PMR is progr ammed indirectly through BCRs 45, 46, and 47. When BCR45 is written and the PMA T_MODE bit (BCR45, bit 7) is set to 1, P attern Match logic is enabled. No bus accesses into the PMR are possible when the PMAT_MODE bit is set, and BCR46, BCR47, and all other bits in BCR45 are ignored. When PMA T_MODE is set, a read of BCR45 returns all bits undeﬁned except for PMAT_MODE. In

MPDETECT

MPPEN

MPMODE

MPEN

Magic Packet

Link Change

LCMODE

Link Change

MPMAT

LCDET

DET

CLR

BCR47 BCR46

BCR45

SET

CLR

SET

CLR

SET

CLR

PMAT

Pattern Match

Input

Pattern

PME_STATUS

Pattern Match RAM (PMR)

PME Status

PME_EN

MPMAT

PME_EN_OVR LCEVENT

PME

SET

CLR

POR

H_RESET

POR

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order to access the contents of the PMR, PMAT_MODE bit should be programmed to 0.

When BCR45 is written to set the PMAT_MODE bit to 0, the Pattern Match logic is disabled and accesses to the PMR are possible. Bits 6:0 of BCR45 specify the address of the PMR word to be accessed. Writing to BCR45 does not immediately affect the contents of the PMR. F ollo wing the write to BCR45, the PMR word addressed by bits 6:0 of BCR45 may be read by reading BCR45, BCR46, and BCR47 in any order. To write to the PMR word, the write to BCR45 must be followed by a write to BCR46 and a write to BCR47 in that order to complete the operation. The PMR will not actually be written until the write to BCR47 is complete.

The ﬁrst two 40-bit words in this RAM serve as pointers and contain enable bits for the eight possible match patterns. The remainder of the RAM contains the match patterns and associated match pattern control bits. Byte 0 of the ﬁrst word contains the pattern enable bits. Any bit position set in this byte enables the corresponding match pattern in the PMR, as an example if the bit 3 is set, then pattern 3 is enabled for matching. Bytes 1 to 4 in the ﬁrst word are pointers to the beginning of the patterns 0 to 3, and bytes 1 to 4 in the second word are pointers to the beginning of patterns 4 to 7, respectively. Byte 0 of the second word has no function associated with it. Byte 0 of the w ords 2 to 63 is the control ﬁeld of the PMR. Bit 7 of this ﬁeld is the End of Packet (EOP) bit. When this bit is set, it indicates the end of a pattern in the PMR. Bits 6-4 of the control ﬁeld byte are the SKIP bits. The value of the SKIP ﬁeld indicates the number of the Dwords to be skipped before the pattern in this PMR word is compared with data from the incoming frame. A maxim um of se v en Dwords may be skipped. Bits 3-0 of the control ﬁeld byte are the MASK bits. These bits correspond to the pattern match bytes 3-0 of the same PMR word (PMR bytes 4-1). If bit

of this ﬁeld is 0, then byte n of the corresponding pattern word is ignored. If this ﬁeld is programmed to 3, then bytes 0 and 1 of the pattern match ﬁeld (bytes 2 and 1 of the word) are used, and bytes 3 and 2 are ignored in the pattern matching operation.

The contents of the PMR are not affected by H_RESET, S_RESET, or STOP. The contents are undeﬁned after a power up reset (POR).

Magic Packet Mode

In Magic Pack et mode, the controller remains fully powered up (all VDD and VDDB pins must remain at their supply levels). The device will not generate any bus master transfers. No transmit operations will be initiated on the network. The de vice will continue to receiv e frames from the network, but all frames will be automatically ﬂushed from the receive FIFO. Slave accesses to the controller are still possible. A Magic Packet is a

frame that is addressed to the controller and contains a data sequence anywhere in its data ﬁeld made up of 16 consecutive copies of the device's physical address (PADR[47:0]). The controller will search incoming frames until it ﬁnds a Magic Packet frame. It star ts scanning for the sequence after processing the length ﬁeld of the frame. The data sequence can begin anywhere in the data ﬁeld of the frame, but must be detected before the controller reaches the frame's FCS ﬁeld. Any deviation of the incoming frame's data sequence from the required physical address sequence, even by a single bit, will prevent the detection of that frame as a Magic Packet frame.

The controller supports two different modes of address detection for a Magic P ack et frame. If MPPLBA (CSR5, bit 5) or EMPPLBA (CSR116, bit 6) are at their default value of 0, the controller will only detect a Magic Pac ket frame if the destination address of the packet matches the content of the physical address register (PADR). If MPPLBA or EMPPLBA are set to 1, the destination address of the Magic Packet frame can be unicast, multicast, or broadcast.

Note: The setting of MPPLBA or EMPPLBA only effects the address detection of the Magic Packet frame . The Magic Packet's data sequence must be made up of 16 consecutive copies of the device's physical address (PADR[47:0]), regardless of what kind of destination address it has.

There are two general methods to place the controller into Magic Packet mode. The ﬁrst is the software method. In this method, either the BIOS or other software sets the MPMODE bit (CSR5, bit 1). Then the controller must be put into suspend mode (see description of CSR5, bit 0), allowing any current network activity to ﬁnish. Finally, either PG must be deasserted (hardware control), or MPEN (CSR5, bit 2) must be set to 1 (software control).

Note: FASTSPNDE (CSR7, bit 15) has no meaning in Magic Packet mode.

The second method is the hardware method. In this method, the MPPEN bit (CSR116, bit 4) is set at power up by the loading of the EEPROM. This bit can also be set by software. The controller will be placed in the Magic Packet Mode when either the PG input is deasserted or the MPEN bit is set. Magic Packet mode can be disabled at any time by asserting PG or clearing MPEN bit.

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94 Am79C978

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Figure 48. Pattern Match RAM

When the controller detects a Magic Packet frame, it sets the MPMAT bit (CSR116, bit 5), the MPINT bit (CSR5, bit 4), and the PME_STATUS bit (PMCSR, bit

15). If the PME_EN or the PME_EN_OVR bits are set, the PME

will be asserted as well. If IENA (CSR0, bit 6) and MPINTE (CSR5, bit 3) are set to 1, INTA will be asserted. Any one of the four LED pins can be programmed to indicate that a Magic Packet frame has been received. MPSE (BCR4-7, bit 9) must be set to 1 to enable that function.

Note: The polarity of the LED pin can be programmed

to be active HIGH by setting LEDPOL (BCR4-7, bit 14) to 1.

Once a Magic Packet frame is detected, the controller will discard the frame internally , but will not resume nor-

mal transmit and receive operations until PG is asserted or MPEN is cleared. Once both of these events has occurred, indicating that the system has detected the Magic Packet and is awake, the controller will continue polling receive and transmit descriptor rings where it left off. It is not necessary to re-initialize the device. If the part is re-initialized, then the descriptor locations will be reset and the controller will not start where it left off.

If magic packet mode is disabled by the assertion of PG, then in order to immediately re-enable Magic Packet mode, the PG pin must remain deasserted for at least 200 ns before it is reasserted. If Magic Packet mode is disabled by clearing MPEN bit, then it may be immediately re-enabled by setting MPEN back to 1.

BCR 47 BCR 46 BCR 45 BCR Bit Number 15 8 7 0 15 8 7 0 15 8

PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0

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Am79C978 95

PRELIMINARY

The PCI bus interface cloc k (CLK) is not required to be running while the device is operating in Magic Packet mode. Either of the INTA, the LED pins, or the PME signal may be used to indicate the receipt of a Magic Packet frame when the CLK is stopped. If the system wishes to stop the CLK, it will do so after enabling the Magic Packet mode.

CAUTION: To prevent unwanted interrupts from other active parts of the controller, care must be taken to mask all likely interruptible ev ents during Magic Packet mode. An example would be the interrupts from the Media Independent Interface, which could occur while the device is in Magic Packet mode.

IEEE 1149.1 (1990) Test Access Port Interface

An IEEE 1149.1-compatible boundary scan Test Access Port is provided for board-le v el contin uity test and diagnostics. All digital input, output, and input/output pins are tested. The following paragraphs summarize the IEEE 1149.1-compatible test functions implemented in the controller.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK, TMS, TDI, and TDO), deﬁned as the Test Access Port (TAP). It includes a ﬁnite state machine (FSM), an instruction register, a data register arra y, and a power-on reset circuit. Internal pull-up resistors are provided for the TDI, TCK, and TMS pins.

TAP Finite State Machine

The TAP engine is a 16-state ﬁnite state machine (FSM), driven by the Test Clock (TCK), and the Test Mode Select (TMS) pins. An independent power-on reset circuit is provided to ensure that the FSM is in the TEST_LOGIC_RESET state at power-up. Therefore, the TRST is not provided. The FSM is also reset when TMS and TDI are high for ﬁve TCK periods.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements (BYPASS, EXTEST, and SAMPLE instructions), three additional instructions (IDCODE, TRIBYP, and SETBYP) are provided to further ease board-level testing. All unused instruction codes are reserved. See Table 20 for a summary of supported instructions.

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE instruction is always inv oked. The decoding logic gives signals to control the data ﬂow in the data registers according to the current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two stages. A ﬂip-ﬂop and a latch are used for the Serial Shift Stage and the Parallel Output Stage, respectiv ely. There are four possible operation modes in the BSR cell shown in Table 21.

Other Data Registers

Other data registers are the following:

1. Bypass register (1 bit)

2. Device ID register (32 bits) (Table 22).

Note: The content of the Device ID register is the same as the content of CSR88.

Table 20. IEEE 1149.1 Supported Instruction

Summary

Instruction

Name

Instruction

Code

Description Mode

Selected

Data

EXTEST 0000 External T est T est BSR IDCODE 0001

ID Code

Inspection

Normal ID REG

SAMPLE 0010

Sample

Boundary

Normal BSR

TRIBYP 0011 Force Float Normal Bypass

SETBYP 0100

Control

Boundary to

I/0

Test Bypass

BYPASS 1111 Bypass Scan Normal Bypass

Table 21. BSR Mode Of Operation

1 Capture 2 Shift 3 Update 4 System Function

Table 22. Device ID Register

Bits 31-28 Version Bits 27-12 Part Number (0010 0110 0010 0110)

Bits 11-1

Manufacturer ID. The 11 bit manuf acturer ID cod for AMD is 00000000001 in accordance with JEDEC publication 106-A.

Bit 0 Always a logic 1

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96 Am79C978

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NAND T ree Testing

The controller provides a NAND tree test mode to allow checking connectivity to the device on a printed circuit board. The NAND tree is built on all PCI bus pins.

NAND tree testing is enabled by asserting RST. P G input should be driven HIGH during NAND tree testing. All PCI bus signals will become inputs on the assertion of RST. The result of the NAND tree test can be observed on the INTA pin. See Figure 49.

Pin 141 (RST) is the ﬁrst input to the NAND tree. Pin 142 (CLK) is the second input to the NAND tree, followed by pin 143 (GNT

). All other PCI bus signals follow , counterclockwise , with pin 61 (AD0) being the last. Table 23 and Table 24 shows the complete list of pins connected to the NAND tree.

RST

must be asserted low to start a NAND tree test sequence. Initially, all NAND tree inputs except RST should be driven high. This will result in a high output at the INTA pin. If the NAND tree inputs are driven from high to low in the same order as they are connected to build the NAND tree, INTA will toggle every time an additional input is driven low. INTA will change to low, when CLK is driven low and all other NAND tree inputs stay high. INTA will toggle back to high, when GNT is additionally driven low. The square wave will continue until all NAND tree inputs are driven low. INT

A will be high, when all NAND tree inputs are driven low. See Figure 50.

Some of the pins connected to the NAND tree are outputs in normal mode of operation. They must not be driven from an external source until the controller is conﬁgured for NAND tree testing.

Figure 49. NAND Tree Circuitry (160 PQFP)

Am79C972

Core

RST (pin141)

CLK (pin 142)

VDD

GNT (pin 143)

AD0 (pin 61)

INTA (pin 140)

B A

MUX

....

INTA

Am79C978

Core

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Table 23. NAND Tree Pin Sequence (160 PQFP)

Table 24. NAND Tree Pin Sequence (144 TQFP)

NAND Tree

Input No. Pin No. Name

NAND T ree

Input No. Pin No. Name

NAND Tree

Input No. Pin No. Name

1 141 RST

18 9 AD20 35 36 AD13 2 142 PCI_CLK 19 11 AD19 36 38 AD12 3 143 GNT

20 12 AD18 37 43 AD11 4 144 REQ

21 14 AD17 38 45 AD10 5 146 AD31 22 16 AD16 39 46 AD9 6 149 AD30 23 17 C/BE

2 40 47 AD8

7 150 AD29 24 19 FRAME

41 48 C/BE0

8 151 AD28 25 20 IRD

Y 42 50 AD7

9 152 AD27 26 22 TRD

Y 43 52 AD6

10 154 AD26 27 24 DEVSEL

44 53 AD5

11 156 AD25 28 25 ST

OP 45 55 AD4

12 157 AD24 29 27 PERR

46 56 AD3

13 158 C/BE

3 30 28 SERR 47 58 AD2 14 3 IDSEL 31 30 PAR 48 60 AD1 15 4 AD23 32 32 C/BE

1 49 61 AD0 16 6 AD22 33 33 AD15 50 17 8 AD21 34 35 AD14 51

NAND Tree

Input No. Pin No. Name

NAND T ree

Input No. Pin No. Name

NAND Tree

Input No. Pin No. Name

1 127 RST

18 7 AD20 35 34 AD13 2 128 PCI_CLK 19 9 AD19 36 36 AD12 3 129 GNT

20 10 AD18 37 37 AD11 4 130 REQ

21 12 AD17 38 39 AD10 5 132 AD31 22 14 AD16 39 40 AD9 6 135 AD30 23 15 C/BE

2 40 41 AD8

7 136 AD29 24 17 FRAME

41 42 C/BE0

8 137 AD28 25 18 IRD

Y 42 44 AD7

9 138 AD27 26 20 TRD

Y 43 46 AD6

10 140 AD26 27 22 DEVSEL

44 47 AD5

11 142 AD25 28 23 ST

OP 45 49 AD4

12 143 AD24 29 25 PERR

46 50 AD3

13 144 C/BE

3 30 26 SERR 47 52 AD2 14 1 IDSEL 31 28 PAR 48 54 AD1 15 2 AD23 32 30 C/BE

1 49 55 AD0 16 4 AD22 33 31 AD15 17 6 AD21 34 33 AD14

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98 Am79C978

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Figure 50. NAND Tree Waveform

Reset

There are four different types of RESET oper ations that may be performed on the Am79C978 device, H_RESET, S_RESET, STOP, and POR. The following is a description of each type of RESET operation.

H_RESET

Hardware Reset (H_RESET) is an Am79C978 reset operation that has been created by the proper assertion of the RST pin of the Am79C978 device while the PG pin is HIGH. When the minimum pulse width timing as speciﬁed in the RST pin description has been satisﬁed, an internal reset operation will be performed.

H_RESET will program most of the CSR and BCR registers to their default value. Note that there are several CSR and BCR registers that are undeﬁned after H_RESET. See the sections on the individual registers for details.

H_RESET will clear most of the registers in the PCI conﬁguration space. H_RESET will cause the microcode program to jump to its reset state. Following the end of the H_RESET operation, the controller will attempt to read the EEPROM device through the EEPROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the controller will be in 16-bit I/O mode after the reset operation. A DWord write operation to the RDP (I/O offset

10h) must be performed to set the device into 32-bit I/O mode.

S_RESET

Software Reset (S_RESET) is an Am79C978 reset operation that has been created by a read access to the Reset register, which is located at offset 14h in Word I/O mode or offset 18h in DWord I/O mode from the Am79C978 I/O or memory mapped I/O base address.

S_RESET will reset all of or some portions of CSR0, 3, 4, 15, 80, 100, and 124 to default values. For the identity of individual CSRs and bit locations that are affected by S_RESET, see the individual CSR register descriptions. S_RESET will not affect any PCI conﬁguration space location. S_RESET will not affect any of the BCR register values. S_RESET will cause the microcode program to jump to its reset state. Following the end of the S_RESET operation, the controller will not attempt to read the EEPROM device. After S_RESET, the host must perform a full re-initialization of the controller before starting network activity. S_RESET will cause REQ to deassert immediately. STOP (CSR0, bit 2) or SPND (CSR5, bit 0) can be used to terminate any pending bus mastership request in an orderly sequence.

S_RESET terminates all network activity abruptly. The host can use the suspend mode (SPND, CSR5, bit 0) to terminate all network activity in an orderly sequence before issuing an S_RESET.

RST

CLK

GNT

REQ

AD[31:0]

C/BE[3:0]

IDSEL

FRAME

IRDY

TRDY

DEVSEL

STOP

PERR

SERR

PAR

INTA

FFFFFFFF

0000FFFF

...

... ...

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STOP

A STOP reset is generated by the assertion of the STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0, when the stop bit currently has a value of 0, will initiate a STOP reset. If the STOP bit is already a 1, then writing a 1 to the STOP bit will not generate a STOP reset.

STOP will reset all or some portions of CSR0, 3, and 4 to default values. For the identity of individual CSRs and bit locations that are affected by STOP, see the individual CSR register descriptions. ST OP will not aff ect any of the BCR and PCI conﬁguration space locations. STOP will cause the microcode program to jump to its reset state. Following the end of the STOP operation, the controller will not attempt to read the EEPROM device.

Note: STOP will not cause a deasser tion of the REQ signal, if it happens to be active at the time of the write to CSR0. The controller will wait until it gains bus ownership, and it will ﬁrst ﬁnish all scheduled bus master accesses before the STOP reset is executed.

STOP terminates all network activity abruptly. The host can use the suspend mode (SPND , CSR5, bit 0) to ter-

minate all network activity in an orderly sequence before setting the STOP bit.

Power on Reset

Power on Reset (POR) is generated when the controller is powered up. POR generates a hardware reset (H_RESET). In addition, it clears some bits that H_RESET does not affect.

Software Access

PCI Conﬁguration Registers

The controller implements the 256-byte conﬁguration space as deﬁned by the PCI draft speciﬁcation revision

2.2. The 64-byte header includes all registers required to identify the controller and its function. Additionally, PCI Power Management Interface registers are implemented at location 40h - 47h. The layout of the PCI conﬁguration space is shown in Table 25.

The PCI conﬁguration registers are accessible only by conﬁguration cycles. All multi-b yte numeric ﬁelds f ollow little endian byte ordering. All write accesses to Reserved locations have no eff ect; reads from these locations will return a data value of 0.

Table 25. PCI Conﬁguration Space Layout

I/O Resources

The Am79C978 controller requires 32 bytes of address space for access to all the various internal registers as well as to some setup information stored in an external serial EEPROM. A software reset port is available, too.

The Am79C978 controller supports mapping the address space to both I/O and memory space. The value in the PCI I/O Base Address register determines the start address of the I/O address space. The register is typically programmed by the PCI conﬁguration utility after system power-up. The PCI conﬁguration utility

31 24 23 16 15 8 7 0 Offset

Device ID Vendor ID 00h

Status Command 04h

Base-Class Sub-Class Programming IF Revision ID 08h

Reserved Header Type Latency Timer Reserved 0Ch

I/O Base Address 10h

Memory Mapped I/O Base Address 14h

Reserved 18h Reserved 1Ch Reserved 20h Reserved 24h Reserved 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved CAP-PTR 34h

Reserved 38h

MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch

PMC NXT_ITM_PTR CAP_ID 40h

DATA_REG PMCSR_BSE PMCSR 44H

Reserved

. .

Reserved FCh

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100 Am79C978

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must also set the IOEN bit in the PCI Command register to enable I/O accesses to the Am79C978 controller . F or memory mapped I/O access, the PCI Memory Mapped I/O Base Address register controls the start address of the memory space. The MEMEN bit in the PCI Command register must also be set to enable the mode. Both base address registers can be active at the same time.

The Am79C978 controller supports two modes for accessing the I/O resources. For backwards compatibility with AMD's 16-bit Ethernet controllers, Word I/O is the default mode after power up . The device can be conﬁgured to DWord I/O mode by software.

I/O Registers

The Am79C978 controller registers are divided into two groups. The Control and Status Registers (CSR) are used to conﬁgure the Ethernet MAC engine and to obtain status information. The Bus Control Registers (BCR) are used to conﬁgure the bus interface unit and the LEDs. Both sets of registers are accessed using indirect addressing.

The CSR and BCR share a common Register Address Port (RAP). There are, however, separate data ports. The Register Data Port (RDP) is used to access a CSR. The BCR Data Port (BDP) is used to access a BCR.

In order to access a particular CSR location, the RAP should ﬁrst be written with the appropriate CSR address. The RDP will then point to the selected CSR. A read of the RDP will yield the selected CSR data. A write to the RDP will write to the selected CSR. In order to access a particular BCR location, the RAP should ﬁrst be written with the appropriate BCR address. The BDP will then point to the selected BCR. A read of the BDP will yield the selected BCR data. A write to the BDP will write to the selected BCR.

Once the RAP has been written with a value, the RAP value remains unchanged until another RAP write occurs, or until an H_RESET or S_RESET occurs. RAP is cleared to all 0s when an H_RESET or S_RESET occurs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The Am79C978 controller allows for connection of a serial EEPROM. The ﬁrst 16 bytes of the EEPROM will be automatically loaded into the Address PROM (APROM) space after H_RESET. Additionally, the ﬁrst six bytes of the EEPROM will be loaded into CSR12 to CSR14. The Address PROM space is a convenient place to store the value of the 48-bit IEEE station address. It can be overwritten by the host computer, and its content has no effect on the operation of the Am79C978 controller. The software must copy the station address from the Address PROM space to the ini-

tialization block in order for the receiver to accept unicast frames directed to this station.

The six bytes of the IEEE station address occupy the ﬁrst six locations of the Address PROM space. The next six bytes are reserved. Bytes 12 and 13 should match the value of the checksum of bytes 1 through 11 and 14 and 15. Bytes 14 and 15 should each be ASCII “W” (57h). The above requirements must be met in order to be compatible with AMD driver software. APROMWE bit (BCR2, bit 8) must be set to 1 to enable write access to the Address PROM space.

Reset Register

A read of the Reset register creates an internal software reset (S_RESET) pulse in the Am79C978 controller. The internal S_RESET pulse that is generated by this access is different from both the assertion of the hardware RST pin (H_RESET) and from the assertion of the software STOP bit. Speciﬁcally, S_RESET is the equivalent of the assertion of the RST pin (H_RESET) except that S_RESET has no effect on the BCR or PCI Conﬁguration space locations.

The NE2100 LANCE-based family of Ethernet cards requires that a write access to the Reset register follows each read access to the Reset register. The Am79C978 controller does not have a similar requirement. The write access is not required and does not have any effect.

Note: The Am79C978 controller cannot service any slave accesses f or a very short time after a read access of the Reset register, because the internal S_RESET operation takes about 1 ms to ﬁnish. The Am79C978 controller will terminate all slave accesses with the assertion of DEVSEL and STOP while TRDY is not asserted, signaling to the initiator to disconnect and retry the access at a later time.

Word I/O Mode

After H_RESET, the Am79C978 controller is programmed to operate in Word I/O mode . D WIO (BCR18, bit 7) will be cleared to 0. Table 26 shows how the 32 bytes of address space are used in Word I/O mode.

All I/O resources must be accessed in word quantities and on word addresses. The Address PROM locations can also be read in byte quantities. The only allowed DWord operation is a write access to the RDP, which switches the device to DWord I/O mode. A read access other than listed in the table below will yield undeﬁned data; a write operation may cause unexpected reprogramming of the Am79C978 control registers. Tab le 27 shows legal I/O accesses in Word I/O mode.

Datasheet Am79C978VCW, Am79C978KCW Datasheet (AMD Advanced Micro Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual