PRELIMINARY
Am79C970A
PCnetTM-PCI II Single-Chip Full-Duplex Ethernet Controller
for PCI Local Bus Product
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller for the Peripheral Component Interconnect (PCI) local bus
Supports ISO 8802-3 (IEEE/ANSI 802.3) and
Ethernet standards
Direct interface to the PCI local bus (Revision
2.0 compliant)
High-performance 32-bit Bus Master architec-
ture with integrated DMA buffer Management
Unit for low CPU and bus utilization
Software compatible with AMD PCnet Family,
LANCE/C-LANCE, and Am79C900 ILACC register and descriptor architecture
Compatible with PCnet Family driver software
Full-duplex operation for increased network
bandwidth
Big endian and little endian byte alignments
supported
3.3 V/5 V signaling for PCI bus interface
Low-power CMOS design with two sleep
modes allows reduced power consumption for
critical battery powered applications and Green
PCs
Integrated Magic PacketTMsupport for remote
wake up of Green PCs
Individual 272-byte transmit and 256-byte receive FIFOs provide frame buffering for increased system latency and support the
following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit pad-
ding (individually programmable)
— Automatic runt frame rejection
— Automatic selection of received collision frames
Microwire EEPROM interface supports
jumperless design and provides through-chip
programming
Supports optional Boot PROM for diskless
node applications
Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
end of receive frame
Integrated Manchester Encoder/Decoder
Provides Integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with automatic
port selection
Automatic Twisted-Pair receive polarity detection and automatic correction of the receive
polarity
Optional byte padding to long-word boundary
on receive
Dynamic transmit FCS generation programmable on a frame-by-frame basis
Internal/external loopback capabilities
Supports the following types of network inter-
faces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted-Pair medium
JTAG Boundary Scan (IEEE 1149.1) test access
port interface and NAND Tree test mode for
board-level production connectivity test
Supports LANCE General Purpose Serial Interface (GPSI)
Supports External Address Detection Interface
(EADI)
4 programmable LEDs for status indication
132-pin PQFP package
Advanced
Micro
Devices
GENERAL DESCRIPTION
The 32-bit PCnet-PCI II single-chip full-duplex Ethernet
controller is a highly integrated Ethernet system solution
designed to address high-performance system application requirements. It is a flexible bus-mastering device
that can be used in any application, including networkready PCs, printers, fax modems, and bridge/router de-
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
signs. The bus-master architecture provides high data
throughput in the system and low CPU and system bus
utilization. The PCnet-PCI II controller is fabricated with
AMD’s advanced low-power CMOS process to
provide low operating and standby current for power
sensitive applications.
Publication# 19436 Rev. A Amendment/+1
Issue Date: April 1995
AMD
P R E L I M I N A R Y
The PCnet-PCI II controller is a complete Ethernet node
integrated into a single VLSI device. It contains a bus
interface unit, a DMA buffer management unit, an IEEE
802.3-compliant Media Access Control (MAC) function,
individual 272-byte transmit and 256-byte receive
FIFOs, an IEEE 802.3-compliant Attachment Unit
Interface (AUI) and Twisted-Pair Transceiver Media
Attachment Unit (10BASE-T MAU) that can both
operate in either half-duplex or full-duplex mode.
The PCnet-PCI II controller is register compatible with
the LANCE (Am7990) Ethernet controller, the
C-LANCE (Am79C90) Ethernet controller, the ILACC
(Am79C900) Ethernet controller, and all Ethernet
controllers in the PCnet Family, including the
PCnet-ISA controller (Am79C960), PCnet-ISA+
controller (Am79C961), PCnet-ISA II controller
(Am79C961A), PCnet-32 controller (Am79C965),
PCnet-PCI controller (Am79970), and the PCnet-SCSI
controller (Am79C974). The buffer management unit
supports the C-LANCE, ILACC, and PCnet descriptor
software models. The PCnet-PCI II controller is
software compatible with the Novell
NE2100 and
NE1500 Ethernet adapter card architectures.
The 32-bit multiplexed bus interface unit provides a di-
rect interface to PCI local bus applications, simplifying
the design of an Ethernet node in a PC system. The
PCnet-PCI II controller provides the complete interface
to an Expansion ROM, allowing add-on card designs
with only a single load per PCI bus interface pin. With its
built-in support for both little and big endian byte alignment, this controller also addresses proprietary non-PC
applications. The PCnet-PCI II controller’s
advanced CMOS design allows the bus interface to be
connected to either a 5 V or a 3.3 V signaling environment. Both NAND Tree and JTAG test interfaces
are provided.
The PCnet-PCI II controller supports automatic
configuration in the PCI configuration space. Additional
PCnet-PCI II configuration parameters, including the
unique IEEE physical address, can be read from an external non-volatile memory (Microwire EEPROM) immediately following system reset.
The controller has the capability to automatically select
either the AUI port or the Twisted-Pair transceiver. Only
one interface is active at any one time. Both network interfaces can be programmed to operate in either halfduplex or full-duplex mode. The individual transmit and
receive FIFOs optimize system overhead, providing sufficient latency during frame transmission and reception,
and minimizing intervention during normal network error
recovery. The integrated Manchester encoder/decoder
(MENDEC) eliminates the need for an external Serial Interface Adapter (SIA) in the system. The built-in General
Purpose Serial Interface (GPSI) allows the MENDEC to
be by-passed. In addition, the device
provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity, activity, or jabber status. The PCnet-PCI II controller also
provides an External Address Detection Interface
(EADI) to allow fast external hardware address filtering
in internetworking applications.
For power sensitive applications where low stand-by
current is desired, the device incorporates two Sleep
functions to reduce over-all system power consumption,
excellent for notebooks and Green PCs. In conjunction
with these low power modes, the PCnet-PCI II controller
also has integrated functions to support Magic Packet,
an inexpensive technology that allows remote wake up
of Green PCs.
2
Am79C970A
BLOCK DIAGRAM
CLK
RST
AD[31:00]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
LOCK
IDSEL
DEVSEL
REQ
GNT
PERR
SERR
INTA
NOUT
SLEEP
PCI Bus
Interface
Unit
P R E L I M I N A R Y
Rcv
FIFO
Xmt
FIFO
FIFO
Control
GPSI
802.3
Port
MAC
Core
EADI
Port
Manchester
Encoder/
Decoder
(PLS) & AUI
Port
10BASE-T
MAU
AMD
DXCVR
TXEN
TXCLK
TXDAT
RXEN
RXCLK
RXDAT
CLSN
SRDCLK
SRD
SF/BD
EAR
XTAL1
XTAL2
DO+/DI +/CI+/-
TXD+/TXP+/RXD+/-
LNKST
TCK
TMS
TDI
TDO
JTAG
Port
Control
Buffer
Management
Unit
Microwire
EEPROM
Interface
LED
Control
Expansion
ROM
Interface
EECS
EESK
EEDI
EEDO
LED1
LED2
LED3
ERA[7:0]
ERD[7:0]
ERACLK
EROE
19436A-1
3Am79C970A
AMD
P R E L I M I N A R Y
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL DESCRIPTION 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RELATED PRODUCTS 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONNECTION DIAGRAM 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESIGNATIONS 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Pin Number 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Group 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Driver Type 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPTION 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interface 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Interface 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire EEPROM Interface 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion ROM Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attachment Unit Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Serial Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Address Detection Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 Test Access Port Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Pins 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BASIC FUNCTIONS 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Bus Interface Function 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interface 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Network Interfaces 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DETAILED FUNCTIONS 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Bus Interface Unit 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Configuration Transfers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave I/O Transfers 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion ROM Transfers 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exclusive Access 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Cycle Termination 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect When Busy 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect Of Burst Transfer 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect When Locked 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity Error Response 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Bus Interface Unit 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Acquisition 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Master DMA Transfers 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Non-Burst Read Transfer 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Burst Read Transfer 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Non-Burst Write Transfer 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Burst Write Transfer 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Initiated Termination 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect With Data Transfer 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect Without Data Transfer 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Abort 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Am79C970A
P R E L I M I N A R Y
AMD
Master Initiated Termination 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preemption During Non-Burst Transaction 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preemption During Burst Transaction 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Abort 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity Error Response 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Parity Error Handling 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Block DMA Transfers 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptor DMA Transfers 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO DMA Transfers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Burst FIFO DMA Transfers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst FIFO DMA Transfers 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Management Unit 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Re-Initialization 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Suspend 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Management 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptor Rings 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor Table Entry 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptor Table Entry 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Media Access Control 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit and Receive Message Data Encapsulation 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framing 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Destination Address Handling 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Media Access Management 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Medium Allocation 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Handling 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Operation 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Function Programming 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Pad Generation 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit FCS Generation 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Exception Conditions 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Carrier 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Late Collision 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SQE Test Error 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Operation 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Function Programming 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Matching 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Pad Stripping 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive FCS Checking 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Exception Conditions 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback Operation 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI Loopback Modes 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Loopback Modes 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T-MAU Loopback Modes 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Loopback Features 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Magic Packet Mode 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manchester Encoder/Decoder 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Crystal Characteristics 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Drive Characteristics 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MENDEC Transmit Path 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Timing and Operation 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Path 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Signal Conditioning 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5Am79C970A
AMD
P R E L I M I N A R Y
Clock Acquisition 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Tracking 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carrier Tracking and End of Message 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Decoding 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Tolerance Definition 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attachment Unit Interface 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Termination 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Detection 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted-Pair Transceiver 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Transmit Function 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Receive Function 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Test Function 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polarity Detection and Reversal 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Interface Status 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Detection Function 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Quality Error Test Function 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jabber Function 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Interface Connection 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full-Duplex Operation 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full-Duplex Link Status LED Support 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Serial Interface 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Address Detection Interface 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion ROM Interface 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Microwire Interface 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic EEPROM Read Operation 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Auto-Detection 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct Access to the Microwire Interface 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM-programmable Registers 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM MAP 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Support 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Savings Modes 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 Test Access Port Interface 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Circuit 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP Finite State Machine 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Instructions 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Register and Decoding Logic 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Register 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Data Registers 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND Tree Testing 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H_RESET 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S_RESET 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Access 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Registers 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Resources 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address PROM Space 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Register 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word I/O Mode 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Double Word I/O Mode 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USER ACCESSIBLE REGISTERS 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Registers 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Am79C970A
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AMD
PCI Vendor ID 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Device ID Register 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Command Register 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Status Register 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Revision ID Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Programming Interface Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Sub-Class Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Base-Class Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Latency Timer Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Header Type Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI I/O Base Address Register 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Memory Mapped I/O Base Address Register 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Expansion ROM Base Address Register 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Line Register 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Pin Register 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI MIN_GNT Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI MAX_LAT Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAP Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAP: Register Address Port 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Registers 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR0: PCnet-PCI II Controller Controller Status Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR1: Initialization Block Address 0 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR2: Initialization Block Address 1 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR3: Interrupt Masks and Deferral Control 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR4: Test and Features Control 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR5: Extended Control and Interrupt 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR6: RX/TX Descriptor Table Length 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR8: Logical Address Filter 0 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR9: Logical Address Filter 1 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR10: Logical Address Filter 2 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR11: Logical Address Filter 3 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR12: Physical Address Register 0 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR13: Physical Address Register 1 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR14: Physical Address Register 2 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR15: Mode 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR16: Initialization Block Address Lower 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR17: Initialization Block Address Upper 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR18: Current Receive Buffer Address Lower 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR19: Current Receive Buffer Address Upper 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR20: Current Transmit Buffer Address Lower 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR21: Current Transmit Buffer Address Upper 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR22: Next Receive Buffer Address Lower 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR23: Next Receive Buffer Address Upper 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR24: Base Address of Receive Descriptor Ring Lower 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR25: Base Address of Receive Descriptor Ring Upper 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR26: Next Receive Descriptor Address Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR27: Next Receive Descriptor Address Upper 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR28: Current Receive Descriptor Address Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR29: Current Receive Descriptor Address Upper 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR30: Base Address of Transmit Descriptor Ring Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR31: Base Address of Transmit Descriptor Ring Upper 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR32: Next Transmit Descriptor Address Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR33: Next Transmit Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR34: Current Transmit Descriptor Address Lower 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR35: Current Transmit Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7Am79C970A
AMD
P R E L I M I N A R Y
CSR36: Next Next Receive Descriptor Address Lower 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR37: Next Next Receive Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR38: Next Next Transmit Descriptor Address Lower 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR39: Next Next Transmit Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR40: Current Receive Byte Count 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR41: Current Receive Status 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR42: Current Transmit Byte Count 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR44: Next Receive Byte Count 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR45: Next Receive Status 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR46: Poll Time Counter 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR47: Polling Interval 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR58: Software Style 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR60: Previous Transmit Descriptor Address Lower 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR61: Previous Transmit Descriptor Address Upper 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR62: Previous Transmit Byte Count 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR63: Previous Transmit Status 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR64: Next Transmit Buffer Address Lower 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR65: Next Transmit Buffer Address Upper 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR66: Next Transmit Byte Count 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR67: Next Transmit Status 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR72: Receive Descriptor Ring Counter 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR74: Transmit Descriptor Ring Counter 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR76: Receive Descriptor Ring Length 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR78: Transmit Descriptor Ring Length 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR80: DMA Transfer Counter and FIFO Watermark Control 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR82: Bus Activity Timer 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR84: DMA Address Register Lower 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR85: DMA Address Register Upper 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR86: Buffer Byte Counter 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR88: Chip ID Register Lower 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR89: Chip ID Register Upper 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR94: Transmit Time Domain Reflectometry Count 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR100: Bus Timeout 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR112: Missed Frame Count 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR114: Receive Collision Count 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR122: Advanced Feature Control 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR124: Test Register 1 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Configuration Registers 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR0: Master Mode Read Active 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR1: Master Mode Write Active 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR2: Miscellaneous Configuration 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR4: Link Status LED (LNKST) 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR5: LED1 Status 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR6: LED2 Status 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR7: LED3 Status 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR9: Full-Duplex Control 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR16: I/O Base Address Lower 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR16: I/O Base Address Upper 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR18: Burst and Bus Control Register 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR19: EEPROM Control and Status 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR20: Software Style 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR21: Interrupt Control 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR22: PCI Latency Register 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Block 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RLEN and TLEN 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Am79C970A
P R E L I M I N A R Y
AMD
RDRA and TDRA 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LADRF 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PADR 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptors 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD0 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD1 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD2 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD3 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptors 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD0 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD1 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD2 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD3 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER SUMMARY 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Registers 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Configuration Registers 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATING 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATING RANGES 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC CHARACTERISTICS 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SWITCHING CHARACTERISTICS 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Interface 174. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI 175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI 176. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EADI 177. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KEY TO SWITCHING WAVEFORMS 178. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SWITCHING TEST CIRCUITS 178. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SWITCHING WAVEFORMS 180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Bus Interface 180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Interface 184. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI 186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EADI 190. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PHYSICAL DIMENSIONS 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX A: PCnet-PCI II Compatible Media Interface Modules A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Filters and Transformers A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Isolation Transformers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC/DC Converters A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manufacturer Contact Information A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX B: Recommendation For Power And Ground Decoupling B-1. . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX C: Alternative Method For Initialization C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX D: Look-Ahead Packet Processing Concept D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction of the LAPP Concept D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outline of the LAPP Flow D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LAPP Software Requirements D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9Am79C970A
AMD
P R E L I M I N A R Y
LAPP Rules for Parsing of Descriptors D-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Some Examples of LAPP Descriptor Interaction D-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Size Tuning D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
An Alternative LAPP Flow—the TWO Interrupt Method D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX E: PCnet-PCI II and PCnet-PCI Differences E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
New Features E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Register Bit Changes E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Space E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Registers E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Configuration Registers E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptor E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List Of Pin Changes E-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Am79C970A
P R E L I M I N A R Y
RELATED PRODUCTS
Part No. Description
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
TM
)
(ILACC)
TM
(HIMIBTM)
Plug n’ Play support)
Am79C900 Integrated Local Area Communications Controller
Am79C940 Media Access Controller for Ethernet (MACE
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft
Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses)
Am79C970 PCnet-PCI II Single-Chip Ethernet Controller for PCI Local Bus
Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C981 Integrated Multiport Repeater Plus
TM
(IMR+TM)
Am79C987 Hardware Implemented Management Information Base
AMD
Plug n’ Play support)
11Am79C970A
AMD
P R E L I M I N A R Y
CONNECTION DIAGRAM – 132-PIN PQFP
AD28
AD29
VSSB
AD30
AD31
TDO
REQ
VSS
TMS
GNT
VDD
CLK
RST
VSS
132
131
130
129
128
127
126
125
124
123
122
121
120
VDDB
AD27
AD26
VSSB
AD25
AD24
C/BE3
VDD
TDI
IDSEL
VSS
AD23
AD22
VSSB
AD21
AD20
VDDB
AD19
AD18
VSSB
AD17
AD16
C/BE2
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
VSS
PERR
SERR
VDDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
343536373839404142434445464748495051525354555657585960616263646566
119
Am79C970A
PCnet-PCI II
TCK
118
INTA
117
RESERVED
116
SLEEP
EECS
115
114
VSS
113
EESK/LED1/SFBD
EEDI/LNKST
112
111
EEDO/LED3/SRD
VDD
110
109
AVDD2
CI+
108
107
CI-
106
DI+
105
DI-
104
AVDD1
DO+
103
102
DO-
101
AVSS1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXP+
TXD-
TXP-
AVDD4
RXD+
RXD-
VSS
LED2/SRDCLK
ERD0/RXDAT
ERD1/RXCLK
VDD
ERD2/RXEN
VSS
ERD3/CLSN
ERD4/TXCLK
VSS
ERD5
ERD6/TXEN
VDD
ERD7/TXDAT
ERA0
ERA1
VSS
ERA2
ERA3
ERA4
ERA5
VSS
Pin 1 is marked for orientation
RESERVED = Don't connect
Pin 1 is marked for orientation.
RESERVED = Don’t connect
12
PAR
AD15
AD14
AD13
AD12
VSSB
C/BE1
AD11
AD10
VSSB
AD9
AD8
VDDB
C/BE0
AD7
AD6
AD5
VSSB
AD4
AD3
AD2
AD1
VSSB
AD0
EAR
VDD
EROE
VSS
VSS
ERACLK
DXCVR/NOUT
ERA7
ERA6
19436A-2
Am79C970A
P R E L I M I N A R Y
CONNECTION DIAGRAM – 144-PIN TQFP
NC
NC
AD28
AD29
VSSB
AD30
AD31
TDO
REQ
VSS
TMS
GNT
VDD
CLK
RST
VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
NC
VDDB
AD27
AD26
VSSB
AD25
AD24
C/BE3
VDD
TDI
IDSEL
VSSB
AD23
AD22
VSSB
AD21
AD20
VDDB
AD19
AD18
VSSB
AD17
AD16
C/BE2
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
VSS
PERR
SERR
VDDB
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
129
PCnet-PCI II
Am79C970AVC
49
50
51
52
TCK
128
53
INTA
127
54
RESERVED
SLEEP
EECS
VSS
126
125
124
123
55
56
57
58
EESK/LED1/SFBD
EEDI/LNKST
122
121
59
60
EED0/LED3/SRD
120
61
VDD
119
62
AVDD2
CI+
118
117
63
64
CI-
116
65
DI+
115
66
DI-
114
67
AVDD1
DO+
113
112
68
69
DI-
111
70
AVSS1
NC
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
71
72
AMD
NC
NC
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXP+
TXD-
TXP-
AVDD4
RXD+
RXD-
VSS
LED2/SRDCLK
ERD0/RXDAT
ERD1/RXCLK
VDD
ERD2/RXEN
VSS
ERD3/CLSN
ERD4/TXCLK
VSS
ERD5
ERD6/TXEN
VDD
ERD7/TXDAT
ERA0
ERA1
VSS
ERA2
ERA3
ERA4
ERA5
VSS
NC
NC
PAR
AD15
AD14
AD13
VSSB
C/BE1
Pin 1 is marked for orientation.
RESERVED = Don’t connect
AD12
AD11
AD10
VSSB
AD9
AD8
VDDB
C/BE0
AD7
AD6
AD5
VSSB
AD4
AD3
AD2
AD1
VSSB
AD0
NC
VSS
EROE
DXCVR/NOUT
VSS
ERACLK
EAR
VDD
ERA7
ERA6
NC
19436A-3
13Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS – 132-PIN PQFP
Listed By Pin Number
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 VDDB 34 PAR 67 VSS 100 AVSS1
2 AD27 35 C/BE1 68 ERA5 101 DO-
3 AD26 36 AD15 69 ERA4 102 DO+
4 VSSB 37 VSSB 70 ERA3 103 AVDD1
5 AD25 38 AD14 71 ERA2 104 DI-
6 AD24 39 AD13 72 VSS 105 DI+
7 C/BE3 40 AD12 73 ERA1 106 CI-
8 VDD 41 AD11 74 ERA0 107 CI+
9 TDI 42 AD10 75 ERD7/TXDAT 108 AVDD2
10 IDSEL 43 VSSB 76 VDD 109 VDD
11 VSS 44 AD9 77 ERD6/TXEN 110 EEDO/LED3/SRD
12 AD23 45 AD8 78 ERD5 111 EEDI/LNKST
13 AD22 46 VDDB 79 VSS 112 EESK/LED1/SFBD
14 VSSB 47 C/BE0 80 ERD4/TXCLK 113 VSS
15 AD21 48 AD7 81 ERD3/CLSN 114 EECS
16 AD20 49 AD6 82 VSS 115 SLEEP
17 VDDB 50 VSSB 83 ERD2/RXEN 116 RESERVED
18 AD19 51 AD5 84 VDD 117 INTA
19 AD18 52 AD4 85 ERD1/RXCLK 118 TCK
20 VSSB 53 AD3 86 ERD0/RXDAT 119 VSS
21 AD17 54 AD2 87 LED2/SRDCLK 120 RST
22 AD16 55 VSSB 88 VSS 121 CLK
23 C/BE2 56 AD1 89 RXD- 122 VDD
24 FRAME 57 AD0 90 RXD+ 123 GNT
25 IRDY 58 EAR 91 AVDD4 124 TMS
26 TRDY 59 VDD 92 TXP- 125 VSS
27 DEVSEL 60 EROE 93 TXD- 126 REQ
28 STOP 61 VSS 94 TXP+ 127 TDO
29 LOCK 62 DXCVR/NOUT 95 TXD+ 128 AD31
30 VSS 63 VSS 96 AVDD3 129 AD30
31 PERR 64 ERACLK 97 XTAL1 130 VSSB
32 SERR 65 ERA7 98 AVSS2 131 AD29
33 VDDB 66 ERA6 99 XTAL2 132 AD28
14
Am79C970A
P R E L I M I N A R Y
AMD
PIN DESIGNATIONS – 132-PIN PQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
AD[31:0] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I N/A 1
DEVSEL Device Select IO STS6 1
FRAME Cycle Frame IO STS6 1
GNT Bus Grant I N/A 1
IDSEL Initialization Device Select I N/A 1
INTA Interrupt IO TS6 1
IRDY Initiator Ready IO STS6 1
LOCK Bus Lock I N/A 1
PAR Parity IO TS3 1
PERR Parity Error IO STS6 1
REQ Bus Request IO TS3 1
RST Reset I N/A 1
SERR System Error IO TS6 1
STOP Stop IO STS6 1
TRDY Target Ready IO STS6 1
Board Interface
LED1 LED1 O LED 1
LED2 LED2 O LED 1
LED3 LED3 O LED 1
SLEEP Sleep Mode I N/A 1
XTAL1 Crystal Input I N/A 1
XTAL2 Crystal Output O XTAL 1
Microwire EEPROM Interface
EECS Microwire Serial EEPROM Chip Select O O6 1
EEDI Microwire Serial EEPROM Data In O LED 1
EEDO Microwire Address EEPROM Data Out I N/A 1
EESK Microwire Serial PROM Clock IO LED 1
Expansion ROM Interface
ERA[7:0] Expansion ROM Address Bus O O6 8
ERACLK Expansion ROM Address Clock O O6 1
ERD[7:0] Expansion ROM Data Bus I N/A 8
EROE Expansion ROM Output Enable O O6 1
15Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS – 132-PIN PQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
Attachment Unit Interface (AUI)
CI+/CI- AUI Collision Differential Pair I N/A 2
DI+/DI- AUI Data In Differential Pair I N/A 2
DO+/DO- AUI Data Out Differential Pair O DO 2
DXCVR Disable Transceiver O O6 1
10BASE-T Interface
LNKST Link Status O LED 1
RXD+/RXD- Receive Differential Pair I N/A 2
TXD+/TXD- Transmit Differential Pair O TDO 2
TXP+/TXP- Transmit Pre-distortion Differential Pair O TPO 2
General Purpose Serial Interface (GPSI)
CLSN Collision I N/A 1
RXEN Receive Enable I N/A 1
RXDAT Receive Data I N/A 1
RXCLK Receive Clock I N/A 1
TXCLK Transmit Clock I N/A 1
TXDAT Transmit Data O O6 1
TXEN Transmit Enable O O6 1
External Address Detection Interface (EADI)
EAR External Address Reject Low I N/A 1
SFBD Start Frame Byte Delimiter O LED 1
SRD Serial Receive Data O LED 1
SRDCLK Serial Receive Data Clock O LED 1
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK Test Clock I N/A 1
TDI Test Data In I N/A 1
TDO Test Data Out O TS6 1
TMS Test Mode Select I N/A 1
Test Interface
NOUT NAND Tree Test Output O O6 1
Power Supplies
AV
AV
V
V
V
V
DD
SS
DD
SS
DDB
SSB
Analog Power P N/A 4
Analog Ground P N/A 2
Digital Power P N/A 6
Digital Ground P N/A 12
I/O Buffer Power P N/A 4
I/O Buffer Ground P N/A 8
16
Am79C970A
P R E L I M I N A R Y
PIN DESIGNATIONS – 144-PIN TQFP
Listed By Pin Number
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 NC 37 NC 73 NC 109 NC
2 VDDB 38 PAR 74 VSS 110 AVSS1
3 AD27 39 C/BE1 75 ERA5 111 DO-
4 AD26 40 AD15 76 ERA4 112 DO+
5 VSSB 41 VSSB 77 ERA3 113 AVDD1
6 AD25 42 AD14 78 ERA2 114 DI-
7 AD24 43 AD13 79 VSS 115 DI+
8 C/BE3 44 AD12 80 ERA1 116 CI-
9 VDD 45 AD11 81 ERA0 117 CI+
10 TDI 46 AD10 82 ERD7/TXDAT 118 AVDD2
11 IDSEL 47 VSSB 83 VDD 119 VDD
12 VSSB 48 AD9 84 ERD6/TXEN 120 EEDO/LED3/SRD
13 AD23 49 AD8 85 ERD5 121 EEDI/LNKST
14 AD22 50 VDDB 86 VSS 122 EESK/LED1/SFBD
15 VSSB 51 C/BE0 87 ERD4/TXCLK 123 VSS
16 AD21 52 AD7 88 ERD3/CLSN 124 EECS
17 AD20 53 AD6 89 VSS 125 SLEEP
18 VDDB 54 VSSB 90 ERD2/RXEN 126 Reserved
19 AD19 55 AD5 91 VDD 127 INTA
20 AD18 56 AD4 92 ERD1/RXCLK 128 TCK
21 VSSB 57 AD3 93 ERD0/RXDAT 129 VSS
22 AD17 58 AD2 94 LED2/SRDCLK 130 RST
23 AD16 59 VSSB 95 VSS 131 CLK
24 C/BE2 60 AD1 96 RXD- 132 VDD
25 FRAME 61 AD0 97 RXD+ 133 GNT
26 IRDY 62 EAR 98 AVDD4 134 TMS
27 TRDY 63 VDD 99 TXP- 135 VSS
28 DEVSEL 64 EROE 100 TXD- 136 REQ
29 STOP 65 VSS 101 TXP+ 137 TDO
30 LOCK 66 DXCVR/NOUT 102 TXD+ 138 AD31
31 VSS 67 VSS 103 AVDD3 139 AD30
32 PERR 68 ERACLK 104 XTAL1 140 VSSB
33 SERR 69 ERA7 105 AVSS2 141 AD29
34 VDDB 70 ERA6 106 XTAL2 142 AD28
35 NC 71 NC 107 NC 143 NC
36 NC 72 NC 108 NC 144 NC
AMD
NC - Indicates no connect
17Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS – 144-PIN TQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
AD[31:0] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I N/A 1
DEVSEL Device Select IO STS6 1
FRAME Cycle Frame IO STS6 1
GNT Bus Grant I N/A 1
IDSEL Initialization Device Select I N/A 1
INTA Interrupt IO TS6 1
IRDY Initiator Ready IO STS6 1
LOCK Bus Lock I N/A 1
PAR Parity IO TS3 1
PERR Parity Error IO STS6 1
REQ Bus Request IO TS3 1
RST Reset I N/A 1
SERR System Error IO TS6 1
STOP Stop IO STS6 1
TRDY Target Ready IO STS6 1
Board Interface
LED1 LED1 O LED 1
LED2 LED2 O LED 1
LED3 LED3 O LED 1
SLEEP Sleep Mode I N/A 1
XTAL1 Crystal Input I N/A 1
XTAL2 Crystal Output O XTAL 1
Microwire EEPROM Interface
EECS Microwire Serial EEPROM Chip Select O O6 1
EEDI Microwire Serial EEPROM Data In O LED 1
EEDO Microwire Address EEPROM Data Out I N/A 1
EESK Microwire Serial PROM Clock IO LED 1
Expansion ROM Interface
ERA[7:0] Expansion ROM Address Bus O O6 8
ERACLK Expansion ROM Address Clock O O6 1
ERD[7:0] Expansion ROM Data Bus I N/A 8
EROE Expansion ROM Output Enable O O6 1
18
Am79C970A
P R E L I M I N A R Y
AMD
PIN DESIGNATIONS – 144-PIN TQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
Attachment Unit Interface (AUI)
CI+/CI- AUI Collision Differential Pair I N/A 2
DI+/DI- AUI Data In Differential Pair I N/A 2
DO+/DO- AUI Data Out Differential Pair O DO 2
DXCVR Disable Transceiver O O6 1
10BASE-T Interface
LNKST Link Status O LED 1
RXD+/RXD- Receive Differential Pair I N/A 2
TXD+/TXD- Transmit Differential Pair O TDO 2
TXP+/TXP- Transmit Pre-distortion Differential Pair O TPO 2
General Purpose Serial Interface (GPSI)
CLSN Collision I N/A 1
RXEN Receive Enable I N/A 1
RXDAT Receive Data I N/A 1
RXCLK Receive Clock I N/A 1
TXCLK Transmit Clock I N/A 1
TXDAT Transmit Data O O6 1
TXEN Transmit Enable O O6 1
External Address Detection Interface (EADI)
EAR External Address Reject Low I N/A 1
SFBD Start Frame Byte Delimiter O LED 1
SRD Serial Receive Data O LED 1
SRDCLK Serial Receive Data Clock O LED 1
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK Test Clock I N/A 1
TDI Test Data In I N/A 1
TDO Test Data Out O TS6 1
TMS Test Mode Select I N/A 1
Test Interface
NOUT NAND Tree Test Output O O6 1
Power Supplies
AV
AV
V
V
V
V
DD
SS
DD
SS
DDB
SSB
Analog Power P N/A 4
Analog Ground P N/A 2
Digital Power P N/A 6
Digital Ground P N/A 12
I/O Buffer Power P N/A 4
I/O Buffer Ground P N/A 8
19Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS
Listed By Driver Type
The next table describes the various types of drivers that
are used in the PCnet-PCI II controller:
Name Type IOL (mA) IOH (mA) Load (pF)
LED LED 12 -0.4 50
O6 Totem Pole 6 -0.4 50
OD6 Open Drain 6 N/A 50
STS6 Sustained Tri-State
TS3 Tri-State 3 -2 50
TS6 Tri-State 6 -2 50
All IOL and IOH values shown in the table above apply to
5 V signaling. See the section “DC Characteristics” for
the values applying to 3.3 V signaling.
TM
DO, TDO and TPO are differential output drivers. The
characteristic of these and the XTAL output are described in the section “DC Characteristics”.
A sustained tri-state signal is a low active signal that is
driven high for one clock period before it is left floating.
6-250
20
Am79C970A
P R E L I M I N A R Y
AMD
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM79C970A K C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and Formed in a Tray
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0
PACKAGE TYPE
K = Plastic Quad Flat Pack (PQB132)
V = Thin Quad Flat Pack (PDL144)
°C to +70°C)
Valid Combinations
AM79C970A
DEVICE NUMBER/DESCRIPTION
Am79C970A
PCnet-PCI II Single-Chip Full-Duplex Controller
for PCI Local Bus
KC, KC\W, VC,
VC\W
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
SPEED OPTION
Not Applicable
Valid Combinations
21Am79C970A
AMD
P R E L I M I N A R Y
PIN DESCRIPTION
PCI Interface
AD[31:0]
Address and Data Input/Output
Address and data are multiplexed on the same bus interface pins. During the first clock of a transaction
AD[31:0] contain a physical address (32 bits). During
the subsequent clocks AD[31:0] contain data. Byte ordering is little endian by default. AD[7:0] are defined as
least significant byte and AD[31:24] are defined as the
most significant byte. For FIFO data transfers, the
PCnet-PCI II controller can be programmed for big
endian byte ordering. See CSR3, bit 2 (BSWP) for
more details.
During the address phase of the transaction, when the
PCnet-PCI II controller is a bus master, AD[31:2] will
address the active Double Word (DWord). The
PCnet-PCI II controller always drives AD[1:0] to ‘00’ during the address phase indicating linear burst order.
When the PCnet-PCI II controller is not a bus master,
the AD[31:0] lines are continuously monitored to determine if an address match exists for slave transfers.
During the data phase of the transaction, AD[31:0] are
driven by the PCnet-PCI II controller when performing
bus master write and slave read operations. Data on
AD[31:0] is latched by the PCnet-PCI II controller when
performing bus master read and slave write operations.
When RST is active, AD[31:0] are inputs for NAND
tree testing.
C/BE[3:0]
Bus Command and Byte Enables Input/Output
Bus command and byte enables are multiplexed on the
same bus interface pins. During the address phase of
the transaction, C/BE[3:0] define the bus command.
During the data phase C/BE[3:0] are used as byte enables. The byte enables define which physical byte
lanes carry meaningful data. C/BE0 applies to byte 0
(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The
function of the byte enables is independent of the byte
ordering mode (BSWP, CSR3, bit 2).
When RST is active, C/BE[3:0] are inputs for NAND
tree testing.
CLK
Clock Input
This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of CLK and all parameters
are defined with respect to this edge. The PCnet-PCI II
controller operates over a range of 0 MHz to 33 MHz.
This clock is not used to drive the network functions.
When RST is active, CLK is an input for NAND
tree testing.
DEVSEL
Device Select Input/Output
The PCnet-PCI II controller drives DEVSEL when it
detects a transaction that selects the device as a target.
The device samples DEVSEL to detect if a target
claims a transaction that the PCnet-PCI II controller
has initiated.
When RST is active, DEVSEL is an input for NAND
tree testing.
FRAME
Cycle Frame Input/Output
FRAME is driven by the PCnet-PCI II controller when it
is the bus master to indicate the beginning and duration
of a transaction. FRAME is asserted to indicate a bus
transaction is beginning. FRAME is asserted while data
transfers continue. FRAME is deasserted before the final data phase of a transaction. When the PCnet-PCI II
controller is in slave mode, it samples FRAME to determine the address phase of transaction.
When RST is active, FRAME is an input for NAND
tree testing.
GNT
Bus Grant Input
This signal indicates that the access to the bus has been
granted to the PCnet-PCI II controller.
The PCnet-PCI II controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNT
without an active REQ from the PCnet-PCI II controller,
the device will drive the AD[31:0], C/BE[3:0] and
PAR lines.
When RST is active, GNT is an input for NAND
tree testing.
IDSEL
Initialization Device Select Input
This signal is used as a chip select for the
PCnet-PCI II controller during configuration read and
write transactions.
When RST is active, IDSEL is an input for NAND
tree testing.
22
Am79C970A
P R E L I M I N A R Y
INTA
Interrupt Request Input/Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, EXDINT, IDON,
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,
SINT, SLPINT, TINT, TXSTRT and UINT. Each status
flag has either a mask or an enable bit which allows for
suppression of INTA assertion. The flags have the
following meaning:
Table 1. Interrupt Flags
BABL Babble
EXDINT Excessive Deferral
IDON Initialization Done
JAB Jabber
MERR Memory Error
MISS Missed Frame
MFCO Missed Frame Count Overflow
MPINT Magic Packet Interrupt
RCVCCO Receive Collision Count Overflow
RINT Receive Interrupt
SLPINT Sleep Interrupt
SINT System Error
TINT Transmit Interrupt
TXSTRT Transmit Start
UINT User Interrupt
By default INTA is an open-drain output. For applications that need a high-active edge sensitive interrupt
signal, the INTA pin can be configured for this mode by
setting INTLEVEL (BCR2, bit 7) to ONE.
When RST is active, INTA is an input for NAND
tree testing.
IRDY
Initiator Ready Input/Output
IRDY indicates the ability of the initiator of the transaction to complete the current data phase. IRDY is used in
conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the PCnet-PCI II controller is a bus master, it asserts IRDY during all write data phases to indicated that
valid data is present on AD[31:0]. During all read data
phases the device asserts IRDY to indicate that it is
ready to accept the data.
When the PCnet-PCI II controller is the target of a transaction, it checks IRDY during all write data phases to determine if valid data is present on AD[31:0]. During all
AMD
read data phases the device checks IRDY to determine
if the initiator is ready to accept the data.
When RST is active, IRDY is an input for NAND
tree testing.
LOCK
Lock Input
In slave mode, LOCK is an input to the PCnet-PCI II controller. A bus master can lock the device to guarantee an
atomic operation that requires multiple transactions.
The PCnet-PCI II controller will never assert LOCK as
a master.
When RST is active, LOCK is an input for NAND
tree testing.
PAR
Parity Input/Output
Parity is even parity across AD[31:0] and C/BE[3:0].
When the PCnet-PCI II controller is a bus master, it generates parity during the address and write data phases.
It checks parity during read data phases. When the
PCnet-PCI II controller operates in slave mode, it
checks parity during every address phase. When it is the
target of a cycle, it checks parity during write data
phases and it generates parity during read data phases.
When RST is active, PAR is an input for NAND
tree testing.
PERR
Parity Error Input/Output
During any slave write transaction and any master read
transaction, the PCnet-PCI II controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to ONE. During any master write transaction the PCnet-PCI II controller monitors PERR to see if
the target reports a data parity error.
When RST is active, PERR is an input for NAND
tree testing.
REQ
Bus Request Input/Output
The PCnet-PCI II controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the PCnet-PCI II controller does not
request the bus.
When RST is active, REQ is an input for NAND
tree testing.
RST
Reset Input
When RST is asserted low, then the PCnet-PCI II controller performs an internal system reset of the type
23Am79C970A
AMD
H_RESET (HARDWARE_RESET). RST must be held
for a minimum of 30 clock periods. While in the H_RESET state, the PCnet-PCI II controller will disable or
deassert all outputs. RST may be asynchronous to CLK
when asserted or deasserted. It is recommended that
the deassertion be synchronous to guarantee clean and
bounce free edge.
When RST is active, NAND tree testing is enabled. All
PCI interface pins are in input mode. The result of the
NAND tree testing can be observed on the NOUT
output (pin 62).
P R E L I M I N A R Y
SERR
System Error Input/Output
During any slave transaction, the PCnet-PCI II controller
asserts SERR when it detects an address parity error
and reporting of the error is enabled by setting PERREN
(PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to ONE.
By default SERR is an open-drain output. For component test it can be programmed to be an active-high totem-pole output.
When RST is active, TRDY is an input for NAND
tree testing.
Board Interface
LED1
LED1 Output
This output is designed to directly drive an LED. By default, LED1 indicates receive activity on the network.
This pin can also be programmed to indicate other
network status (see BCR5). The LED1 pin polarity is
programmable, but by default, it is active LOW.
Note that the LED1 pin is multiplexed with the EESK and
SFBD pins.
LED2
LED2 Output
This output is designed to directly drive an LED. By default, LED2 indicates correct receive polarity on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR6). The LED2
pin polarity is programmable, but by default, it is
active LOW.
When RST is active, SERR is an input for NAND
tree testing.
STOP
Stop Input/Output
In slave mode, the PCnet-PCI II controller drives the
STOP signal to inform the bus master to stop the current
transaction. In bus master mode, the PCnet-PCI II controller checks STOP to determine if the target wants to
disconnect the current transaction.
When RST is active, STOP is an input for NAND
tree testing.
TRDY
Target Ready Input/Output
TRDY indicates the ability of the target of the transaction
to complete the current data phase. TRDY is used in
conjunction with IRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the PCnet-PCI II controller is a bus master, it
checks TRDY during all read data phases to determine if
valid data is present on AD[31:0]. During all write data
phases the device checks TRDY to determine if the target is ready to accept the data.
When the PCnet-PCI II controller is the target of a transaction, it asserts TRDY during all read data phases to indicate that valid data is present on AD[31:0]. During all
write data phases the device asserts TRDY to indicate
that it is ready to accept the data.
Note that the LED2 pin is multiplexed with the
SRDCLK pin.
LED3
LED3 Output
This output is designed to directly drive an LED. By default, LED3 indicates transmit activity on the network.
This pin can also be programmed to indicate other network status (see BCR7). The LED3 pin polarity is programmable, but by default, it is active LOW.
Note that the LED3 pin is multiplexed with the EEDO
and SRD pins.
Special attention must be given to the external circuitry
attached to this pin. When this pin is used to drive an
LED while an EEPROM is used in the system, then buffering is required between the LED3 pin and the LED circuit. If an LED circuit were directly attached to this pin, it
would create an I
by the serial EEPROM attached to this pin. If no
EEPROM is included in the system design, then the
LED3 signal may be directly connected to an LED without buffering. For more details regarding LED connection, see the section “LED Support”.
OL requirement that could not be met
SLEEP
Sleep Input
When SLEEP is asserted, the PCnet-PCI II controller
performs an internal system reset of the S_RESET type
and then proceeds into a power savings mode. All
PCnet-PCI II controller outputs will be placed in their
normal reset condition. All PCnet-PCI II controller inputs
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Am79C970A
P R E L I M I N A R Y
will be ignored except for the SLEEP pin itself. Deassertion of SLEEP results in wake-up. The system must refrain from starting the network operations of the
PCnet-PCI II controller device for 0.5 s following the
deassertion of the SLEEP signal in order to allow internal analog circuits to stabilize.
Both CLK and XTAL1 inputs must have valid clock signals present in order for the SLEEP command to
take effect.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the assertion of SLEEP until three clock cycles after the completion of a hardware reset operation.
The SLEEP pin must not be left unconnected. It should
be tied to VDD, if the power savings mode is not used.
XTAL1
Crystal Oscillator In Input
The internal clock generator uses a 20 MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the crystal frequency. XTAL1
may alternatively be driven using an external 20 MHz
CMOS level clock signal. Refer to the section “External
Crystal Characteristics” for more details.
Note that when the PCnet-PCI II controller is in coma
mode, there is an internal 22 kΩ resistor from XTAL1 to
ground. If an external source drives XTAL1, some
power will be consumed driving this resistor. If XTAL1 is
driven LOW at this time power consumption will be minimized. In this case, XTAL1 must remain active for at
least 30 cycles after the assertion of SLEEP and
deassertion of REQ.
XTAL2
Crystal Oscillator Out Output
The internal clock generator uses a 20 MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the crystal frequency. If an external clock source is used on XTAL1, then XTAL 2 should
be left unconnected.
Microwire EEPROM Interface
EECS
EEPROM Chip Select Output
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EECS is connected to the Microwire EEPROM chip select pin. It is controlled by either the PCnet-PCI II controller during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
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EEDI
EEPROM Data In Output
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EEDI is connected to the Microwire EEPROM data input
pin. It is controlled by either the PCnet-PCI II controller
during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 0.
Note that the EEDI pin is multiplexed with the
LNKST pin.
EEDO
EEPROM Data Out Input
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EEDO is connected to the Microwire EEPROM data output pin. It is controlled by either the PCnet-PCI II controller during command portions of a read of the entire
EEPROM, or indirectly by the host system by reading
from BCR19, bit 0.
Note that the EEDO pin is multiplexed with the LED3
and SRD pins.
EESK
EEPROM Serial clock Input/Output
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EESK is connected to the Microwire EEPROM clock pin.
It is controlled by either the PCnet-PCI II controller directly during a read of the entire EEPROM, or indirectly
by the host system by writing to BCR19, bit 1.
Note that the EESK pin is multiplexed with the LED1 and
SFBD pins.
The EESK pin is also used during EEPROM Auto-detection to determine whether or not an EEPROM is present
at the PCnet-PCI II controller Microwire interface. At the
rising edge of CLK during the last clock during which
RST is asserted, EESK is sampled to determine the
value of the EEDET bit in BCR19. A sampled HIGH
value means that an EEPROM is present, and EEDET
will be set to ONE. A sampled LOW value means that an
EEPROM is not present, and EEDET will be cleared to
ZERO. See the section “EEPROM Auto-Detection” for
more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in order to resolve the EEDET setting.
25Am79C970A
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P R E L I M I N A R Y
Expansion ROM Interface
ERA[7:0]
Expansion ROM Address Output
These pins provide the address to the Expansion ROM.
When EROE is asserted and ERACLK is driven HIGH,
ERA[7:0] contain the upper 8 bits of the Expansion ROM
address. They must be latched externally. When EROE
is asserted and ERACLK is low, ERA[7:0] contain the
lower 8 bits of the Expansion ROM address.
All ERA outputs are forced to a constant level to conserve power while no access to the Expansion ROM
is performed.
ERACLK
Expansion ROM Address Clock Output
When EROE is asserted and ERACLK is driven HIGH,
ERA[7:0] contain the upper 8 bits of the Expansion
ROM address. ERACLK is used to latch the address
bits externally. Both ’373 (transparent latch) and ’374
(D flip-flop) types of address latch are supported.
ERD[7:0]
Expansion ROM Data Input
Data from the Expansion ROM is transferred on
ERD[7:0]. When EROE is high, the ERD[7:0] inputs are
internally disabled and can be left floating.
Note that the ERD[7:0] pins are multiplexed with the
GPSI interface.
EROE
Expansion ROM Output Enable Output
This signal is asserted when the Expansion ROM
is read.
Attachment Unit Interface
±
CI
Collision In Input
CI± is a differential input pair signaling the PCnet-PCI II
controller that a collision has been detected on the network media, indicated by the CI± inputs being driven
with a 10 MHz pattern of sufficient amplitude and pulse
width to meet ISO 8802-3 (IEEE/ANSI 802.3) standards. Operates at pseudo ECL levels.
DI±
Data In Input
DI± is a differential input pair to the PCnet-PCI II controller carrying Manchester encoded data from the network.
Operates at pseudo ECL levels.
DO±
Data Out Output
DO± is a differential output pair from the PCnet-PCI II
controller for transmitting Manchester encoded data to
the network. Operates at pseudo ECL levels.
DXCVR
Disable Transceiver Output
The DXCVR signal is provided to power down an external transceiver or DC-to-DC converter in designs that
provide more than one network connection.
The polarity of the asserted state of the DXCVR output is
controlled by DXCVRPOL (BCR2, bit 4). By default, the
DXCVR output is high when asserted. When the
10BASE-T interface is the active network port, the
DXCVR output is always deasserted. When the AUI or
GPSI interface is the active network port, the assertion
of the DXCVR output is controlled by the setting of
DXCVRCTL (BCR2, bit 5).
Note that the DXCVR pin is multiplexed with the
NOUT pin.
Twisted Pair Interface
LNKST
Link Status Output
This output is designed to directly drive an LED. By default, LNKST indicates an active link connection on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR4). The
LNKST pin polarity is programmable, but by default, it is
active LOW.
Note that the LNKST pin is multiplexed with the
EEDI pin.
RXD±
10BASE-T Receive Data Input
10BASE-T port differential receivers.
TXD±
10BASE-T Transmit Data Output
10BASE-T port differential drivers.
TXP±
10BASE-T Pre-Distortion Control Output
These outputs provide transmit pre-distortion control in
conjunction with the 10BASE-T port differential drivers.
General Purpose Serial Interface
CLSN
Collision Input
CLSN is an input, indicating that a collision has occurred
on the network.
Note that the CLSN pin is multiplexed with the ERD3 pin.
RXCLK
Receive Clock Input
RXCLK is an input. Rising edges of the RXCLK signal
are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.
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P R E L I M I N A R Y
Note that the RXCLK pin is multiplexed with the
ERD1 pin.
RXDAT
Receive Data Input
RXDAT is an input. Rising edges of the RXCLK signal
are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.
Note that the RXDAT pin is multiplexed with the
ERD0 pin.
RXEN
Receive Enable
Input
RXEN is an input. When this signal is HIGH, it indicates
to the core logic that the data on the RXDAT input pin
is valid.
Note that the RXEN pin is multiplexed with the
ERD2 pin.
TXCLK
Transmit Clock Input
TXCLK is an input, providing a clock signal for MAC activity, both transmit and receive. Rising edges of the
TXCLK can be used to validate TXDAT output data.
Note that the TXCLK pin is multiplexed with the
ERD4 pin.
TXDAT
Transmit Data Output
TXDAT is an output, providing the serial bit stream for
transmission, including preamble, SFD data and FCS
field, if applicable. TXDAT floats when the GPSI interface is not enabled.
Note that the TXDAT pin is multiplexed with the
ERD7 pin.
TXEN
Transmit Enable Output
TXEN is an output, providing an enable signal for transmission. Data on the TXDAT pin is not valid unless the
TXEN signal is HIGH. TXEN should have an external
pull-down resistor attached (e.g. 3.3 kΩ) to ensure the
output is held inactive until the GPSI interface
is enabled.
Note that the TXEN pin is multiplexed with the ERD6 pin.
External Address Detection Interface
EAR
External Address Reject Low Input
The incoming frame will be checked against the internally active address detection mechanisms and the
AMD
result of this check will be ORd with the value on the
EAR pin. The EAR pin is defined as REJECT. The pin
value is “OR”ed with the internal address detection result to determine if the current frame should be accepted
or rejected.
The EAR pin is internally pulled-up and can be left unconnected, if the EADI interface is not used.
SFBD
Start Frame—Byte Delimiter Output
An initial rising edge on the SFBD signal indicates that a
start of frame delimiter has been detected. The serial bit
stream will follow on the SRD signal, commencing with
the destination address field. SFBD will go high for 4 bit
times (400 ns) after detecting the second ONE in the
SFD (Start of Frame Delimiter) of a received frame.
SFBD will subsequently toggle every 400 ns (1.25 MHz
frequency) with each rising edge indicating the first bit of
each subsequent byte of the received serial bit stream.
SFBD will be inactive during frame transmission.
Note that the SFBD pin is multiplexed with the EESK
and LED1 pins.
SRD
Serial Receive Data Output
SRD is the decoded NRZ data from the network. This
signal can be used for external address detection. When
the 10BASE-T port is selected, transitions on SRD will
only occur during receive activity. When the AUI or GPSI
port is selected, transitions on SRD will occur during
both transmit and receive activity.
Note that the SRD pin is multiplexed with the EEDO and
LED3 pins.
SRDCLK
Serial Receive Data Clock Output
Serial Receive Data is synchronous with reference to
SRDCLK. When the 10BASE-T port is selected, transitions on SRDCLK will only occur during receive activity.
When the AUI or GPSI port is selected, transitions
on SRDCLK will occur during both transmit and
receive activity.
Note that the SRDCLK pin is multiplexed with the
LED2 pin.
IEEE 1149.1 Test Access Port Interface
TCK
Test Clock Input
TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10 MHz.
TCK has an internal pull-up resistor. The TCK input
27Am79C970A
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P R E L I M I N A R Y
operates in the same signaling environment as the PCI
bus interface.
TDI
Test Data In Input
TDI is the test data input path to the PCnet-PCI II controller. The pin has an internal pull-up resistor. The TDI
input operates in the same signaling environment as the
PCI bus interface.
TDO
Test Data Out Output
TDO is the test data output path from the PCnet-PCI II
controller. The pin is tri-stated when the JTAG port is inactive. The TDO output operates in the same signaling
environment as the PCI bus interface.
TMS
Test Mode Select Input
A serial input bit stream on the TMS pin is used to define
the specific boundary scan test to be executed. The pin
has an internal pull-up resistor. The TMS input operates
in the same signaling environment as the PCI
bus interface.
Test Interface
NOUT
NAND Tree Out Output
When RST is asserted, the results of the NAND tree
testing can be observed on the NOUT pin.
Note that the NOUT pin is multiplexed with the
DXCVR pin.
avoid excessive noise on these lines. Refer to
Appendix B and the PCnet Family Board Design and
Layout Recommendations application note (PID
#19595A) for details.
AV
SS
Analog Ground (2 Pins) Power
There are two analog ground pins. Special attention
should be paid to the printed circuit board layout to avoid
excessive noise on these lines. Refer to Appendix B and
the PCnet Family Board Design and Layout
Recommendations application note (PID #19595A)
for details.
V
DD
Digital Power (6 Pins) Power
There are six power supply pins that are used by the internal digital circuitry. All V
pins must be connected to
DD
a +5 V supply.
V
DDB
I/O Buffer Power (4 Pins) Power
There are four power supply pins that are used by the
PCI bus input/output buffer drivers. In a system with 5 V
signaling environment, all V
pins must be connected
DDB
to a +5 V supply. In a system with 3.3 V signaling
nvironment, all V
pins must be connected to a
DDB
+3.3 V supply.
V
SS
Digital Ground (12 Pins) Ground
There are 12 ground pins that are used by the internal
digital circuitry.
Power Supply Pins
AV
DD
Analog Power (4 Pins) Power
There are four analog +5 V supply pins. Special attention should be paid to the printed circuit board layout to
28
Am79C970A
V
SSB
I/O Buffer Ground (8 Pins) Ground
There are 8 ground pins that are used by the PCI bus input/output buffer drivers.
P R E L I M I N A R Y
BASIC FUNCTIONS
System Bus Interface Function
The PCnet-PCI II controller is designed to operate as a
bus master during normal operations. Some slave I/O
accesses to the PCnet-PCI II controller are required in
normal operations as well. Initialization of the
PCnet-PCI II controller is achieved through a combination of PCI Configuration Space accesses, bus slave accesses, bus master accesses and an optional read of a
serial EEPROM that is performed by the PCnet-PCI II
controller. The EEPROM read operation is performed
through the Microwire interface. The ISO 8802-3
(IEEE/ANSI 802.3) Ethernet Address may reside within
the serial EEPROM. Some PCnet-PCI II controller configuration registers may also be programmed by the
EEPROM read operation.
The Address PROM, on-chip bus-configuration registers, and the Ethernet controller registers occupy 32
bytes of address space. Both, I/O and memory mapped
I/O access are supported. Base Address registers in the
PCI configuration space allow locating the address
space on a wide variety of starting addresses.
For diskless stations, the PCnet-PCI II controller supports an Expansion ROM of up to 64 Kbytes in size. The
host can map the Expansion ROM to any memory address that aligns to a 64K boundary by modifying the
Expansion ROM Base Address register in the PCI configuration space.
Software Interface
The software interface to the PCnet-PCI II controller is
divided into three parts. One part is the PCI configuration registers. They are used to identify the PCnet-PCI II
controller, and are also used to setup the configuration
of the device. The setup information includes the I/O or
memory mapped I/O base address, mapping of the
Expansion ROM and the routing of the PCnet-PCI II
controller interrupt channel. This allows for a
jumperless implementation.
The second portion of the software interface is the direct
access to the I/O resources of the PCnet-PCI II controller. The PCnet-PCI II controller occupies 32 bytes of ad-
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dress space that must begin on a 32-byte block
boundary. The address space can be mapped into both
I/O or memory space (memory mapped I/O). The I/O
Base Address Register in the PCI Configuration Space
defines the start address of the address space if it is
mapped to I/O space. The Memory Mapped I/O Base
Address Register defines the start address of the address space if it is mapped to memory space. The
32-byte address space is used by the software to program the PCnet-PCI II controller operating mode, enable and disable various features, monitor operating
status, and request particular functions to be executed
by the PCnet-PCI II controller.
The third portion of the software interface is the descriptor and buffer areas that are shared between the software and the PCnet-PCI II controller during normal
network operations. The descriptor area boundaries are
set by the software and do not change during normal
network operations. There is one descriptor area for receive activity and there is a separate area for transmit
activity. The descriptor space contains relocatable
pointers to the network frame data and it is used to transfer frame status from the PCnet-PCI II controller to the
software. The buffer areas are locations that hold frame
data for transmission or that accept frame data that has
been received.
Network Interfaces
The PCnet-PCI II controller can be connected to an
802.3 network via one of three network interfaces. The
Attachment Unit Interface (AUI) provides an ISO 8802-3
(IEEE/ANSI 802.3) compliant differential interface to a
remote MAU or an on-board transceiver. The
10BASE-T interface provides a twisted-pair Ethernet
port. While in auto-selection mode, the interface in use
is determined by an auto-sensing mechanism which
checks the link status on the 10BASE-T port. If there is
no active link status, then the device assumes an AUI
connection. The General Purpose Serial Interface
(GPSI) allows bypassing the Manchester Encoder/Decoder (MENDEC).
The PCnet-PCI II controller implements half or full-duplex Ethernet over all three network interfaces.
29Am79C970A
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DETAILED FUNCTIONS
Slave Bus Interface Unit
The slave bus interface unit (BIU) controls all accesses
P R E L I M I N A R Y
(BCR), the Address PROM (APROM) locations and the
Expansion ROM. The table below shows the response
of the PCnet-PCI II controller to each of the PCI com-
mands in slave mode.
to the PCI configuration space, the Control and Status
Registers (CSR), the Bus Configuration Registers
Table 2. Slave Commands
C[3:0] Command Use
0000 Interrupt Acknowledge Not Used
0001 Special Cycle Not Used
0010 I/O Read Read of CSR, BCR and APROM
0011 I/O Write Write to CSR, BCR and APROM
0100 Reserved
0101 Reserved
0110 Memory Read Memory Mapped I/O Read of CSR, BCR and APROM
Read of the Expansion ROM
0111 Memory Write Memory Mapped I/O Write of CSR, BCR and APROM
Dummy Write to the Expansion ROM
1000 Reserved
1001 Reserved
1010 Configuration Read Read of the Configuration Space
1011 Configuration Write Write to the Configuration Space
1100 Memory Read Multiple Aliased to Memory Read
1101 Dual Address Cycle Not Used
1110 Memory Read Line Aliased to Memory Read
1111 Memory Write Invalidate Aliased to Memory Write
Slave Configuration Transfers
The host can access the PCnet-PCI II controller PCI
configuration space with a configuration read or write
command. The PCnet-PCI II controller will assert
DEVSEL during the address phase when IDSEL is asserted, AD[1:0] are both ZERO, and the access is a configuration cycle. AD[7:2] select the DWord location in the
configuration space. The PCnet-PCI II controller ignores AD[10:8], because it is a single function device.
AD[31:11] are don’t care.
The active bytes within a DWord are determined by the
byte enable signals. 8-bit, 16-bit and 32-bit transfers are
supported. DEVSEL is asserted two clock cycles after
the host has asserted FRAME. All configuration cycles
are of fixed length. The PCnet-PCI II controller will assert TRDY on the 4th clock of the data phase.
The PCnet-PCI II controller does not support burst
transfers for access to configuration space. When the
AD31 — AD11 AD10 — AD8 AD7 — AD2 AD1 AD0
Don’t care Don’t care DWord index 0 0
host keeps FRAME asserted for a second data phase,
the PCnet-PCI II controller will disconnect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET is on-going, the PCnet-PCI II controller will
terminate the access on the PCI bus with a disconnect/
retry response.
The PCnet-PCI II controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register,
bit 7), which is hardwired to ONE. The PCnet-PCI II controller is capable of detecting a configuration cycle even
when its address phase immediately follows the data
phase of a transaction to a different target without any
idle state in-between. There will be no contention on
the DEVSEL, TRDY and STOP signals, since the
PCnet-PCI II controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
30
Am79C970A
CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
P R E L I M I N A R Y
1 23456
ADDR
1010
BE
PAR PAR
DATA
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7
STOP
IDSEL
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Figure 1. Slave Configuration Read
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CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
P R E L I M I N A R Y
1 23456
ADDR
1011
PAR
DATA
BE
PAR
7
STOP
IDSEL
Figure 2. Slave Configuration Write
Slave I/O Transfers
After the PCnet-PCI II controller is configured as an I/O
device by setting IOEN (for regular I/O mode) or
MEMEN (for memory mapped I/O mode) in the PCI
Command register, it starts monitoring the PCI bus for
access to its CSR, BCR or EEPROM locations. If configured for regular I/O mode, the PCnet-PCI II controller
will look for an address that falls within its 32 bytes of I/O
address space (starting from the I/O base address). The
PCnet-PCI II controller asserts DEVSEL if it detects an
address match and the access is an I/O cycle. If configured for memory mapped I/O mode, the PCnet-PCI II
controller will look for an address that falls within its 32
bytes of memory address space (starting from the memory mapped I/O base address). The PCnet-PCI II controller asserts DEVSEL if it detects an address match
and the access is a memory cycle. DEVSEL is asserted
two clock cycles after the host has asserted FRAME.
The PCnet-PCI II controller will not assert DEVSEL if it
detects an address match, but the PCI command is not
of the correct type. In memory mapped I/O mode, the
PCnet-PCI II controller aliases all accesses to the I/O resources of the command types “Memory Read Multiple”
19436A-5
and “Memory Read Line” to the basic Memory Read
command. All accesses of the type “Memory Write and
Invalidate” are aliased to the basic Memory Write command. 8-bit, 16-bit and 32-bit non-burst transactions are
supported. The PCnet-PCI II controller decodes only the
upper 30 address lines to determine which I/O resource
is accessed.
The typical number of wait states added to a slave I/O or
memory mapped I/O read or write access on the part of
the PCnet-PCI II controller is 6 to 7 clock cycles,
depending upon the relative phases of the internal
Buffer Management Unit clock and the CLK signal,
since the internal Buffer Management Unit clock is a
divide-by-two version of the CLK signal.
The PCnet-PCI II controller does not support burst
transfers for access to its I/O resources. When the host
keeps FRAME asserted for a second data phase,
the PCnet-PCI II controller will disconnect the transfer.
The PCnet-PCI II controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register,
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bit 7), which is hardwired to ONE. The PCnet-PCI II
controller is capable of detecting an I/O or a memory
mapped I/O cycle even when its address phase immediately follows the data phase of a transaction to a different target, without any idle state in-between. There will
CLK
FRAME
AD
C/BE
PAR
IRDY
1 2345678
ADDR
0010
PAR
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be no contention on the DEVSEL, TRDY and STOP
signals, since the PCnet-PCI II controller asserts
DEVSEL on the second clock after FRAME is asserted
(medium timing).
109
DATA
BE
11
PAR
TRDY
DEVSEL
STOP
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Figure 3. Slave Read Using I/O Command
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FRAME
DEVSEL
CLK
AD
C/BE
PAR
IRDY
TRDY
P R E L I M I N A R Y
1 2345678
ADDR
0111
PAR
DATA
BE
PAR
109
11
STOP
Figure 4. Slave Write Using Memory Command
Expansion ROM Transfers
The host must initialize the Expansion ROM Base Address register at offset 30h in the PCI configuration
space with a valid address before enabling the access to
the device. The base address must be aligned to a 64K
boundary as indicated by ROMSIZE (PCI Expansion
ROM Base Address register, bits 15–11). The
PCnet-PCI II controller will not react to any access to the
Expansion ROM until both MEMEN (PCI Command register, bit 1) and ROMEN (PCI Expansion ROM Base Address register, bit 0) are set to ONE. After the Expansion
ROM is enabled, the PCnet-PCI II controller will assert
DEVSEL on all memory read accesses with an address
between ROMBASE and ROMBASE + 64K – 4. The
PCnet-PCI II controller aliases all accesses to the Expansion ROM of the command types “Memory Read
Multiple” and “Memory Read Line” to the basic Memory
Read command. Eight-bit, 16-bit and 32-bit read transfers are supported.
Since setting MEMEN also enables memory mapped
access to the I/O resources, attention must be given the
PCI Memory Mapped I/O Base Address register, before
enabling access to the Expansion ROM. The host must
set the PCI Memory Mapped I/O Base Address register
19436A-7
to a value that prevents the PCnet-PCI II controller from
claiming any memory cycles not intended for it.
The PCnet-PCI II controller will always read four bytes
for every host Expansion ROM read access. TRDY will
not be asserted until all four bytes are loaded into an internal scratch register. The cycle TRDY is asserted depends on the programming of the Expansion ROM
interface timing. The following figure assumes that
ROMTMG (BCR18, bits 15–12) is at its default value.
Since the target latency for the Expansion ROM access
is considerably long, the PCnet-PCI II controller disconnects at the second data phase, when the host tries do
to perform a burst read operation of the Expansion
ROM. This behavior complies with the requirements for
latency issues in the PCI environment and allows other
devices to get fair access to the bus.
When the host tries to write to the Expansion ROM, the
PCnet-PCI II controller will claim the cycle by asserting
DEVSEL. TRDY will be asserted one clock cycle later.
The write operation will have no effect.
The PCnet-PCI II controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register,
34
Am79C970A
P R E L I M I N A R Y
bit 7), which is hardwired to ONE. The PCnet-PCI II controller is capable of detecting a memory cycle even
when its address phase immediately follows the data
phase of a transaction to a different target without any
CLK
FRAME
AD
C/BE
PAR
IRDY
1 2345 424344
ADDR
CMD
BE
PAR
AMD
idle state in-between. There will be no contention on
the DEVSEL, TRDY and STOP signals, since the
PCnet-PCI II controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
45
DATA
PAR
TRDY
DEVSEL
STOP
DEVSEL is sampled
Figure 5. Expansion ROM Read
Exclusive Access
The host can lock a set of transactions to the
PCnet-PCI II controller. The lock allows exclusive access to the device and can be used to guarantee atomic
operations. The PCnet-PCI II controller transitions from
the unlocked to the locked state when LOCK is deasserted during the address phase of a transaction that selects the device as the target. The controller stays in the
locked state until both FRAME and LOCK are
deasserted, or until the device signals a target abort.
Note that this protocol means the device locks itself on
any normal transaction. The controller will unlock
automatically at the end of a normal transaction, because FRAME and LOCK will be deasserted. The lock
spans over the whole slave address space. The lock
only applies to slave accesses. The PCnet-PCI II
controller might perform bus master cycles while being
locked in slave mode. When another master tries to
19436A-8
access the PCnet-PCI II controller while it is in the
locked state, the device terminates the access with a
disconnect/retry sequence.
Slave Cycle Termination
There are three scenarios besides normal completion of
a transaction where the PCnet-PCI II controller is the
target of a slave cycle and it will terminate the access.
Disconnect When Busy
The PCnet-PCI II controller cannot service any slave access while it is reading the contents of the Microwire
EEPROM. Simultaneous access is not possible to avoid
conflicts, since the Microwire EEPROM is used to initialize some of the PCI configuration space locations and
most of the BCRs. The Microwire EEPROM read operation will always happen automatically after the deassertion of the RST pin. In addition, the host can start the
35Am79C970A
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P R E L I M I N A R Y
read operation by setting the PREAD bit (BCR19, bit
14). While the EEPROM read is on-going, the
PCnet-PCI II controller will disconnect any slave access
where it is the target by asserting STOP together with
DEVSEL, while driving TRDY high. STOP will stay as-
serted until the host removes FRAME.
Note that I/O and memory slave accesses will only be
disconnected if they are enabled by setting the IOEN or
MEMEN bit in the PCI Command register. Without the
enable bit set, the cycles will not be claimed at all. Since
CLK
1 2345
FRAME
AD
C/BE
ADDR
CMD
H_RESET clears the IOEN and MEMEN bits, for the
automatic EEPROM read after H_RESET the disconnect only applies to configuration cycles.
A second situation where the PCnet-PCI II controller will
generate a PCI disconnect/retry cycle is when the host
tries to access any of the I/O resources right after having
read the Reset register. Since the access generates an
internal reset pulse of about 1 µs in length, all further
slave accesses will be deferred until the internal reset
operation is completed.
DATA
BE
PAR
IRDY
TRDY
DEVSEL
STOP
PAR PAR
Figure 6. Disconnect Of Slave Cycle When Busy
19436A-9
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P R E L I M I N A R Y
Disconnect Of Burst Transfer
The PCnet-PCI II controller does not support burst access to the configuration space, the I/O resources, or to
the Expansion ROM. The host indicates a burst transaction by keeping FRAME asserted during the data phase.
CLK
1 2345
FRAME
AD
C/BE
PAR
IRDY
1st DATA
BE
AMD
When the PCnet-PCI II controller sees FRAME and
IRDY asserted in the clock cycle before it wants to as-
serts TRDY, it also asserts STOP at the same time. The
transfer of the first data phase is still successful, since
IRDY and TRDY are both asserted.
DATA
BE
PAR
PAR
TRDY
DEVSEL
STOP
Figure 7. Disconnect Of Slave Burst Transfer—No Host Wait States
19436A-10
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P R E L I M I N A R Y
When the host is not yet ready when the PCnet-PCI II
controller asserts TRDY, the device will wait for the host
to assert IRDY. When the host asserts IRDY and
FRAME is still asserted, the PCnet-PCI II controller will
CLK
1 23456
FRAME
AD
C/BE
PAR
IRDY
1st DATA
BE
PAR
finish the first data phase by deasserting TRDY one
clock later. At the same time, it will assert STOP to signal
a disconnect to the host. STOP will stay asserted until
the host removes FRAME.
DATA
BE
PAR
TRDY
DEVSEL
STOP
Figure 8. Disconnect Of Slave Burst Transfer—Host Inserts Wait States
19436A-11
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P R E L I M I N A R Y
Disconnect When Locked
When the PCnet-PCI II controller is locked by one
master and another master tries to access the controller, the device will disconnect the access. When the
PCnet-PCI II controller is in the locked state and it sees
LOCK asserted together with FRAME, it knows that
CLK
1 23456
FRAME
LOCK
AD
C/BE
ADDR
CMD
AMD
another master tried to access it. The PCnet-PCI II controller will respond to the access by asserting STOP together with DEVSEL while driving TRDY high, thereby
disconnecting the cycle. STOP will stay asserted until
the other master removes FRAME.
DATA
BE
PAR
IRDY
TRDY
DEVSEL
STOP
PAR PAR
Figure 9. Disconnect Of Slave Cycle When Locked
19436A-12
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P R E L I M I N A R Y
Parity Error Response
When the PCnet-PCI II controller is not the current bus
master, it samples the AD[31:0], C/BE[3:0] and the PAR
lines during the address phase of any PCI command for
a parity error. When it detects an address parity error,
the controller sets PERR (PCI Status register, bit 15) to
ONE. When reporting of that error is enabled by setting
SERREN (PCI Command register, bit 8) and PERREN
CLK
1 2345
FRAME
AD
C/BE
(PCI Command register, bit 6) to ONE, the Pcnet-PCI II
controller also drives the SERR signal low for one clock
cycle and sets SERR (PCI Status register, bit 14) to
ONE. The assertion of SERR follows the address phase
by two clock cycles. The PCnet-PCI II controller will not
assert DEVSEL for a PCI transaction that has an address parity error, when PERREN and SERREN are set
to ONE.
ADDR
CMD
1st DATA
BE
PAR
SERR
DEVSEL
PAR
Figure 10. Address Parity Error Response
PAR
19436A-13
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P R E L I M I N A R Y
During the data phase of an I/O write, memory mapped
I/O write or configuration write command that selects
the PCnet-PCI II controller as target, the device samples
the AD[31:0] and C/BE[3:0] lines for parity on the clock
edge data is transferred. PAR is sampled in the following clock cycle. If a parity error is detected and reporting
of that error is enabled by setting PERREN (PCI Command register, bit 6) to ONE, PERR is asserted one
clock later. The parity error will always set PERR (PCI
Status register, bit 15) to ONE even when PERREN is
cleared to ZERO. The PCnet-PCI II controller will finish
a transaction that has a data parity error in the normal
CLK
FRAME
AD
C/BE
1 2345678
ADDR
CMD
AMD
way by asserting TRDY. The corrupted data will be written to the addressed location.
Figure 11 shows a transaction that suffered a parity
error at the time data was transferred (clock 7, IRDY and
TRDY are both asserted). PERR is driven high at the
beginning of the data phase and then drops low due to
the parity error on clock 9, two clock cycles after the data
was transferred. After PERR is driven low, the
PCnet-PCI II controller drives PERR high for one clock
cycle, since PERR is a sustained tri-state signal.
109
DATA
BE
PAR
PERR
IRDY
TRDY
DEVSEL
PAR
PAR
Figure 11. Slave Cycle Data Parity Error Response
19436A-14
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Master Bus Interface Unit
The master bus interface unit (BIU) controls the
acquisition of the PCI bus and all accesses to the
P R E L I M I N A R Y
transmit buffer memory. The table below shows the usage of PCI commands by the PCnet-PCI II controller in
master mode.
initialization block, descriptor rings and the receive and
Table 3. Master Commands
C[3:0] Command Use
0000 Interrupt Acknowledge Not Used
0001 Special Cycle Not Used
0010 I/O Read Not Used
0011 I/O Write Not Used
0100 Reserved
0101 Reserved
0110 Memory Read Read of the Initialization Block and Descriptor Rings
Read of the Transmit Buffer in Non-burst Mode
0111 Memory Write Write to the Descriptor Rings and to the Receive Buffer
1000 Reserved
1001 Reserved
1010 Configuration Read Not Used
1011 Configuration Write Not Used
1100 Memory Read Multiple Read of the Transmit Buffer in Burst Mode
1101 Dual Address Cycle Not Used
1110 Memory Read Line Read of the Transmit Buffer in Burst Mode
1111 Memory Write Invalidate Not Used
Bus Acquisition
The PCnet-PCI II controller microcode will determine
when a DMA transfer should be initiated. The first step in
any PCnet-PCI II controller bus master transfer is to
acquire ownership of the bus. This task is handled by
synchronous logic within the BIU. Bus ownership is requested with the REQ signal and ownership is granted
by the arbiter through the GNT signal.
Figure 12 shows the PCnet-PCI II controller bus
acquisition. REQ is asserted and the arbiter returns
GNT while another bus master is transferring data. The
PCnet-PCI II controller waits until the bus is idle
(FRAME and IRDY deasserted) before it starts driving
AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted
at clock 5 indicating a valid address and command on
AD[31:0] and C/BE[3:0]. The PCnet-PCI II controller
does not use address stepping which is reflected by
ADSTEP (bit 7) in the PCI Command register being
hardwired to ZERO.
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to ZERO , REQ is deasserted at the same time
as FRAME is asserted. (The PCnet-PCI II controller
never performs more than one burst transaction within a
single bus mastership period). If EXTREQ is set to ONE,
the PCnet-PCI II controller does not deassert REQ until
it starts the last data phase of the transaction.
Once asserted, REQ remains active until GNT has become active, independent of subsequent setting of the
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The assertion of H_RESET or S_RESET, however, will cause
REQ to go inactive immediately.
42
Am79C970A
CLK
FRAME
AD
C/BE
IRDY
REQ
GNT
P R E L I M I N A R Y
1 2345
ADDR
CMD
AMD
19436A-15
Figure 12. Bus Acquisition
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
PCnet-PCI II controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Basic Non-Burst Read Transfer
By default, the PCnet-PCI II controller uses non-burst
cycles in all bus master read operations. All
PCnet-PCI II controller non-burst read accesses are of
the PCI command type Memory Read (type 6). Note that
during a non-burst read operation, all byte lanes will always be active. The PCnet-PCI II controller will internally discard unneeded bytes.
The PCnet-PCI II controller typically performs more
than one non-burst read transactions within a single bus
mastership period. FRAME is dropped between consecutive non-burst read cycles. REQ however stays
asserted until FRAME is asserted for the last
transaction. The PCnet-PCI II controller supports zero
wait state read cycles. It asserts IRDY immediately after
the address phase and at the same time starts
sampling DEVSEL.
43Am79C970A
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P R E L I M I N A R Y
The following figure shows two non-burst read transactions. The first transaction has zero wait states. In the
CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
1 2345678
ADDR
0110
PAR
DATA
0000
second transaction, the target extends the cycle by asserting TRDY one clock later.
11
PAR
ADDR
0110
PAR PAR
109
DATA
0000
DEVSEL
REQ
GNT
DEVSEL is sampled
Figure 13. Non-Burst Read Transfer
Basic Burst Read Transfer
The PCnet-PCI II controller supports burst mode for all
bus master read operations. The burst mode must be
enabled by setting BREADE (BCR18, bit 6). To allow
burst transfers in descriptor read operations, the
PCnet-PCI II controller must also be programmed to use
SWSTYLE THREE (BCR20, bits 7–0). All burst read
accesses to the initialization block and descriptor ring
are of the PCI command type Memory Read (type 6).
Burst read accesses to the transmit buffer typically are
longer than two data phases. When MEMCMD (BCR18,
bit 9) is cleared to ZERO, all burst read accesses to the
transmit buffer are of the PCI command type Memory
Read Line (type 14). When MEMCMD (BCR18, bit 9) is
set to ONE, all burst read accesses to the transmit buffer
19436A-16
are of the PCI command type Memory Read Multiple
(type 12). AD[1:0] will both be ZERO during the address
phase indicating a linear burst order. Note that during a
burst read operation, all byte lanes will always be active.
The PCnet-PCI II controller will internally discard
unneeded bytes.
The PCnet-PCI II controller will always perform only a
single burst read transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The PCnet-PCI II controller
supports zero wait state read cycles. It asserts IRDY immediately after the address phase and at the same time
starts sampling DEVSEL. FRAME is deasserted when
the next to last data phase is completed.
44
Am79C970A
P R E L I M I N A R Y
The following figure shows a typical burst read access.
The PCnet-PCI II controller arbitrates for the bus, is
granted access, and reads three 32-bit words (DWord)
from the system memory and then releases the bus. In
the example, the memory system extends the data
CLK
FRAME
AD
C/BE
PAR
IRDY
1 2345678
ADDR
PAR
AMD
phase of the each access by one wait state. The example assumes that EXTREQ (BCR18, bit 8) is cleared to
ZERO, therefore, REQ is deasserted in the same cycle
as FRAME is asserted.
11
PAR
DATA
DATA
00000110
PAR PAR
109
DATA
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
Figure 14. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)
Basic Non-Burst Write Transfer
By default, the PCnet-PCI II controller uses non-burst
cycles in all bus master write operations. All
PCnet-PCI II controller non-burst write accesses are of
the PCI command type Memory Write (type 7). The
byte enable signals indicate the byte lanes that have
valid data.
The PCnet-PCI II controller typically performs more
than one non-burst write transactions within a single bus
19436A-17
mastership period. FRAME is dropped between
consecutive non-burst write cycles. REQ however stays
asserted until FRAME is asserted for the last transaction. The PCnet-PCI II controller supports zero wait
state write cycles except with the case of descriptor
write transfers. (See the section “Descriptor DMA
Transfers” for the only exception.) It asserts IRDY immediately after the address phase and at the same time
starts sampling DEVSEL.
45Am79C970A
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P R E L I M I N A R Y
The following figure shows two non-burst write transactions. The first transaction has two wait states. The target inserts one wait state by asserting DEVSEL one
clock late and another wait state by also asserting TRDY
CLK
FRAME
AD
C/BE
PAR
IRDY
1 2345678
ADDR
0111
PAR
DATA
one clock late. The second transaction shows a zero
wait state write cycle. The target asserts DEVSEL and
TRDY in the same cycle as the PCnet-PCI II controller
asserts IRDY.
109
DATA
BE
PAR
PAR
BE
ADDR
0111
PAR
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
Figure 15. Non-Burst Write Transfer
Basic Burst Write Transfer
The PCnet-PCI II controller supports burst mode for all
bus master write operations. The burst mode must be
enabled by setting BWRITE (BCR18, bit 5). To allow
burst transfers in descriptor write operations, the
PCnet-PCI II controller must also be programmed to use
SWSTYLE THREE (BCR20, bits 7–0). All PCnet-PCI II
controller burst write transfers are of the PCI command
type Memory Write (type 7). AD[1:0] will both be ZERO
during the address phase indicating a linear burst order.
The byte enable signals indicate the byte lanes that
have valid data.
19436A-18
The PCnet-PCI II controller will always perform a single
burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The PCnet-PCI II controller
supports zero wait state write cycles except with the
case of descriptor write transfers. (See the section
“Descriptor DMA Transfers” for the only exception.) It
asserts IRDY immediately after the address phase and
at the same time starts sampling DEVSEL. FRAME is
deasserted when the next to the last data phase
is completed.
46
Am79C970A
P R E L I M I N A R Y
The following figure shows a typical burst write access.
The PCnet-PCI II controller arbitrates for the bus, is
granted access, and writes four 32-bit words (DWords)
to the system memory and then releases the bus. In this
example, the memory system extends the data phase of
the first access by one wait state. The following three
CLK
12345678
FRAME
AD
C/BE
PAR
IRDY
ADDR
0111
DATA
PAR
AMD
data phases take one clock cycle each, which is determined by the timing of TRDY. The example assumes
that EXTREQ (BCR18, bit 8) is set to ONE, therefore,
REQ is not deasserted until the next to last data phase
is finished.
9
DATA DATA
BE
PAR
PAR PAR
DATA
PAR
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
19436A-19
Figure 16. Burst Write Transfer (EXTREQ = 1)
47Am79C970A
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P R E L I M I N A R Y
Target Initiated Termination
When the PCnet-PCI II controller is a bus master, the
cycles it produces on the PCI bus may be terminated by
the target in one of three different ways.
Disconnect With Data Transfer
The figure below shows a disconnection in which one
last data transfer occurs after the target asserted STOP.
STOP is asserted on clock 4 to start the termination
CLK
FRAME
AD
C/BE
1 2345678
ADDR
i
DATA
DATA
00000111
sequence. Data is still transferred during this
cycle, since both IRDY and TRDY are asserted. The
PCnet-PCI II controller terminates the current transfer
with the deassertion of FRAME on clock 5 and of IRDY
one clock later. It finally releases the bus on clock 6. The
PCnet-PCI II controller will re-request the bus after 2
clock cycles, if it wants to transfer more data. The starting address of the new transfer will be the address of the
next untransferred data.
9
10
ADDRi+8
0111
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
PAR
DEVSEL is sampled
Figure 17. Disconnect With Data Transfer
PAR
19436A-20
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Am79C970A
P R E L I M I N A R Y
Disconnect Without Data Transfer
The figure below shows a target disconnect sequence
during which no data is transferred. STOP is asserted
on clock 4 without TRDY being asserted at the same
time. The PCnet-PCI II controller terminates the access
with the deassertion of FRAME on clock 5 and of IRDY
CLK
FRAME
AD
C/BE
PAR
1 2345678
ADDR
DATA
i
00000111
PAR
PAR
AMD
one clock cycle later. It finally releases the bus on
clock 6. The PCnet-PCI II controller will re-request the
bus after 2 clock cycles to retry the last transfer. The
starting address of the new transfer will be the address
of the last untransferred data.
ADDR
0111
10
i
9
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled
19436A-21
Figure 18. Disconnect Without Data Transfer
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P R E L I M I N A R Y
Target Abort
The figure below shows a target abort sequence. The
target asserts DEVSEL for one clock. It then deasserts
DEVSEL and asserts STOP on clock 4. A target can use
the target abort sequence to indicate that it cannot service the data transfer and that it does not want the
transaction to be retried. Additionally, the PCnet-PCI II
controller cannot make any assumption about the success of the previous data transfers in the current transaction. The PCnet-PCI II controller terminates the
current transfer with the deassertion of FRAME on clock
5 and of IRDY one clock cycle later. It finally releases the
bus on clock 6.
Since data integrity is not guaranteed, the PCnet-PCI II
controller cannot recover from a target abort event. The
PCnet-PCI II controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI
CLK
1 23456
FRAME
configuration registers will not be cleared. Any on-going
network transmission is terminated in an orderly sequence. If less than 512 bits have been transmitted onto
the network, the transmission will be terminated immediately, generating a runt packet. If 512 bits or more
have been transmitted, the message will have the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is detected at the
receiving station.
RTABORT (PCI Status register, bit 12) will be set to indicate that the PCnet-PCI II controller has received a target abort. In addition, SINT (CSR5, bit 11) will be set to
ONE. When SINT is set, INTA is asserted if the enable
bit SINTE (CSR5, bit 10) is set to ONE. This mechanism
can be used to inform the driver of the system error. The
host can read the PCI Status register to determine the
exact cause of the interrupt.
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
ADDR
0111
DATA
0000
PAR PAR
50
DEVSEL is sampled
19436A-22
Figure 19. Target Abort
Am79C970A
P R E L I M I N A R Y
Master Initiated Termination
There are three scenarios besides normal completion of
a transaction where the PCnet-PCI II controller will terminate the cycles it produces on the PCI bus.
Preemption During Non-Burst Transaction
When the PCnet-PCI II controller performs multiple
CLK
1 234567
FRAME
AD
C/BE
PAR
ADDR
AMD
non-burst transactions, it keeps REQ asserted until the
assertion of FRAME for the last transaction. When GNT
is removed, the PCnet-PCI II controller will finish the
current transaction and then release the bus. If it is not
the last transaction, REQ will remain asserted to regain
bus ownership as soon as possible.
DATA
BE0111
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
Figure 20. Preemption During Non-Burst Transaction
19436A-23
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P R E L I M I N A R Y
Preemption During Burst Transaction
When the PCnet-PCI II controller operates in burst
mode, it only performs a single transaction per bus mastership period, where transaction is defined as one address phase and one or multiple data phases. The
central arbiter can remove GNT at any time during the
transaction. The PCnet-PCI II controller will ignore the
deassertion of GNT and continue with data transfers, as
long as the PCI Latency Timer is not expired. When the
Latency Timer is ZERO and GNT is deasserted, the
PCnet-PCI II controller will finish the current data phase,
deassert FRAME, finish the last data phase and release
the bus. If EXTREQ (BCR18, bit 8) is cleared to ZERO, it
will immediately assert REQ to regain bus ownership as
CLK
FRAME
AD
1 234
ADDR
DATA
soon as possible. If EXTREQ is set to ONE, REQ will
stay asserted. When the preemption occurs after the
counter has counted down to ZERO, the PCnet-PCI II
controller will finish the current data phase, deassert
FRAME, finish the last data phase and release the bus.
Note that it is important for the host to program the PCI
Latency Timer according to the bus bandwidth requirement of the PCnet-PCI II controller. The host can determine this bus bandwidth requirement by reading the PCI
MAX_LAT and MIN_GNT registers.
The figure below assumes that the PCI Latency Timer
has counted down to ZERO on clock 7.
DATA
5
DATA
6
78
DATA
DATA
9
C/BE
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
BE0111
PAR
DEVSEL is sampled
PAR PAR PAR
Figure 21. Preemption During Burst Transaction
PAR
PAR
19436A-24
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P R E L I M I N A R Y
Master Abort
The PCnet-PCI II controller will terminate its cycle with a
Master Abort sequence if DEVSEL is not asserted within
4 clocks after FRAME is asserted. Master Abort is
treated as a fatal error by the PCnet-PCI II controller.
The PCnet-PCI II controller will reset all CSR locations
to their STOP_RESET values. The BCR and PCI configuration registers will not be cleared. Any on-going network transmission is terminated in an orderly sequence.
If less than 512 bits have been transmitted onto the network, the transmission will be terminated immediately,
generating a runt packet. If 512 bits or more have been
transmitted, the message will have the current FCS
CLK
FRAME
AD
1 234
ADDR
AMD
inverted and appended at the next byte boundary to
guarantee an FCS error is detected at the
receiving station.
RMABORT (in the PCI Status register, bit 13) will be set
to indicate that the PCnet-PCI II controller has terminated its transaction with a master abort. In addition,
SINT (CSR5, bit 11) will be set to ONE. When SINT is
set, INTA is asserted if the enable bit SINTE (CSR5, bit
10) is set to ONE. This mechanism can be used to inform the driver of the system error. The host can read
the PCI Status register to determine the exact cause
of the interrupt.
5
DATA
6
78
9
C/BE
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
0111
DEVSEL is sampled
Figure 22. Master Abort
PAR
0000
PAR
19436A-25
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P R E L I M I N A R Y
Parity Error Response
During every data phase of a DMA read operation, when
the target indicates that the data is valid by asserting
TRDY, the PCnet-PCI II controller samples the
AD[31:0], C/BE[3:0] and the PAR lines for a data parity
error. When it detects a data parity error, the controller
sets PERR (PCI Status register, bit 15) to ONE. When
reporting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to ONE, the PCnet-PCI II
controller also drives the PERR signal low and sets
DATAPERR (PCI Status register, bit 8) to ONE. The
CLK
FRAME
AD
C/BE
1 234
ADDR
assertion of PERR follows the corrupted data/byte enables by two clock cycles and PAR by one clock cycle.
The figure below shows a transaction that has a parity
error in the data phase. The PCnet-PCI II controller asserts PERR on clock 8, two clock cycles after data is
valid. The data on clock 5 is not checked for parity, since
on a read access PAR is only required to be valid
one clock after the target has asserted TRDY. The
PCnet-PCI II controller then drives PERR high for one
clock cycle, since PERR is a sustained tri-state signal.
BE0111
5
DATA
6
78
9
PAR
PERR
IRDY
TRDY
DEVSEL
DEVSEL is sampled
PAR
Figure 23. Master Cycle Data Parity Error Response
During every data phase of a DMA write operation, the
PCnet-PCI II controller checks the PERR input to see if
the target reports a parity error. When it sees the PERR
input asserted, the controller sets PERR (PCI Status
register, bit 15) to ONE. When PERREN (PCI Command register, bit 6) is set to ONE, the PCnet-PCI II controller also sets DATAPERR (PCI Status register, bit 8)
to ONE.
Whenever the PCnet-PCI II controller is the current bus
master and a data parity error occurs, SINT (CSR5, bit
11) will be set to ONE. When SINT is set, INTA is as-
PAR
19436A-26
serted if the enable bit SINTE (CSR5, bit 10) is set to
ONE. This mechanism can be used to inform the driver
of the system error. The host can read the PCI Status
register to determine the exact cause of the interrupt.
The setting of SINT due to a data parity error is not dependent on the setting of PERREN (PCI Command
register, bit 6).
By default, a data parity error does not affect the state of
the MAC engine. The PCnet-PCI II controller treats the
data in all bus master transfers that have a parity
54
Am79C970A
P R E L I M I N A R Y
error as if nothing has happened. All network
activity continues.
Advanced Parity Error Handling
For all DMA cycles, the PCnet-PCI II controller provides
a second, more advanced level of parity error handling.
This mode is enabled by setting APERREN (BCR20,
bit 10) to ONE.
When APERREN is set to ONE, the BPE bits (RMD1
and TMD1, bit 23) are used to indicate parity error in
data transfers to the receive and transmit buffers. Note
that since the advanced parity error handling uses an
additional bit in the descriptor, SWSTYLE (BCR20, bits
7–0) must be set to ONE, TWO or THREE to program
the PCnet-PCI II controller to use 32-bit software
structures. The PCnet-PCI II controller will react in the
following way when a data parity error occurs:
■ Initialization block read: STOP (CSR0, bit 2) is set to
ONE and causes a STOP_RESET of the device.
■ Descriptor ring read: Any on-going network activity is
terminated in an orderly sequence and then STOP
(CSR0, bit 2) is set to ONE to cause a STOP_RESET
of the device.
■ Descriptor ring write: Any on-going network activity
is terminated in an orderly sequence and then STOP
(CSR0, bit 2) is set to ONE to cause a STOP_RESET
of the device.
AMD
■ Transmit buffer read: BPE (TMD1, bit 23) is set in the
current transmit descriptor. Any on-going network
transmission is terminated in an orderly sequence.
■ Receive buffer write: BPE (RMD1, bit 23) is set in the
last receive descriptor associated with the frame.
Terminating on-going network transmission in an orderly sequence means that if less than 512 bits have
been transmitted onto the network, the transmission will
be terminated immediately, generating a runt packet. If
512 bits or more have been transmitted, the message
will have the current FCS inverted and appended at the
next byte boundary to guarantee an FCS error is detected at the receiving station.
APERREN does not affect the reporting of address parity errors or data parity errors that occur when the
PCnet-PCI II controller is the target of the transfer.
55Am79C970A
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P R E L I M I N A R Y
Initialization Block DMA Transfers
During execution of the PCnet-PCI II controller bus
master initialization procedure, the PCnet-PCI II controller microcode will repeatedly request DMA transfers
from the BIU. During each of these initialization block
DMA transfers, the BIU will perform two data transfer cycles reading one DWord per transfer and then it will relinquish the bus. When SSIZE32 (BCR20, bit 8) is set to
ONE (i.e. the initialization block is organized as 32-bit
software structures), there are 7 DWords to transfer during the bus master initialization procedure, so four bus
mastership periods are needed in order to complete the
initialization sequence. Note that the last DWord transfer of the last bus mastership period of the initialization
sequence accesses an unneeded location. Data from
this transfer is discarded internally. When SSIZE32 is
cleared to ZERO (i.e. the initialization block is
CLK
FRAME
1 2345678
organized as 16-bit software structures), then three bus
mastership periods are needed to complete the
initialization sequence.
The PCnet-PCI II controller supports two transfer
modes for reading the initialization block: non-burst and
burst mode; with burst mode being the preferred mode
when the PCnet-PCI II controller is used in a PCI
bus application.
When BREADE is cleared to ZERO (BCR18, bit 6), all
initialization block read transfers will be executed in
non-burst mode. There is a new address phase for
every data phase. FRAME will be dropped between
the two transfers. The two phases within a bus
mastership period will have addresses of ascending
contiguous order.
109
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
IADD
DEVSEL is sampled
DATA
0000
PAR
19436A-27
PAR
IADDi+4
0110
PAR
i
PAR
DATA
00000110
56
Figure 24. Initialization Block Read In Non-Burst Mode
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P R E L I M I N A R Y
When BREADE is set to ONE (BCR18, bit 6), all initialization block read transfers will be executed in burst
CLK
1 234567
FRAME
AD
IADD
C/BE
PAR
IRDY
TRDY
mode. AD[1:0] will be ZERO during the address phase
indicating a linear burst order.
i
DATA DATA
00000110
PAR PAR
PAR
AMD
DEVSEL
REQ
GNT
DEVSEL is sampled
19436A-28
Figure 25. Initialization Block Read In Burst Mode
57Am79C970A
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P R E L I M I N A R Y
Descriptor DMA Transfers
PCnet-PCI II controller microcode will determine when a
descriptor access is required. A descriptor DMA read
will consist of two data transfers. A descriptor DMA write
will consist of one or two data transfers. The descriptor
DMA transfers within a single bus mastership period will
always be of the same type (either all read or all write).
During descriptor read accesses, the byte enable signals will indicate that all byte lanes are active. Should
some of the bytes not be needed, then the PCnet-PCI II
controller will internally discard the extraneous information that was gathered during such a read.
The settings of SWSTYLE (BCR20, bits 7–0) and
BREADE (BCR18, bit 6) affect the way the PCnet-PCI II
controller performs descriptor read operations.
When SWSTYLE is set to ZERO, ONE or TWO, all
descriptor read operations are performed in non-burst
mode. The setting of BREADE has no effect in
this configuration.
When SWSTYLE is set to THREE, the descriptor entries
are ordered to allow burst transfers. The PCnet-PCI II
controller will perform all descriptor read operations in
burst mode, if BREADE is set to ONE.
Table 4. Descriptor Read Sequence
SWSTYLE BREADE
BCR18[6] BCR20[7:0] AD Bus Sequence
0 X Address = XXXX XX00h
Turn around cycle
Data = MD1[31:24], MD0[23:0]
Idle
Address = XXXX XX04h
Turn around cycle
Data = MD2[15:0], MD1[15:0]
1,2 X Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX00h
Turn around cycle
Data = MD0[31:0]
3 0 Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX08h
Turn around cycle
Data = MD0[31:0]
3 1 Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Data = MD0[31:0]
58
Am79C970A
CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
P R E L I M I N A R Y
1 2345678
MD1
PAR
DATA DATA
00000110
PAR
MD0
PAR PAR
00000110
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109
REQ
GNT
DEVSEL is sampled
Figure 26. Descriptor Ring Read In Non-Burst Mode
During descriptor write accesses, only the byte lanes
which need to be written are enabled.
If buffer chaining is used, accesses to the descriptors of
all intermediate buffers consist of only one data transfer
to return ownership of the buffer to the system. When
SWSTYLE (BCR20, bits 7–0) is cleared to ZERO (i.e.
the descriptor entries are organized as 16-bit software
structures), the descriptor access will write a single byte.
When SWSTYLE (BCR20, bits 7–0) is set to ONE, TWO
19436A-29
or THREE (i.e. the descriptor entries are organized as
32-bit software structures), the descriptor access will
write a single word. On all single buffer transmit or receive descriptors, as well as on the last buffer in chain,
writes to the descriptor consist of two data transfers. The
first one writing a DWord containing status information.
The second data transfer writing a byte (SWSTYLE
cleared to ZERO) or otherwise a word containing additional status and the ownership bit (i.e. MD1[31]).
59Am79C970A
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CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
P R E L I M I N A R Y
1 234567
MD1
PAR PAR
DATA
00000110
DATA
PAR
REQ
GNT
DEVSEL is sampled
Figure 27. Descriptor Ring Read In Burst Mode
The settings of SWSTYLE (BCR20, bits 7–0) and
BWRITE (BCR18, bit 5) affect the way the PCnet-PCI II
controller performs descriptor write operations.
When SWSTYLE is set to ZERO, ONE or TWO, all
descriptor write operations are performed in non-burst
mode. The setting of BWRITE has no effect in
this configuration.
When SWSTYLE is set to THREE, the descriptor entries
are ordered to allow burst transfers. The PCnet-PCI II
controller will perform all descriptor write operations in
burst mode, if BWRITE is set to ONE.
A write transaction to the descriptor ring entries is the
only case where the PCnet-PCI II controller inserts a
wait state when being the bus master. Every data phase
in non-burst and burst mode is extended by one clock
cycle, during which IRDY is deasserted.
19436A-30
Table 5. Descriptor Write Sequence
SWSTYLE BWRITE
BCR20[7:0] BCR18[5] AD Bus Sequence
0 X Address = XXXX XX04h
Data = MD2[15:0], MD1[15:0]
Idle
Address = XXXX XX00h
Data = MD1[31:24]
1,2 X Address = XXXX XX08h
Data = MD2[31:0]
Idle
Address = XXXX XX04h
Data = MD1[31:16]
3 0 Address = XXXX XX00h
Data = MD2[31:0]
Idle
Address = XXXX XX04h
Data = MD1[31:16]
60
3 1 Address = XXXX XX00h
Data = MD2[31:0]
Data = MD1[31:16]
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Note that the figure below assumes that the
PCnet-PCI II controller is programmed to use 32-bit
software structures (SWSTYLE = 1, 2, or 3). The byte
CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
1 2345678
MD2
00000111
PAR
enable signals for the second data transfer would be
0111b, if the device was programmed to use 16-bit software structures (SWSTYLE = 0).
109
DATA
PAR
MD1
PAR
DATA
00110111
PAR
AMD
DEVSEL
REQ
GNT
DEVSEL is sampled
19436A-31
Figure 28. Descriptor Ring Write In Non-Burst Mode
61Am79C970A
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CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
P R E L I M I N A R Y
1 2 4 6 7 8
35
MD2
0110
PAR
DATA
0000 0011
PAR
DATA
PAR
REQ
GNT
DEVSEL is sampled
Figure 29. Descriptor Ring Write In Burst Mode
FIFO DMA Transfers
PCnet-PCI II controller microcode will determine when a
FIFO DMA transfer is required. This transfer mode will
be used for transfers of data to and from the
PCnet-PCI II controller FIFOs. Once the PCnet-PCI II
controller BIU has been granted bus mastership, it will
perform a series of consecutive transfer cycles before
relinquishing the bus. All transfers within the master cycle will be either read or write cycles, and all transfers
will be to contiguous, ascending addresses. Both nonburst and burst cycles are used, with burst mode being
the preferred mode when the device is used in a PCI
bus application.
Non-Burst FIFO DMA Transfers
In the default mode the PCnet-PCI II controller uses
non-burst transfers to read and write data when
accessing the FIFOs. Each non-burst transfer will be
performed sequentially, with the issue of an address,
and the transfer of the corresponding data with appropriate output signals to indicate selection of the active data
bytes during the transfer. FRAME will be deasserted
62
Am79C970A
19436A-32
after every address phase. The number of data transfer
cycles contained within a single bus mastership period
is in general dependent on the programming of the
DMAPLUS option (CSR4, bit 14). Several other factors
will also affect the length of the bus mastership period.
The possibilities are as follows:
If DMAPLUS is cleared to ZERO, a maximum of 16
transfers will be performed by default. This default value
may be changed by writing to the DMA Transfer Counter
(CSR80). Note that DMAPLUS = 0 merely sets a
maximum value. The minimum number of transfers in
the bus mastership period will be determined by all of
the following variables: the settings of the FIFO watermarks (CSR80), the conditions of the FIFOs, the value
of the DMA Transfer Counter (CSR80), the value of the
DMA Bus Timer (CSR82), and any occurrence of
preemption that takes place during the bus
mastership period.
If DMAPLUS is set to ONE, bus cycles will continue until
the transmit FIFO is filled to its high threshold (read
transfers) or the receive FIFO is emptied to its low
P R E L I M I N A R Y
threshold (write transfers), or until the DMA Bus Activity
Timer (CSR82) has expired. The exact number of total
transfer cycles in the bus mastership period is dependent on all of the following variables: the settings of the
FIFO watermarks, the conditions of the FIFOs, the
latency of the system bus to the PCnet-PCI II controller’s
bus request, the speed of bus operation and bus
preemption events. The DMA Transfer Counter is
disabled when DMAPLUS is set to ONE. The TRDY response time of the memory device will also affect the
number of transfers, since the speed of the accesses
will affect the state of the FIFO. During accesses, the
FIFO may be filling or emptying on the network end. For
example, on a receive operation, a slower TRDY response will allow additional data to accumulate inside of
the FIFO. If the accesses are slow enough, a complete
DWord may become available before the end of the bus
mastership period and thereby increase the number of
transfers in that period. The general rule is that the
longer the Bus Grant latency, the slower the bus transfer
operations, the slower the clock speed, the higher the
transmit watermark or the lower the receive watermark,
the longer the bus mastership period will be.
AMD
Note that the PCI Latency Timer is not significant during
non-burst transfers.
Burst FIFO DMA Transfers
Bursting is only performed by the PCnet-PCI II controller
if the BREADE and/or BWRITE bits of BCR18 are set.
These bits individually enable/disable the ability of the
PCnet-PCI II controller to perform burst accesses
during master read operations and master write
operations, respectively.
A burst transaction will start with an address phase, followed by one or more data phases. AD[1:0] will always
be ZERO during the address phase indicating a linear
burst order.
During FIFO DMA read operations, all byte lanes will always be active. The PCnet-PCI II controller will internally discard unused bytes. During the first and the last
data phases of a FIFO DMA burst write operation, one or
more of the byte enable signals may be inactive. All
other data phases will always write a complete DWord.
63Am79C970A
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P R E L I M I N A R Y
The following figure shows the beginning of a FIFO DMA
write with the beginning of the buffer not aligned to a
DWord boundary. The PCnet-PCI II controller starts off
by writing only three bytes during the first data phase.
CLK
1 23456
FRAME
AD
C/BE
PAR
IRDY
This operation aligns the address for all other data transfers to a 32-bit boundary so that the PCnet-PCI II controller can continue bursting full DWords.
ADD
DATA
0001
PAR PAR
DATA DATA
00000111
PAR
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
Figure 30. FIFO Burst Write At Start Of Unaligned Buffer
19436A-33
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P R E L I M I N A R Y
If a receive buffer does not end on a DWord boundary,
the PCnet-PCI II controller will perform a non-DWord
write on the last transfer to the buffer. The following figure shows the final three FIFO DMA transfers to a receive buffer. Since there were only nine bytes of space
left in the receive buffer, the PCnet-PCI II controller
burst three data phases. The first two data phases write
a full DWord, the last one only writes a single byte.
Note that the PCnet-PCI II controller will always perform
a DWord transfer as long as it owns the buffer space,
CLK
1 234567
FRAME
AD
C/BE
ADD
AMD
even when there are less then four bytes to write. For example, if there is only one byte left for the current receive
frame, the PCnet-PCI II controller will write a full DWord,
containing the last byte of the receive frame in the least
significant byte position (BSWP is cleared to ZERO,
CSR3, bit 2). The content of the other three bytes is
undefined. The message byte count in the receive
descriptor always reflects the exact length of the
received frame.
DATA
DATA DATA
00000111
1110
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
Figure 31. FIFO Burst Write At End Of Unaligned Buffer
In a PCI bus application the PCnet-PCI II controller
should be set up to have the length of a bus mastership
period be controlled only by the PCI Latency Timer. The
Timer bit (CSR4, bit 13) should remain at its default
value of ZERO so that the DMA Bus Activity Timer
(CSR82) is not enabled. The DMA Transfer Counter
(CSR80) should be disabled by setting DMAPLUS
(CSR4, bit 14) to ONE. In this mode, the PCnet-PCI II
controller will continue transferring FIFO data until the
PAR PAR
PAR
PAR
19436A-34
transmit FIFO is filled to its high threshold (read transfers) or the receive FIFO is emptied to its low threshold
(write transfers), or the PCnet-PCI II controller is
preempted, and the PCI Latency Timer is expired. The
host should use the values in the PCI MIN_GNT and
MAX_LAT registers to determine the value for the PCI
Latency Timer.
65Am79C970A
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P R E L I M I N A R Y
In applications that don’t use the PCI Latency Timer or
that don’t support preemption the following rules apply
to limit the time the PCnet-PCI II controller takes up on
the bus.
If DMAPLUS is cleared to ZERO, a maximum of 16
transfers will be performed by default. This default value
may be changed by writing to the DMA Transfer Counter
(CSR80). Note that DMAPLUS = 0 merely sets a maximum value. The minimum number of transfers in the bus
mastership period will be determined by all of the following variables: the settings of the FIFO watermarks
(CSR80), the conditions of the FIFOs, the value of the
DMA Transfer Counter (CSR80) and the value of the
DMA Bus Activity Timer (CSR82).
If DMAPLUS is set to ONE, bursting will continue until
the transmit FIFO is filled to its high threshold (read
transfers) or the receive FIFO is emptied to its low
threshold (write transfers), or until the DMA Bus Activity
Timer (CSR82) has expired. The exact number of total
transfer cycles in the bus mastership period is
dependent on all of the following variables: the settings
of the FIFO watermarks, the conditions of the FIFOs, the
latency of the system bus to the PCnet-PCI II controller’s
bus request, and the speed of bus operation. The DMA
Transfer Counter is disabled when DMAPLUS is set to
ONE. The TRDY response time of the memory device
will also affect the number of transfers, since the speed
of the accesses will affect the state of the FIFO. During
accesses, the FIFO may be filling or emptying on the
network end. For example, on a receive operation, a
slower TRDY response will allow additional data to ac-
cumulate inside of the FIFO. If the accesses are slow
enough, a complete DWord may become available before the end of the bus mastership period and thereby
increase the number of transfers in that period. The general rule is that the longer the Bus Grant latency, the
slower the bus transfer operations, the slower the clock
speed, the higher the transmit watermark or the lower
the receive watermark, the longer the total burst length
will be.
When a FIFO DMA burst operation is preempted, the
PCnet-PCI II controller will not relinquish bus ownership
until the PCI Latency Timer expires. The DMA Transfer
Counter will freeze at the current value while the
PCnet-PCI II controller is waiting to regain bus ownership. It will continue counting when the FIFO DMA burst
operation restarts. The Bus Activity Timer will be reset to
its starting value when the PCnet-PCI II controller regains bus ownership.
The PCI Latency Timer cannot be disabled. Systems
that support preemption and that want to control the
duration of the PCnet-PCI II controller bus mastership
period with the DMA Transfer Counter or the Bus
Activity Timer must program the PCI Latency Timer with
a high value so that it does not expire before the other
two registers do.
BUFFER MANAGEMENT UNIT
The Buffer Management Unit (BMU) is a microcoded
state machine which implements the initialization procedure and manages the descriptors and buffers. The
buffer management unit operates at half the speed of
the CLK input.
Initialization
PCnet-PCI II controller initialization includes the reading
of the initialization block in memory to obtain the operating parameters. The initialization block can be organized in two ways. When SSIZE32 (BCR20, bit 8) is at its
default value of ZERO, all initialization block entries are
logically 16-bits wide to be backwards compatible with
the Am79C90 C-LANCE and Am79C96x PCnet-ISA
family. When SSIZE32 (BCR20, bit 8) is set to ONE, all
initialization block entries are logically 32-bits wide.
Note that the PCnet-PCI II controller always performs
32-bit bus transfers to read the initialization block entries. The initialization block is read when the INIT bit in
CSR0 is set. The INIT bit should be set before or concurrent with the STRT bit to insure correct operation. Once
the initialization block has been completely read in and
internal registers have been updated, IDON will be set in
CSR0, generating an interrupt (if IENA is set).
The PCnet-PCI II controller obtains the start address of
the initialization block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most significant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The initialization block
contains the user defined conditions for PCnet-PCI II
controller operation, together with the base addresses
and length information of the transmit and receive
descriptor rings.
There is an alternate method to initialize the PCnet-PCI
II controller. Instead of initialization via the initialization
block in memory, data can be written directly into the appropriate registers. Either method or a combination of
the two may be used at the discretion of the
programmer. Please refer to Appendix C for details on
this alternate method.
Re-Initialization
The transmitter and receiver sections of the PCnet-PCI
II controller can be turned on via the initialization block
(DTX, DRX, CSR15, bits 1–0). The states of the transmitter and receiver are monitored by the host through
CSR0 (RXON, TXON bits). The PCnet-PCI II controller
should be re-initialized if the transmitter and/or the receiver were not turned on during the original initialization, and it was subsequently required to activate them
or if either section was shut off due to the detection of an
error condition (MERR, UFLO, TX BUFF error).
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
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P R E L I M I N A R Y
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same in
the PCnet-PCI II controller as in the CLANCE. In particular, upon restart, the PCnet-PCI II controller reloads
the transmit and receive descriptor pointers with their
respective base addresses. This means that the software must clear the descriptor OWN bits and reset its
descriptor ring pointers before restarting the PCnet-PCI
II controller. The reload of descriptor base addresses is
performed in the CLANCE only after initialization, so a
restart of the CLANCE without initialization leaves the
CLANCE pointing at the same descriptor locations as
before the restart.
Suspend
The PCnet-PCI II controller offers a suspend mode that
allows easy updating of the CSR registers without going
through a full re-initialization of the device. The suspend
mode also allows stopping the device with orderly termination of all network activity.
The host requests the PCnet-PCI II controller to
enter the suspend mode by setting SPND (CSR5, bit 0)
to ONE. When the host sets SPND to ONE, the
PCnet-PCI II controller first finishes all on-going transmit activity and updates the corresponding transmit descriptor entries. It then finishes all on-going receive
activity and updates the corresponding receive descriptor entries. It then sets the read-version of SPND to ONE
and enters the suspend mode. The host must poll SPND
until it reads back ONE to determine that the PCnet-PCI
II controller has entered the suspend mode. In suspend
mode, all of the CSR and BCR registers are accessible.
As long as the PCnet-PCI II controller is not reset while
in suspend mode (by H_RESET, S_RESET or by setting the STOP bit), no re-initialization of the device is required after the device comes out of suspend mode.
When the host clears SPND, the PCnet-PCI II controller
will leave the suspend mode and will continue at the
transmit and receive descriptor ring locations, where it
had left off.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in
memory. There are two descriptor rings, one for
transmit and one for receive. Each descriptor describes
a single buffer. A frame may occupy one or more buffers. If multiple buffers are used, this is referred to as
buffer chaining.
Descriptor Rings
Each descriptor ring must occupy a contiguous area of
memory. During initialization the user-defined base address for the transmit and receive descriptor rings, as
well as the number of entries contained in the descriptor
rings are set up. The programming of the software style
AMD
(SWSTYLE, BCR20, bits 7–0) affects the way the descriptor rings and their entries are arranged.
When SWSTYLE is at its default value of ZERO, the descriptor rings are backwards compatible with the
Am79C90 C-LANCE and Am79C96x PCnet-ISA family.
The descriptor ring base addresses must be aligned to
an 8-byte boundary and a maximum of 128 ring entries
is allowed when the ring length is set through the TLEN
and RLEN fields of the initialization block. Each ring
entry contains a subset of the three 32-bit transmit or receive message descriptors (TMD, RMD) that are organized as four 16-bit structures (SSIZE (BCR20, bit 8) is
set to ZERO). Note that even though the PCnet-PCI II
controller treats the descriptor entries as 16-bit structures, it will always perform 32-bit bus transfers to access the descriptor entries. The value of CSR2, bits
15–8 is used as the upper 8-bits for all memory addresses during bus master transfers.
When SWSTYLE is set to ONE, TWO or THREE, the
descriptor ring base addresses must be aligned to a
16-byte boundary and a maximum of 512 ring entries is
allowed when the ring length is set through the TLEN
and RLEN fields of the initialization block. Each ring entry is organized as three 32-bit message descriptors
(SSIZE32 (BCR20, bit 8) is set to ONE). The fourth
DWord is reserved. When SWSTYLE is set to THREE,
the order of the message descriptors is optimized to allow read and write access in burst mode.
For any software style, the ring lengths can be set beyond this range (up to 65535) by writing the transmit and
receive ring length registers (CSR76, CSR78) directly.
Each ring entry contains the following information:
■ The address of the actual message data buffer in
user or host memory
■ The length of the message buffer
■ Status information indicating the condition of the
buffer
To permit the queuing and de-queuing of message buffers, ownership of each buffer is allocated to either the
PCnet-PCI II controller or the host. The OWN bit within
the descriptor status information, either TMD or RMD, is
used for this purpose. When OWN is set to ONE, it signifies that the PCnet-PCI II controller currently has ownership of this ring descriptor and its associated buffer.
Only the owner is permitted to relinquish ownership or to
write to any field in the descriptor entry. A device that is
not the current owner of a descriptor entry cannot assume ownership or change any field in the entry. A
device may, however, read from a descriptor that it does
not currently own. Software should always read descriptor entries in sequential order. When software finds that
the current descriptor is owned by the PCnet-PCI II
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controller, then the software must not read ahead to the
next descriptor. The software should wait at a descriptor
it does not own until the PCnet-PCI II controller sets
OWN to ZERO to release ownership to the software.
(When LAPPEN (CSR3, bit 5) is set to ONE, this rule is
modified. See the LAPPEN description.)
At initialization, the PCnet-PCI II controller reads the
base address of both the transmit and receive descriptor
rings into CSRs for use by the PCnet-PCI II controller
during subsequent operations.
CSR2
CSR1
IADR[15:0]IADR[31:16]
The following figure illustrates the relationship between
the initialization base address, the initialization block,
the receive and transmit descriptor ring base addresses, the receive and transmit descriptors and the
receive and transmit data buffers, when SSIZE32 is
cleared to ZERO.
Note that the value of CSR2, bits 15–8 is used as the
upper 8-bits for all memory addresses during bus
master transfers.
N
N
N
N
•
•
•
Rcv Descriptor
Ring
1st desc.
start
RMD0
RMD
RMD
RMD
2nd
desc.
RMD0
Initialization
PADR[15:0]
PADR[31:16]
PADR[47:32]
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RDRA[15:0]
RLE
RES
TDRA[15:0]
TLE RES
Block
MOD
RDRA[23:16]
TDRA[23:16]
Rcv
Buffers
Xmt
Buffers
Data
Buffer
1st desc.
start
TMD
Data
Buffer
1
1
M
Xmt Descriptor
TMD
Data
Buffer
2
M
Ring
TMD
Data
Buffer
2
M
TMD
2nd
desc.
M
TMD
Data
Buffer
N
•
•
Data
Buffer
M
•
68
19436A-35
Figure 32. 16-Bit Software Model
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The following figure illustrates the relationship between
the initialization base address, the initialization block,
the receive and transmit descriptor ring base
CSR1CSR2
IADR[31:16] IADR[15:0]
Initialization
Block
TLE
RES
RES
RES
RLE
PADR[31:0]
LADRF[31:0]
LADRF[63:32]
RDRA[31:0]
TDRA[31:0]
MODE
PADR[47:32]
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addresses, the receive and transmit descriptors and the
receive and transmit data buffers, when SSIZE32 is set
to ONE.
N
N
N
N
•
•
•
Rcv Descriptor
RMD
1
M
Ring
RMD
Buffer
Data
2
M
RMD
M
2nd
desc.
start
RMD
Data
Buffer
N
M
•
•
•
Rcv
Buff
1st
desc.
start
RMD
Data
Buffer
Xmt Descriptor
1st
desc.
start
Ring
2nd
desc.
start
Figure 33. 32-bit Software Model
Polling
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity being performed by the PCnet-PCI II controller, then the
PCnet-PCI II controller will periodically poll the current
receive and transmit descriptor entries in order to ascertain their ownership. If the DPOLL bit in CSR4 is set,
then the transmit polling function is disabled.
A typical polling operation consists of the following: The
PCnet-PCI II controller will use the current receive descriptor address stored internally to vector to the
TMD0
Data
Buffer
M
19436A-36
Xmt
Buff
TMD0
Buffer
Data
1
TMD1
TMD2
Data
Buffer
2
TMD3
appropriate Receive Descriptor Table Entry (RDTE). It
will then use the current transmit descriptor address
(stored internally) to vector to the appropriate Transmit
Descriptor Table Entry (TDTE). The accesses will be
made in the following order: RMD1, then RMD0 of the
current RDTE during one bus arbitration, and after that,
TMD1, then TMD0 of the current TDTE during a second
bus arbitration. All information collected during polling
activity will be stored internally in the appropriate CSRs,
if the OWN bit is set. (i.e. CSR18, CSR19, CSR20,
CSR21, CSR40, CSR42, CSR50, CSR52).
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A typical receive poll is the product of the
following conditions:
1. PCnet-PCI II controller does not own the current
DTE and the poll time has elapsed and
RXON = 1 (CSR0, bit 5), or
2. PCnet-PCI II controller does not own the next RDTE
and there is more than one receive descriptor in the
ring and the poll time has elapsed and
RXON = 1.
If RXON is cleared to ZERO, the PCnet-PCI II controller
will never poll RDTE locations.
In order to avoid missing frames the system should have
at least on RDTE available. To minimize poll activity two
RDTEs should be available. In this case, the poll operation will only consist of the check of the status of the
current TDTE.
A typical transmit poll is the product of the following
conditions:
1. PCnet-PCI II controller does not own the current
TDTE and DPOLL = 0 (CSR4, bit 12) and TXON = 1
(CSR0, bit 4) and the poll time has elapsed, or
2. PCnet-PCI II controller does not own the current
TDTE and DPOLL = 0 and TXON = 1 and a frame
has just been received, or
3. PCnet-PCI II controller does not own the current
TDTE and DPOLL = 0 and TXON = 1 and a frame
has just been transmitted.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately
perform a polling operation. If RDTE ownership has not
been previously established, then an RDTE poll will be
performed ahead of the TDTE poll. If the microcode is
not executing the poll counting code when the TDMD bit
is set, then the demanded poll of the TDTE will be
delayed until the microcode returns to the poll
counting code.
The user may change the poll time value from the default of 65,536 clock periods by modifying the value in
the Polling Interval register (CSR47).
Transmit Descriptor Table Entry
If, after a Transmit Descriptor Table Entry (TDTE) access, the PCnet-PCI II controller finds that the OWN bit
of that TDTE is not set, the PCnet-PCI II controller resumes the poll time count and re-examines the same
TDTE at the next expiration of the poll time count.
If the OWN bit of the TDTE is set, but the Start of Packet
(STP) bit is not set, the PCnet-PCI II controller will immediately request the bus in order to clear the OWN bit
of this descriptor. (This condition would normally be
found following a late collision (LCOL) or retry (RTRY)
error that occurred in the middle of a transmit frame
chain of buffers.) After resetting the OWN bit of this descriptor, the PCnet-PCI II controller will again
immediately request the bus in order to access the next
TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be cleared. In the C-LANCE the buffer length of 0
is interpreted as a 4096-byte buffer. A zero length buffers is acceptable as long as it is not the last buffer in a
chain (STP = 0 and ENP = 1).
If the OWN bit and STP are set, then microcode control
proceeds to a routine that will enable transmit data
transfers to the FIFO. The PCnet-PCI II controller will
look ahead to the next transmit descriptor after it has
performed at least one transmit data transfer from the
first buffer.
If the PCnet-PCI II controller does not own the next
TDTE (i.e. the second TDTE for this frame), it will complete transmission of the current buffer and update the
status of the current (first) TDTE with the BUFF and
UFLO bits being set. If DXSUFLO (CSR3, bit 6) is
cleared to ZERO, the underflow error will cause the
transmitter to be disabled (CSR0, TXON = 0). The
PCnet-PCI II controller will have to be re-initialized to restore the transmit function. Setting DXSUFLO to ONE
enables the PCnet-PCI II controller to gracefully recover
from an underflow error. The device will scan the transmit descriptor ring until it finds either the start of a new
frame or a TDTE it does not own. To avoid an underflow
situation in a chained buffer transmission, the system
should always set the transmit chain descriptor own bits
in reverse order.
If the PCnet-PCI II controller does own the second
TDTE in a chain, it will gradually empty the contents of
the first buffer (as the bytes are needed by the transmit
operation), perform a single-cycle DMA transfer to update the status of the first descriptor (clear the OWN bit
in TMD1), and then it may perform one data DMA access on the second buffer in the chain before executing
another lookahead operation. (i.e. a lookahead to the
third descriptor.)
It is imperative that the host system never reads the
TDTE OWN bits out of order. The PCnet-PCI II controller normally clears OWN bits in strict FIFO order. However, the PCnet-PCI II controller can queue up to two
frames in the transmit FIFO. When the second frame
uses buffer chaining, the PCnet-PCI II controller might
return ownership out of normal FIFO order. The OWN
bit for last (and maybe only) buffer of the first frame is not
cleared until transmission is completed. During the
transmission the PCnet-PCI II controller will read in buffers for the next frame and clear their OWN bits for all but
the last one. The first and all intermediate buffers of the
second frame can have their OWN bits cleared before
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the PCnet-PCI II controller returns ownership for the last
buffer of the first frame.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, transmit status of the current buffer will be immediately updated. If the buffer does not contain the end of packet,
the PCnet-PCI II controller will skip over the rest of the
frame which experienced the error. This is done by returning to the polling microcode where the PCnet-PCI II
controller will clear the OWN bit for all descriptors with
OWN = 1 and STP = 0 and continue in like manner until a
descriptor with OWN = 0 (no more transmit frames in the
ring) or OWN = 1 and STP = 1 (the first buffer of a new
frame) is reached.
At the end of any transmit operation, whether successful
or with errors, immediately following the completion of
the descriptor updates, the PCnet-PCI II controller will
always perform another polling operation. As described
earlier, this polling operation will begin with a check of
the current RDTE, unless the PCnet-PCI II controller already owns that descriptor. Then the PCnet-PCI II controller will poll the next TDTE. If the transmit descriptor
OWN bit has a ZERO value, the PCnet-PCI II controller
will resume incrementing the poll time counter. If the
transmit descriptor OWN bit has a value of ONE, the
PCnet-PCI II controller will begin filling the FIFO with
transmit data and initiate a transmission. This end-ofoperation poll coupled with the TDTE lookahead operation allows the PCnet-PCI II controller to avoid inserting
poll time counts between successive transmit frames.
By default, whenever the PCnet-PCI II controller completes a transmit frame (either with or without error) and
writes the status information to the current descriptor,
then the TINT bit of CSR0 is set to indicate the completion of a transmission. This causes an interrupt signal if
the IENA bit of CSR0 has been set and the TINTM bit of
CSR3 is cleared. The PCnet-PCI II controller provides
two modes to reduce the number of transmit interrupts.
The interrupt of a successfully transmitted frame can be
suppressed by setting TINTOKD (CSR5, bit 15) to ONE.
Another mode, which is enabled by setting LTINTEN
(CSR5, bit 14) to ONE, allows suppression of interrupts
for successful transmissions for all but the last frame in
a sequence.
Receive Descriptor Table Entry
If the PCnet-PCI II controller does not own both the current and the next Receive Descriptor Table Entry
(RDTE) then the PCnet-PCI II controller will continue to
poll according to the polling sequence described above.
If the receive descriptor ring length is one, then there is
no next descriptor to be polled.
If a poll operation has revealed that the current and the
next RDTE belong to the PCnet-PCI II controller then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
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the PCnet-PCI II controller retains ownership of the current and the next RDTE.
When receive activity is present on the channel, the
PCnet-PCI II controller waits for the complete address
of the message to arrive. It then decides whether to accept or reject the frame based on all active addressing
schemes. If the frame is accepted the PCnet-PCI II controller checks the current receive buffer status register
CRST (CSR41) to determine the ownership of the
current buffer.
If ownership is lacking, the PCnet-PCI II controller will
immediately perform a final poll of the current RDTE. If
ownership is still denied, the PCnet-PCI II controller has
no buffer in which to store the incoming message. The
MISS bit will be set in CSR0 and the Missed Frame
Counter (CSR112) will be incremented. An interrupt will
be generated if IENA (CSR0, bit 6) is set to ONE and
MISSM (CSR3, bit 12) is cleared to ZERO. Another
poll of the current RDTE will not occur until the frame
has finished.
If the PCnet-PCI II controller sees that the last poll
(either a normal poll, or the final effort described in the
above paragraph) of the current RDTE shows valid ownership, it proceeds to a poll of the next RDTE. Following
this poll, and regardless of the outcome of this poll,
transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive
descriptor, the PCnet-PCI II controller will continue to
perform receive data DMA transfers to the first buffer. If
the frame length exceeds the length of the first buffer,
and the PCnet-PCI II controller does not own the second
buffer, ownership of the current descriptor will be
passed back to the system by writing a ZERO to
the OWN bit of RMD1 and status will be written
indicating buffer (BUFF = 1) and possibly overflow
(OFLO = 1) errors.
If the frame length exceeds the length of the first (current) buffer, and the PCnet-PCI II controller does own
the second (next) buffer, ownership will be passed back
to the system by writing a ZERO to the OWN bit of
RMD1 when the first buffer is full. The OWN bit is the
only bit modified in the descriptor. Receive data
transfers to the second buffer may occur before the
PCnet-PCI II controller proceeds to look ahead to the
ownership of the third buffer. Such action will depend
upon the state of the FIFO when the OWN bit has been
updated in the first descriptor. In any case, lookahead
will be performed to the third buffer and the information
gathered will be stored in the chip, regardless of the
state of the ownership bit.
This activity continues until the PCnet-PCI II controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The PCnet-PCI II controller will subsequently
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update the current RDTE status with the end of frame
(ENP) indication set, write the message byte count
(MCNT) for the entire frame into RMD2 and overwrite
the “current” entries in the CSRs with the “next” entries.
Media Access Control
The Media Access Control (MAC) engine incorporates
the essential protocol requirements for operation of a
compliant Ethernet/802.3 node, and provides the interface between the FIFO sub-system and the Manchester
Encoder/Decoder (MENDEC).
This section describes operation of the MAC engine
when operating in half-duplex mode. When operating in
half-duplex mode, the MAC engine is fully compliant to
Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard
1990 Second Edition) and ANSI/IEEE 802.3 (1985).
When operating in full-duplex mode, the MAC engine
behavior changes as described in the section
“Full-Duplex Operation”.
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post- message processing.
These include the ability to disable retries after a collision, dynamic FCS generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce
minimum frame size attributes, automatic re-transmission without reloading the FIFO, and automatic deletion
of collision fragments.
The two primary attributes of the MAC engine are:
■ Transmit and receive message data encapsulation
— Framing (frame boundary delimitation, frame
synchronization)
— Addressing (source and destination address
handling)
— Error detection (physical medium transmission
errors)
■ Media Access Management
— Medium allocation (collision avoidance)
— Contention resolution (collision handling)
Transmit and Receive Message Data
Encapsulation
The MAC engine provides minimum frame size enforcement for transmit and receive frames. When
APAD_XMT (CSR, bit 11) is set to ONE, transmit messages will be padded with sufficient bytes (containing
00h) to ensure that the receiving station will observe an
information field (destination address, source address,
length/type, data and FCS) of 64 bytes. When
ASTRP_RCV (CSR4, bit 10) is set to ONE, the receiver
will automatically strip pad bytes from the received message by observing the value in the length field, and stripping excess bytes if this value is below the minimum
data size (46 bytes). Both features can be
independently over-ridden to allow illegally short (less
than 64 bytes of frame data) messages to be transmitted
and/or received. The use of this feature reduces bus
utilization because the pad bytes are not transferred into
or out of main memory.
Framing
The MAC engine will autonomously handle the construction of the transmit frame. Once the transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80), and access to the channel is currently permitted, the MAC engine will commence the 7
byte preamble sequence (10101010b, where first bit
transmitted is a 1). The MAC engine will subsequently
append the Start Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
transmit FIFO. Once the data has been completed, the
MAC engine will append the FCS (most significant bit
first) which was computed on the entire data portion of
the frame. The data portion of the frame consists of destination address, source address, length/type, and
frame data. The user is responsible for the correct ordering and content in each of these fields in the frame.
The receive section of the MAC engine will detect an incoming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8 bits of information before searching for the SFD sequence. Once the SFD is detected, all
subsequent bits are treated as part of the frame. The
MAC engine will inspect the length field to ensure minimum frame size, strip unnecessary pad characters (if
enabled), and pass the remaining bytes through the receive FIFO to the host. If pad stripping is performed, the
MAC engine will also strip the received FCS bytes, although normal FCS computation and checking will occur. Note that apart from pad stripping, the frame will be
passed unmodified to the host. If the length field has a
value of 46 or greater, all frame bytes including FCS will
be passed unmodified to the receive buffer, regardless
of the actual frame length.
If the frame terminates or suffers a collision before 64
bytes of information (after SFD) have been received, the
MAC engine will automatically delete the frame from
the receive FIFO, without host intervention. The
PCnet-PCI II controller has the ability to accept
runt packets for diagnostics purposes and
proprietary networks.
Destination Address Handling
The first 6 bytes of information after SFD will be interpreted as the destination address field. The MAC engine
provides facilities for physical (unicast), logical (multicast) and broadcast address reception.
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Error Detection
The MAC engine provides several facilities which report
and recover from errors on the medium. In addition, it
protects the network from gross errors due to inability of
the host to keep pace with the MAC engine activity.
On completion of transmission, the following transmit
status is available in the appropriate Transmit Message
Descriptor (TMD) and Control and Status Register
(CSR) areas:
■ The number of transmission retry attempts (ONE,
MORE, RTRY, and TRC).
■ Whether the MAC engine had to Defer (DEF) due to
channel activity.
■ Excessive deferral (EXDEF), indicating that the
transmitter has experienced Excessive Deferral on
this transmit frame, where Excessive Deferral is defined in ISO 8802-3 (IEEE/ANSI 802.3).
■ Loss of Carrier (LCAR), indicating that there was an
interruption in the ability of the MAC engine to
monitor its own transmission. Repeated LCAR errors indicate a potentially faulty transceiver or network connection.
■ Late Collision (LCOL) indicates that the transmission
suffered a collision after the slot time. This is indicative of a badly configured network. Late collisions
should not occur in a normal operating network.
■ Collision Error (CERR) indicates that the transceiver
did not respond with an SQE Test message within
the first 4 µs after a transmission was completed.
This may be due to a failed transceiver,
disconnected or faulty transceiver drop cable, or the
fact the transceiver does not support this feature (or
it is disabled).
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails to
keep the transmit FIFO filled sufficiently, causing an underflow, the MAC engine will guarantee the message is
either sent as a runt packet (which will be deleted by the
receiving station) or has an invalid FCS (which will also
cause the receiver to reject the message).
The status of each receive message is available in the
appropriate Receive Message Descriptor (RMD) and
CSR areas. All received frames are passed to the host
regardless of any error. The FRAM error will only be reported if an FCS error is detected and there are a non
integral number of bytes in the message.
During the reception, the FCS is generated on every serial bit (including the dribbling bits) coming from the cable, although the internally saved FCS value is only
updated on the eighth bit (on each byte boundary). The
MAC engine will ignore up to 7 additional bits at the end
of a message (dribbling bits), which can occur under
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normal network operating conditions. The framing error
is reported to the user as follows:
■ If the number of dribbling bits are 1 to 7 and there is
no FCS error, then there is no Framing error
(FRAM = 0).
■ If the number of dribbling bits are 1 to 7 and there is a
FCS error, then there is also a Framing error
(FRAM = 1).
■ If the number of dribbling bits is ZERO, then there is
no Framing error. There may or may not be a
FCS error.
■ If the number of dribbling bits is EIGHT, then there is
no Framing error. FCS error will be reported and the
receive message count will indicated one extra byte.
Counters are provided to report the Receive Collision
Count and Runt Packet Count, for network statistics and
utilization calculations.
Note that if the MAC engine detects a received frame
which has a 00b pattern in the preamble (after the first
8-bits which are ignored), the entire frame will be ignored. The MAC engine will wait for the network to go
inactive before attempting to receive additional frames.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The
802.3/Ethernet protocols define a media access mecha-
nism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter Packet Gap) after the last activity, before transmitting on the
media. The channel is a multidrop communications media (with various topological configurations permitted)
which allows a single station to transmit and all other
stations to receive. If two nodes simultaneously contend
for the channel, their signals will interact causing loss of
data, defined as a collision. It is the responsibility of the
MAC to attempt to avoid and recover from a collision, to
guarantee data integrity for the end-to-end transmission
to the receiving station.
Medium Allocation
The IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
for traffic by watching for carrier activity. When carrier is
detected, the media is considered busy, and the MAC
should defer to the existing message.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard also allows optional two part deferral after a receive message.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
Note: It is possible for the PLS carrier sense indication to
fail to be asserted during a collision on the media. If the
deference process simply times the interFrame gap
based on this indication it is possible for a short
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interFrame gap to be generated, leading to a potential
reception failure of a subsequent frame. To enhance
system robustness the following optional measures,as
specified in 4.2.8, are recommended when InterFrame
Spacing Part 1 is other than ZERO:
1. Upon completing a transmission, start timing the
interpacket gap, as soon as transmitting and carrier
Sense are both false.
2. When timing an interFrame gap following reception,
reset the interFrame gap timing if carrier Sense becomes true during the first 2/3 of the interFrame gap
timing interval. During the final 1/3 of the interval the
timer shall not be reset to ensure fair access to the
medium. An initial period shorter than 2/3 of the
interval is permissible including ZERO.”
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-framespacing time of 6.0 µs. The second part of the
inter-frame-spacing interval is therefore 3.6 µs.
The PCnet-PCI II controller will perform the two part deferral algorithm as specified in Section 4.2.8 (Process
Deference). The Inter Packet Gap (IPG) timer will start
timing the 9.6 µs InterFrameSpacing after the receive
carrier is deasserted. During the first part deferral (InterFrame Spacing Part1 – IFS1) the PCnet-PCI II controller will defer any pending transmit frame and respond to
the receive message. The IPG counter will be cleared to
ZERO continuously until the carrier deasserts, at which
point the IPG counter will resume the 9.6 µs count once
again. Once the IFS1 period of 6.0 µs has elapsed, the
PCnet-PCI II controller will begin timing the second part
deferral (Inter-Frame Spacing Part2 – IFS2) of 3.6 µs.
Once IFS1 has completed, and IFS2 has commenced,
the PCnet-PCI II controller will not defer to a receive
frame if a transmit frame is pending. This means that the
PCnet-PCI II controller will not attempt to receive the receive frame, since it will start to transmit, and generate a
collision at 9.6 µs. The PCnet-PCI II controller will complete the preamble (64-bit) and jam (32-bit) sequence
before ceasing transmission and invoking the random
backoff algorithm.
This transmit two part deferral algorithm is implemented
as an option which can be disabled using the DXMT2PD
bit in CSR3. Two part deferral after transmission is
useful for ensuring that severe IPG shrinkage cannot
occur in specific circumstances, causing a transmit
message to follow a receive message so closely as to
make them indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should
generate the SQE Test message (a nominal 10 MHz
burst of 5–15 Bit Times duration) on the CI± pair (within
0.6–1.6 µs after the transmission ceases). During the
time period in which the SQE Test message is expected
the PCnet-PCI II controller will not respond to receive
carrier sense.
See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1):
“At the conclusion of the output function, the DTE opens
a time window during which it expects to see the
signal_quality_error signal asserted on the Control
In circuit. The time window begins when the
CARRIER_STATUS becomes CARRIER_OFF. If execution of the output function does not cause
CARRIER_ON to occur, no SQE test occurs in the DTE.
The duration of the window shall be at least 4.0
µ
more than 8.0
s. During the time window the Carrier
µ
s but no
Sense Function is inhibited.”
The PCnet-PCI II controller implements a carrier sense
“blinding” period of 4.0 µs length starting from the
deassertion of carrier sense after transmission. This effectively means that when transmit two part deferral is
enabled (DXMT2PD is cleared) the IFS1 time is from
4 µs to 6 µs after a transmission. However, since IPG
shrinkage below 4 µs will rarely be encountered on a
correctly configured network, and since the fragment
size will be larger than the 4 µs blinding window, the IPG
counter will be reset by a worst case IPG shrinkage/fragment scenario and the PCnet-PCI II controller will defer
its transmission. If carrier is detected within the 4.0 to
6.0 µs IFS1 period, the PCnet-PCI II controller will not
restart the “blinding” period, but only restart IFS1.
Collision Handling
Collision detection is performed and reported to
the MAC engine by the integrated Manchester
Encoder/Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the preamble/SFD has been completed, but prior to 512 bits being
transmitted, the MAC Engine will abort the transmission, and append the jam sequence immediately. The
jam sequence is a 32-bit all ZEROs pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of collision will cause the transmission to be re-scheduled to a
time determined by the random backoff algorithm. If a
single retry was required, the ONE bit will be set in the
transmit frame status. If more than one retry was required, the MORE bit will be set. If all 16 attempts experienced collisions, the RTRY bit will be set (ONE and
MORE will be clear), and the transmit message will be
flushed from the FIFO. If retries have been disabled by
setting the DRTY bit in CSR15, the MAC Engine will
abandon transmission of the frame on detection of the
first collision. In this case, only the RTRY bit will be set
and the transmit message will be flushed from the FIFO.
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If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the jam
sequence and set the LCOL bit. No retry attempt will be
scheduled on detection of a late collision, and the transmit message will be flushed from the FIFO.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a “truncated binary exponential backoff”
algorithm which provides a controlled pseudo random
mechanism to enforce the collision backoff interval, before re-transmission is attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to retransmit the frame. The delay is an integer multiple of
slot Time. The number of slot times to delay before the
nth re-transmission attempt is chosen as a uniformly
distributed random integer r in the range:
≤
r <2k
0
where
k = min (n,10).”
The PCnet-PCI II controller provides an alternative algorithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This aids in networks where large numbers of nodes are
present, and numerous nodes can be in collision. It effectively accelerates the increase in the backoff time in
busy networks, and allows nodes not involved in the collision to access the channel whilst the colliding nodes
await a reduction in channel activity. Once channel activity is reduced, the nodes resolving the collision time
out their slot time counters as normal.
This modified backoff algorithm is enabled when EMBA
(CSR3, bit 3) is set to ONE.
TRANSMIT OPERATION
The transmit operation and features of the PCnet-PCI II
controller are controlled by programmable options. The
PCnet-PCI II controller offers a 272-byte transmit FIFO
to provide frame buffering for increased system latency,
automatic re-transmission with no FIFO reload, and
automatic transmit padding.
Transmit Function Programming
Automatic transmit features such as retry on collision,
FCS generation/transmission, and pad field insertion
can all be programmed to provide flexibility in the
(re-)transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the
initialization block.
Automatic pad field insertion is controlled by the
AMD
APAD_XMT bit in CSR4.
The disable FCS generation/transmission feature can
be programmed as a static feature or dynamically on a
frame by frame basis.
Transmit FIFO Watermark (XMTFW) in CSR80 sets the
point at which the BMU requests more data from the
transmit buffers for the FIFO. A minimum of XMTFW
empty spaces must be available in the transmit FIFO before the BMU will request the system bus in order to
transfer transmit frame data into the transmit FIFO.
Transmit Start Point (XMTSP) in CSR80 sets the point
when the transmitter actually attempts to transmit a
frame onto the media. A minimum of XMTSP bytes must
be written to the transmit FIFO for the current frame before transmission of the current frame will begin. (When
automatically padded packets are being sent, it is conceivable that the XMTSP is not reached when all of the
data has been transferred to the FIFO. In this case, the
transmission will begin when all of the frame data has
been placed into the transmit FIFO.) The default value of
XMTSP is 01b, meaning there has to be 64 bytes in the
transmit FIFO to start a transmission.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble). This allows
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed with no software intervention from the host/controlling process. Setting the
APAD_XMT bit in CSR4 enables the automatic padding
feature. The pad is placed between the LLC data field
and FCS field in the 802.3 frame. FCS is always added if
the frame is padded, regardless of the state of
DXMTFCS (CSR15, bit 3) or ADD_FCS/NO_FCS
(TMD1, bit 29). The transmit frame will be padded by
bytes with the value of 00h. The default value of
APAD_XMT is 0, which will disable automatic pad generation after H_RESET.
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes encapsulated in the frame (length field as defined in the
ISO 8802-3 (IEEE/ANSI 802.3) standard). The length
value contained in the message is not used by the
PCnet-PCI II controller to compute the actual number of
pad bytes to be inserted. The PCnet-PCI II controller will
append pad bytes dependent on the actual number of
bits transmitted onto the network. Once the last data
byte of the frame has completed, prior to appending the
FCS, the PCnet-PCI II controller will check to ensure
that 544 bits have been transmitted. If not, pad bytes are
added to extend the frame size to this value, and the
FCS is then added.
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Preamble
1010....1010
56
Bits
SFD
10101011
8
Bits
Destination
Address
6
Bytes
P R E L I M I N A R Y
Source
Address
Bytes
Figure 34. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
The 544 bit count is derived from the following :
Minimum frame size (excluding 64 bytes 512 bits
preamble/SFD, including FCS)
Preamble/SFD size 8 bytes 64 bits
FCS size 4 bytes 32 bits
At the point that FCS is to be appended, the transmit-
ted frame should contain:
Preamble/SFD + (Min Frame Size – FCS)
64 + (512 – 32) = 544 bits
A minimum length transmit frame from the PCnet-PCI II
controller will therefore be 576 bits, after the FCS
is appended.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS
(CSR15, bit 3). If DXMTFCS is cleared to ZERO, the
transmitter will generate and append the FCS to the
transmitted frame. If the automatic padding feature is invoked (APAD_XMT is set in CSR4), the FCS will be appended by the PCnet-PCI II controller regardless of the
state of DXMTFCS or ADD_FCS/NO_FCS (TMD1, bit
29). Note that the calculated FCS is transmitted most
significant bit first. The default value of DXMTFCS is 0
after H_RESET.
ADD_FCS (TMD1, bit 29) allows the automatic generation and transmission of FCS on a frame by frame basis.
DXMTFCS should be cleared to ZERO in this mode. To
generate FCS for a frame, ADD_FCS must be set in the
first descriptor of a frame (STP is set to ONE). Note that
bit 29 of TMD1 has the function of ADD_FCS if
SWSTYLE (BCR20, bits 7–0) is programmed to ZERO,
TWO or THREE.
When SWSTYLE is set to ONE for ILACC backwards
compatibility, bit 29 of TMD1 changes its function to
NO_FCS. When DXMTFCS is cleared to ZERO and
NO_FCS is set to ONE in the last descriptor of a frame
(ENP is set to ONE), the PCnet-PCI II controller will not
generate and append an FCS to a transmit frame.
Length
6
2
Bytes
LLC
Data
Pad FCS
46 – 1500
Bytes
Transmit Exception Conditions
Exception conditions for frame transmission fall into two
distinct categories. Those which are the result of normal
network operation, and those which occur due to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-PCI II controller include collisions within the slot time with automatic retry. The
PCnet-PCI II controller will ensure that collisions which
occur within 512 bit times from the start of transmission
(including preamble) will be automatically retried with no
host intervention. The transmit FIFO ensures this by
guaranteeing that data contained within the FIFO will
not be overwritten until at least 64 bytes (512 bits) of preamble plus address, length and data fields have been
transmitted onto the network without encountering a collision. Note that if DRTY (CSR15, bit 5) is set to ONE or if
the network interface is operating in full-duplex mode,
no collision handling is required, and any byte of frame
data in the FIFO can be overwritten as soon as it
is transmitted.
If 16 total attempts (initial attempt plus 15 retries) fail, the
PCnet-PCI II controller sets the RTRY bit in the current
transmit TDTE in host memory (TMD2), gives up
ownership (resets the OWN bit to ZERO) for this frame,
and processes the next frame in the transmit ring
for transmission.
Abnormal network conditions include:
■ Loss of carrier.
■ Late collision.
■ SQE Test Error. (Does not apply to 10BASE-T port.)
These conditions should not occur on a correctly configured 802.3 network operating in half-duplex mode, and
will be reported if they do. None of these conditions will
occur on a network operating in full-duplex mode. (See
the section “Full-Duplex Operation” for more detail.)
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
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Bytes
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P R E L I M I N A R Y
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be cleared until the STP (the next
frame) is found.
Loss of Carrier
When operating in half-duplex mode, a loss of carrier
condition will be reported if the PCnet-PCI II controller
cannot observe receive activity whilst it is transmitting
on the AUI or GPSI port. In AUI mode, after the
PCnet-PCI II controller initiates a transmission it will expect to see data “looped-back” on the DI± pair. This will
internally generate a “carrier sense”, indicating that the
integrity of the data path to and from the MAU is intact,
and that the MAU is operating correctly. This “carrier
sense” signal must be asserted before the last bit is
transmitted on DO±. If “carrier sense” does not become
active in response to the data transmission, or becomes
inactive before the end of transmission, the loss of carrier (LCAR) error bit will be set in TMD2 after the frame
has been transmitted. The frame will not be retried on
the basis of an LCAR error. In GPSI mode, LCAR will
be asserted if RXEN does not go active during
the transmission.
When the 10BASE-T port is selected, LCAR will be reported for every frame transmitted while the network interface is in the Link Fail state.
Late Collision
A late collision will be reported if a collision condition occurs after one slot time (512 bit times) after the transmit
process was initiated (first bit of preamble commenced).
The PCnet-PCI II controller will abandon the transmit
process for that frame, set Late Collision (LCOL) in the
associated TMD2, and process the next transmit frame
in the ring. Frames experiencing a late collision will not
be retried. Recovery from this condition must be performed by upper layer software.
SQE Test Error
During the inter packet gap time following the completion of a transmitted message, the AUI CI± pair is asserted by some transceivers as a self-test. The integral
Manchester Encoder/Decoder will expect the SQE Test
Message (nominal 10 MHz sequence) to be returned via
the CI± pair within a 40 network bit-time period after DI±
goes inactive (this does not apply if the 10BASE-T port
is selected). If the CI± input is not asserted within the 40
network bit-time period following the completion of
transmission, then the PCnet-PCI II controller will set
the CERR bit in CSR0. In GPSI mode, CLSN must be
asserted after the transmission or otherwise CERR will
be set. CERR will be asserted in 10BASE-T mode after
transmit if T-MAU is in Link Fail state. CERR will never
cause INTA to be activated. It will, however, set the ERR
bit CSR0.
AMD
Receive Operation
The receive operation and features of the PCnet-PCI II
controller are controlled by programmable options. The
PCnet-PCI II controller offers a 256-byte receive FIFO
to provide frame buffering for increased system latency,
automatic flushing of collision fragments (runt packets),
automatic receive pad stripping and a variety of address
match options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility
in the reception of messages using the 802.3
frame format.
All receive frames can be accepted by setting the PROM
bit in CSR15. Acceptance of unicast and broadcast
frames can be individually turned off by setting the
DRCVPA or DRCVBC bits in CSR15. The Physical Address register (CSR12 to CSR14) stores the address
the PCnet-PCI II controller compares to the destination
address of the incoming frame for a unicast address
match. The Logical Address Filter register (CSR8 to
CSR11) serves as a hash filter for multicast
address match.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established during H_RESET is 01b which sets the watermark flag at 64
bytes filled.
For test purposes, the PCnet-PCI II controller can be
programmed to accept runt packets by setting RPA
in CSR124.
Address Matching
The PCnet-PCI II controller supports three types of address matching: unicast, multicast, and broadcast. The
normal address matching procedure can be modified by
programming three bits in CSR15, the mode register
(PROM, DRCVPA, and DRCVBC).
If the first bit received after the start of frame delimiter
(the least significant bit of the first byte of the destination
address field) is 0, the frame is unicast, which indicates
that the frame is meant to be received by a single node.
If the first bit received is 1, the frame is multicast, which
indicates that the frame is meant to be received by a
group of nodes. If the destination address field contains
all ONEs, the frame is broadcast, which is a special type
of multicast. Frames with the broadcast address in the
destination address field are meant to be received by all
nodes on the local area network.
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P R E L I M I N A R Y
When a unicast frame arrives at the PCnet-PCI II controller, the controller will accept the frame if the destination address field of the incoming frame exactly matches
the 6-byte station address stored in the Physical Address registers (PADR, CSR12 to CSR14). The byte ordering is such that the first byte received from the
network (after the SFD) must match the least significant
byte of CSR12 (PADR[7:0]), and the sixth byte received
must match the most significant byte of CSR14
(PADR[47:40]).
When DRCVPA (CSR15, bit 13) is set to ONE, the
PCnet-PCI II controller will not accept unicast frames.
If the incoming frame is multicast, the PCnet-PCI II controller performs a calculation on the contents of the
destination address field to determine whether or not to
accept the frame. This calculation is explained in
the section that describes the Logical Address
Filter (LADRF).
When all bits of the LADRF registers are 0, no multicast
frames are accepted, except for broadcast frames.
Although broadcast frames are classified as special
multicast frames, they are treated differently by the
PCnet-PCI II controller hardware. Broadcast frames are
always accepted, except when DRCVBC (CSR15, bit
14) is set.
None of the address filtering described above applies
when the PCnet-PCI II controller is operating in the promiscuous mode. In the promiscuous mode, all properly
formed packets are received, regardless of the contents
of their destination address fields. The promiscuous
mode overrides the Disable Receive Broadcast bit
(DRCVBC bit l4 in the MODE register) and the Disable
Receive Physical Address bit (DRCVPA, CSR15,
bit 13).
The PCnet-PCI II controller operates in promiscuous
mode when PROM (CSR15, bit 15) is set.
In addition, the PCnet-PCI II controller provides the External Address Detection Interface (EADI) to allow
Table 6. Receive Address Match
external address filtering. See the section “External Address Detection Interface” for further detail.
The receive descriptor entry RMD1 contains three bits
that indicate which method of address matching caused
the PCnet-PCI II controller to accept the frame. Note
that these indicator bits are only available when the
PCnet-PCI II controller is programmed to use 32-bit
structures for the descriptor entries (BCR20, bit 7–0,
SWSTYLE is set to ONE, TWO or THREE).
PAM (RMD1, bit 22) is set by the PCnet-PCI II controller
when it accepted the received frame due to a match of
the frame’s destination address with the content of the
physical address register.
LAFM (RMD1, bit 21) is set by the PCnet-PCI II controller when it accepted the received frame based on the
value in the logical address filter register.
BAM (RMD1, bit 20) is set by the PCnet-PCI II controller
when it accepted the received frame because the
frame’s destination address is of the type “Broadcast”.
If DRCVBC (CSR15, bit 14) is cleared to ZERO, only
BAM, but not LAFM will be set when a Broadcast frame
is received, even if the Logical Address Filter is programmed in such a way that a Broadcast frame would
pass the hash filter. If DRCVBC is set to ONE and the
Logical Address Filter is programmed in such a way that
a Broadcast frame would pass the hash filter, LAFM will
be set on the reception of a Broadcast frame.
When the PCnet-PCI II controller operates in promiscuous mode and none of the three match bits is set, it is an
indication that the PCnet-PCI II controller only accepted
the frame because it was in promiscuous mode.
When the PCnet-PCI II controller is not programmed to
be in promiscuous mode, but the EADI interface is enabled, then when none of the three match bits is set, it is
an indication that the PCnet-PCI II controller only accepted the frame because it was not rejected by driving
the EAR pin LOW within 64 bytes after SFD.
PAM LAFM BAM DRCVBC Comment
0 0 0 X Frame accepted due to PROM = 1 or no EADI reject
1 0 0 X Physical Address Match
0 1 0 0 Logical Address Filter Match; Frame is not of Type Broadcast
0 1 0 1 Logical Address Filter Match; Frame can be of Type Broadcast
0 0 1 0 Broadcast Frame
Automatic Pad Stripping
During reception of an 802.3 frame the pad field can be
stripped automatically. Setting ASTRP_RCV (CSR4, bit
0) to ONE enables the automatic pad stripping feature.
The pad field will be stripped before the frame is passed
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Am79C970A
to the FIFO, thus preserving FIFO space for additional
frames. The FCS field will also be stripped, since it is
computed at the transmitting station based on the data
and pad field characters, and will be invalid for a receive
frame that has had the pad characters stripped.
P R E L I M I N A R Y
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the ISO 8802-3
(IEEE/ANSI 802.3) definition) contained in the frame.
The length indicates the actual number of LLC data
bytes contained in the message. Any received frame
which contains a length field less than 46 bytes will have
56
Bits
Preamble
1010....1010
Start of Frame
at Time = 0
8
Bits
SFD
10101011
6
Bytes
Destination
Address
Bytes
Source
Address
Bit
0
the pad field stripped (if ASTRP_RCV is set). Receive
frames which have a length field of 46 bytes or greater
will be passed to the host unmodified.
The figure below shows the byte/bit ordering of the received length field for an 802.3 compatible frame format.
46 – 1500
Bytes
6
2
Bytes
Length
Bit 7Bit
0
LLC
Data
1 – 1500
Bytes
Pad FCS
45 – 0
Bytes
Bit
7
AMD
4
Bytes
Increasing Time
Significant
Figure 35. 802.3 Frame And Length Field Transmission Order
Since any valid Ethernet Type field value will always be
greater than a normal 802.3 Length field (≥ 46), the
PCnet-PCI II controller will not attempt to strip valid
Ethernet frames. Note that for some network protocols,
the value passed in the Ethernet Type and/or 802.3
Length field is not compliant with either standard and
may cause problems if pad stripping is enabled.
Receive FCS Checking
Reception and checking of the received FCS is performed automatically by the PCnet-PCI II controller.
Note that if the Automatic Pad Stripping feature is enabled, the FCS for padded frames will be verified
against the value computed for the incoming bit stream
including pad characters, but the FCS value for a padded frame will not be passed to the host. If an FCS error
is detected in any frame, the error will be reported in the
CRC bit in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
Most
Byte
Least
Significant
Byte
distinct categories: those which are the result of normal
network operation, and those which occur due to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-PCI II controller are basically collisions within the slot time and automatic runt
packet rejection. The PCnet-PCI II controller will ensure
that collisions which occur within 512 bit times from the
start of reception (excluding preamble) will be automatically deleted from the receive FIFO with no host intervention. The receive FIFO will delete any frame which is
composed of fewer than 64 bytes provided that the Runt
Packet Accept (RPA bit in CSR124) feature has not
been enabled and the network interface is operating in
half-duplex mode. This criterion will be met regardless
of whether the receive frame was the first (or only) frame
in the FIFO or if the receive frame was queued behind a
previously received message.
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P R E L I M I N A R Y
Abnormal network conditions include:
■ FCS errors
■ Late Collision
Host related receive exception conditions include MISS,
BUFF, and OFLO. These are described in the section
“Buffer Management Unit”.
Loopback Operation
Loopback is a mode of operation intended for system diagnostics. In this mode, the transmitter and receiver are
both operating at the same time so that the controller receives its own transmissions. The controller provides
two basic types of loopback. In internal loopback mode,
the transmitted data is looped back to the receiver inside
the controller without actually transmitting any data to
the external network. The receiver will move the received data to the next receive buffer, where it can be
examined by software. Alternatively, in external loopback mode, data can be transmitted to and received
from the external network.
Loopback operation is enabled by setting LOOP
(CSR15, bit 2) to ONE. The mode of loopback operation
is dependent on the active network port and on the settings of the control bits INTL (CSR15, bit 6), MENDECL
(CSR15, bit 10) and TMAULOOP (BCR2, bit 14). The
setting of the full-duplex control bits in BCR9 has no effect on the loopback operation.
GPSI Loopback Modes
When GPSI is the active network port there are only two
modes of loopback operation: internal and external
loopback. The settings of MENDECL and TMAULOOP
have no effect for this port.
lected. Data is routed from the transmit FIFO through
the MENDEC back to the receive FIFO. No data is transmitted to the network. All signals on the receive and collision inputs are ignored.
External loopback operation is selected by setting INTL
to ZERO. The programming of MENDECL has no effect
in this mode. The AUI transmitter is enabled and data is
transmitted to the network. The PCnet-PCI II controller
expects data to be looped back to the receive inputs outside the chip. Collision detection is active in this mode.
T-MAU Loopback Modes
When T-MAU is the active network port there are four
modes of loopback operation: internal loopback with
and without MENDEC and two external loopback
modes.
When INTL and MENDECL are set to ONE, internal
loopback without MENDEC is selected. Data coming
out of the transmit FIFO is fed directly to the receive
FIFO. The T-MAU does not transmit any data to the network, but it continues to send link pulses. All signals on
the receive inputs are ignored. LCAR (TMD2, bit 27) will
always read ZERO, regardless of the link state. The programming of TMAULOOP has no effect.
When INTL is set to ONE and MENDECL is cleared to
ZERO, internal loopback including the MENDEC is selected. Data is routed from the transmit FIFO through
the MENDEC back to the receive FIFO. The T-MAU
does not transmit any data to the network, but it continues to send link pulses. All signals on the receive inputs
are ignored. LCAR (TMD2, bit 27) will always read
ZERO, regardless of the link state. The programming of
TMAULOOP has no effect.
When INTL is set to ONE, internal loopback is selected.
Data coming out of the transmit FIFO is fed directly to
the receive FIFO. All GPSI outputs are inactive, inputs
are ignored.
External loopback operation is selected by setting INTL
to ZERO. Data is transmitted to the network and is expected to be looped back to the GPSI receive pins outside the chip. Collision detection is active in this mode.
AUI Loopback Modes
When AUI is the active network port there are three
modes of loopback operation: internal with and without
MENDEC and external loopback. The setting of
TMAULOOP has no effect for this port.
When INTL and MENDECL are set to ONE, internal
loopback without MENDEC is selected. Data coming
out of the transmit FIFO is fed directly to the receive
FIFO. The AUI transmitter is disabled and signals on the
receive and collision inputs are ignored.
When INTL is set to ONE and MENDECL is cleared to
ZERO, internal loopback including the MENDEC is se-
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Am79C970A
External loopback operation works slightly different
when the T-MAU is the active network port. In a
10BASE-T network, the hub does not generate a receive carrier back to the PCnet-PCI II controller while
the chip is transmitting. The T-MAU provides this function internally. A true external loopback covering all the
components on the printed circuit board can only be performed by using a special connector that connects the
transmit pins of the RJ-45 jack to its receive pins. When
INTL is cleared to ZERO and TMAULOOP is set to ONE,
data is transmitted to the network and is expected to be
routed back to the chip. Collision detection is disabled in
this mode. The link state machine is forced into the link
pass state. LCAR will always read ZERO. The programming of MENDECL has no effect in this mode.
The PCnet-PCI II controller provides a special external
loopback mode that allows the device to be connected
to a live 10BASE-T network. The virtual external loopback mode is invoked by setting INTL and TMAULOOP
to ZERO. In this mode, data coming out of the transmit
FIFO is fed directly into the receive FIFO. Additionally,
all transmit data is output to the network. The link state
P R E L I M I N A R Y
machine is active as is the collision detection logic. The
programming of MENDECL has no effect in this mode.
Miscellaneous Loopback Features
All transmit and receive function programming, such as
automatic transmit padding and receive pad stripping,
operates identically in loopback as in normal operation.
Loopback mode can be performed with any frame size.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is invoked. This is to be backwards compatible to the
C-LANCE (Am79C90) software.
Since the PCnet-PCI II controller has two FCS generators there are no more restrictions on FCS generation or
checking or on testing multicast address detection as
they exist in the half-duplex PCnet family devices and in
the C-LANCE and ILACC. On receive the PCnet-PCI II
controller now provides true FCS status. The descriptor
for a frame with an FCS error will have the FCS bit
(RMD1, bit 27) set to ONE. The FCS generator on the
transmit side can still be disabled by setting DXMTFCS
(CSR15, bit 3) to ONE.
In internal loopback operation the PCnet-PCI II controller provides a special mode to test the collision logic.
When FCOLL (CSR15, bit 4) is set to ONE, a collision is
forced during every transmission attempt. This will result in a Retry error.
Magic Packet Mode
Magic Packet mode is enabled by performing three
steps. First, the PCnet-PCI II controller must be put into
suspend mode (see description of CSR5, bit 0), allowing
any current network activity to finish. Next, MPMODE
(CSR5, bit 1) must be set to ONE if it has not been set
already. Finally, either SLEEP must be asserted (hardware control) or MPEN (CSR5, bit 2) must be set to ONE
(software control).
In Magic Packet mode, the PCnet-PCI II controller remains fully powered-up (all VDD and VDDB pins must remain at their supply levels). The device will not generate
any bus master transfers. No transmit operations will be
initiated on the network. The device will continue to receive frames from the network, but all frames will be
automatically flushed from the receive FIFO. Slave accesses to the PCnet-PCI II controller are still possible.
Magic Packet mode can be disabled at any time by
deasserting SLEEP or clearing MPEN.
A Magic Packet frame is a frame that is addressed to the
PCnet-PCI II controller and contains a data sequence in
its data field made up of sixteen consecutive physical
addresses (PADR[47:0]). The PCnet-PCI II controller
will search incoming frames until it finds a Magic Packet
frame. The device starts scanning for the sequence after processing the Length field of the frame. The data se-
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quence can begin anywhere in the data field of the
frame, but must be detected before the PCnet-PCI II
controller reaches the frame’s FCS field. The PCnetPCI II controller is designed such that it does not need
the synchronization sequence (6 bytes of all ONEs
(“FFFFFFFFFFFFh”) at the beginning of the data field),
to correctly recognize the proper data sequence. However, any deviation of the incoming frame’s Magic Packet data sequence from the required physical address
sequence, even by a single bit, will prevent the detection
of that frame as a Magic Packet frame.
The PCnet-PCI II controller supports two different
modes of address detection for a Magic Packet frame. If
MPPLBA (CSR5, bit 5) is at its default value of ZERO,
the PCnet-PCI II controller will only detect a Magic
Packet frame if the destination address of the frame
matches the content of the physical address register
(PADR). If MPPLBA is set to ONE, the destination address of the Magic Packet frame can be unicast, multicast, or broadcast. Note that the setting of MPPLBA
only effects the address detection of the Magic Packet
frame. The Magic Packet data sequence must be made
up of sixteen consecutive physical addresses
(PADR[47:0]), even if the packet contains a valid destination address that is not the physical address.
When the PCnet-PCI II controller detects a Magic Packet frame, it sets MPINT (CSR5, bit 4) to ONE. If INEA
(CSR0, bit 6) and MPINTE (CSR5, bit 3) are set to ONE,
INTA will be asserted. The interrupt signal can be used
wake up the system. As an alternative, one of the four
LED pins can be programmed to indicated that a Magic
Packet frame has been received. MPSE (BCR4–7, bit 9)
must be set to ONE to enable that function. Note that the
polarity of the LED pin can be programmed to be active
High by setting LEDPOL (BCR4–7, bit 14) to ONE.
Once a Magic Packet frame is detected, the PCnet-PCI
II controller will discard the frame internally, but will not
resume normal transmit and receive operations until
SLEEP is deasserted or MPEN is cleared, disabling
Magic Packet mode. Once either of these events has
occurred indicating that the system has detected the assertion of INTA or an LED pin and is now “awake”, the
controller will continue polling the receive and transmit
descriptor rings where it left off. Reinitialization should
not be performed.
If Magic Packet mode is disabled by the deassertion of
SLEEP, then in order to immediately reenable Magic
Packet mode, the SLEEP pin must remain deasserted
for at least 200 ns before it is reasserted. If Magic Packet
mode is disabled by clearing MPEN, then it may be immediately reenabled by setting MPEN back to ONE.
The bus interface clock (CLK) must continue running if
INTA is used to indicate the detection of a magic packet.
81Am79C970A
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A system that wants to stop the clock during Magic
Packet mode should use one of the LED pins as an indicator of Magic Packet frame detection. It should also
stop the clock after enabling Magic Packet mode, otherwise PCI bus activity, including accessing CSR5 to set
MPMODE and possibly MPEN to a ONE, could be affected. The clock should be restarted before Magic
Packet mode is disabled if MPEN is being cleared or the
clock must be restarted right after magic packet mode is
disabled if SLEEP is being deasserted. Otherwise, the
receive FIFO may overflow if new frames arrive. The
network clock (XTAL1) must continue running at all
times while in Magic Packet mode.
MANCHESTER ENCODER/DECODER
The integrated Manchester Encoder/Decoder
(MENDEC) provides the PLS (Physical Layer Signaling)
P R E L I M I N A R Y
functions required for a fully compliant ISO 8802-3
(IEEE/ANSI 802.3) station. The MENDEC provides the
encoding function for data to be transmitted on the network using the high accuracy on-board oscillator, driven
by either the crystal oscillator or an external CMOS level
compatible clock. The MENDEC also provides the decoding function from data received from the network.
The MENDEC contains a Power On Reset (POR) circuit, which ensures that all analog portions of the
PCnet-PCI II controller are forced into their correct state
during power up, and prevents erroneous data transmission and/or reception during this time.
External Crystal Characteristics
When using a crystal to drive the oscillator, the following
crystal specification may be used to ensure less than
±0.5 ns jitter at DO±:
Table 7. Crystal Characteristics
Parameter Min Nom Max Units
1. Parallel Resonant Frequency 20 MHz
2. Resonant Frequency Error –50 +50 PPM
3. Change in Resonant Frequency
With Respect To Temperature (0 – 70 C)* –40 +40 PPM
4. Crystal Load Capacitance 20 50 pF
5. Motional Crystal Capacitance (C1) 0.022 pF
6. Series Resistance 35 ohm
7. Shunt Capacitance 7pF
8. Drive Level TBD mW
* Requires trimming specification, not trim is 50 PPM total.
External Clock Drive Characteristics
When driving the oscillator from a CMOS level
external clock source, XTAL2 must be left floating
(unconnected). An external clock having the following
characteristics must be used to ensure less than ±0.5 ns
jitter at DO±.
Table 8. External Clock Source Characteristics
Clock Frequency: 20 MHz ±0.01%
Rise/Fall Time (tR/tF): <= 6 ns from 0.5 V to VDD –0.5 V
XTAL1 HIGH/LOW Time (tHIGH/tLOW): 20 ns min.
XTAL1 Falling Edge to Falling Edge Jitter: <
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
±0.2 ns at 2.5 V input (VDD/2)
signed to operate into terminated transmission lines.
When operating into a 78 Ω terminated transmission
line, the transmit signaling meets the required output
serial bit stream. The transmit outputs (DO±) are de-
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levels and skew for Cheapernet, Ethernet and
IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental mode crystal oscillator provides
the basic timing reference for the MENDEC portion of
the PCnet-PCI II controller. The crystal frequency is
divided by two to create the internal transmit clock reference. Both the 10 MHz and 20 MHz clocks are fed into
the Manchester Encoder. The internal transmit clock is
used by the MENDEC to synchronize the Internal Transmit Data (ITXDAT) and Internal Transmit Enable
(ITXEN) from the controller. The internal transmit clock
is also used as a stable bit rate clock by the receive section of the MENDEC and controller.
The oscillator requires an external 0.01% timing reference. If an external crystal is used, the accuracy requirements are tighter because allowance for the on-board
parasitics must be made to deliver a final accuracy
of 0.01%.
Transmission is enabled by the controller. As long as the
ITXEN request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO±. When the internal request is dropped by the con-
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troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
Table 9. TSEL Effect
TSEL LOW: The idle state of DO± yields ZERO
differential to operate transformercoupled loads.
TSEL HIGH: In this idle state, DO+ is positive with
respect to DO– (logical HIGH).
Receiver Path
The principal functions of the receiver are to signal the
PCnet-PCI II controller that there is information on the
receive pair, and separate the incoming Manchester encoded data stream into clock and NRZ data.
The receiver section (see the figure below) consists of
two parallel paths. The receive data path is a ZERO
threshold, wide bandwidth line receiver. The carrier path
is an offset threshold bandpass detecting line receiver.
Both receivers share common bias networks to allow
operation over a wide input common mode range.
DI±
*Internal signal
Data
Receiver
Noise
Reject
Filter
Figure 36. Receiver Block Diagram
Input Signal Conditioning
Transient noise pulses at the input data stream are rejected by the Noise Rejection Filter. Pulse width rejection is proportional to transmit data rate.
The Carrier Detection circuitry detects the presence of
an incoming data frame by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acquisition. Clock acquisition requires a valid Manchester bit
pattern of 1010b to lock onto the incoming message.
Manchester
Decoder
Carrier
Detect
Circuit
IRXDAT*
IRXCLK*
IRXEN*
19436A-39
When input amplitude and pulse width conditions are
met at DI±, the internal enable signal from the MENDEC
to controller (IRXEN) is asserted and a clock acquisition
cycle is initiated.
Clock Acquisition
When there is no activity at DI± (receiver is idle), the receive oscillator is phase locked to the internal transmit
clock. The first negative clock transition (bit cell center of
first valid Manchester ZERO) after IRXEN is asserted
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interrupts the receive oscillator. The oscillator is then restarted at the second Manchester ZERO (bit time 4) and
is phase locked to it. As a result, the MENDEC acquires
the clock from the incoming Manchester bit pattern in 4
bit times with a 1010b Manchester bit pattern.
IRXCLK and IRXDAT are enabled 1/4 bit time after clock
acquisition in bit cell 5. IRXDAT is at a HIGH state when
the receiver is idle (no IRXCLK). IRXDAT however, is
undefined when clock is acquired and may remain HIGH
or change to LOW state whenever IRXCLK is enabled.
At 1/4 bit time into bit cell 5, the controller portion of the
PCnet-PCI II controller sees the first IRXCLK transition.
This also strobes in the incoming fifth bit to the MENDEC
as Manchester ONE. IRXDAT may make a transition after the IRXCLK rising edge in bit cell 5, but its state is still
undefined. The Manchester ONE at bit 5 is clocked to
IRXDAT output at 1/4 bit time in bit cell 6.
P R E L I M I N A R Y
PLL Tracking
After clock acquisition, the phase-locked clock is compared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a correction circuit. This circuit ensures that the phaselocked clock remains locked on the received signal.
Individual bit cell phase corrections of the Voltage Controlled Oscillator (VCO) are limited to 10% of the phase
difference between BCC and phase-locked clock.
Hence, input data jitter is reduced in IRXCLK by 10 to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI± inputs after
IRXEN is asserted for an end of message. IRXEN deasserts 1 to 2 bit times after the last positive transition on
the incoming message. This initiates the end of reception cycle. The time delay from the last rising edge of the
message to IRXEN deassert allows the last bit to be
strobed by IRXCLK and transferred to the controller section, but prevents any extra bit(s) at the end of message.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI± inputs. Input error is
less than ± 35 mV to minimize sensitivity to input rise
and fall time. IRXCLK strobes the data receiver output at
1/4 bit time to determine the value of the Manchester bit,
and clocks the data out on IRXDAT on the following
IRXCLK. The data receiver also generates the signal
used for phase detector comparison to the internal
MENDEC voltage controlled oscillator (VCO).
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. The clock is phase-locked to the negative
transition at the bit cell center of the second ZERO in
the pattern.
Since data is strobed at 1/4 bit time, Manchester transitions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criterion for an error, a definition of Jitter
Handling is:
The peak deviation approaching or crossing 1/4 bit cell
position from nominal input transition, for which the
MENDEC section will properly decode data.
Attachment Unit Interface
The Attachment Unit Interface (AUI) is the PLS (Physical Layer Signaling) to PMA (Physical Medium Attachment) interface which effectively connects the DTE to a
MAU. The differential interface provided by the
PCnet-PCI II controller is fully compliant to Section 7 of
ISO 8802-3 (ANSI/IEEE 802.3).
After the PCnet-PCI II controller initiates a transmission
it will expect to see data “looped-back” on the DI± pair
(when the AUI port is selected). This will internally generate a “carrier sense”, indicating that the integrity of the
data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted before end of transmission. If ”carrier
sense” does not become active in response to the data
transmission, or becomes inactive before the end of
transmission, the loss of carrier (LCAR) error bit will be
set in the transmit descriptor ring (TMD2, bit 27) after the
frame has been transmitted.
Differential Input Termination
The differential input for the Manchester data (DI±) is
externally terminated by two 40.2 Ω resistors and one
optional common-mode bypass capacitor, as shown in
the diagram below. The differential input impedance,
Z
IDF, and the common-mode input impedance, ZICM,
are specified so that the Ethernet specification for cable
termination impedance is met using standard 1% resistor terminators. If SIP devices are used, 39 ohms is also
a suitable value. The CI± differential inputs are terminated in exactly the same way as the DI± pair.
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DI+
PCnet-PCI II
DI-
40.2 Ω
Figure 37. AUI Differential Input Termination
Collision Detection
A MAU detects the collision condition on the network
and generates a 10 MHz differential signal at the
CI± inputs. This collision signal passes through an input
stage which detects signal levels and pulse duration.
When the signal is detected by the MENDEC it sets the
ICLSN line HIGH. The condition continues for approximately 1.5 bit times after the last LOW-to-HIGH transition on CI±.
Twisted-pair Transceiver
This section describes operation of the Twisted Pair
Transceiver (T-MAU) when operating in half-duplex
mode. When in half-duplex mode, the T-MAU
implements the Medium Attachment Unit (MAU) functions for the Twisted Pair Medium as specified by the
supplement to IEEE 802.3 standard (Type 10BASE-T).
When operating in full-duplex mode, the MAC engine
behavior changes as described in the section
“Full-Duplex Operation”.
The T-MAU provides twisted pair driver and receiver circuits, including on-board transmit digital predistortion
and receiver squelch and a number of additional features including Link Status indication, Automatic
Twisted Pair Receive Polarity Detection/Correction and
Indication, Receive Carrier Sense, Transmit Active and
Collision Present indication.
Twisted Pair Transmit Function
The differential driver circuitry in the TXD± and TXP±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted Pair cable, as specified
by the 10BASE-T supplement to the ISO 8802-3
(IEEE/ANSI 802.3) Standard. The transmit function for
data output meets the propagation delays and jitter
specified by the standard.
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AUI Isolation
Transformer
40.2 Ω
0.01 µF
to
0.1 µF
19436A-40
Twisted Pair Receive Function
The receiver complies with the receiver specifications of
the ISO 8802-3 (IEEE/ANSI 802.3) 10BASE-T Standard, including noise immunity and received signal rejection criteria (“Smart Squelch”). Signals meeting
these criteria appearing at the RXD± differential input
pair are routed to the MENDEC. The receiver function
meets the propagation delays and jitter requirements
specified by the standard. The receiver squelch level
drops to half its threshold value after unsquelch to allow
reception of minimum amplitude signals and to offset
carrier fade in the event of worst case signal attenuation
and crosstalk noise conditions.
Note that the 10BASE-T Standard defines the receive
input amplitude at the external Media Dependent Interface (MDI). Filter and transformer loss are not specified.
The T-MAU receiver squelch levels are defined to
account for a 1 dB insertion loss at 10 MHz, which is typical for the type of receive filters/transformers employed.
Normal 10BASE-T compatible receive thresholds are
employed when the LRT bit (CSR15, bit 9) is cleared to
ZERO. When the LRT bit is set to ONE, the Low Receive
Threshold option is invoked, and the sensitivity of the
T-MAU receiver is increased. This allows longer line
lengths to be employed, exceeding the 100 m target distance of normal 10BASE-T (assuming typical 24 AWG
cable). The increased receiver sensitivity compensates
for the increased signal attenuation caused by the additional cable distance.
However, making the receiver more sensitive means
that it is also more susceptible to extraneous noise, primarily caused by coupling from co-resident services
(crosstalk). For this reason, it is recommended that
when using the Low Receive Threshold option that the
service should be installed on 4-pair cable only.
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P R E L I M I N A R Y
Multipair cables within the same outer sheath have
lower crosstalk attenuation, and may allow noise emitted from adjacent pairs to couple into the receive pair,
and be of sufficient amplitude to falsely unsquelch
the T-MAU.
Link Test Function
The Link Test Function is implemented as specified by
the 10BASE-T standard. During periods of transmit pair
inactivity, “Link beat pulses” will be periodically sent
over the twisted pair medium to constantly monitor
medium integrity.
When the link test function is enabled (DLNKTST bit in
CSR15 is cleared), the absence of link beat pulses and
receive data on the RXD± pair will cause the T-MAU to
go into a Link Fail state. In the Link Fail state, data transmission, data reception, data loopback and the collision
detection functions are disabled, and remain disabled
until valid data or more than five consecutive link pulses
appear on the RXD± pair. During Link Fail, the Link
Status signal is inactive. When the link is identified as
functional, the Link Status signal is asserted. The
LNKST pin displays the Link Status signal by default.
The T-MAU will power up in the Link Fail state and the
normal algorithm will apply to allow it to enter the Link
Pass state. If T-MAU is selected using the PORTSEL
bits in CSR15, the T-MAU will be forced into the Link Fail
state when moving from AUI to T-MAU selection.
Transmission attempts during Link Fail state will produce no network activity and will produce LCAR and
CERR error indications.
In order to interoperate with systems which do not implement Link Test, this function can be disabled by setting
the DLNKTST bit in CSR15. With link test disabled, the
data driver, receiver and loopback functions as well as
collision detection remain enabled irrespective of the
presence or absence of data or link pulses on the RXD±
pair. Link Test pulses continue to be sent regardless of
the state of the DLNKTST bit.
Polarity Detection and Reversal
The T-MAU receive function includes the ability to invert
the polarity of the signals appearing at the RXD± pair if
the polarity of the received signal is reversed (such as in
the case of a wiring error). This feature allows data
frames received from a reverse wired RXD± input pair to
be corrected in the T-MAU prior to transfer to the
MENDEC. The polarity detection function is activated
following H_RESET or Link Fail, and will reverse the receive polarity based on both the polarity of any previous
link beat pulses and the polarity of subsequent frames
with a valid End Transmit Delimiter (ETD).
When in the Link Fail state, the T-MAU will recognize
link beat pulses of either positive or negative polarity.
Exit from the Link Fail state is made due to the reception
of 5–6 consecutive link beat pulses of identical polarity.
On entry to the Link Pass state, the polarity of the last 5
link beat pulses is used to determine the initial receive
polarity configuration and the receiver is reconfigured to
subsequently recognize only link beat pulses of the previously recognized polarity.
Positive link beat pulses are defined as received signal
with a positive amplitude greater than 585 mV (LRT = 1)
with a pulse width of 60 ns–200 ns. This positive excursion may be followed by a negative excursion. This definition is consistent with the expected received signal at
a correctly wired receiver, when a link beat pulse which
fits the template of Figure 14-12 of the 10BASE-T Standard is generated at a transmitter and passed through
100 m of twisted pair cable.
Negative link beat pulses are defined as received signals with a negative amplitude greater than 585 mV with
a pulse width of 60–200 ns. This negative excursion
may be followed by a positive excursion. This definition
is consistent with the expected received signal at a reverse wired receiver, when a link beat pulse which fits
the template of Figure 14-12 in the 10BASE-T Standard
is generated at a transmitter and passed through 100 m
of twisted pair cable.
The polarity detection/correction algorithm will remain
“armed” until two consecutive frames with valid ETD of
identical polarity are detected. When “armed”, the receiver is capable of changing the initial or previous polarity configuration based on the ETD polarity.
On receipt of the first frame with valid ETD following
H_RESET or Link Fail, the T-MAU will utilize the
inferred polarity information to configure its RXD± input,
regardless of its previous state. On receipt of a second
frame with a valid ETD with correct polarity, the
detection/correction algorithm will “lock-in” the received
polarity. If the second (or subsequent) frame is not detected as confirming the previous polarity decision, the
most recently detected ETD polarity will be used as the
default. Note that frames with invalid ETD have no effect
on updating the previous polarity decision. Once two
consecutive frames with valid ETD have been received,
the T-MAU will disable the detection/correction
algorithm until either a Link Fail condition occurs or
H_RESET is activated.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when
enabled by the LED control bits in the Bus Configuration
Registers (BCR4 to BCR7).
Twisted Pair Interface Status
When the T-MAU is in Link Pass state, three signals
(XMT, RCV and COL) indicate whether the T-MAU is
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transmitting, receiving, or in a collision state with both
functions active simultaneously. These signals are internal signals that can be programmed to appear on any
of the LED output pins. Programming is done by writing
to BCR4 to BCR7.
In the Link Fail state, XMT, RCV and COL are inactive.
Collision Detection Function
Activity on both twisted pair signals RXD± and TXD± at
the same time constitutes a collision, thereby causing
the internal COL signal to be activated. COL will remain
active until one of the two colliding signals changes from
active to idle. However, transmission attempt in Link Fail
state results in LCAR and CERR indication. COL stays
active for 2 bit times at the end of a collision.
Signal Quality Error Test Function
The Signal Quality Error (SQE) test function (also called
Heartbeat) is disabled when the 10BASE-T port
is selected.
Jabber Function
The Jabber function prevents the twisted pair transmit
function of the T-MAU TXD± from being active for an excessive period of time (20 ms to 150 ms). This prevents
any one node from disrupting the network due to a
“stuck-on” or faulty transmitter. If this maximum transmit
time is exceeded, the T-MAU transmitter circuitry is
disabled, the JAB bit is set (CSR4, bit 1) and the COL
signal is asserted. Once the transmit data stream is removed, the T-MAU waits an “unjab” time of 250 ms to
750 ms before it deasserts COL and re-enables the
transmit circuitry.
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Power Down
The T-MAU circuitry can be made to go into a power
savings mode. The T-MAU will go into the power down
mode when H_RESET is active, when coma mode is active, or when the T-MAU is not selected. Refer to the
section “Power Savings Modes” for descriptions of the
various power down modes.
Any of the three conditions listed above resets the internal logic of the T-MAU and places the device into power
down mode. In this mode, the Twisted Pair driver pins
(TXD±, TXP±) are driven LOW, and the internal T-MAU
status signals (LNKST, RCVPOL, XMT, RCV and COL)
signals are inactive.
After coming out of the power down mode, the T-MAU
will remain in the reset state for an additional 10 µs. Immediately after the reset condition is removed, the
T-MAU will be forced into the Link Fail state. The T-MAU
will move to the Link Pass state only after 5–6 link beat
pulses and/or a single received message is detected on
the RD± pair.
In snooze mode, the T-MAU receive circuitry will remain
enabled even while the SLEEP pin is driven LOW.
10BASE-T Interface Connection
The figure below shows the proper 10BASE-T network
interface design. Refer to Appendix A for a list of compatible 10BASE-T filter/transformer modules.
Note that the recommended resistor values and filter
and transformer modules are the same as those used by
the IMR+ (Am79C981).
PCnet–PCI II
Transformer
TXD+
TXP+
TXD-
TXP-
RXD+
RXD-
61.9 Ω
422 Ω
61.9 Ω
422 Ω
1.21 KΩ
XMT
Filter
RCV
Filter
100 Ω
Figure 38. 10BASE-T Interface Connection
Filter &
Module
1:1
1:1
RJ45
Connector
TD+
1
2
TD-
3
RD+
6
RD-
19436A-41
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P R E L I M I N A R Y
Full-Duplex Operation
The PCnet-PCI II controller supports full-duplex operation on all three network interfaces: AUI, 10BASE-T, and
GPSI. full-duplex operation allows simultaneous transmit and receive activity on the TXD± and RXD± pairs of
the 10BASE-T port, the DO± and DI± pairs of the AUI
port, or the TXDAT and RXDAT pins of the GPSI port.
Full-duplex operation is enabled by the FDEN and
AUIFD bits located in BCR9. When operating in full-duplex mode, the following changes to the device operation are made:
Bus Interface/Buffer Management Unit changes:
■ The first 64 bytes of every transmit frame are not preserved in the transmit FIFO during transmission of
the first 512 bits as described in the section “Transmit Exception Conditions”. Instead, when full-duplex
mode is active and a frame is being transmitted, the
XMTFW bits (CSR80, bits 9–8) always govern when
transmit DMA is requested.
■ Successful reception of the first 64 bytes of every receive frame is not a requirement for receive DMA to
begin as described in the section “Receive Exception Condition”. Instead, receive DMA will be requested as soon as either the Receive FIFO
Watermark (CSR80, bits 13–12) is reached or a
complete valid receive frame is detected, regardless
of length. This receive FIFO operation is identical to
when the RPA bit (CSR124, bit 3) is set during halfduplex mode operation.
MAC Engine changes:
■ Changes to the Transmit Deferral mechanism:
– Transmission is not deferred while receive is
active.
– The Inter Packet Gap (IPG) counter which gov-
erns transmit deferral during the IPG between
back-to-back transmits is started when transmit
activity for the first packet ends instead of when
transmit and carrier activity ends.
■ When the AUI or GPSI port is active, Loss of Carrier
(LCAR) reporting is disabled. (LCAR is still reported
when the 10BASE-T port is active if a packet is transmitted while in Link Fail state.)
■ The 4.0 µs carrier sense blinding period after a trans-
mission during which the SQE test normally occurs is
disabled.
■ When the AUI or GPSI port is active, the SQE Test
error reporting (CERR) is disabled. (CERR is still reported when the 10BASE-T port is active if a packet
is transmitted while in Link Fail state.)
■ The collision indication input to the MAC engine is
ignored.
T-MAU changes:
■ The internal transmit to receive feedback path which
is used to indicate carrier sense during normal transmission in half-duplex mode is disabled.
■ The collision detect circuit is disabled.
■ The SQE test function is disabled.
Full-Duplex Link Status LED Support
The PCnet-PCI II controller provides a bit in each of the
LED Status registers (BCR4, BCR5, BCR6, BCR7) to
display the Full-Duplex Link Status. If the FDLSE bit
(bit 8) is set, a value of ONE will be sent to the associated LEDOUT bit when the T-MAU is in the Full-Duplex
Link Pass state.
General Purpose Serial Interface
The General Purpose Serial Interface (GPSI) provides a
direct interface to the MAC section of the PCnet-PCI II
controller. All signals are digital and data is non-encoded. The GPSI allows use of an external Manchester
encoder/decoder such as the Am7992B Serial Interface
Adapter (SIA). In addition, it allows the PCnet-PCI II
controller to be used as a MAC sublayer engine in a repeater designs based on the Am79C981 IMR+.
GPSI mode is invoked by setting the GPSIEN bit
(CSR124, bit 4) to ONE and by selecting the interface
through the PORTSEL bits of the Mode register
(CSR15, bits 8–7).
The GPSI interface uses some of the same pins as the
interface to the Expansion ROM. Simultaneous use of
both functions is not possible. Reading from the Expansion ROM and then reconfiguring the pins to the GPSI
mode is supported. With this approach an external
transceiver is required to prevent contention between
the GPSI signals and the data outputs from the Expansion ROM. EROE can be used as control signal for the
external transceiver.
After an H_RESET all pins are internally configured to
function as Expansion ROM interface. When the GPSI
interface is selected by setting PORTSEL (CSR15, bits
8–7) to 10b, the PCnet-PCI II controller will terminate all
further read accesses to Expansion ROM by asserting
TRDY within two clock cycles. The read data will
be undefined.
During the boot procedure the system will try to find an
Expansion ROM. A PCI system assumes that an Expansion ROM is present when it reads the ROM signature
55h (byte 0) and AAh (byte 1). A design without Expansion ROM can guarantee that the Expansion ROM detection fails by connecting two adjacent ERD pins
together. The recommended pins are pin 77
(ERD6/TXEN) and pin 78 (ERD5), since TXEN should
have an external pull-down.
GPSI signal functions are described in the pin description section under the GPSI subheading.
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Table 10. GPSI Pin Configuration
PCnet-PCI II
PCnet-PCI II PCnet-PCI II Controller
C-LANCE Controller Controller Expansion
GPSI Function GPSI I/O Type GPSI Pin GPSI Pin Pin Number ROM Pin
Collision I CLSN CLSN 81 ERD3
Receive Clock I RCLK RXCLK 85 ERD1
Receive Data I RX RXDAT 86 ERD0
Receive Enable I RENA RXEN 83 ERD2
Transmit Clock I TCLK TXCLK 80 ERD4
Transmit Data O TX TXDAT 75 ERD7
Transmit Enable O TENA TXEN 77 ERD6
Note that the XTAL1 input must always be driven with a
clock source, even if GPSI mode is to be used. It is not
necessary for the XTAL1 clock to meet the normal frequency and stability requirements in this case. Any frequency between 8 MHz and 20 MHz is acceptable.
However, voltage drive requirements do not change.
When GPSI mode is used, XTAL1 must be driven for
several reasons:
■ The default H_RESET configuration for the PCnetPCI II controller is AUI port selected and until GPSI
mode is selected, the XTAL1 clock is needed for
some internal operations (namely, RESET).
■ The XTAL1 clock drives the EEPROM read operation, regardless of the network mode selected.
■ The XTAL1 clock determines the length the internal
S_RESET caused by the read of the Reset register,
regardless of the network mode.
Note that if a clock slower than 20 MHz is provided at the
XTAL1 input, the time needed for EEPROM read and
the internal S_RESET will increase.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic. Note
that when the 10BASE-T port is selected, transitions on
SRDCLK will only occur during receive activity. When
the AUI or GPSI port is selected, transitions on SRDCLK
will occur during both transmit and receive activity. Once
a received frame commences and data and clock are
available from the decoder, the EADI logic will monitor
the alternating (1,0) preamble pattern until the two
ONEs of the Start Frame Delimiter (SFD, 10101011 bit
pattern) are detected, at which point the SFBD output
will be driven HIGH.
The SFBD signal will initially be LOW. The assertion of
SFBD is a signal to the external address detection logic
that the SFD has been detected and that subsequent
SRDCLK cycles will deliver packet data to the external
logic. Therefore, when SFBD is asserted, the external
address matching logic should begin de-serialization of
the SRD data and send the resulting destination address to a Content Addressable Memory (CAM) or other
address detection device. In order to reduce the amount
of logic external to the PCnet-PCI II controller for multi-
External Address Detection Interface
The External Address Detection Interface (EADI) is provided to allow external address filtering. It is selected by
setting the EADISEL bit in BCR2 to ONE. This feature is
typically utilized for terminal servers, bridges and/or
router products. The EADI interface can be used in conjunction with external logic to capture the packet destination address from the serial bit stream as it arrives at
the PCnet-PCI II controller, compare the captured address with a table of stored addresses or identifiers, and
then determine whether or not the PCnet-PCI II controller should accept the packet.
The EADI interface outputs are delivered directly from
the NRZ decoded data and clock recovered by the
Manchester decoder or input into the GPSI port. This allows the external address detection to be performed in
parallel with frame reception and address comparison in
the MAC Station Address Detection (SAD) block of the
PCnet-PCI II controller.
ple address decoding systems, the SFBD signal will
toggle at each new byte boundary within the packet,
subsequent to the SFD. This eliminates the need for externally supplying byte framing logic.
SRD is the decoded NRZ data from the network. This
signal can be used for external address detection. Note
that when the 10BASE-T port is selected, transitions on
SRD will only occur during receive activity. When the
AUI or GPSI port is selected, transitions on SRD will occur during both transmit and receive activity.
The EAR pin should be driven LOW by the external address comparison logic to reject a frame.
If an address match is detected by comparison with
either the Physical Address or Logical Address Filter
registers contained within the PCnet-PCI II controller or
the frame is of the type “Broadcast”, then the frame will
be accepted regardless of the condition of EAR. When
AMD
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the EADISEL bit of BCR2 is set to ONE and the PCnetPCI II controller is programmed to promiscuous mode
(PROM bit of the Mode Register is set to ONE), then all
incoming frames will be accepted, regardless of any activity on the EAR pin.
Internal address match is disabled when PROM
(CSR15, bit 15) is cleared to ZERO, DRCVBC (CSR15,
bit 14) and DRCVPA (CSR15, bit 13) are set to ONE and
the Logical Address Filter registers (CSR8 to CSR11)
are programmed to all ZEROs.
When the EADISEL bit of BCR2 is set to ONE and internal address match is disabled, then all incoming frames
will be accepted by the PCnet-PCI II controller, unless
the EAR pin becomes active during the first 64 bytes of
the frame (excluding preamble and SFD). This allows
external address lookup logic approximately 58 byte
times after the last destination address bit is available to
generate the EAR signal, assuming that the PCnet-PCI
II controller is not configured to accept runt packets. The
EADI logic only samples EAR from 2 bit times after SFD
until 512 bit times (64 bytes) after SFD. The frame will be
accepted if EAR has not been asserted during this window. If Runt Packet Accept (CSR124, bit 3) is enabled,
then the EAR signal must be generated prior to the receive message completion, if frame rejection is to be
guaranteed. Runt packet sizes could be as short as 12
byte times (assuming 6 bytes for source address, 2
bytes for length, no data, 4 bytes for FCS) after the last
Table 11. EADI Operations
bit of the destination address is available. EAR must
have a pulse width of at least 110 ns.
Note that when the PCnet-PCI II controller is operating
in full-duplex mode or runt packet accept is turned on
(CSR124, bit 3) the Receive FIFO Watermark (CSR80,
bits 13–12) must be programmed to 64 (01b) or 128
(10b) to allow the full window of 512 bit times after SFD
for the assertion of EAR. If the watermark was programmed to 16 (00b), receive FIFO DMA could start before EAR is asserted to reject the frame.
The EADI outputs continue to provide data throughout
the reception of a frame. This allows the external logic
to capture frame header information to determine
protocol type, inter-networking information, and other
useful data.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
are set). This configuration is useful as a semi-powerdown mode in that the PCnet-PCI II controller will not
perform any power-consuming DMA operations. However, external circuitry can still respond to control
frames on the network to facilitate remote node control.
The table below summarizes the operation of the
EADI interface:
PROM EAR Required Timing Received Messages
1 X No timing requirements All received frames
0 1 No timing requirements All received frames
0 0 Low for 110 ns during the window from PCnet-PCI II controller internal physical
2 bits after SFD to 512 bits after SFD address and logical address filter
matches and broadcast frames
Expansion ROM Interface
The Expansion ROM is an 8-bit ROM connected to the
PCnet-PCI II controller Expansion ROM Data bus
(ERD). It can be of up to 64 Kbytes in size. The Expansion ROM Address bus (ERA) is 8 bits wide. An external
latch is required to store the upper 8 bits of the 16-bit address to the ROM. All ERA outputs are forced to a constant level to conserve power while no access to the
Expansion ROM is performed.
EROE is asserted during the Expansion ROM read op-
of the ROM. In an application that does not use the GPSI
port, EROE can be left unconnected and the OE input of
the ROM can be tied to ground to always enable the
ROM data outputs. The CE input of the ROM can either
be tied to ground or it can also be connected to EROE.
The signal ERACLK is provided to strobe the upper 8
bits of the address into an external latch. The timing relation of ERACLK to ERA is such that both ’373 (transparent latch) and ’374 (D flip-flop) types of address latch
can be used.
eration. This signal can be used to control the OE input
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Expansion ROM
CE OE A[15:8] A[7:0] D[7:0]
Latch
EROE ERACLK ERA[7:0] ERD[7:0]
PCnet–PCI II
Figure 39. Expansion ROM Interface
AMD
19436A-42
The PCnet-PCI II controller will always read four bytes
for every host Expansion ROM read access. The interface to the Expansion ROM runs synchronous to the
PCI bus interface clock. The PCnet-PCI II controller will
start the read operation to the Expansion ROM by driving the upper 8-bits of the Expansion ROM address on
ERA[7:0]. This happens in the same clock cycle that the
device claims the transfer by asserting DEVSEL. One
clock later, EROE is asserted and ERACLK goes high to
allow latching of the upper address bits externally. The
upper portion of the Expansion ROM address will be the
same for all four byte read cycles. ERACLK is asserted
for one clock. ERA[7:0] are driven with the upper 8-bits
of the Expansion ROM address for one more clock cycle
after ERACLK goes low. Next, the PCnet-PCI II controller starts driving the lower 8 bits of the Expansion ROM
address on ERA[7:0].
The time the PCnet-PCI II controller waits for data to be
valid is programmable. ROMTMG (BCR18, bits 15–12)
defines the time from when the PCnet-PCI II controller
drives ERA[7:0] with the lower 8-bits of the Expansion
ROM address to when the PCnet-PCI II controller
latches in the data on the ERD[7:0] inputs. The register
value specifies the time in number of clock cycles. When
ROMTMG is set to Nine (the default value), ERD[7:0] is
sampled with the next rising edge of CLK nine clock cycles after ERA[7:0] was driven with a new address
value. The clock edge that is used to sample the data is
also the clock edge that generates the next Expansion
ROM address. Only the first three bytes of Expansion
ROM data are stored in holding registers. The fourth
byte is passed directly from the ERD[7:0] inputs to the
AD[31:24] outputs. One clock cycle after the last data
byte is available, PCnet-PCI II controller asserts TRDY.
Two clock cycles after the data is transferred on the PCI
bus, EROE is deasserted.
The access time for the Expansion ROM device (t
ACC)
can be calculated by subtracting the clock to output delay for the ERA[7:0] outputs (t
clock setup time for the ERD[7:0] inputs (t
VAL(ERA)) and the input to
SU(ERD)) from
the time defined by ROMTMG:
t
ACC ≤ ROMTMG* clock period – tVAL(ERA) – tSU(ERD)
For an adapter card application, the value used for clock
period should be 30 ns to guarantee correct interface
timing at the maximum clock frequency of 33 MHz.
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The timing diagram below assumes the default programming of ROMTMG (1001b = 9 CLK). After reading
the first byte, the PCnet-PCI II controller reads in three
more bytes by incrementing the lower portion of the
CLK
FRAME
C/BE
PAR
IRDY
TRDY
DEVSEL
STOP
ERA
ERD
EROE
ERACLK
1234567891011121314151617181920
AD
A[15:8] A[7:2],0,0
ROM address. After the last byte is strobed in, TRDY will
be asserted on clock 44. When the host tries to perform
a burst read of the Expansion ROM, the PCnet-PCI II
will disconnect the access at the second data phase.
21 22
A[7:2],0,1
23
CLK
FRAME
C/BE
PAR
IRDY
TRDY
DEVSEL
STOP
ERA
ERD
EROE
ERACLK
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AD
A[7:2],1,0 A[7:2],1,1
Figure 40. Expansion ROM Bus Read Sequence
The host must program the Expansion ROM Base Address register in the PCI configuration space before the
first access to the Expansion ROM. The PCnet-PCI II
controller will not react to any access to the Expansion
ROM until both MEMEN (PCI Command register, bit 1)
and ROMEN (PCI Expansion ROM Base Address register, bit 0) are set to ONE. After the Expansion ROM is
enabled, the PCnet-PCI II controller will claim all memory read accesses with an address between ROMBASE
and ROMBASE + 64K – 4 (ROMBASE, PCI Expansion
ROM Base Address register, bits 31–11). The address
44 45
19436A-43
output to the Expansion ROM is the offset from the address on the PCI bus to ROMBASE. The PCnet-PCI II
controller aliases all accesses to the Expansion ROM of
the command types “Memory Read Multiple” and “Memory Read Line” to the basic Memory Read command.
Since setting MEMEN also enables memory mapped
access to the I/O resources, attention must be given to
the PCI Memory Mapped I/O Base Address register, before enabling access to the Expansion ROM. The host
must set the PCI Memory Mapped I/O Base Address
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register to a value that prevents the PCnet-PCI II
controller from claiming any memory cycles not intended for it.
The Expansion ROM interface uses some of the same
pins as the GPSI interface. Simultaneous use of both
functions is not possible. Reading from the Expansion
ROM and then reconfiguring the pins to the GPSI mode
is supported. An external transceiver is required to prevent contention between the GPSI signals and the data
outputs from the Expansion ROM. EROE can be used
as control signal for the external transceiver.
After an H_RESET all pins are internally configured to
function as Expansion ROM interface. When the GPSI
interface is selected by setting PORTSEL (CSR15, bits
8–7) to 10b, the PCnet-PCI II controller will terminate
all further read accesses to Expansion ROM by asserting TRDY within two clock cycles. The read data will
be undefined.
During the boot procedure the system will try to find an
Expansion ROM. A PCI system assumes that an
Expansion ROM is present when it reads the ROM signature 55h (byte 0) and AAh (byte 1). A design without
Expansion ROM can guarantee that the Expansion
ROM detection fails by connecting two adjacent ERD
pins together and tying them high or low.
EEPROM Microwire Interface
The PCnet-PCI II controller contains a built-in capability
for reading and writing to an external serial EEPROM.
This built-in capability consists of an interface for direct
connection to a Microwire compatible EEPROM, an
automatic EEPROM read feature, and a user-programmable register that allows direct access to the Microwire
interface pins.
Automatic EEPROM Read Operation
Shortly after the deassertion of the RST pin, the
PCnet-PCI II controller will read the contents of the
EEPROM that is attached to the Microwire interface.
Because of this automaticread capability of the PCnetPCI II controller, an EEPROM can be used to program
many of the features of the PCnet-PCI II controller at
power-up, allowing system-dependent configuration information to be stored in the hardware, instead of inside
the device driver.
If an EEPROM exists on the Microwire interface, the
PCnet-PCI II controller will read the EEPROM contents
at the end of the H_RESET operation. The EEPROM
contents will be serially shifted into a temporary register
and then sent to various register locations on board the
PCnet-PCI II controller. Access to the PCnet-PCI II controller configuration space, the Expansion ROM or any
I/O resource is not possible during the EEPROM read
operation. The PCnet-PCI II controller will terminate any
access attempt with the assertion of DEVSEL and
AMD
STOP while TRDY is not asserted, signaling to the initia-
tor to disconnect and retry the access at a later time.
A checksum verification is performed on the data that is
read from the EEPROM. If the checksum verification
passes, PVALID (BCR19, bit 15) will be set to ONE. If
the checksum verification of the EEPROM data fails,
PVALID will be cleared to ZERO and the PCnet-PCI II
controller will force all EEPROM-programmable BCR
registers back to their H_RESET default values. The
content of the Address PROM locations (offsets 0h–Fh
from the I/O or memory mapped I/O base address),
however, will not be cleared. The 8 bit checksum for the
entire 36 bytes of the EEPROM should be FFh.
If no EEPROM is present at the time of the automatic
read operation, the PCnet-PCI II controller will recognize this condition and will abort the automatic read operation and clear both the PREAD and PVALID bits in
BCR19. All EEPROM-programmable BCR registers will
be assigned their default values after H_RESET. The
content of the Address PROM locations (offsets 0h–Fh
from the I/O or memory mapped I/O base address) will
be undefined.
If the user wishes to modify any of the configuration bits
that are contained in the EEPROM, then the seven command, data and status bits of BCR19 can be used to
write to the EEPROM. After writing to the EEPROM, the
host should set the PREAD bit of BCR19. This action
forces a PCnet-PCI II controller re-read of the EEPROM
so that the new EEPROM contents will be loaded into
the EEPROM-programmable registers on board the
PCnet-PCI II controller. (The EEPROM-programmable
registers may also be reprogrammed directly, but only
information that is stored in the EEPROM will be preserved at system power-down.) When the PREAD bit of
BCR19 is set, it will cause the PCnet-PCI II controller to
ignore further accesses to the PCnet-PCI II controller
configuration space, the Expansion ROM, or any I/O resource until the completion of the EEPROM read operation. The PCnet-PCI II controller will terminate these
access attempts with the assertion of DEVSEL and
STOP while TRDY is not asserted, signaling to the initia-
tor to disconnect and retry the access at a
later time.
EEPROM Auto-Detection
The PCnet-PCI II controller uses the EESK/LED1/SFBD
pin to determine if an EEPROM is present in the system.
At the rising edge of CLK during the last clock during
which RST is asserted, the PCnet-PCI II controller will
sample the value of the EESK/LED1/SFBD pin. If the
sampled value is a ONE, then the PCnet-PCI II controller assumes that an EEPROM is present, and the
EEPROM read operation begins shortly after the RST
pin is deasserted. If the sampled value of
EESK/LED1/SFBD is a ZERO, the PCnet-PCI II
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controller assumes that an external pulldown device is
holding the EESK/LED1/SFBD pin low indicating that
there is no EEPROM in the system. Note that if the designer creates a system that contains an LED circuit on
the EESK/LED1/SFBD pin but has no EEPROM present, then the EEPROM auto-detection function will incorrectly conclude that an EEPROM is present in the
system. However, this will not pose a problem for the
PCnet-PCI II controller, since the checksum verification
will fail.
Direct Access to the Microwire Interface
The user may directly access the Microwire port through
the EEPROM register, BCR19. This register contains
bits that can be used to control the Microwire interface
pins. By performing an appropriate sequence of accesses to BCR19, the user can effectively write to and
read from the EEPROM. This feature may be used by a
system configuration utility to program hardware configuration information into the EEPROM.
EEPROM-programmable Registers
The following registers contain configuration information that will be programmed automatically during the
EEPROM read operation:
■ BCR5 LED1 Status register
■ BCR6 LED2 Status register
■ BCR7 LED3 Status register
■ BCR9 Full-Duplex Control register
■ BCR18 Burst and Bus Control
register
■ BCR22 PCI Latency register
If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)
are cleared to ZERO, then the EEPROM read has
experienced a failure and the contents of the EEPROM
programmable BCR register will be set to default
H_RESET values. The content of the Address PROM
locations, however, will not be cleared.
Note that accesses to the Address PROM I/O locations
do not directly access the Address EEPROM itself. Instead, these accesses are routed to a set of shadow registers on board the PCnet-PCI II controller that are
loaded with a copy of the EEPROM contents during the
automatic read operation that immediately follows the
H_RESET operation.
■ I/O offsets 0h–Fh Address PROM locations
■ BCR2 Miscellaneous Configuration
register
■ BCR4 Link Status LED register
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EEPROM MAP
The automatic EEPROM read operation will access 18
EEPROM contents is shown below, beginning with the
byte that resides at the lowest EEPROM address:
words (i.e. 36 bytes) of the EEPROM. The format of the
Table 12. EEPROM Content
Word Byte Byte
Address Addr. Most Significant Byte Addr. Least Significant Byte
00h 01h Second byte of the ISO 8802-3 00h First byte of the ISO 8802-3
(Lowest (IEEE/ANSI 802.3) station physical (IEEE/ANSI 802.3) station physical
EEPROM address for this node address for this node, where first byte
address) refers to the first byte to appear on
the 802.3 medium
01h 03h Fourth byte of the node address 02h Third byte of the node address
02h 05h Sixth byte of the node address 04h Fifth byte of the node address
03h 07h Reserved Location: must be 00h 06h Reserved location must be 00h
04h 09h Hardware ID: must be 11h if compatibility 08h Reserved location must be 00h
to AMD drivers is desired
05h 0Bh User programmable space 0Ah User programmable space
06h 0Dh MSByte of two-byte checksum, which is the 0Ch LSByte of two-byte checksum, which
is the sum of bytes 00h–0Bh and bytes is the sum of bytes 00h–0Bh and bytes
0Eh and 0Fh 0Eh and 0Fh
07h 0Fh Must be ASCII W (57h) if compatibility to 0Eh Must be ASCII W (57h) if compatibility to
AMD driver software is desired AMD driver software is desired
08h 11h BCR4[15:8] (Link Status LED) 10h BCR4[7:0] (Link Status LED)
09h 13h BCR5[15:8] (LED1 Status) 12h BCR5[7:0] (LED1 Status)
0Ah 15h BCR18[15:8] (Burst and Bus Control) 14h BCR18[7:0] (Burst and Bus Control)
0Bh 17h BCR2[15:8] (Miscellaneous Configuration) 16h BCR2[7:0] (Miscellaneous Configuration)
0Ch 19h BCR6[15:8] (LED2 Status) 18h BCR6[7:0] (LED2 Status)
0Dh 1Bh BCR7[15:8] (LED3 Status) 1Ah BCR7[7:0] (LED3 Status)
0Eh 1Dh BCR9[15:8] (Full-Duplex Control) 1Ch BCR9[7:0] (Full-Duplex Control)
0Fh 1Fh Checksum adjust byte for the first 36 bytes 1Eh Reserved location must be 00h
of the EEPROM contents, checksum of the
first 36 bytes of the EEPROM should
total to FFh
10h 21h BCR22[15:8] (PCI Latency) 20h BCR22[7:0] (PCI Latency)
11h 23h Reserved location must be 00h 22h Reserved location must be 00h
AMD
Note that the first bit out of any word location in the
EEPROM is treated as the MSB of the register that is being programmed. For example, the first bit out of
EEPROM word location 08h will be written into BCR4,
bit 15, the second bit out of EEPROM word location 08h
will be written into BCR4, bit 14, etc.
There are two checksum locations within the EEPROM.
The first checksum will be used by AMD driver software
to verify that the ISO 8802-3 (IEEE/ANSI 802.3) station
address has not been corrupted. The value of bytes 0Ch
and 0Dh should match the sum of bytes 00h through
0Bh and 0Eh and 0Fh. The second checksum location
— byte 21h — is not a checksum total, but is, instead, a
checksum adjustment. The value of this byte should be
such that the total checksum for the entire 36 bytes of
EEPROM data equals the value FFh. The checksum
adjust byte is needed by the PCnet-PCI II controller in
order to verify that the EEPROM content has not
been corrupted.
LED Support
The PCnet-PCI II controller can support up to four LEDs.
LED outputs LNKST, LED1 and LED2 allow for direct
connection of an LED and its supporting pullup device.
LED output LED3 may require an additional buffer
between the PCnet-PCI II controller output pin and the
LED and its supporting pullup device.
Because the LED3 output is multiplexed with other
PCnet-PCI II controller functions, it may not always be
possible to connect an LED circuit directly to the LED3
pin. In applications that want to use the pin to drive an
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LED and also have an EEPROM, it might be necessary
to buffer the LED3 circuit from the EEPROM connection.
When an LED circuit is directly connected to the
EEDO/LED3/SRD pin, then it is not possible for most
Microwire EEPROM devices to sink enough I
maintain a valid low level on the EEDO input to the
PCnet-PCI II controller. In applications where an
EEPROM is not needed, the LED3 pin may be directly
connected to an LED circuit. The PCnet-PCI II controller
LED3 pin driver will be able to sink enough current to
properly drive the LED circuit.
P R E L I M I N A R Y
to indicate one or more of the following network status or
activities: Collision Status, Full-Duplex Link Status,
Half-Duplex Link Status, Jabber Status, Magic Packet
Status, Receive Match, Receive Polarity, Receive
OL to
Status and Transmit Status. The LED pins can be configured to operate in either open-drain mode (active low)
or in totem-pole mode (active high). The output can be
stretched to allow the human eye to recognize even
short events that last only several microseconds. After
H_RESET, the four LED outputs are configured in the
following manner:
Each LED can be programmed through a BCR register
Table 13. LED Default Configuration
LED Output Indication Driver Mode Pulse Stretch
LNKST Link Status Open Drain – Active Low Enabled
LED1 Receive Status Open Drain – Active Low Enabled
LED2 Receive Polarity Open Drain – Active Low Enabled
LED3 Transmit Status Open Drain – Active Low Enabled
For each LED register, each of the status signals is
ANDed with its enable signal, and these signals are all
ORed together to form a combined status signal. Each
LED pins combined status signal can be programmed to
run to a pulse stretcher, which consists of a 3-bit shift
register clocked at 38 Hz (26 ms). The data input of each
shift register is normally at logic 0. The OR gate output
for each LED register asynchronously sets all three bits
of its shift register when the output becomes asserted.
The inverted output of each shift register is used to control an LED pin. Thus the pulse stretcher provides 2–3
clocks of stretched LED output, or 52 ms to 78 ms.
COL
COLE
FDLS
FDLSE
JAB
JABE
LNKST
LNKSTE
MFS
MFSE
RCV
RCVE
RCVM
RCVME
RXPOL
RXPOLE
XMT
XMTE
To
Pulse
Stretch
19436A-44
Figure 41. LED Control Logic
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Power Savings Modes
The PCnet-PCI II controller supports two hardware
power savings modes. Both are entered by driving the
SLEEP pin LOW.
The power down mode that yields the most power savings is called coma mode. In coma mode, the entire
device is shut down. All inputs are ignored except the
SLEEP pin itself. Coma mode is enabled when AWAKE
(BCR2, bit 2) is at its default value of ZERO and SLEEP
is asserted.
The second power saving mode is called snooze mode.
In snooze mode, enabled by setting AWAKE to ONE
and driving the SLEEP pin LOW, the T-MAU receive circuitry will remain active even while the SLEEP pin is
driven LOW. The LNKST output is the only one of the
LED pins that continues to function. All other sections of
the device are shut down. The LNKSTE bit must be set
in BCR4 to enable indication of a good 10BASE-T link if
there are link beat pulses or valid frames present. This
LNKST pin can be used to drive an LED and/or external
hardware that directly controls the SLEEP pin of the
PCnet-PCI II controller. This configuration effectively
wakes the system when there is any activity on the
10BASE-T link. Snooze mode can be used only if the
T-MAU is the selected network port. Link beat pulses
are not transmitted during snooze mode.
The SLEEP pin must not be asserted while the PCnetPCI II controller is requesting the bus or while a slave or
bus master cycle is in progress. A recommended
method is to set the PCnet-PCI II controller into
suspend
prior to asserting the SLEEP pin. Another recommended method is to
STOP bit in CSR0 to ONE prior to asserting the
SLEEP pin.
Before the sleep mode is invoked, the PCnet-PCI II
controller will perform an internal S_RESET. This
S_RESET operation will not affect the values of the BCR
registers or the PCI configuration space. S_RESET terminates all network activity abruptly. The host can use
the suspend mode (SPND, CSR5, bit 0) to terminate all
network activity in an orderly sequence before issuing
an S_RESET.
When coming out of the sleep mode, the PCnet-PCI II
controller can be programmed to generate an interrupt
and inform the driver about the wake-up. The
PCnet-PCI II controller will set SLPINT (CSR5, bit 9),
mode by setting the SPND bit in CSR5 to ONE
stop
the device by setting the
AMD
when coming out of the sleep mode. INTA will be
asserted, when the enable bit SLPINTE (CSR5, bit 8) is
set to ONE. Note that the assertion of INTA due to
SLPINT is not dependent on the main interrupt enable
bit INEA (CSR0, bit 6), which will be cleared by the reset
going into the sleep mode.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the assertion of SLEEP until three clock cycles after the completion of a hardware reset operation.
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board level continuity test and diagnostics. All digital input, output and input/output pins are
tested. Analog pins, including the AUI differential driver
(DO±) and receivers (DI±, CI±), and the crystal input
(XTAL1/XTAL2) pins, are not tested. The T-MAU drivers
TXD±, TXP± and receiver RXD± are also not tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the
PCnet-PCI II controller.
Boundary Scan Circuit
The boundary scan test circuit requires four pins (TCK,
TMS, TDI and TDO), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an instruction register, a data register array, and a power-on
reset circuit. Internal pull-up resistors are provided for
the TDI, TCK, and TMS pins. The boundary scan circuit
remains active during Sleep mode.
TAP Finite State Machine
The TAP engine is a 16-state finite state machine
(FSM), driven by the Test Clock (TCK) and the Test
Mode Select (TMS) pins. An independent power-on
reset circuit is provided to ensure the FSM is in the
TEST_LOGIC_RESET state at power-up. The FSM
is also reset when TMS and TDI are high for five
TCK periods.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP and
SETBYP) are provided to further ease board-level testing. All unused instruction codes are reserved. See the
following table for a summary of supported instructions.
97Am79C970A
AMD
P R E L I M I N A R Y
Table 14. IEEE 1149.1 Supported Instruction Summary
Instruction Name Instruction Code Description Mode Selected Data Register
EXTEST 0000 External Test Test BSR
IDCODE 0001 ID Code Inspection Normal ID REG
SAMPLE 0010 Sample Boundary Normal BSR
TRIBYP 0011 Force Float Normal Bypass
SETBYP 0100 Control Boundary To 1/0 Test Bypass
BYPASS 1111 Bypass Scan Normal Bypass
Instruction Register and Decoding Logic
After the TAP FSM is reset, the IDCODE instruction is
always invoked. The decoding logic gives signals to
control the data flow in the Data registers according to
Other Data Registers
1. Bypass Register (1 bit)
2. Device ID register (32 bits)
the current instruction.
Table 16. Device ID Register
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two
stages. A flip-flop and a latch are used for the Serial Shift
Stage and the Parallel Output Stage, respectively.
There are four possible operation modes in the
BSR cell:
Table 15. Boundary Scan Register Mode
Bits 31–28 Version
Bits 27–12 Part Number (0010 0100 0011 XXXX)
Bits 11–1 Manufacturer ID. The 11 bit
manufacturer ID cod for AMD is
00000000001 in accordance with
JEDEC publication 106-A.
Bit 0 Always a logic 1
Of Operation
Note that the content of the Device ID register is the
1 Capture
2 Shift
3 Update
4 System Function
same as the content of CSR88.
98
Am79C970A
P R E L I M I N A R Y
NAND Tree Testing
The PCnet-PCI II controller provides a NAND tree test
mode to allow checking connectivity to the device on a
printed circuit board. The NAND tree is built on all PCI
bus signals.
VDD
RST (pin 120)
INTA (pin 117)
CLK (pin 121)
AMD
NAND tree testing is enabled by asserting RST. All PCI
bus signals will become inputs on the assertion of RST.
The result of the NAND tree test can be observed on the
NOUT pin.
PCnet-PCI II
Core
VDD
AD0 (pin 57)
Figure 42. NAND Tree Circuitry
B
A
MUX
S
O
NOUT
(pin 62)
19436A-45
99Am79C970A
AMD
Pin 120 (RST) is the first input to the NAND tree. Pin 117
(INTA) is the second input to the NAND tree, followed by
pin 121 (CLK). All other PCI bus signals follow, counter-
P R E L I M I N A R Y
NC and all power supply pins are not part of the NAND
tree. The table below shows the complete list of pins
connected to the NAND tree.
clockwise, with pin 57 (AD0) being the last. Pins labeled
Table 17. NAND Tree Pin Sequence
NAND NAND NAND
Tree Tree Tree
Input No. Pin No. Name Input No. Pin No. Name Input No. Pin No. Name
1 120 RST 18 15 AD21 35 36 AD15
2 117 INTA 19 16 AD20 36 38 AD14
3 121 CLK 20 18 AD19 37 39 AD13
4 123 GNT 21 19 AD18 38 40 AD12
5 126 REQ 22 21 AD17 39 41 AD11
6 128 AD31 23 22 AD16 40 42 AD10
7 129 AD30 24 23 C/BE2 41 44 AD9
8 131 AD29 25 24 FRAME 42 45 AD8
9 132 AD28 26 25 IRDY 43 47 C/BE0
10 2 AD27 27 26 TRDY 44 48 AD7
11 3 AD26 28 27 DEVSEL 45 49 AD6
12 5 AD25 29 28 STOP 46 51 AD5
13 6 AD24 30 29 LOCK 47 52 AD4
14 7 C/BE331 31PERR 48 53 AD3
15 10 IDSEL 32 32 SERR 49 54 AD2
16 12 AD23 33 34 PAR 50 56 AD1
17 13 AD22 34 35 C/BE1 51 57 AD0
RST must be asserted low to start a NAND tree test sequence. Initially, all NAND tree inputs except RST
should be driven high. This will result in a high output at
the NOUT pin. If the NAND tree inputs are driven from
high to low in the same order as they are connected to
build the NAND tree, NOUT will toggle every time an additional input is driven low. NOUT will change to low,
when INTA is driven low and all other NAND tree inputs
stay high. NOUT will toggle back to high, when CLK is
additionally driven low. The square wave will continue
until all NAND tree inputs are driven low. NOUT will be
high, when all NAND tree inputs are driven low.
Note, that some of the pins connected to the NAND tree
are outputs in normal mode of operation. They must not
be driven from an external source until the PCnet-PCI II
controller is configured for NAND tree testing.
100
Am79C970A
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