Datasheet AM79C873KCW Datasheet (AMD Advanced Micro Devices)

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PRELIMINARY

Am79C873

NetPHY™ -1
10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support

DISTINCTIVE CHARACTERISTICS

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100BASE-FX direct interface to industry
standard electrical/optical transceivers

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10/100BASE-TX physical-layer, single-chip
transceiver

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Compliant with the IEEE 802.3u 100BASE-TX
standard

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Compliant with the ANSI X3T12 TP-PMD 1995
standard

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Compliant with the IEEE 802.3u Auto­Negotiation protocol for automatic link type
selection

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Supports the MII with serial management
interface

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Supports Full Duplex operation for 10 Mbps and
100 Mbps

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High performance 100 Mbps clock generator
and data recovery circuitry

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Adaptive equalization circuitry for 100 Mbps
receiver

Controlled output edge rates in 100 Mbps
Supports a 10BASE-T interface without the

need for an external filter
Provides Loopback mode for system

diagnostics
Includes flexible LED configuration capability
Digital clock recovery circuit using advanced

digital algorithm to reduce jitter
Low-power, high-performance CMOS process
Available in a 100-pin PQFP package

GENERAL DESCRIPTION

The NetPHY-1 device is a physical-layer, single-chip,
low-power transceiver for 100BASE-TX, 100BASE-FX,
and 10BASE-T operations. On the media side, it pro­vides a direct interface to Fiber Media for 100BASE-FX
Fast Ethernet, Unshielded Twisted Pair Category 5
Cable (UTP5) for 100BASE-TX Fast Ethernet, or
UTP5/UTP3 Cable for 10BASE-T Ethernet. Through
the IEEE 802.3u Media Independent Interface (MII),
the NetPHY-1 device connects to the Medium Access
Control (MAC) layer, ensuring a high interoperability
among products from different vendors.

The NetPHY-1 device uses a low-power, high-perfor­mance CMOS process. It contains the entire physical

layer functions of 100BASE-FX and 100BASE-TX as
defined by the IEEE 802.3u standard, including the
Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), 100BASE-TX Twisted Pair Physical
Medium Dependent (TP-PMD) sublayer, and a
10BASE-T Encoder/Decoder (ENDEC). The NetPHY-1
device provides strong support for the Auto-Negotiation
function utilizing automatic media speed and protocol
selection. The NetPHY-1 device incorporates an inter­nal wave-shaping filter to control rise/fall time, eliminat­ing the need for external filtering on the 10/100
Mbps signals.

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 22164 Rev: AAmendment/+2
Issue Date: February 1999

BLOCK DIAGRAM

PRELIMINARY

MII

Signals

MII

Interface/

Control

4B/5B

Encoder

4B/5B

Decoder

Scrambler

Alignment

Register

Code­group

25M OSCI

TX CGM

Parallel

to Serial

Descrambler

Collision
Detection

NRZ

NRZI

25M CLK

Digital

Logic

Carrier

to

Serial to

Parallel

Sense

NRZI to

MLT-3

125M CLK

LED1-4

LED

Driver

NRZI to

NRZ

Auto-

Negotiation

MLT-3

Driver

Rise/Fall

Time

CTL

RX

CRM

10BASE-T

Module

PECL
Driver

MLT-3 to

NRZI

Receiver

RX
TX

PECL

Adaptive

EQ

FXTD±

100TXD±

RXI±

FXRD±
FXSD+

RXI±
10TXD±

22164A-1

2 Am79C873

CONNECTION DIAGRAM

AV

cc
FXSD­FXSD+

FXRD-

FXRD+

AGND

AV
AV

RXI-

RXI+
AGND
AGND

10TXO-

10TXO+

AV

AV
AGND
AGND

FXTD-

FXTD+

AV

AV
AGND
AGND

100TXO-

100TXO+

AV

AV

OSCI/X1

1
2

3
4
5
6
7

cc

8

cc

9
10
11
12
13
14
15

cc

16

cc

17
18

19
20
21

cc

22

cc

23
24
25
26
27

cc

28

cc

29
30

X2

AGND

100

31

AGND

99

32

PRELIMINARY

OPMODE1

OPMODE2

OPMODE3

RPTR/NODE

BPALIGN

BP4B5B

BPSCR

10BTSER

91

92

93

94

95

96

97

98

Am79C873/KC

NetPHY-1

39

38

37

36

35

34

33

OPMODE0

PHYAD3

PHYAD4

88

89

90

43

424041

44

DV

87

cc

DGND

86

45

PHYAD2

PHYAD1

84

85

47

46

TESTMODE

PHYAD0

82

83

49

48

RESET

81

80
79

78
77

76
75
74

73
72

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

RX_EN
RX_ER/RXD4
RX_DV
COL
CRS
RX_CLK
DV

cc
DGND
RXD0

RXD1
RXD2
RXD3
DV

cc
DGND
MDIO

MDC
TX_CLK
TX_EN
DV

cc
DGND

TXD0
TXD1
TXD2
TXD3
TX_ER/TXD4
TXLED
RXLED
LINKLED
DGND
COLLED

AGND

cc

AV

OSC/XTL

AGND

BGRET

BGREF

DGND

DGND

DGND

cc

DV

UTP

TRIDRV

SPEED10

RX_LOCK

NC

DGND

CLK25M

LINKSTS

cc

DV

FDXLED

Am79C873 3

22164A-2

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD standard products are available in se ver al packages and operating ranges . The order number (V alid Combination) is f ormed
by a combination of the elements below.

Am79C873

Am79C873

KC\W

Valid Combinations

KC\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0˚C to +70˚C)

P ACKA GE TYPE

K = Plastic Quad Flat Pack (PQR100)

SPEED OPTION

Not Applicable

DEVICE NUMBER/DESCRIPTION

Am79C873
NetPHY-1™ 10/100 Mbps Ethernet Physical Layer
Single-Chip Transceiver with 100BASE-FX Support

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

4 Am79C873

PRELIMINARY

RELATED AMD PRODUCTS

Part No. Description

Controllers

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE™)

Integrated Controllers

Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus
Am79C965A PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses
Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus
Am79C971 PCnet-FAST Single-Chip Full Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
Am79C972 PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
Am79C973/

Am79C975
Am79C978 PCnet-Home Single-chip 1/10 Mbps PCI Home networking Controller

Physical Layer Devices (Single-Port)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD)
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Physical Layer Devices (Multi-Port)

Am79C871 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™)
Am79C988A Quad Integrated Ethernet Transceiver (QuIET™)
Am79C989 Quad Ethernet Switching Transceiver (QuEST™)

Integrated Repeater/Hub Devices

Am79C981 Integrated Multiport Repeater Plus (IMR+)
Am79C982 Basic Integrated Multiport Repeater (bIMR)
Am79C983 Integrated Multiport Repeater 2 (IMR2™)
Am79C984A Enhanced Integrated Multiport Repeater (eIMR™)

PCnet-Fast III Single-chip 10/100 Mbps PCI Ethernet Controller With Integrated PHY

Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™)
Am79C987 Hardware Implemented Management Information Base (HIMIB™)

Am79C873 5

PRELIMINARY

CONTENTS

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MII Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Device Configuration/Control/Status Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

PHY Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MII Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

100BASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

100BASE Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4B5B Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

NRZ-to-NRZI Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PECL Driver For 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MLT-3 Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MLT-3 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

100BASE Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

100BASE-TX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

100BASE-FX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Adaptive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PECL Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MLT-3-to-NRZI Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

NRZI-to-NRZ Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Serial-to-Parallel Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Code Group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4B5B Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10BASE-T Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Collision Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MII Serial Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Key to Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Basic Mode Control Register (BMCR) - Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Basic Mode Status Register (BMSR) - Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PHY ID Identifier Register 1 (PHYIDR1) - Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PHY Identifier Register 2 (PHYIDR2) - Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Auto-Negotiation Advertisement Register(ANAR) - Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register 5 . . . . . . . . . . . . . . . . . . . . 25

Auto-Negotiation Expansion Register (ANER) - Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AMD Specified Configuration Register (DSCR) - Register 16. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AMD Specified Configuration and Status Register (DSCSR) - Register 17. . . . . . . . . . . . . . . . . 29

10BASE-T Configuration/Status (10BTCSRSCR) - Register 18 . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Am79C873

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

MII 100BASE-TX Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

MII 100BASE-TX Transmit Timing Parameters (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . 34

MII 100BASE-TX Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

MII-100BASE-TX Receive Timing Parameter (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . 35

Auto-Negotiation and Fast Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Auto-Negotiation and Fast Link Pulse Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MII 10BASE-T Nibble Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MII-10BASE-T Nibble Transmit Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MII 10BASE-T Receive Nibble Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

MII-10BASE-T Receive Nibble Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10BASE-T SQE (Heartbeat) Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10BASE-T Jab and Unjab Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

MDIO Timing when OUTPUT by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MDIO Timing when OUTPUT by NetPHY-1 Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MII Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MAGNETICS SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

CRYSTAL SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

NETPHY-1 MII EXAMPLE SCHEMATIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Am79C873 7

PRELIMINARY

PIN DESCRIPTIONS
MII Interface
TX_ER/TXD4

Transmit Error Input

In 100 Mbps mode, if this signal is asserted high and
TX_EN is active, the HALT symbol is substituted for the
actual data nibble. In 10 Mbps mode, this input
is ignored.

In bypass modes (BP4B5B or BPALIGN), TX_ER be­comes the TXD4 pin, the fifth TXD data bit.

TXD[3:0]

Transmit Data Input

These are the transmit data input pins for nibble
data from the MII in 100 Mbps or 10 Mbps nibble
mode (25 MHz
Mbps nibble mode).

In 10 Mbps serial mode, the TXD0 pin is used as the
serial data input pin. TXD[3:1] are ignored.

for 100 Mbps mode, 2.5 MHz for 10

TX_EN

Transmit Enable Input

Active high input indicates the presence of valid nib­ble data on TXD[3:0] for both 100 Mbps or 10 Mbps
nibble mode.

RXD[3:0]

Receive Data Output/Z

Nibble wide receive data (synchronous to RX_CLK - 25
MHz for 100BASE-TX mode, 2.5 MHz for 10BASE-T
nibble mode). Data is dr iven on the falling edge of
RX_CLK.

In 10 Mbps serial mode, the RXD0 pin is used as the
data output pin. RXD[3:1] are ignored.

1

RX_CLK

Receive Clock Output/Z

Provides the recovered receive clock for different
modes of operation:

- 25 MHz nibble clock in 100 Mbps mode

- 2.5 MHz nibble clock in 10 Mbps nibble mode

- 10 MHz receive clock in 10 Mbps serial mode

1

CRS

Carrier Sense Output/Z

This pin is asserted high to indicate the presence of
carrier due to receive or transmit activities in 10BASE­T or 100BASE-TX Half Duplex modes.

In Repeater, when Full Duplex or Loopback mode is a
logic 1, it indicates the presence of carrier due only to
receive activity.

1

In 10 Mbps serial mode, active high indicates the pres­ence of valid 10 Mbps data on TXD0.

TX_CLK

Transmit Clock Output/Z

This pin provides the transmit clock output from the
NetPHY-1 deviceas follows:

- 25 MHz nibble transmit clock derived from trans­mit Phase Locked Loop (TX PLL) in 100BASE-TX
mode

- 2.5 MHz transmit clock in 10BASE-T nibble mode

- 10 MHz transmit clock in 10BASE-T serial mode

1

MDC

Management Data Clock Input

This pin is the synchronous clock to the MDIO manage­ment data input/output serial interface which is asyn­chronous to transmit and receive clocks . The maxim um
clock rate is 2.5 MHz.

MDIO

Management Data I/O Input/Output

This pin is the bidirectional management instruction/
data signal that may be driven by the station manage­ment entity or the PHY. This pin requires a 1.5 K Ω pull­up resistor.

COL

Collision Detect Output/Z

This pin is asserted high to indicate detection of colli­sion conditions in 10 Mbps and 100 Mbps Half Duplex­modes. In 10BASE-T Half Duplex mode with Heartbeat
set active (bit 13, register 18h), it is also asserted for a
duration of approximately 1ms at the end of transmis­sion to indicate heartbeat. In Full Duplex mode, this
signal is always logic 0. There is no heartbeat function
in Full Duplex mode.

1

RX_DV

Receive Data Valid Output/Z

This pin is asserted high to indicate that valid data is
present on RXD[3:0].

1

RX_ER/RXD4

Receive Error Output/Z

This pin is asserted high to indicate that an invalid sym­bol has been detected inside a received packet in 100
Mbps mode.

In a bypass mode (BP4B5B or BPALIGN modes),
RX_ER becomes RXD4, the fifth RXD data bit of the
5B symbols.

1

1. Goes to high impedance.

8 Am79C873

PRELIMINARY

RX_EN

Receive Enable Input

This pin is active high enabled for receive signals
RXD[3:0], RX_CLK, RX_D V and RX_ER. A low on this
input tri-states these output pins. For normal operation
in a NODE application, this pin should be pulled high.

Media Interface
RXI±

100/10 Mbps-TX/T Twisted Pair Differential Input
Pair Input

These pins are the differential receive input for
10BASE-T and 100BASE-TX. They are capable of re­ceiving 100BASE-TX MLT-3 or 10BASE-T Manchester
encoded data.

FXRD±

100BASE-FX PECL Differential Input Pair Input

These pins are the differential receive input for
100BASE-FX. They are capable of receiving
100BASE-FX.

FXSD±

100BASE-FX PECL Signal Detect Input

These input signals from the FX-PMD transceiver indi­cate detection of a receive signal from the Fiber Media.

function will change to indicate the Polarity status for 10
Mbps operation. If polarity is inv erted, the POLLED will
go ON.

COLLED

Collision LED Output

This pin indicates the presence of collision activity for
10 Mbps and 100 Mbps operation. This LED has no
meaning for 10 Mbps or 100 Mbps Full Duplex opera­tion (Active low).

LINKLED

Link LED Output

This pin indicates Good Link status for 10 Mbps and
100 Mbps operation (Active low). It functions as the
TRAFFIC LED when bit 5 of register 16 is set to 1. In
TRAFFIC LED mode, it is always ON when the link is
OK. The TRAFFIC LED flashes when transmitting or
receiving.

RXLED

Receive LED Output Drain

This pin indicates the presence of receive activity for 10
Mbps and 100 Mbps operation (Active low). The Net­PHY-1 device incorporates a “monostable” function on
the RXLED output. This ensures that even minimal re­ceive activity will generate an adequate LED ON time.

(TRAFFIC LED)

10TXO±

10BASE-T Differential Output Pair Output

This output pair provides controlled rise and fall times
designed to filter the transmitters output.

100TXO±

100BASE-TX Twisted Pair Differential Output Pair

Output

This output pair drives MLT-3 encoded data to the
100 M twisted pair cable and provides controlled rise
and fall times designed to filter the transmitters output,
reducing any associated EMI.

FXTD±

100BASE-FX PECL Differential Output PairOutput

These pins are the differential transmit output for
100BASE-FX. They are capable of transmitting
100BASE-FX

LED Interface

These outputs can directly drive LEDs or provide status
information to a network management device.

FDXLED

Polarity/Full Duplex LED Output

This pin indicates Full Duplex mode status for 100
Mbps and 10 Mbps operation (Active low). If bit 4 of
Register 16 (FDXLED_MODE) is set, the FDXLED pin

(POLLED)

TXLED

Transmit LED Output Drain

This pin indicates the presence of transmit activity for 10
Mbps and 100 Mbps operation (Active low). The Net­PHY-1 device incorporates a “monostable” function on
the TXLED output. This ensures that even minimal
transmit activity will generate an adequate LED ON time.

Device Configuration/Control/Status
Interface

UTP

UTP Cable Indication Output

This pin is the UTP Cable Indication. When UTP=1, it
indicates that the UTP cable is being used.

SPEED10

Speed 10 Mbps Output

When set high, this bit indicates a 10 Mbps operation,
when set low 100 Mbps operation. This pin can drive
a low current LED to indicate that 100 Mbps operation
is selected.

RX_LOCK

Lock for Clock/Data Recovery PLL Output

When this pin is high, it indicates that the receiver re­covery PLL logic has locked to the input data stream.

Am79C873 9

PRELIMINARY

LNKSTS

Link Status Register Bit Output

This pin reflects the status of bit 2 register 1.

OPMODE0-OPMODE3

OPMODE0-OPMODE3 Input

These pins are used to control the forced or advertised
operating mode of the NetPHY-1 device (see table be­low). The v alue is latched into the NetPHY-1 device reg­isters at power-up/rese..

OP-

MODE3

0000

0001

0010

0011

0100

OP-

MODE2

OP-

MODE1

OP-

MODE0 Function

Auto-Negotiation
enable with all
capabilities with
Flow Control

Auto-Negotiation
enable without all
capabilities without
Flow Control

Auto-Negotiation
100TX FDX with
Flow Control only

Auto-Negotiation
100TX FDX/HDX
without Flow
Control

Auto-Negotiation
10TP FDX with
Flow Control only

TPR/NODE

R

Repeater/Node Mode Input

When set high, this bit selects REPEA TER mode; when
set low, it selects NODE. In REPEATER mode or
NODE mode with Full Duplex configured, the Carrier
Sense (CRS) output from the NetPHY-1 device will be
asserted only during receive activity . In NODE mode or
a mode not configured for Full Duplex operation, CRS
will be asserted during receive or transmit activity. At
power-up/reset, the value on this pin is latched into
Register 16, bit 11.

BPALIGN

Bypass Alignment Input

This pin allows 100 Mbps transmit and receive data
streams to bypass all of the transmit and receive oper­ations when set high. At power-up/reset, the value on
this pin is latched into bit Register 16, bit 13.

BP4B5B

Bypass 4B5B Encoder/Decoder Input

This pin allows 100 Mbps transmit and receive data
streams to bypass the 4B to 5B encoder and 5B to 4B
decoder circuits when set high. At power-up/reset, the

value on this pin is latched into Register 16, bit 15.

BPSCR

Bypass Scrambler/Descrambler Input

This pin allows 100 Mbps transmit and receive data
streams to bypass the scrambler and descrambler cir­cuits when set high. At power-up/reset, the value on
this pin is latched into Register 16, bit 14.

Auto-Negotiation

0101

0110

0111

1000

1001

1010

1011

1111

10TX FDX/HDX
without Flow
Control

Manual select
100TX FDX

Manual select
100TX HDX

Manual select
10TX FDX

Manual select
10TX HDX

Manual select
100FX FDX

Manual select
100FX HDX

Auto-Negotiation
10/100TX. HDX
only

10BTSER

Serial/Nibble Select Input

10 Mbps Serial Operation:
When set high, this input selects a serial data transfer

mode. Manchester encoded transmit and receive data
is exchanged serially with a 10 MHz clock rate on the
least significant bits of the nibble-wide MII data buses,
pin TXD[0] and RXD[0] respectively. This mode is in­tended for use with the NetPHY-1 device connected to
a device (MAC or Repeater) that has a 10 Mbps serial
interface. Serial operation is not supported in 100 Mbps
mode. For 100 Mbps, this input is ignored.

10 and 100 Mbps Nibble Operation:
When set low, this input selects the MII compliant nib-

ble data transfer mode . Transmit and receive data is e x­changed in nibbles on the TXD[3:0] and RXD[3:0] pins
respectively.

At power-up/reset, the value on this pin is latched into
Register 18, bit 10.

10 Am79C873

PRELIMINARY

■

Clock Interface
OSCI/X1

Crystal or Oscillator Input Input

This pin should be connected to a 25 MHz (±50 ppm)
crystal if OSC/XTL=0 or a 25 MHz (±50 ppm) external
TTL oscillator input, if OSC/XTLB=1.

X2

Crystal Oscillator Output Output

An external 25 MHz (±50 ppm) crystal should be con­nected to this pin if OSC/XTL=0, or left unconnected if
OSC/XTL=1.

OSC/XTL

Crystal or Oscillator Selector Pin Output

OSC/XTL=0: An external 25 MHz (±50ppm) crystal
should be connected to X1 and X2 pins.

OSC/XTL=1 : An external 25 MHz (±50ppm) oscilla­tor should be connected to X1 and X2 should be left
unconnected.

CLK25M

25 MHz Clock Output Output/Z

This clock is derived directly from the crystal circuit.

PHY Address Interface

The PHYAD[4:0] pins provide up to 32 unique PHY
addresses. An address selection of all zeros (00000)
will result in a PHY isolation condition. See the isolate
bit description in the BMCR, address 00.

PHYAD0

PHY Address 0 Input

This pin provides PHY address bit 0 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 8 during power up/reset.

PHYAD4

PHY Address 4 Input

This pin provides PHY address bit 4 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 4 during power up/reset.

Miscellaneous
NC

No Connect

These pins are to be left unconnected (floating).

BGREF

Bandgap V oltage Reference Input

Connect a 6.01K Ω, 1% resistor between this pin and
the BGRET pin to provide an accurate current refer­ence for the NetPHY-1 device.

BGRET

Bandgap Voltage Reference Return Input

This is the return pin for 6.01K Ω resistor connection.

TRIDRV

Tri-State Digital Output Input

When set high, all digital output pins are set to a high
impedance state, and I/O pins, go to input mode.

RESET

Reset Input

This pin is the active low input that initializes the NetPHY­1 device. It should remain low for 30 ms after VCC has
stabilized at 5 Vdc (nominal) before it transitions high.

TESTMODE

Test Mode Control Pin Input

TESTMODE=0: Normal operating mode.
TESTMODE=1: Enable test mode.

PHYAD1

PHY Address 1 Input

This pin provides PHY address bit 1 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 7 during power up/reset.

PHYAD2

PHY Address 2 Input

This pin provides PHY address bit 2 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 6 during power up/reset.

PHYAD3

PHY Address 3 Input

This pin provides PHY address bit 3 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 5 during power up/reset.

Am79C873 11

Power and Ground Pins

The power (VCC) and ground (GND) pins of the Net­PHY-1 device are grouped in pairs of two categories ­Digital Circuitry Power/Ground Pairs and Analog Cir­cuitry Power/Ground Pair.

DGND

Digital Logic Ground Power

These pins are the digital supply pairs.

DVCC

Digital Logic Power Supply Power

These pins are the digital supply pairs.

AGND

Analog Circuit Ground Power

These pins are the analog circuit supply pairs.

AVCC

Analog Circuit Power Supply Power

These pins are the analog circuit supply pairs.

PRELIMINARY

FUNCTIONAL DESCRIPTION

The NetPHY-1 Fast Ethernet single-chip transceiver,
provides the functionality as specified in the IEEE

802.3u standard, integrates complete 100BASE-FX,
100BASE-TX modules and a complete 10BASE-T
module. The NetPHY-1 device provides a Media Inde­pendent Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).

MII Interface

Carrier

Sense

The NetPHY-1 device performs all Physical Coding
Sublayer (PCS), Physical Media Access (PMA),
Twisted Pair Physical Medium Dependent (TP-PMD)
sublayer, 10BASE-T Encoder/Decoder, and Twisted
Pair Media Access Unit (TPMAU) functions. Figure 1
shows the major functional blocks implemented in the
NetPHY-1 device.

100Base

Transmitter

100Base
Receiver

10Base-T

Tranceiver

Collision

Detection

Auto

Negotiation

MII Serial

Management

Interface

Figure 1. Functional Block Diagram

MII Interface

The purpose of the MII interface is to provide a simple,
easy to implement connection between the MAC Rec­onciliation layer and the PHY. The MII is designed to
make the differences between various media transpar­ent to the MAC sublayer.

The MII consists of a nibble wide receive data bus, a
nibble wide transmit data bus , and control signals to f a­cilitate data transfers between the PHY and the Recon­ciliation layer.

■ TXD (transmit data) is a nibble (4 bits) of data that
are driven by the reconciliation sublayer synchro­nously with respect to TX_CLK. For each TX_CLK
period which TX_EN is asserted, TXD (3:0) are ac­cepted for transmission by the PHY.

■ TX_CLK (transmit clock) output to the MAC recon­ciliation sublay er is a continuous clock that pro vides
the timing reference for the transfer of the TX_EN,
TXD, and TX_ER signals.

22164A-3

■ TX_EN (transmit enable) input from the MAC recon­ciliation sublay er to indicate nibbles are being pre­sented on the MII for transmission on the physical
medium. TX_ER (transmit coding error) transitions
synchronously with respect to TX_CLK. If TX_ER is
asserted for one or more clock periods, and TX_EN
is asserted, the PHY will emit one or more symbols
that are not part of the valid data delimiter set some­where in the frame being transmitted.

■ RXD (receive data) is a nibble (4 bits) of data that
are sampled by the reconciliation sublayer syn­chronously with respect to RX_CLK. For each
RX_CLK period which RX_DV is asserted, RXD
(3:0) are transferred from the PHY to the MAC
reconciliation sublayer.

■ RX_CLK (receive clock) output to the MA C reconcil­iation sublayer is a continuous clock that provides
the timing reference for the transfer of the RX_DV,
RXD, and RX_ER signals.

12 Am79C873

PRELIMINARY

■ RX_D V (receive data valid) input from the PHY to in­dicate the PHY is presenting recovered and de­coded nibbles to the MAC reconciliation sub lay er . To
interpret a receive frame correctly by the reconcilia­tion sublayer, RX_DV must encompass the frame
starting no later than the Star t-of-Frame delimiter
and excluding any End-Stream delimiter.

■ RX_ER (receive error) transitions synchronously
with respect to RX_CLK. RX_ER will be asserted

TXD

CRS

TXD

IDLE

SSD

J/K

Preamble SFD Data

Preamble

SFD

for 1 or more clock periods to indicate to
the reconciliation sublayer that an error was
detected somewhere in the frame being transmit­ted from the PHY to the reconciliation sublayer.

■ CRS (carrier sense) is asserted by the PHY when
either the transmit or receive medium is non-idle and
deasserted by the PHY when the transmit and receive
medium are idle. Figure 2 depicts the behavior of CRS
during 10BASE-T and 100BASE-TX transmission.

100Base-TX

Data

ESD

T/R

EFD

IDLE

CRS

Figure 2. Carrier Sense during 10BASE-T and 100BASE-TX Transmission

100BASE Operation

The 100BASE transmitter receives 4-bit nibble data
clocked in at 25 MHz at the MII and outputs a scram­bled 5-bit encoded MLT-3 signal to the media at 100
Mbps. The on-chip clock circuit converts the 25 MHz
clock into a 125 MHz clock for internal use.

The IEEE 802.3u specification defines the Media Inde­pendent Interface. The interface specification defines a
dedicated receive data bus and a dedicated transmit
data bus.

10Base-T

22164A-4

These two busses include various controls and signal
indications that facilitate data transfers between the
NetPHY-1 device and the Reconciliation layer.

100BASE T ransmit

The 100BASE transmitter consists of the functional
blocks shown in Figure 3. The 100BASE transmit sec­tion converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125 million symbols per sec­ond serial data stream.

Am79C873 13

PRELIMINARY

MII

Signals

MII

Interface/

Control

4B/5B

Encoder

Scrambler

25M OSCI

TX CGM

Parallel
to Serial

NRZ

to

NRZI

NRZI to

MLT-3

LED1-4#

LED

Driver

MLT-3

Driver

Rise/Fall

Time

CTL

10BASE-T

Module

PECL

Driver

RX
TX

FXTD±

100TXD±

RXI±
10TXD±

Register

Collision

Detection

Figure 3. 100BASE Transmitter Functional Block Diagram

The block diagram in Figure 3 provides an overview of
the functional blocks contained in the transmit section.
The transmitter section contains the following func­tional blocks:

■ 4B5B Encoder

■ Scrambler

■ Parallel-to-Serial Converter

■ NRZ-to-NRZI Converter

■ PECL Driver (For FX Operation)

■ NRZI to MLT-3 (For TX Operation)

■ MLT-3 Driver (For TX Operation)

4B5B Encoder

The 4B5B encoder converts 4-bit (4B) nibble data gen­erated by the MAC Reconciliation Layer into a 5-bit
(5B) code group for transmission (see Table 1). This
conversion is required f or control and pack et data to be

Carrier

Sense

Auto-

Negotiation

22164A-5

combined in code groups. The 4B5B encoder substi­tutes the first 8 bits of the MAC preamble with a J/K
code-group pair (11000 10001) upon transmit.

The 4B5B encoder continues to replace subsequent
4B preamble and data nibbles with corresponding 5B
code-groups. At the end of the transmit packet, upon
the deassertion of the Transmit Enable signal from the
MAC Reconciliation lay er , the 4B5B encoder injects the
T/R code-group pair (01101 00111) indicating end of
frame. After the T/R code-group pair , the 4B5B encoder
continuously injects IDLEs into the transmit data
stream until Transmit Enable is asserted and the next
transmit packet is detected.

The NetPHY-1 device includes a Bypass 4B5B conver­sion option within the 100BASE-TX transmitter for sup­port of applications like 100 Mbps repeaters which do
not require 4B5B conversion.

14 Am79C873

PRELIMINARY

Table 1. 4B5B Code Group

4B code

Symbol Meaning

0 Data 0 0000 11110
1 Data 1 0001 01001
2 Data 2 0010 10100
3 Data 3 0011 10101
4 Data 4 0100 01010
5 Data 5 0101 01011
6 Data 6 0110 01110
7 Data 7 0111 01111
8 Data 8 1000 10010

9 Data 9 1001 10011
A Data A 1010 10110
B Data B 1011 10111
C Data C 1100 11010
D Data D 1101 11011
E Data E 1110 11100

3210

5B Code

43210

the twisted pair cable in 100BASE-TX operation. By
scrambling the data, the total energy presented to the
cable is randomly distributed over a wide frequency
range. Without the scrambler, energy levels on the
cable could peak beyond FCC limitations at frequen­cies related to repeated 5B sequences like continuous
transmission of IDLE symbols. The scrambler output is
combined with the NRZ 5B data from the code-group
encoder via an XOR logic function. The result is a
scrambled data stream with sufficient randomization to
decrease radiated emissions at critical frequencies.
Since EMI is not a concern in a fiber application, the
scrambler is bypassed in 100BASE-FX.

Parallel-to-Serial Converter

The Parallel-to-Serial Converter receives parallel 5B
scrambled data from the scrambler and serializes it
(i.e., converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ-to-NRZI Encoder block

NRZ-to-NRZI Converter

After the transmit data stream has been scrambled and
serialized, the data must be NRZI encoded for compati­bility with the TP-PMD standard for 100BASE-TX trans­mission over Category-5 unshielded twisted pair cable.

F Data F 1111 11101

I Idle undefined 11111

J SFD (1) 0101 11000
K SFD (2) 0101 10001
T ESD (1) undefined 01101
R ESD (2) undefined 00111
H Error undefined 00100
V Invalid undefined 00000
V Invalid undefined 00001
V Invalid undefined 00010
V Invalid undefined 00011
V Invalid undefined 00101
V Invalid undefined 00110
V Invalid undefined 01000
V Invalid undefined 01100
V Invalid undefined 10000
V Invalid undefined 11001

Scrambler

The scrambler is required to control the radiated emis­sions (EMI) by spreading the transmit energy across
the frequency spectrum at the media connector and on

PECL Driver For 100BASE-FX

The PECL driver accepts NRZI coded data and converts
it to PECL signal levels f or transmission over fiber media.

The output pair is a differential pseudo ECL (PECL) in­terface designed to connect directly to a standard fiber
optic PMD. The differential driver for the FXTD± is cur­rent mode and is designed to drive resistive termination
in a complementary mode. The FXTD± pins are inca­pable of sourcing current, this implies that VOH must
be set by the ratios of the Thevenin termination resis­tors for each of the lines. RIOH is a pull-up resistor con­nected from the FXTD± output to VCC. RIOL is a pull­down resistor connected from the FXTD± output to
ground. RIOH and RIOL are electrically in parallel from
an AC standpoint. A target impedance of 50 Ω is
needed for the transmission line impedance. A value of
62 Ω for RIOH and a value of 300 Ω for RIOL will yield
a Thevenin equivalent characteristic impedance of

49.7 Ω and a VOH value of VCC-.88 volts, compatible
with PECL circuits. VOL is required to be VDD-1.81 or
greater. A sink current of 19 milli-amps (mA) would
achieve this through the output termination resistors.

MLT-3 Converter

The ML T-3 conv ersion is accomplished by converting the
data stream output from the NRZI encoder into two bi­nary data streams with alternately phased logic
one events .

Am79C873 15

PRELIMINARY

MLT-3 Driver

The two binary data streams created at the MLT -3 con­verter are fed to the twisted pair output driver which
converts these streams to current sources and alter­nately drives either side of the transmit transformer pri­mary winding resulting in a minimal current MLT-3
signal. Refer to Figure 4 for the block diagram of the
MLT-3 converter.

100BASE Receiver

The 100BASE receiver contains several function
blocks that conv ert the scrambled 125 Mbps serial data
to synchronous 4-bit nibble data that is then provided to
the MII.

The receive section contains the following functional
blocks:

D

Q
Q

CK

Binary plus

■ Signal Detect

■ Adaptive Equalization

■ MLT-3-to-Binary Decoder

■ Clock Recovery Module

■ NRZI -o-NRZ Decoder

■ Serial-to-Parallel Converter

■ Descrambler

■ Code Group Alignment

■ 4B5B Decoder

100BASE-TX Signal Detect

The signal detect function meets the specifications man­dated by the ANSI XT12 TP-PMD 100BASE-TX stan­dards for both voltage thresholds and timing parameters .

Binary In

Binary minus

Binary In

MLT-3

Figure 4. MLT-3 Converter Block Diagram

100BASE-FX Signal Detect

The NetPHY-1 device accepts signal detect information
on the FXSD pin at PECL signal levels from the FX
Optical Module.

Adaptive Equalization

When transmitting data at high speeds over copper
twisted pair cable, attenuation based on frequency be­comes a concern. In high speed twisted pair signaling,
the frequency content of the transmitted signal can
vary greatly during normal operation based on the ran­domness of the scrambled data stream. This variation

Common

Driver

MLT-3

22164A-6

in signal attenuation caused by frequency variations
must be compensated for to ensure the integrity of the
received data.

In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to
adapt to various cable lengths and cable types depend­ing on the installed environment. The selection of long
cable lengths for a given implementation, requires sig­nificant compensation which will be over-kill in a situa­tion that includes shorter, less attenuating cable
lengths. Conv ersely, the selection of short or intermedi­ate cable lengths requiring less compensation will

16 Am79C873

PRELIMINARY

cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization
must be adaptive to ensure proper conditioning of the
received signal independent of the cable length.

PECL Receiver

The PECL receiver accepts PECL signal-level data
from the FX Optical Module and presents it to the Clock
Recovery Module.

MLT-3-to-NRZI Decoder

The NetPHY-1 device decodes the MLT-3 information
from the Digital Adaptive Equalizer into NRZI data. The
relationship between NRZI and MLT-3 data is shown in
Figure 4.

Clock Recovery Module

The Clock Recovery Module accepts NRZI data from
the MLT-3-to-NRZI decoder or the PECL Receiver. The
Clock Recovery Module locks onto the data stream and
extracts the 125 MHz reference clock. The extracted
and synchronized clock and data are presented to the
NRZI-to-NRZ Decoder.

NRZI-to-NRZ Decoder

The transmit data stream is required to be NRZI en­coded in for compatibility with 100BASE transmission
over. This con version process must be reversed on the
receive end. The NRZI-to-NRZ decoder, receives the
NRZI data stream from the Clock Recovery Module
and converts it to a NRZ data stream to be presented
to the Serial to Parallel conversion block.

Serial-to-Parallel Converter

The Serial-to-Parallel Converter receives a serial data
stream from the NRZI-to-NRZ converter, and converts
the data stream to parallel data to be presented to the
descrambler.

Descrambler

Because of the scrambling process required to control
the radiated emissions of transmit data streams, the re­ceiver must descramble the receive data streams. The
descrambler receives scrambled parallel data streams
from the Serial to Parallel converter, descrambles the
data streams, and presents the data streams to the
Code Group alignment block.

Note: The scrambler is bypassed for 100BASE-FX
operation.

Code Group Alignment

The Code Group Alignment block receives unaligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned on
a fixed boundary.

4B5B Decoder

The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first two 5-bit code
groups received are the start-of-frame delimiter (J/K
symbols). The J/K symbol pair is stripped and two nib­bles of preamble pattern are substituted. The last two
code groups are the end-of-frame delimiter (T/R sym­bols).The T/R symbol pair is also stripped from the nib­ble presented to the Reconciliation layer.

10BASE-T Operation

The 10BASE-T transceiver is IEEE 802.3u compliant.
When the NetPHY-1 device is operating in 10BASE-T
mode, the coding scheme is Manchester. Data pro­cessed for transmit is presented to the MII interface in
nibble format, converted to a serial bit stream, then
Manchester encoded. When receiving, the Manchester
encoded bit stream is decoded and converted into nib­ble format for presentation to the MII interface.

Collision Detection

For Half Duplex oper ation, a collision is detected when
the transmit and receive channels are active simulta­neously. When a collision has been detected, it will be
reported by the COL signal on the MII interface. Colli­sion detection is disabled in Full Duplex operation.

Carrier Sense

Carrier Sense (CRS) is asserted in Half Duplex oper­ation during transmission or reception of data. During
Full Duplex mode, CRS is asserted only during
receive operations.

Auto-Negotiation

The objective of Auto-Negotiation is to pro vide a means
to exchange information between segment linked de­vices and to automatically configure both devices to
take maximum advantage of their abilities. It is impor­tant to note that Auto-Negotiation does not test the link
segment characteristics. The A uto-Negotiation function
provides a means for a device to advertise supported
modes of operation to a remote link partner, acknowl­edge the receipt and understanding of common modes
of operation, and to reject un-shared modes of opera­tion. This allows devices on both ends of a segment to
establish a link at the best common mode of operation.
If more than one common mode exists between the two
devices, a mechanism is provided to allow the devices
to resolve to a single mode of operation using a prede­termined priority resolution function.

Auto-Negotiation also provides a parallel detection
function for devices that do not support the Auto-Nego­tiation feature. During Parallel detection there is no ex­change of configuration information, instead, the
receive signal is examined. If it is discovered that the
signal matches a technology that the receiving device

Am79C873 17

PRELIMINARY

supports, a connection will be automatically estab­lished using that technology. This allows devices that
do not support Auto-Negotiation but support a common
mode of operation to establish a link.

MII Serial Management

The MII serial management interface consists of a data
interface, basic register set, and a serial management
interface to the register set. Through this interface it is
possible to control and configure multiple PHY devices ,
get status and error information, and determine the
type and capabilities of the attached PHY device(s).

The NetPHY-1 devices management functions corre­spond to MII specification for IEEE 802.3u-1995
(Clause 22) for registers 0 through 6 with vendor-spe­cific registers 16,17, and 18.

In read/write operation, the management data frame is
64-bits long and starts with 32 contiguous logic one bits

MDC

MDIO Read

32 "1"s

Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle

0 1 1 0 A4A3A0R4R3R0

Write

(preamble) synchronization clock cycles on MDC. The
Start of Frame Delimiter (SFD) is indicated by a <01>
pattern followed by the operation code (OP):<10> indi­cates Read operation and <01> indicates Write opera­tion. For read operation, a 2-bit tur naround (TA) filing
between Register Address field and Data field is pro­vided for MDIO to avoid contention. Following the turn­around time, 16-bit data is read from or written onto
management registers.

Serial Management Interface

The serial control interface uses a simple two-wired se­rial interface to obtain and control the status of the phys­ical layer through the MII interface. The serial control
interface consists of Management Data Clock (MDC),
and Management Data Input/Output (MDI/O) signals.

The MDIO pin is bidirectional and may be shared by up
to 32 devices.

D15 D14 D1 D0

0

Z

Read

MDC

MDIO Write

22164A-7

Figure 5. Management Interface - Read Frame Structure

A3 A0 R4 R3 R0

32 "1"s 0 1 10

Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle

A4

Write

D15 D14 D1 D0

01

22164A-8

Figure 6. Management Interface - Write Frame Structure

18 Am79C873

PRELIMINARY

Register Description

Register Address Register Name Description

0 BMCR Basic Mode Control Register
1 BMSR Basic Mode Status Register
2 PHYIDR1 PHY Identifier Register 1
3 PHYIDR2 PHY Identifier Register 2
4 ANAR Auto-Negotiation Advertisement Register
5 ANLPAR Auto-Negotiation Link Partner Ability Register

6 ANER Auto-Negotiation Expansion Register
16 DSCR AMD Specified Configuration Register
17 DSCSR AMD Specified Configuration/Status Register
18 10BTCSR 10BASE-T Configuration/Status Register

Others Reserved Reserved For Future Use-Do Not Read/Write To These Registers

Key to Default

In the register description that follows, the default col­umn takes the form:

<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset V alue>:

1 Bit set to logic one
0 Bit set to logic zero
X No default value

(Pin No.) Value latched in from pin number at reset

<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high

Am79C873 19

PRELIMINARY

Basic Mode Control Register (BMCR) ­Register 0

Bit Bit Name Default Description

Reset:

1=Software reset
0=Normal operation

0.15 Reset 0, RW/SC

0.14 Loopback 0, RW

0.13 Speed Selection 1, RW

When set this bit configures the PHY status and control registers to their
default states. This bit will return a value of one until the reset process is
complete.

Loopback:
Loopback control register
1=Loopback enabled
0=Normal operation
When in 100M operation is selected, setting this bit will cause the

descrambler to lose synchronization. A 720ms “dead time” will occur
before any valid data appears at the MII receive outputs.

Speed Select:
1=100 Mbps
0=10 Mbps
Link speed may be selected either by this bit or by Auto-Negotiation if bit

12 of this register is set. When Auto-Negotiation is enabled, this bit will
return Auto-Negotiation link speed.

0.12

0.11 Power Down 0, RW

0.10 Isolate

Auto-Negotiation

Enable

1, RW

(PHYAD=

00000),
RW

Auto-Negotiation Enable:
1= Auto-Negotiation enabled:
0= Auto-Negotiation disabled:
When auto-Negotiation is enabled bits 8 and 13 will contain the Auto-

Negotiation results. When Auto-Negotiation is disabled bits 8 and 13 will
determine the duplex mode and link speed.

Power Down:
1=Power Down
0=Normal Operation
Setting this bit will power down the NetPHY-1 device with the exception of

the crystal oscillator circuit.

Isolate:
1= Isolate
0= Normal Operation
When this bit is set the data path will be isolated from the MII interface.

TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL and CRS will be
placed in a high impedance state. The management interface is not
effected by this bit. When the PHY Address is set to 00000 the isolate bit
will be set upon power-up/reset.

20 Am79C873

PRELIMINARY

Basic Mode Control Register (BMCR) ­Register 0 (Continued)

Bit Bit Name Default Description

Restart Auto-Negotiation:

1= Restart Auto-Negotiation.
0= Normal Operation

0.9

0.8 Duplex Mode 1, RW

0.7 Collision T est 0, RW

Restart Auto-

Negotiation

0, RW/SC

When this bit is set the Auto-Negotiation process is re-initiated. When
Auto-Negotiation is disabled (bit 12 of this register cleared), this bit has no
function and it should be cleared. This bit is self-clearing and will return a
value of 1 until Auto-Negotiation is initiated. The operation of the Auto­Negotiation process will not be affected by the management entity that
clears this bit.

Duplex Mode:
1= Full Duplex operation.
0= Normal operation
If Auto-Negotiation is disabled, setting this bit will cause the NetPHY-1

device to operate in Full Duplex mode . When A uto-Negotiation is enabled,
this bit reflects the duplex selected by Auto-Negotiation.

Collision Test:
1= Collision Test enabled.
0= Normal Operation
When set, this bit will cause the COL signal to be asserted in response to

the assertion of TX_EN.

0.6 Reserved 0, RO

Reserved:
Write as 0, ignore on read.

Am79C873 21

PRELIMINARY

Basic Mode Status Register (BMSR) ­Register 1

Bit Bit Name Default Description

100BASE-T4 Capable:

1.15 100BASE-T4 0,RO/P

1.14

1.13

100BASE-TX

Full Duplex

100BASE-TX

Half Duplex

1,RO/P

1,RO/P

1=NetPHY-1 device is able to perform in 100BASE-T4 mode.
0=NetPHY-1 device is not able to perform in 100BASE-T4 mode.

100BASE-TX Full Duplex Capable:
1=NetPHY-1 device is able to perform 100BASE-TX in Full Duplex mode.
0=NetPHY-1 device is not able to perform 100BASE-TX in Full Duplex

mode.
100BASE-TX Half Duplex Capable:

1=NetPHY-1 device is able to perform 100BASE-TX in Half Duplex mode.
0=NetPHY-1 device is not able to perform 100BASE-TX in Half Duplex

mode.

1.12

1.11

1.10-1.7 Reserved 0,RO

1.6

1.5

1.4 Remote Fault

10BASE-T

Full Duplex

10BASE-T

Half Duplex

MF Preamble

Suppression

Auto-Negotiation

Complete

1,RO/P

1,RO/P

0,RO

0,RO

0,

RO/LH

10BASE-T Full Duplex Capable:
1=NetPHY-1 device is able to perform 10BASE-T in Full Duplex mode.
0=NetPHY-1 device is not able to perform 10BASE-T in Full Duplex mode.

10BASE-T Half Duplex Capable:
1=NetPHY-1 device is able to perform 10BASE-T in Half Duplex mode.
0=NetPHY -1 de vice is not able to perf orm 10BASE-T in Half Duplex mode.

Reserved:
Write as 0, ignore on read.

MII Frame Preamble Suppression:
1=PHY will accept management frames with preamble suppressed.
0=PHY will not accept management frames with preamble suppressed.

Auto-Negotiation Complete:
1=Auto-Negotiation process completed.
0=Auto-Negotiation process not completed.

Remote Fault:
1= Remote fault condition detected (cleared on read or by a chip reset).

Fault criteria and detection method is NetPHY-1 device implementation
specific. This bit will set after the RF bit in the ANLPAR (bit 13, register
address 05) is set.

0= No remote fault condition detected.

1.3

1.2 Link Status 0,RO/LL

Auto-Negotiation

Ability

1,RO/P

Auto Configuration Ability:
1=NetPHY-1 device able to perform Auto-Negotiation.
0=NetPHY-1 device not able to perform Auto-Negotiation.

Link Status:
1=Valid link established (for either 10 Mbps or 100 Mbps operation).
0=Link not established.
The link status bit is implemented with a latching function, so that the

occurrence of a link failure condition causes the Link Status bit to be
cleared and remain cleared until it is read via the management interface.

22 Am79C873

PRELIMINARY

Basic Mode Status Register (BMSR) ­Register 1

Bit Bit Name Default Description

Jabber Detect:

1=Jabber condition detected.

1.1 Jabber Detect

0,

RO/LH

0=No jabber condition detected.
This bit is implemented with a latching function. Once Jabber conditions

are detected this bit will remain set until a read operation is completed
through a management interface or a NetPHY-1 device reset. This bit
works only in 10 Mbps mode.

1.0

Extended

Capability

1,RO/P

PHY ID Identifier Register 1 (PHYIDR1) ­Register 2

Extended Capability:

1=Extended register capable.
0=Basic register capable only.

Unique Identifier (OUI), a vendor's model number,
and a model revision number. The IEEE assigned OUI
is 00606E.

The PHY Identifier Registers 1 and 2 work together in
a single identifier of the NetPHY-1 device. The Identifier
consists of a concatenation of the Organizationally

Bit Bit Name Default Description

OUI Most Significant Bits:

2.15-2.0 OUI_MSB <0181H>

This register stores bits 3 - 18 of the OUI (00606E) to bits 15 - 0 of this
register, respectiv ely. The most significant tw o bits of the OUI are ignored
(the IEEE standard refers to these as bit 1 and 2).

PHY Identifier Register 2 (PHYIDR2) ­Register 3

Bit Bit Name Default Description

OUI Least Significant Bits:

3.15-3.10 OUI_LSB <101110>,RO/P

Bits 19 - 24 of the OUI (00606E) are mapped to bits 15 - 10 of this register,
respectively .

3.9-3.4 VNDR_MDL <000000>,R O/P

3.3-3.0 MDL_REV <0001>,RO/P

Vendor Model Number:
Six bits of the vendor model number mapped to bits 9 - 4 (most significant

bit to bit 9).
Model Revision Number:

Four bits of the vendor model re vision number mapped to bits 3 - 0 (most
significant bit to bit 3).

Am79C873 23

PRELIMINARY

Auto-Negotiation Advertisement Register(ANAR) - Register 4

This register contains the advertised abilities of the NetPHY-1 device as they will be transmitted to link partners dur­ing Auto-Negotiation.

Bit Bit Name Default Description

Next Page Indication:

0=No next page available

4.15 NP 0,RO/P

4.14 ACK 0,RO

4.13 RF 0, RW

1=Next page available
The NetPHY-1 device does not support the next page function. This bit is

permanently set to 0
Acknowledge:

1=Link partner ability data reception acknowledged.
0=Not acknowledged.
The NetPHY-1 device's Auto-Negotiation state machine will automatically

control this bit in the outgoing FLP bursts and set it at the appropriate time
during the Auto-Negotiation process. Software should not attempt to write
to this bit.

Remote Fault:
1=Local Device senses a fault condition.
0=No fault detected.

4.12-4.11 Reserved 0, RW

4.10 FCS 0, RW

4.9 T4 0, RO/P

4.8 TX_FDX 1, RW

4.7 TX_HDX 1, RW

4.6 10_FDX 1, RW

4.5 10_HDX 1, RW

Reserved:
Write as 0, ignore on read.

Flow Control Support:
1=Controller chip supports flow control ability.
0=Controller chip does not support flow control ability.

100BASE-T4 Support:
1=100BASE-T4 supported by the local device.
0=100BASE-T4 not supported.
The NetPHY-1 device does not support 100BASE-T4 so this bit is

permanently set to 0.
100BASE-TX Full Duplex Support:

1=100BASE-TX Full Duplex supported by the local device.
0=100BASE-TX Full Duplex not supported.

100BASE-TX Support:
1=100BASE-TX supported by the local device.
0=100BASE-TX not supported.

10BASE-T Full Duplex Support:
1=10BASE-T Full Duplex supported by the local device.
0=10BASE-T Full Duplex not supported.

10BASE-T Support:
1=10BASE-T supported by the local device.
0=10BASE-T not supported.

Protocol Selection Bits:

4.4-4.0 Selector <00001>, RW

These bits contain the binary encoded protocol selector supported by this
node.

<00001> indicates that this device supports IEEE 802.3 CSMA/CD.

24 Am79C873

PRELIMINARY

Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register 5

This register contains the advertised abilities of the link partner as they are received during Auto-Negotiation.

Bit Bit Name Default Description

Next Page Indication:

5.15 NP 0, RO

5.14 ACK 0, RO

5.13 RF 0, RO

0= Link partner, no next page available.
1= Link partner, next page available.

Acknowledge:
1=Link partner ability data reception acknowledged.
0=Not acknowledged.
The NetPHY-1 device's Auto-Negotiation state machine will automatically

control this bit from the incoming FLP bursts. Software should not attempt
to write to this bit.

Remote Fault:
1=Remote fault indicated by link partner.
0=No remote fault indicated by link partner.

5.12-5.10 Reserved 0, RO

5.9 T4 0, RO

5.8 TX_FDX 0, RO

5.7 TX_HDX 0, RO

5.6 10_FDX 0, RO

5.5 10_HDX 0, RO

5.4-5.0 Selector <00000>, RO

Reserved:
Write as 0, ignore on read.

100BASE-T4 Support:
1=100BASE-T4 supported by the link partner.
0=100BASE-T4 not supported by the link partner.

100BASE-TX Full Duplex Support:
1=100BASE-TX Full Duplex supported by the link partner.
0=b 100BASE-TX Full Duplex not supported by the link partner.

100BASE-TX Support:
1=100BASE-TX Half Duplex supported by the link partner.
0=100BASE-TX Half Duplex not supported by the link partne.r

10BASE-T Full Duplex Support:
1=10BASE-T Full Duplex supported by the link partner.
0=10BASE-T Full Duplex not supported by the link partner.

10BASE-T Support:
1=10BASE-T Half Duplex supported by the link partner.
0=10BASE-T Half Duplex not supported by the link partner.

Protocol Selection Bits:
Link partners binary encoded protocol selector.

Am79C873 25

PRELIMINARY

Auto-Negotiation Expansion Register (ANER) - Register 6

Bit Bit Name Default Description

6.15-6.5 Reserved 0, RO

6.4 PDF 0, RO/LH

6.3 LP_NP_ABLE 0, RO

6.2 NP_ABLE 0,RO/P

6.1 PAGE_RX 0, RO/LH

6.0 LP_AN_ABLE 0, RO

Reserved:
Write as 0, ignore on read.

Local Device Parallel Detection Fault:
PDF=1: A fault detected via parallel detection function.
PDF=0: No fault detected via parallel detection function.

Link Partner Next Page Able:
LP_NP_ABLE=1: Link partner, next page available.
LP_NP_ABLE=0: Link partner, no next page.

Local Device Next Page Able:
NP_ABLE=1: NetPHY-1 device, next page available.
NP_ABLE=0: NetPHY-1 device, no next page.
NetPHY-1 device does not support this function, so this bit is always 0.

New Page Received:
A new link code word page received. This bit will be automatically cleared

when the register (Register 6) is read by management.
Link Partner Auto-Negotiation Able:

LP_AN_ABLE=1 indicates that the link partner supports Auto­Negotiation.

26 Am79C873

PRELIMINARY

AMD Specified Configuration Register (DSCR) ­Register 16

Bit Bit Name Default Description

Bypass 4B5B Encoding and 5B4B Decoding:

16.15 BP_4B5B , RW

16.14 BP_SCR Pin 97, RW

16.13 BP_ALIGN Pin 98, RW

1=4B5B encoder and 5B4B decoder function bypassed.
0=Normal 4B5B and 5B4B operation The value of the pin is latched into

this bit at power-up/reset.
Bypass Scrambler/Descrambler Function:

1=Scrambler and descrambler function bypassed.
0=Normal scrambler and descrambler operation.
The value of the input pin is latched into this bit at power-up/reset.

Bypass Symbol Alignment Function:
1= Receive functions (descrambler, symbol alignment and symbol

decoding functions) bypassed. Transmit functions (symbol encoder and
scrambler) bypassed.

0= Normal operation.
The value of the BPALIGN input pin is latched into this bit at power-up/

reset.

16.12 Reserved 0, RW

16.11 REPEATER Pin 94, RW

16.10 TX 1, RW

16.9 UTP 1, RW

16.8 CLK25MDIS 0, RW

Reserved:
This bit must be set as 0.

Repeater/Node Mode:
1=Repeater mode.
0=Node mode.
In Repeater mode, the Carrier Sense (CRS) output from the NetPHY-1

device will be asserted only by receive activity. In NODE mode, or a mode
not configured for Full Duplex operation, CRS will be asserted by either
receive or transmit activity.

The value of the RPTR/NODE input pin is latched into this bit at power-up
reset.

100BASE-TX or FX Mode Control:
1=100BASE-TX operation.
0=100BASE-FX operation.

UTP Cable Control:
1=The media is a UTP cable, 0=STP.

CLK25M Disable:
1=CLK25M output clock signal tri-stated.
0=CLK25M enabled.
This bit should be set to 1 to disable the 25 MHz output and reduce ground

bounce and power consumption. For applications requiring the CLK25M
output, set this bit to 0.

16.7 F_LINK_100 1, RW

16.6 Reserved 0, RW

Force Good Link in 100 Mbps:
1=Normal 100 Mbps operation.
0=Force 100 Mbps good link status.
This bit is useful for diagnostic purposes.

Reserved:
This bit must be written as 0.

Am79C873 27

PRELIMINARY

AMD Specified Configuration Register (DSCR) ­Register 16

Bit Bit Name Default Description

LINKLED Mode Select:

0= Link LED output configured to indicate link status only.

16.5 LINKLED_CTL 0, RW

16.4 FDXLED_MODE 0, RW

16.3 SMRST 0, RW

16.2 MFPSC 0, RW

1= Link LED output configured to indicate traffic status: When the link
status is OK, the LED will be on. When the chip is in transmitting or
receiving, it flashes.

FDXLED Mode Select:
1= FDXLED output configured to indicate polarity in 10BASE-T mode.
0= FDXLED output configured to indicate Full DuplexFull Duplex mode

status for 10 Mbps and 100 Mbps operation.
Reset State Machine:

When this bit is set to 1, all state internal machines will be reset. This bit
will clear after reset is completed.

MF Preamble Suppression Control:
1= MF preamble suppression on.
0= MF preamble suppression off.
MII frame preamble suppression control bi.t

16.1 SLEEP 0, RW

16.0 RLOUT 0, RW

Sleep Mode:
Writing a 1 to this bit will cause NetPHY -1 de vice to enter Sleep mode and

power down all circuits except the oscillator and cloc k generator circuit. To
exit Sleep mode, write 0 to this bit position. The prior configuration will be
retained when the sleep state is terminated, but the state machine will be
reset.

Remote Loopout Control:
When this bit is set to 1, the received data will loop out to the transmit

channel. This is useful for bit error rate testing.

28 Am79C873

PRELIMINARY

AMD Specified Configuration and Status
Register (DSCSR) - Register 17

Bit Bit Name Default Description

100 M Full Duplex Operation:

17.15 100FDX 1, RO

17.14 100HDX 1, RO

17.13 10FDX 1, RO

17.12 10HDX 1, RO

After Auto-Negotiation is completed, the results will be written to this bit.
A 1 in this bit position indicates 10 0M Full Duplex operation. The software
can read bits [15:12] to determine which mode is selected after Auto­Negotiation. This bit is invalid when Auto-Negotiation is disabled.

100 M Half Duplex Operation:
After Auto-Negotiation is completed, the results will be written to this bit.

A 1 in this bit position indicates 100 M Half Duplex operation. The software
can read bits [15:12] to determine which mode is selected after Auto­Negotiation. This bit is invalid when Auto-Negotiation is disabled.

10 M Full Duplex Operation:
After Auto-Negotiation is completed, the results will be written to this bit.

A 1 in this bit position indicates 10 M Full Duplex operation. The software
can read bits [15:12] to determine which mode is selected after Auto­Negotiation. This bit is invalid when Auto-Negotiation is disabled.

10 M Half Duplex Operation:
After Auto-Negotiation is completed, the results will be written to this bit.

A 1 in this bit position indicates 10M Half Duplex operation. The software
can read bits [15:12] to determine which mode is selected after Auto­Negotiation. This bit is invalid when Auto-Negotiation is disabled.

17.11-

17.10

17.8-17.4 PHYAD[4:0] (PHYAD), RW

Bit Bit Name Default Description

17.3-17.0 ANMB[3:0] 0, RO

Reserved 0, RW

Reserved:
Write as 0, ignore on read.

PHY Address Bit 4:0:
The values of the PHYAD[4:0] pins are latched to this register at power-

up/reset. The first PHY address bit tr ansmitted or received is the MSB (bit

4). A station management entity connected to multiple PHY entities m ust
know the appropriate address of each PHY. A PHY address of <00000>
will cause the isolate bit of the BMCR (bit 10, Register Address 00) to be
set.

Auto-Negotiation Monitor Bits:
These bits are for debug only. The Auto-Negotiation status will be written

to these bits.

b3 b2 b1 b0
0000In IDLE state
0001Ability match
0010Acknowledge match
0011Acknowledge match fail
0100Consistency match
0101Consistency match fail
0110Parallel detect signal_link_ready
0111Parallel detect signal_link_ready fail
1000Auto-Negotiation completed successfully

Am79C873 29

PRELIMINARY

10BASE-T Configuration/Status
(10BTCSRSCR) - Register 18

Bit Bit Name Default Description

18.15 Reserved 0, RO

18.14 LP_EN 1, RW

18.13 HBE

18.12 Reserved 0, RO

18.11 JABEN 1, RW

18.10 10BT_SER Pin 98, RW

Inverse Pin 94,

RW

Reserved:
Write as 0, ignore on read.

Link Pulse Enable:
1=Transmission of link pulses enabled.
0=Link pulses disabled, good link condition forced.
This bit is valid only in 10 Mbps operation.

Heartbeat Enable:
1=Heartbeat function enabled.
0=Heartbeat function disabled.
When the NetPHY-1 device is configured for Full Duplex operation, this bit

will be ignored (the collision/heartbeat function is invalid in Full Duplex
mode). The initial state of this bit is the inv erse value of RPTR/NODE input
pin at power on reset.

Reserved:
Write as 0, ignore on read.

Jabber Enable:
1= Jabber function enabled.
0= Jabber function disabled.
Enables or disables the Jabber function when the NetPHY-1 device is in

10BASE-T Full Duplex or 10BASE-T Transceiver Loop-back mode.
10BASE-T Serial Mode:

1=10BASE-T serial mode selected.
0=10BASE-T nibble mode selected.
The value on the 10BTSER input pin is latched into this bit at power-up/

rese.t
Serial mode not supported for 100 Mbps operation.

18.9-18.1 Reserved 0, RO

18.0 POLR 0, RO

Reserved:
Write as 0, ignore on read.

Polarity Reversed:
When this bit is set to 1, it indicates that the 10M cable polarity is reversed.

This bit is set and cleared by 10BASE-T module automatically.

30 Am79C873

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . . –0°C to +70°C

Supply V oltage

with Respect to Ground . . . . . . . . . -4.75 V to +5.25 V

DC Input Voltage (VIN) . . . . . . . . –0.5 V to VCC +0.5 V

DC Output or I/O Pin Voltage (V

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to Ab­solute Maximum Ratings for extended periods may affect
device reliability.

). . . . .–0.5 V to

OUT

VCC +0.5 V

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C

Supply V oltage (VCC)

with Respect to Ground . . . . . . . . +4.75 V to +5.25 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Power Consumption

100BASE-TX Full Duplex . . . . . . . . . . . . . . . . 185 mA

(Measured using Unscrambled IDLE transmission looped
back to RXIN, includes external termination circuitry)

10BASE-T Full Duplex . . . . . . . . . . . . . . . . . . 222 mA

(Measured using Maximum packet size, minimum I.P.G.
transmission looped back to RXIN, includes external termina­tion circuitry)

Auto-Negotiation. . . . . . . . . . . . . . . . . . . . . . 165 mA

(Measured during Parallel Detect until link established)

Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA

(Measured with no link established)

Power Down Mode . . . . . . . . . . . . . . . . . . . . . 40 mA

(Measured while MII Register 0 Bit 11 set true)

DC ELECTRICAL CHARACTERISTICS

= 5 VDC, ±5%, TA = 0 to 70, unless specified otherwise)

(V

CC

Symbol Parameter Conditions Min Typical Max Unit

I

100TX

I

10TTP

I

10TWC

I

PDM

I

AN

I

RST

TTL Inputs
(TXD0-TXD3, TX_CLK, MDIO, TX_EN, TX_DV, TX_ER, TESTMODE, PHYAD0-4, OPMODE0-4, RPTR, BPALIGN, BP4B5B,
BPSCR, 10BTSER, RESET

V
V

I

I

Supply Current 100BASE 100BASE-TX
active

Supply Current 10BASE-TX active
(Random data, Random IPG and

Random size)
Supply Current 10BASE-TX active

(Max. Packet size, Min. IPG and Worst
case data pattern)

Supply Current Power Down Mode Vcc = 5.0 V 40 mA
Supply Current during Auto-Negotiation V
Supply Current during Reset. Vcc = 5.0 V 115 mA

)

Input Low Voltage IIL = -400 uA 0.8 V

IL

Input High Voltage IIH = 100 uA 2.0 V

IH

Input Low Current VIN = 0.4 V -200 uA

IL

Input High Current VIN = 2.7 V 100 uA

IH

V

= 5.0 V 180 185 mA

cc

= 5.0 V 120 mA

V

cc

= 5.0 V 220 mA

V

cc

= 5.0 V 165 mA

cc

Am79C873 31

PRELIMINARY

DC ELECTRICAL CHARACTERISTICS

= 5 VDC, ±5%, TA = 0 to 70, unless specified otherwise) (Continued)

(V

CC

Symbol Parameter Conditions Min Typical Max Unit

MII TTL Outputs
(RXD0-3, RX_EN, RX_DV, RX_ER, CRS, COL, MDIO)

V

OL

V

OH

Output Low Voltage IOL = 4 mA 0.4 V
Output High Voltage

OH = -4 mA 2.4 V

I

Non-MII TTL Outputs
(TXLED, RXLED, LINKLED, COLLED, FDXLED, RX_LOCK)

V

V

OH

V

ICM

Output Low Voltage IOL = 1 mA 0.4 V

OL

Output High Voltage IOH = -0.1 mA 2.4 V
RXI+/RXI- Input Common-Mode Voltage 100 Ω Termination Across 1.5 2.0 2.5 V

Twisted Pair Transmitter

I

TD100

ITD10

100TX+± 100BASE-TX Mode
Differential Output Current

10TX± 10BASE-T Differential Output
Current

19 21 mA

44 50 56 mA

PECL Receiver

VIH - VCC PECL Receiver Voltage - High -1.16 -0.90

VIL - VCC PECL Receiver Voltage - Low -1.81 -1.48

PECL Signal Detect

VIH - VCC PECL Signal Detect Voltage - High -1.16 -0.90

VIL - VCC PECL Signal Detect Voltage - Low -1.81 -1.48

PECL T ransmitter

VOH -

VCC

VOL -

VCC

PECL Output Voltage - High -1.05 -0.88

PECL Output Voltage - Low -1.85 -1.60

AC ELECTRICAL CHARACTERISTICS
(Over full range of operating conditions unless specified otherwise)

Symbol Parameter Conditions Min Typical Max Unit

Transmitter

t

TR/F

t

TM

t

TDC

t

T/T

XOST

100TXO+/- Differential Rise/Fall Time 3.0 5.0 ns
100TXO+/- Differential Rise/Fall Time

Mismatch

100TXO+/- Differential Output Duty

Cycle Distortion

100TXO+/- Differential Output Peak-to-

Peak Jitter

100TXO+/- Differential Voltage

Overshoot

-0.5 0.5 ns

-0.5 0.5 ns

300 ps

5%

32 Am79C873

PRELIMINARY

AC ELECTRICAL CHARACTERISTICS
(Over full range of operating conditions unless specified otherwise) (Continued)

Symbol Parameter Conditions Min Typical Max Unit

PECL T ransmitter (FX Transmit Interface)

pt

pt

pt

pt

pt

TR/F

TM

TDC

PPJ

DDJ

100FXTD+/- Differential Rise/Fall Time 1.0 2.0 ns
100FXTD+/- Differential Rise/F all Time

Mismatch

100FXTD+/- Differential Output Duty
Cycle Distortion

100FXTD+/- Differential Output Peak­to-Peak Jitter

100FXTD+/- Differential Output Data
Dependent Jitter

-0.5 0.5 ns

-0.5 0.5 ns

300 ps

500 ps

Clock Specifications

XNTOL TX Input Clock Frequency Tolerance 25 MHz Frequency ppm
XBTOL TX Output Clock Frequency Tolerance 25 MHz Frequency -100 +100 ppm

t

PWH

tPWL

t

RPWH

t

RPWL

OSC Pulse Width High 14 ns
OSC Pulse Width Low 14 ns
RX_CLK Pulse Width High 14 ns
RX_CLK Pulse Width Low 14 ns

Am79C873 33

PRELIMINARY

MII 100BASE-TX T ransmit Timing

TX_CLK

tTX

s

TXD [0:3],

TX_EN, TX_ER

t

1

CRS

tTX

100TX±

pd

Figure 7. MII 100BASE-TX Transmit Timing Diagram

MII 100BASE-TX T ransmit Timing Parameters (Half Duplex)

Symbol Parameter Conditions Min

tTX

h

tTX

t

2

r/f

22164A-9

Typical

(Note 1

)

Max Unit

tTX

tTX

TXD[0:3], TX_EN, TX_ER Setup To

s

TX_CLK High
TXD[0:3], TX_EN, TX_ER Hold From

h

TX_CLK High

11 - - ns

0--ns

t1 TX_EN Sampled To CRS Asserted - 4 - BT
t2 TX_EN Sampled To CRS De-asserted - 4 - BT

tTX

tTX

TX_EN Sampled To TPO Out (Tx Latency) - 8 - BT

pd

100TX Driver Rise/Fall Time

r/f

90% To 10%, Into
100 Ω Differential

345ns

Note:

1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing.

34 Am79C873

MII 100BASE-TX Receive Timing

RX_CLK

tTX

RXD [0:3],

RX_DV, RX_ER

CRS

t

RXI±

COL

3

t5

Figure 8. MII 100BASE-TX Receive Timing Diagram

PRELIMINARY

pd

t

1

tRX

tRX

S

h

t

t

4

2

22164A-10

MII-100BASE-TX Receive Timing Parameter (Half Duplex)

Typical

Symbol Parameter Conditions Min

tRX

tRX

tRX

t1

t2

RXD[0:3), RX_DV, RX_ER Setup To

s

RX_CLK High
RXD[0:3], RX_DV, RX_ER Hold From

h

RX_CLK High
RXI In To RXD[0:3] Out (RX Latency)

pd

CRS Asserted To RXD[0:3], RX_DV,
RX_ER

CRS De-asserted To RXD[0:3], RX_DV,

RX_ER
t3 RXI In To CRS Asserted
t4 RXI Quiet To CRS De-asserted
t5 RXI In To COL De-asserted

10

10

-15-BT

-4-BT

-0-BT

10-14BT
14-18BT
14-18BT

(Note 1

Note:

1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing.

)

--

--

Max Unit

ns

ns

Am79C873 35

PRELIMINARY

Auto-Negotiation and Fast Link Pulse Timing

Fast Link

Pulses

10TX0±

Clock Pulse

t

1

FLP Burst

t

4

Data Pulse

t

2

t

3

t

5

Clock Pulse

FLP Burst

22164A-11

Figure 9. Auto-Negotiation and Fast Link Pulse Timing Diagram

Auto-Negotiation and Fast Link Pulse Timing Parameters

Symbol Parameter Conditions Min Typical Max Unit

t1 Clock/Data Pulse Width - 100 - ns
t2 Clock Pulse To Data Pulse Period DATA = 1 - 62.5 - us
t3 Clock Pulse To Clock Pulse Period - 125 - us
t4 FLP Burst Width - 2 - ms
t5 FLP Burst To FLP Burst Period - 13.93 - ms

- Clock/Data Pulses Per Burst 33 33 33 ea

MII 10BASE-T Nibble Transmit Timing

TX_CLK

tTX

tTX

S

TXD [0:3],

TX_EN, TX_ER

t

1

CRS

tTX

10TX±

pd

Figure 10. MII 10BASE-T Nibble Transmit Timing Diagram

MII-10BASE-T Nibble T ransmit Timing Parameters

Symbol Parameter Conditions Min Typical Max Unit

tTX

tTX

t1 TX_EN Sampled To CRS Asserted - 2 4 BT
t2 TX_EN Sampled To CRS De-asserted - 15 20 BT

tTX

TXD[0:3), TX_EN, TX_ER Setup To

s

TX_CLK High

TXD[0:3], TX_EN, TX_ER Hold From

h

TX_CLK High

TX_EN Sampled To 10TXO Out (Tx

pd

Latency)

h

t

2

22164A-12

11 - - ns

0--ns

-24BT

36 Am79C873

PRELIMINARY

MII 10BASE-T Receive Nibble Timing Diagram

RX_CLK

tRX

tTX

pd

RXD [0:3],

RX_DV, RX_ER

t

1

CRS

t

3

RXI±

Figure 11. MII 10BASE-T Receive Nibble Timing Diagram

MII-10BASE-T Receive Nibble Timing Parameters

Symbol Parameter Conditions Min Typical Max Unit

tRX

h

S

t

t

4

2

22164A-13

tRX

tRX

tRX

t1

t2

RXD[0:3), RX_DV, RX_ER Setup To

s

RX_CLK High

RXD[0:3], RX_DV, RX_ER Hold From

h

RX_CLK High

RXI In To RXD[0:3] Out (RX Latency) - 7 - BT

pd

CRS Asserted To RXD[0:3], RX_DV,

RX_ER

CRS De-asserted To RXD[0:3], RX_DV,

RX_ER

10 - - ns

10 - - ns

11420BT

--3BT

t3 RXI In To CRS Asserted 1 2 4 BT
t4 RXI Quiet To CRS De-asserted 1 10 15 BT

Am79C873 37

PRELIMINARY

10BASE-T SQE (Heartbeat) Timing

TX_CLK

TX_EN

t

1

COL

Figure 12. 10BASE-T SQE (Heartbeat) Timing Diagram

10BASE-T SQE (Heartbeat) Timing Parameters

Symbol Parameter Conditions Min Typical Max Unit

t1 COL (SQE) Delay After TX_EN Off 0.65 1.3 1.6 ms
t2 COL (SQE) Pulse Duration 0.5 1.1 1.5 ms

t

2

22164A-14

10BASE-T Jab and Unjab Timing

TX_EN

TDX

COL

Figure 13. 10BASE-T Jab and Unjab Timing Diagram

10BASE-T Jab and Unjab Timing Parameters

Symbol Parameter Conditions Min Typical Max Unit

t1 Maximum Transmit Time 20 48 150 ms
t2 Unjab Time 250 505 1500 ms

t

1

t

2

22164A-15

38 Am79C873

PRELIMINARY

MDIO Timing when OUTPUT by STA

MDC

10 ns

(Min)

MDIO

Figure 14. MDIO Timing when OUTPUT by STA Timing Diagram

MDIO Timing when OUTPUT by NetPHY-1 Device

MDC

0 - 300 ns

t

3

MDIO

10 ns
(Min)

t

t

1

2

22164A-16

22164A-17

Figure 15. MDIO Timing when OUTPUT by NetPHY-1 Timing Diagram

MII Timing Parameters

Symbol Parameter Conditions Min Typical Max Unit

t1 MDIO Setup Before MDC When OUTPUT By STA 10 - - ns
t2 MDIO Hold After MDC When OUTPUT By STA 10 - - ns

t3 MDC To MDIO Output Delay

When OUTPTU By

NetPHY-1 device

0 - 100 ns

Am79C873 39

PRELIMINARY

32
31

OSC/XTLB

OSCGND

AGND

AGND

AGND

C18

18 pF

Y1 25M

C19

18 pF

29

30

X1

X2

22164A-18

MAGNETICS SELECTION GUIDE

The NetPHY-1 device requires a 1:1 ratio for both the
receive and the transmit transformers. Refer to Table 2
for transformer requirements. Transformers meeting
these requirements are available from a v ariety of mag­netic manufacturers. Designers should test and qualify
all magnetics before using them in an application. The
transformers listed in Table 2 are electrical equivalent,
but may not be pin-to-pin equivalent.

Table 2. Transformer Requirements

Manufacturer Part Number

Bel Fuse S558-5999-01
Delta LF8200, LF8221

Single Port
TG22-3506ND, TD22-

3506G1, TG22-S010ND,

HALO Electronics, Inc.

TG22-S012ND,
TG110-S050N2

Quad P
TG110-6506NX, TG110-

S450NX, TG110-S452NX

ort

CRYSTAL SELECTION GUIDE

A crystal can be used to generate the 25 MHz refer­ence clock instead of a crystal oscillator. An M-TRON
crystal, par t number is 00301-00169, MP-1 Fund, @

25.000000 MHz, ±50 ppm or equivalent may be used.
The crystal must be a fundamental type, parallel res­onant. Connect to X1 and X2, shunt each crystal lead
to ground with an 18pf capacitor (see Figure 16).

NPI 6181-37, NPI 6120-30,

Nano Pulse Inc.

Pulse Engineering

Valor ST6114, ST6118
YCL 20PMT04, 20PMT05

NPI 6120-37
NPI 6170-30

PE-68517, PE-68515,
H1019, H1012 ----Single

Port
H1027, H1028 ---- Dual Port
PE-69037, H1001,
H1036, H1044 ---- Quad

Port

Figure 16. Crystal Circuit Diagram

40 Am79C873

PRELIMINARY

Table 3. Part List for Example Design

Item No Qty Reference Number Part Description

1 11 C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C13 Capacitor, Decoupling, 0.1 µf, 50 V
2 1 C12 Capacitor, .01 µf, 2KV
3 4 D1,D2,D3,D4 LED, General Purpose
4 1 J1 Connector, RJ45
5 2 L1,L2 Ferrite, Panasonic EXCCL4532U
6 1 OSC1 Oscillator, Crystal, 25 MHz, ±50 ppm
7 2 Q2,Q1 Transistor, NNP, General Purpose, 2N2222
8 2 R1,R2 Resistor, 470Ω, 5%
9 1 R3 Resistor, 820Ω, 5%

10 1 R4 Resistor, 33Ω, 5%
11 1 R5 Resistor, 510Ω, 5%
12 1 R6 Resistor, 6.01KΩ, 1%
13 4 R7,R8,R14,R15 Resistor, 49.9Ω, 1%
14 1 R9 Resistor, 1.5KΩ, 5%
15 4 R10,R11,R12,R13 Resistor, 75Ω, 1%
16 2 R17,R16 Resistor, 10KΩ, 5%
17 1 U1 NetPHY-1 device, PHY/Transceiver, 100 pin QFP
18 1 U2 Magnetics, Pulse Engineering, PE68515
19 3 R17,R18,R21 Resistor 82Ω, 5%
20 2 R19,R21 Resistor 62Ω, 5%
21 3 R22,R23,R26 Resistor 130Ω, 5%
22 2 R24,R25 Resistor 300Ω

, 5%

Am79C873 41

NetPHY-1 MII Example Schematic

GND

VCC

10K

S1

SW SPST

TMODE
PHAD0
PHAD1
PHAD2
GND
VCC
PHAD3
PHAD4
OPMD0
OPMD1
OPMD2
OPMD3
NODEB
BPAGN
BP45B
BPSCR
10SER
GND
GND

10u

VCC

RXDV

RXER

VCC

R9

79

78

81
82
83
84
85
86

87
88
89
90

91
92
93
94
95
96
97
98
99

100

80

RXER

RX_EN

RESET#
TESTMODE
PHYAD0
PHYAD1
PHYAD2
DGND
DVCC
PHYAD3
PHYAD4
OPMODE0
OPMODE1
OPMODE2
OPMODE3
RPTR/NODE#
BPALIGN
BP4B5B
BPSCR

10BTSER

AGND
AGND

RXDV

COL

C1

COL

77

CRS

CRS

76

R1
220

RXCLK

75

RXCLK

VCC

VCC

74

GND

73

GND

PRELIMINARY

VCC

RXD0

72

RXD0

RXD1

71

RXD1

RXD2

70

RXD2

RXD3

69

RXD3

R2

1.5K
VCC

68

DVCC

GND

67

DGND

MDIO

MDIO

66

MDC

MDC

65

R3

220

TXCLK

64

TXCLK

TXEN

63

TXEN

DVCC

Am79C873

NetPHY-1

VCC

62

GND

61

DGND

TXD0

60

TXD0

TXD1

59

TXD1

TXD2

58

TXD2

TXD3

57

TXD3

TXER

56

TXER

TXLED

55

TXLED

RXLED

54

RXLED

LILED

53

DGND

LINKLED

FDXLED#

CLK25M

LINKSTS

RX_LOCK

SPEED10

TRIDRV

OSC/XTL#

AGND

GND

52

COLLED#

DVCC

DGND

UTP

DVCC
DGND
DGND
DGND

BGRET
BGRES

AGND

AVCC

COLLED#

51

U1

50

49
48
47
46

NC

45
44
43
42

41
40
39
38
37
36
35
34
33
32
31

FDXLED

VCC

CLK25M

SD

GND

RXLOCK

SPEED
SIGOK

GND

VCC
GND
GND
GND

GND

VCC

XTLB

VCC

GND

VCC

GND

R24

130

R30

370

R24

R30

130

100TXO+

VCC

R29

AGND

GND

R34

49.9 1%

AGND

100TXO-

AVCC

AVCC

2425262728

TXOM

TXOP

GND

VCC

VCC

Load these components

or OSC1+ R12.

TP15

TP16

FXTD-

FXRD-

FXRD+

OSCI/X

29

Y1

GND GND

FXTD+

FXSD

X2

C16
18P

GND

GND

30

25M

VCC_T
VCC_R

DM9101F

C16, C17

HFBR5103T

FX1

9
8
7
6
5
4
3
2
1

C17
18P

#12

#15

*

10TXO+

FXSD-

AVCC

1

3

2

FXSD-

VCC

FXSD-

82

FXSD+

FXSD+

VCC

456

FXRD+

FXRD-

R35

82

FXRD+

R39
130

AGND

GND

.1u

GND

AVCC

7

VCC

C18

GND

C26

.1u

AVCC

8

VCC

R36

FXRD­R40

130

RXI+

RXI-

9

RXIM

R2 7

49.9 1 %

82

FXRD+

FXSD+

FXRD-

AGND

AGND

11

1213141516

10

RXIP

GND

GND

R2 849.9 1 %

TP19

10TXO-

TXOM

R32

300

FXSD

300

TP18

TXOP

R37

AVCC

VCC

AVCC

VCC

FXT D-

TP17

AGND

AGND

17

GND

R33 62

R38 62

.1u

C23

18

GND

FXTD

19

FXTD-

FXSD

FXTD

20

FXTD+

AVCC

AVCC

212223

VCC

49.9 1%

VCC

42 Am79C873

PRELIMINARY

NetPHY-1 MII Example Schematic (Continued)

VCC

Pin 43

(SPEED)

Pin 36

(BGRET)

Pin 35

(BGRES)

Pin 31

(AGND)

#87

C2
.1u

#86

R23

TX CKT POWER/GROUND AREA

C10

.01u

*

33

R25

* Do Not Load

TXLED
RXLED

LILED
COLLED
FDXLED

CLK25M

SD

RXLOCK

SPEED

SIGOK

VCC

BYPASS CAPACITOR FOR U1

#74

#73 #61

Digital Ckt Power & Ground Area

Locate near U1’s VCC & Ground Pins

Physically place caps on SOLDER SIDE.

Q1

R20
510

2N2222

D12

LED

5.76K 1%

C11

#18 #24 #34

.1u

#27#21

VCC

C24

.1u

GND

VCC_R

VCC_T

LED

LED

LED

LED

#62

C3

.1u

D11

100M

LED

10M

RX CKT POWER/GROUND AREA

No traces or power near this area

Place caps as close as

possible to U1 pins.

(SOLDER SIDE)

C12

#31

.1u

OSC1

8

OUT NC

14

25M

C25

10u

D1

D2

LED

D3

D4

LED

D5

LED

D6

D7

LED

D8

D9

LED

D10

LED

C5

C4

.1u

.1u

#52 #39 #67

R19

820

GND

C13

VCC

.01u

1uH

L1

C27

.1u

C14

#33#28

1
7

GND+VDD

C28

GND

#40#49

.1u

L2

.1u

VCC

RP1

1
2
3
4
5
6

470

RP2

6
5
4
3
2
1

470

GND

#68

C6

GND

C7

.1u

.1u

GND

VCC

GND

Place caps close to U1 pins # as shown by number
by each cap. Physically place cap on SOLDER SIDE.

VCC

# 01

C19

#100

10u

GND

1uH

C20

.1u

TP2

TP3

TP4

RXER

TP5

TP8

TXD0

TP10

#7

#6

TP1

RXD3

RXD2

RXD1

RXCLK

TP7

TP9

C21
.01u

MDC

RXD0

RXDV

TXEN

CRS

#11

VCC

MDIO

TP6

TXER

TXCLK

TXD1

TXD2

TXD3

COL

TP11 TP12

C9
.1u

GND

#8

TP13 TP14

VCC

C22

.1u

Advanced Micro Devices

Title

NetPHY-1 Evaluation Board

Size Document Number Rev

netphy1_ev_0 2.0

B

Date: Sheet

R4 33

R13 33

SW1

SW2

R5 33

R7 33

R1033

R1133

R12 33

R1433

R16 33

VCC

J2

RJ45

1234567

U2

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1 16

116

PE68515

PHAD0

16
15
14
13
12
11
10

9

16

BPSCR
15
14

BPAGN
13
12
11

OPMD2

10

9

1%
75

10
11
12
13
14
15

PHAD3

NODEB

R6 33
R8 33

R15 33

R21

75 1%

RXIM TXOM

RXIP

1
2
3
4
5
6
7
8

SW DIP-8

1
2
3
4
5
6
7
8

SW DIP-8

9

PHAD2

TMODE

XTLB

OPMD1

OPMD0

R17

9
10
11
12
13
14
15

PHAD1

PHAD4

10SER

OPMD3

J1

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

MII CON

8

75 1%

75 1%

TXOP

GND

BP45B

GND

11Monday, May 04, 1998

R18

R22

RP9_1K

.1u/1KV

RP3

8
7
6
5
4
3
2
1

RP7_1K

RP4

10

9
8
7
6
5
4
3
2
1

of

VCC

GND

VCC

C8

GND

Am79C873 43

PHYSICAL DIMENSIONS*
PQR100

HD
D

PRELIMINARY

81100

1

F

80

E

GE

HE

50

51

A2

A1

A

30

31

e

GD

See Detail F

Seating Plane

b

Y

*For Reference Only Notes:

Symbol

Dimensions

In Inches

Dimensions In mm

A 0.130 Max. 3.30 Max.
A1 0.004 Min. 0.10 Min.
A2 0.1120.005 2.85 ±0.13

b 0.012 +0.004 0.31 +0.10

-0.002 -0.05

c 0.006 +0.004 0.15 +0.10

-0.002 -0.05
D 0.551 ±0.005 14.00 ±0.13
E 0.787 ±0.005 20.00 ±0.13
e 0.026 ±0.006 0.65 ±0.15
F 0.742 NOM. 18.85 NOM.

GD 0.693 NOM. 17.60 NOM.
GE 0.929 NOM. 23.60 NOM.
HD 0.740 ±0.012 18.80 ±0.31
HE 0.976 ±0.012 24.79 ±0.31

L 0.047 ±0.008 1.19 ±0.20

L

1

0.095 ±0.008 2.41 ±0.20
y 0.004 Max. 0.15 Max.
q0∞ ~ 12∞ 0∞ ~ 12∞

1. Dimension D & E do not include resin fins.

2. Dimension GD & GE are for PC Board surface
mount pad pitch design reference only.

3. All dimensions are based on metric system.

c

L

L1

GD

0 ~12

~

~~

Detail F

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
NetPHY and PCnet are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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