Datasheet Am29PDS322D Datasheet (SPANSION)

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Am29PDS322D

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Publication Number 23569 Revision A Amendment +4 Issue Date August 7, 2002

Page 2

ADVANCE INFORMATION

Am29PDS322D

32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V) Simultaneous Read/Write Page-Mode Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank.

— Zero latency between read and write operations

■ Page Mode Operation

— 4 word page allows fast asynchronous reads

■ Dual Bank architecture

— One 4 Mbit bank and one 28 Mbit bank

■ SecSi (Secured Silicon) Sector: Extra 64 KByte

sector

— Factory locked and identifiab le: 16 byte Electronic

Serial Number available for factory secure, random ID; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data

— Customer lockable: Can be read, programmed, or

erased just like other sectors. Once locked, data cannot be changed

■ Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly zero.

■ Package options

— 48-ball FBGA

■ Top or bottom boot block

■ Manufactured on 0.23 µm process technology

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHA RA CT ER IST ICS

■ High performance

— Access time as fast 40 ns (100 ns random access

time) at 1.8 V to 2.2 V V

— Random access time of 100 ns at 1.8 V to 2.2 V VCC

will be required as customers migrate downward in voltage

■ Ultra low power consumption (typical values)

— 2.5 mA active read current at 1 MHz for initial page

read

— 24 mA active read current at 10 MHz for initial page

read

— 0.5 mA active read current at 10 MHz for intra-page

read

— 1 mA active read current at 20 MHz for intra-page

read

— 200 nA in standby or automatic sleep mode

■ Minimum 1 million write cycles guaranteed per

sector

■ 20 year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■ Data Management Software (DMS)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

— Eases historical sector erase flash limitations

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

■ WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

— ACC voltage is 8.5 V to 12.5 V

■ Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to prevent any program or erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 23569 Rev: A Amendment/+4 Issue Date: August 7, 2002

Page 3

ADVANCE INFORMATION

GENERAL DESCRIPTION

The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits each. This device is offered in a 48-ball FBGA package. The device is designed to be programmed in system with standard system 1.8 V V

supply. This

device can also be reprogrammed in standard EPROM programmers.

The Am29PDS3 22D offers fast pag e access ti me of 40 ns with ra ndom a ccess t ime of 10 0 ns ( at 1.8 V to

2.2 V V

), allowing operation of high-speed micropro-

cessors without wait states. To eliminate bus contention the device has sepa rate chip enable (C E), write enable (WE), and output enable (OE) controls. The page size is 4 words.

The device requires only a single 1.8 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the me mory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

The device is divided as shown in the following table:

Bank 1 Sectors Bank 2 Sectors

Quantity Size Quantity Size

84 Kwords 7 32 Kwords

4 Mbits total 28 Mbits total

56 32 Kwords

Am29PDS322D Features

The SecSi (Se cured Silicon) S ector is an extra 64 KByte sector capable of being perm anently lo cked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, customer lockable parts can never be used to replace a factory locked part.

Factory locked parts pro vide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Numb er), cust omer co de (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any

other flash sector, or may permanen tly lock their ow n code there.

DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation o f the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set standard. Commands are written to the command

register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically re turns to the read mode.

The sector erase archite cture allow s memo ry sectors to be erased and reprogrammed without affecting the data conten ts of oth er sec tors. Th e devi ce is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase operations in any com bination of the secto rs of memory. This can be achieved in-system or via programming equipment.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly r educed in both modes.

2 Am29PDS322D August 7, 2002

Page 4

ADVANCE INFORMATION

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4

Block Diag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Special Handling Instructions for FBGA Package ....................5

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29PDS322D Device Bus Operations .............................8

Requirements for Reading Array Data .....................................8

Read Mode .......................... ..................................... ................8

Random Read (Non-Page Mode Read) ............................................8

Page Mode R ea d .......... ............... .. .. ............................. .. ... .......9

Table 2. Page Word Mode ................................................................9

Writing Commands/Command Sequences ..............................9

Accelerated Program Operation ........................................................9

Autoselect Function s ..................................................... ....................9

Simultaneous Read/Write Operations with Zero Latency .........9

Standby Mode............................ .............................................. 9

Automatic Sleep Mode .................................... .......................10

RESET#: Hardware Reset Pin ...............................................10

Output Disable Mode ..............................................................10

Table 3. Am29PDS322DT Top Boot Sector Addresses ..................11

Table 4. Am29PDS322DT Top Boot SecSi Sector Address ...........12

Table 5. Am29PDS322DB Bottom Boot Sector Addresses .. ..........12

Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address . . .14

Autoselect Mode..................................................................... 15

Table 7. Autoselect Codes (High Voltage Method) ........................15

Sector/Sector Block Protection and Unprotection.................. 16

Table 8. Top Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................................16

Table 9. Bottom Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................................16

Write Protect (WP#) ................................................................17

Temporary Sector/Sector Block Unprotect .............................17

Figure 1. Temporary Sector Unprotect Operation........................... 17

Figure 2. Temporary Sector Group Unprotect Operation................ 18

Figure 3. In-System Sector Group Protect/Unprotect Algorithms ... 19

SecSi (Secured Silicon) Sector Flash Memory Region ..........20

Factory Locked: SecSi Sector Programmed and Protected

at the Factory ..................................................................................20

Hardware Data Protection ......................................................20

Low VCC Write Inhibit .......................................................................20

Write Pulse “Glitch” Protection ................. ................ .......................21

Logical Inhibit ..................................................................................21

Power-Up Write Inhibit ............... ............................................ .........21

Command Definitions . . . . . . . . . . . . . . . . . . . . . 21

Reading Array Data ................................................................21

Reset Command .......................................................... ...........21

Autoselect Command Sequence .......................................... ..21

Enter SecSi Sector/Exit SecSi Sector Command Sequence ..22

Word Program Command Sequence .....................................22

Unlock Bypass Command Sequence ..............................................22

Chip Erase Command Sequence ...........................................22

Figure 4. Unlock Bypass Algorithm................................................. 23

Figure 5. Program Operation............................... ........................... 23

Sector Erase Command Sequence ...................... ..................24

Erase Suspend/Erase Resume Commands .......................... .24

Figure 6. Erase Operation.............................................................. 25

Am29PDS322D Command Definitions . . . . . . . . 26

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 27

DQ7: Data# Po l lin g .......... ... .. ............................ ... .. .................27

Figure 7. Data# Polling Algorithm............................................. ..... 27

RY/BY#: Ready/Busy#............................................................ 28

DQ6: Toggle Bit I ....................................................................28

Figure 8. Toggle Bit Algorithm........................................................ 28

DQ2: Toggle Bit II ...................................................................29

Reading Toggle Bits DQ6/DQ2 ............................................... 29

DQ5: Exceeded Timing Limits ................................................29

DQ3: Sector Era s e Time r ..................... ... ................ ...............29

Table 11. Write Operation Sta tus ........................ ...........................30

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31

Figure 9. Maximum Negative Overshoot Waveform...................... 31

Figure 10. Maximum Positi ve Ove rshootWaveform...................... 31

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 31

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. I

SleepCurrents).............................................................................. 33

Figure 12. Typical I

Current vs. Time (Showing Active and Automatic

CC1

vs. Frequency......................................... ... 33

CC1

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Test Setup................... ................................................. 34

Table 12. Test Specifications .........................................................34

Key to Switching Waveforms. . . . . . . . . . . . . . . . 34

Figure 14. Input Waveforms and Measurement Levels ................. 34

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 15. Conventional Read Operation Timings......................... 35

Figure 16. Page Mode Read Timings ............................................ 36

Hardware Reset (RESET#) ....................................... .. ...........37

Figure 17. Reset Timings............................................................... 37

Erase and Program Operations .......................................... .. ..38

Figure 18. Program Operation Timings.......................................... 39

Figure 19. Accelerated Program Timing Diagram.......................... 39

Figure 20. Chip/Sector Erase Operation Timings.......................... 40

Figure 21. Back-to-back Read/Write Cycle Timings ...................... 41

Figure 22. Data# Polling Timings (During Embedded Algorithms). 41

Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 42

Figure 24. DQ2 vs. DQ6................................................................. 42

Temporary Sector Unprotect ..................................................43

Figure 25. Temporary Sector Group Unprotect Timing Diagram... 43 Figure 26. Sector Group Protect and Unprotect Timing Diagram.. 44

Alternate CE# Controlled Erase and Program Operations .....45

Figure 27. Alternate CE# Controlled Write (Erase/Program)

OperationTimings....................... ................................................... 46

Erase And Programming Performan ce. . . . . . . . 47

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 47

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48

FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

12 x 6 mm package ................................................................ 48

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49

August 7, 2002 Am29PDS322D 3

Page 5

ADVANCE INFORMATION

PRODUCT SELECTOR GUIDE

Part Number Am29PDS322D

Speed Options Standard Voltage Range: V

= 1.8–2.2 V 10 12

Max Random Address Acce ss Time (ns) 100 120 Max Page Address Access Time (ns) 40 45 CE# Access Time (ns) 100 120 OE# Access Time (ns) 35 40

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

V V

CC SS

A0–A20

RESET#

WE#

CE#

WP#/ACC

Mux

RY/BY#

A0–A20A0–A20

STATE

CONTROL

& COMMAND REGISTER

Upper Bank Address

Upper Bank

Y-Decoder

X-Decoder

Status

Control

OE#

Latches and Control Logic

DQ0–DQ15

Mux

DQ0–DQ15

A0–A20

Lower Bank Address

Mux

X-Decoder

Lower Bank

Y-Decoder

Latches and

Control Logic

DQ0–DQ15 DQ0–DQ15

4 Am29PDS322D August 7, 2002

Page 6

CONNECTION DIAGRAMS

A6 B6 C6 D6 E6 F6 G6 H6

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

A3 B3 C3 D3 E3 F3 G3 H3

ADVANCE INFORMATION

48-Ball FBGA

Top View, Balls Facing Down

DQ15

DQ13 DQ6DQ14DQ7A11A10A8A9

CC DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

SSNCA16A15A14A12A13

A2 B2 C2 D2 E2 F2 G2 H2

A1 B1 C1 D1 E1 F1 G1 H1

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

DQ9 DQ1DQ8DQ0A5A6A17A7

OE#

SSCE#A0A1A2A4A3

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

August 7, 2002 Am29PDS322D 5

Page 7

ADVANCE INFORMATION

PIN DESCRIPTION

A0–A20 = 21 Addresses inputs DQ0–DQ15 = 16 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect/

Acceleration Input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output

= 1.8 volt-only single power supply

NC = Pin Not Connected Internally

(see Product Selector Guide for

speed options and voltage

supply tolerances)

= Device Ground

LOGIC SYMBOL

A0–A20

CE# OE# WE# WP#/ACC RESET#

DQ0–DQ15

RY/BY#

6 Am29PDS322D August 7, 2002

Page 8

ADVANCE INFORMATION

ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

Am29PDS322D B 10 WM I N

OPTIONAL PROCESSING

Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative fo r more information)

TEMPERATURE RANGE

I = Industrial (–40

PACKAGE TYPE

WM = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 12 mm package (FBD048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SE CTOR ARCHITECTURE

T = Top sector B = Bottom sector

°C to +85°C)

Valid Combinations for FBGA Package

Order Number Package Marking

Am29PDS322DT10, Am29PDS322DB10

Am29PDS322DT12, Am29PDS322DB12

DEVICE NUMBER/DESCRIPTION

Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS Boot Sector Page Mode Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales

WMI

P322DT10U, P322DB10U

P322DT12U, P322DB12U

office to confirm availability of specific valid combinations and to check on newly released combinations.

August 7, 2002 Am29PDS322D 7

Page 9

ADVANCE INFORMATION

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are in itiated through the internal command register. The command register itself does not occupy any addressabl e memory l ocation. The register is a latch used to store the commands, along with the ad dress and da ta information needed to execute the command. The contents of the

Table 1. Am29PDS322D Device Bus Operations

Operation CE# OE# WE# RESET# WP#/ACC

register serve as inputs to the intern al state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control l evels they requir e, and the resultin g output. The following subsections de scribe each of these operations in further detail.

Addresses

(Note 1) DQ0–D Q15

Read L L H H L/H A Write L H L H (Note 2) A Standby VCC ± 0.3 V X X VCC ± 0.3 V H X High-Z Output Disable L H H H L/H X High-Z Reset X X X L L/H X High-Z

Sector Protect (Note 1) L H L V

Sector Unprotect (Note 1) L H L V

Temporary Sector Unprotect X X X V

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 9.0–11.0 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

Notes:

1. The sect or protect and sector unprotect funct ions may also be implemented via programming equipment . See the “Sector/Sect or

Block Protection and Unprotection” section.

2. If WP#/ACC = V

protection depends on whether they were last protected or unprotected using the method described in “Sector/S ec t or Bl o ck Protection and Unprotection”. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

= Data Out

OUT

all sectors will be unprotected.

HH,

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE # and OE # pins to V control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs durin g the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to F igure 15 for the

. CE# is the power

timing diagram. I represents the activ e curren t specific ation for r eading array data.

Read Mode

Random Read (Non-Page Mode Read)

The device has two c ontrol functions which mu st be satisfied in order to obtain data at the outputs. CE# is the power control and should be used for device selection. OE# is the output control and should be used to gate data to the output pins if the device is selected.

Address access t ime (t stable addresses to valid output data. The chip enable access time (t dresses and stable CE# to valid da ta at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least t

ACC–tOE

L/H

(Note 2)

(Note 2) A

CC1

) is the delay from the stable ad-

time).

in the DC Characteristics table

SA, A6 = L,

A1 = H, A0 = L

SA, A6 = H,

A1 = H, A0 = L

) is equal to the delay from

ACC

OUT

8 Am29PDS322D August 7, 2002

Page 10

ADVANCE INFORMATION

Page Mode Read

The device is capable of fast Page mode read and is compatible with the Page mode Mask ROM read operation. This mode provides fast er read access speed for random locations within a page. The Page size of the device is 4 words. T he appropriate Page is selected by the higher address bits A20–A2 and the LSB bits A1–A0 determine the specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location.

The random or initial page access is equal to t

and subsequent Page read accesses (as long as

the locations specified by the microprocessor falls within that Page) are equivalent to t

. When CE# is

PACC

deasserted and reasserted for a subsequent access, the access time is t

or tCE. Here again, CE# selects

ACC

the device and OE# is the output c ontrol and s hould be used to gate data to the output pins if the device is selected. Fast Pag e mode accesses ar e obtained by keeping A2–A20 co nstant and changing A0 to A1 to select the specific word within that page. See Figure 16 for timing specifications.

The following table determines the specific word within the selected page:

ACC

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manu facturing throu ghput at the factory.

If the system asserts V

on this pin, the device auto-

matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protec ted sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle progra m command sequence as required by the Unlock Bypass mode. Removing

from the ACC pin returns the device to normal op-

eration.

Autoselect Functions

If the system writes the autoselect command s equence, the device enters the autoselect mo de. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect M ode and Au toselect Command Sequence sections for more inform ation.

Table 2. Page Word Mode

Word A1 A0

Word 0 0 0 Word 1 0 1 Word 2 1 0 Word 3 1 1

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mo de, only two write cycles are required to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indica tes the address space that each sector occupies.

CC2

tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

, and OE# to VIH.

in the DC Characteristics table represents the ac-

Simultaneous Read/Write Operations with Zero Latency

This device is c apable of r eading da ta from on e bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and w rite cycles may be initiated for simultaneous operation with zero latency. I

CC6

and I

in the DC Characteristics table

CC7

represent the current specifications for read-while-program and read-while-erase, respectively.

Standby Mode

When the system is n ot reading or wri ting to the device, it can place the device in the standby mode. In this mode, current consum ption is greatly reduc ed, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V (Note that this is a more restricted voltage range tha n

.) If CE# and RESET# are held at VIH, but not within

± 0.3 V, the device will be in the s tandby mod e,

but the standby current will be greater. The device requires standard ac cess time (t

) for read access

when the device is in either of these standby modes, before it is ready to read data.

± 0.3 V.

August 7, 2002 Am29PDS322D 9

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ADVANCE INFORMATION

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

in the DC Characte ristics table rep resents the

CC3

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

ACC

+ 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.

Automatic sleep mode current is drawn w hen CE# =

± 0.3 V and all inputs are held at VCC ± 0.3 V. If

CE# and RESET# voltages are not held within these tolerances, the automatic sleep mode current will be greater.

in the DC Char acteristics table r epresents the

CC5

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware me thod of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t device immediately term inates any operation in progress, tristates all output pins, and ignores all read/write command s for the duration o f the RESE T# pulse. The device also resets the internal state ma-

, the

chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V vice draws CMOS standby current (I held at V

but not within V

± 0.3 V, the standby cur-

± 0.3 V, the de-

). If RESET# is

CC3

rent will be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is a sserted during a prog ram or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t Algorithms). The system can read data t RESET# pin returns to V

(not during Embedded

READY

after the

Refer to the AC Characteristics tables for RESET# parameters and to Figure 17 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

10 Am29PDS322D August 7, 2002

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ADVANCE INFORMATION

Bank Sector

SA10 001010xxx 32 050000h–057FFFh SA11 001011xxx 32 058000h–05FFFFh SA12 001100xxx 32 060000h–067FFFh SA13 001101xxx 32 068000h–06FFFFh SA14 001110xxx 32 070000h–077FFFh SA15 001111xxx 32 078000h–07FFFFh SA16 010000xxx 32 080000h–087FFFh SA17 010001xxx 32 088000h–08FFFFh SA18 010010xxx 32 090000h–097FFFh SA19 010011xxx 32 098000h–09FFFFh SA20 010100xxx 32 0A0000h–0A7FFFh SA21 010101xxx 32 0A8000h–0AFFFFh

Bank 2

SA22 010110xxx 32 0B0000h–0B7FFFh SA23 010111xxx 32 0B8000h–0BFFFFh SA24 011000xxx 32 0C0000h–0C7FFFh SA25 011001xxx 32 0C8000h–0CFFFFh SA26 011010xxx 32 0D0000h–0D7FFFh SA27 011011xxx 32 0D8000h–0DFFFFh SA28 011100xxx 32 0E0000h–0E7FFFh SA29 011101xxx 32 0E8000h–0EFFFFh SA30 011110xxx 32 0F0000h–0F7FFFh SA31 011111xxx 32 0F8000h–0FFFFFh SA32 100000xxx 32 100000h–107FFFh SA33 100001xxx 32 108000h–10FFFFh SA34 100010xxx 32 110000h–117FFFh SA35 100011xxx 32 118000h–11FFFFh SA36 100100xxx 32 120000h–127FFFh SA37 100101xxx 32 128000h–12FFFFh SA38 100110xxx 32 130000h–137FFFh SA39 100111xxx 32 138000h–13FFFFh SA40 101000xxx 32 140000h–147FFFh SA41 101001xxx 32 148000h–14FFFFh SA42 101010xxx 32 150000h–157FFFh SA43 101011xxx 32 158000h–15FFFFh

Table 3. Am29PDS322DT Top Boot Sector Addresses

Sector Address

A20–A12

SA0 000000xxx 32 000000h–07FFFh SA1 000001xxx 32 008000h–0FFFFh SA2 000010xxx 32 010000h–17FFFh SA3 000011xxx 32 018000h–01FFFFh SA4 000100xxx 32 020000h–027FFFh SA5 000101xxx 32 028000h–02FFFFh SA6 000110xxx 32 030000h–037FFFh SA7 000111xxx 32 038000h–03FFFFh SA8 001000xxx 32 040000h–047FFFh SA9 001001xxx 32 048000h–04FFFFh

Sector Size

(Kwords)

(x16)

Address Range

August 7, 2002 Am29PDS322D 11

Page 13

Bank Sector

SA44 101100xxx 32 160000h–167FFFh SA45 101101xxx 32 168000h–16FFFFh SA46 101110xxx 32 170000h–177FFFh SA47 101111xxx 32 178000h–17FFFFh SA48 110000xxx 32 180000h–187FFFh SA49 110001xxx 32 188000h–18FFFFh

Bank 2

Bank 1

SA50 110010xxx 32 190000h–197FFFh SA51 110011xxx 32 198000h–19FFFFh SA52 110100xxx 32 1A0000h–1A7FFFh SA53 110101xxx 32 1A8000h–1AFFFFh SA54 110110xxx 32 1B0000h–1B7FFFh SA55 110111xxx 32 1B8000h–1BFFFFh SA56 111000xxx 32 1C0000h–1C7FFFh SA57 111001xxx 32 1C8000h–1CFFFFh SA58 111010xxx 32 1D0000h–1D7FFFh SA59 111011xxx 32 1D8000h–1DFFFFh SA60 111100xxx 32 1E0000h–1E7FFFh SA61 111101xxx 32 1E8000h–1EFFFFh SA62 111110xxx 32 1F0000h–1F7FFFh SA63 111111000 4 1F8000h–1F8FFFh SA64 111111001 4 1F9000h–1F9FFFh SA65 111111010 4 1FA000h–1FAFFFh SA66 111111011 4 1FB000h–1FBFFFh SA67 111111100 4 1FC000h–1FCFFFh SA68 111111101 4 1FD000h–1FDFFFh SA69 111111110 4 1FE000h–1FEFFFh SA70 111111111 4 1FF000h–1FFFFFh

ADVANCE INFORMATION

Table 3. Am29PDS322DT Top Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kwords)

Address Range

(x16)

Bank Sector

SA0 000000000 4 000000h–000FFFh SA1 000000001 4 001000h–001FFFh SA2 000000010 4 002000h–002FFFh SA3 000000011 4 003000h–003FFFh SA4 000000100 4 004000h–004FFFh SA5 000000101 4 005000h–005FFFh SA6 000000110 4 006000h–006FFFh SA7 000000111 4 007000h–007FFFh

Bank 1

SA8 000001xxx 32 008000h–00FFFFh

SA9 000010xxx 32 010000h–017FFFh SA10 000011xxx 32 018000h–01FFFFh SA11 000100xxx 32 020000h–027FFFh SA12 000101xxx 32 028000h–02FFFFh SA13 000110xxx 32 030000h–037FFFh SA14 000111xxx 32 038000h–03FFFFh

Table 4. Am29PDS322DT Top Boot SecSi Sector Address

Sector Address A20–A12 Sector Size (x16) Address Range

111111xxx 32 1F8000h–1FFFFh

Table 5. Am29PDS322DB Bottom Boot Sector Addresses

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

12 Am29PDS322D August 7, 2002

Page 14

Bank Sector

SA15 001000xxx 32 040000h–047FFFh SA16 001001xxx 32 048000h–04FFFFh SA17 001010xxx 32 050000h–057FFFh SA18 001011xxx 32 058000h–05FFFFh SA19 001100xxx 32 060000h–067FFFh SA20 001101xxx 32 068000h–06FFFFh SA21 001110xxx 32 070000h–077FFFh SA22 001111xxx 32 078000h–07FFFFh SA23 010000xxx 32 080000h–087FFFh SA24 010001xxx 32 088000h–08FFFFh SA25 010010xxx 32 090000h–097FFFh SA26 010011xxx 32 098000h–09FFFFh SA27 010100xxx 32 0A0000h–0A7FFFh SA28 010101xxx 32 0A8000h–0AFFFFh SA29 010110xxx 32 0B0000h–0B7FFFh SA30 010111xxx 32 0B8000h–0BFFFFh SA31 011000xxx 32 0C0000h–0C7FFFh SA32 011001xxx 32 0C8000h–0CFFFFh SA33 011010xxx 32 0D0000h–0D7FFFh SA34 011011xxx 32 0D8000h–0DFFFFh SA35 011100xxx 32 0E0000h–0E7FFFh SA36 011101xxx 32 0E8000h–0EFFFFh SA37 011110xxx 32 0F0000h–0F7FFFh SA38 011111xxx 32 0F8000h–0FFFFFh

Bank 2

SA39 100000xxx 32 100000h–107FFFh SA40 100001xxx 32 108000h–10FFFFh SA41 100010xxx 32 110000h–117FFFh SA42 100011xxx 32 118000h–11FFFFh SA43 100100xxx 32 120000h–127FFFh SA44 100101xxx 32 128000h–12FFFFh SA45 100110xxx 32 130000h–137FFFh SA46 100111xxx 32 138000h–13FFFFh SA47 101000xxx 32 140000h–147FFFh SA48 101001xxx 32 148000h–14FFFFh SA49 101010xxx 32 150000h–157FFFh SA50 101011xxx 32 158000h–15FFFFh SA51 101100xxx 32 160000h–167FFFh SA52 101101xxx 32 168000h–16FFFFh SA53 101110xxx 32 170000h–177FFFh SA54 101111xxx 32 178000h–17FFFFh SA55 111000xxx 32 180000h–187FFFh SA56 110001xxx 32 188000h–18FFFFh SA57 110010xxx 32 190000h–197FFFh SA58 110011xxx 32 198000h–19FFFFh SA59 110100xxx 32 1A0000h–1A7FFFh SA60 110101xxx 32 1A8000h–1AFFFFh SA61 110110xxx 32 1B0000h–1B7FFFh SA62 110111xxx 32 1B8000h–1BFFFFh

ADVANCE INFORMATION

Table 5. Am29PDS322DB Bottom Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

August 7, 2002 Am29PDS322D 13

Page 15

Bank Sector

SA63 111000xxx 32 1C0000h–1C7FFFh SA64 111001xxx 32 1C8000h–1CFFFFh SA65 111010xxx 32 1D0000h–1D7FFFh SA66 111011xxx 32 1D8000h–1DFFFFh

Bank 2

SA67 111100xxx 32 1E0000h–1E7FFFh SA68 111101xxx 32 1E8000h–1EFFFFh SA69 111110xxx 32 1F0000h–1F7FFFh SA70 111111xxx 32 1F8000h–1FFFFFh

ADVANCE INFORMATION

Table 5. Am29PDS322DB Bottom Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address

Sector Address

A20–A12 Sector Size

000000xxx 32 00000h-07FFFh

Address Range

(x16)

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ADVANCE INFORMATION

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is prim arily intend ed for progr amming equi pment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register .

When using programming equipment, the autoselect mode requires V Address pins A6, A1, and A0 must be as shown in

Description CE# OE# WE#

Manufacturer ID: AMD

Device ID Word 1 L L H X X V Device ID Word 2 L L H X X V Device ID Word 3:

Top or Bottom Boot Sector Protection

Verification SecSi Indicator Bit

(DQ7), WP# protects highest address sector

(8.5 V to 12.5 V) on address pin A9.

Table 7. Autoselect Codes (High Voltage Method)

A20

A11

A12

A10 A9

LLH X XV

LLHSAXV

LLH X XV

Table 7. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 3 through 6). Table 7 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 10. This method does not require V

. Refer to the Autoselect Com-

mand Sequence section for more information.

A7 A6

X L X X X L L 0001h

XLXLLLH 227Eh

X L X H H H L 2206h

XLXHHHH

XLXXXHL

XLXXXHH

A4 A3 A2 A1 A0 DQ15 to DQ0

2201h (Top Boot),

2200h (Bottom Boot)

XX01h (protected),

XX00h (unprotected)

80h (factory locked),

00h (not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

August 7, 2002 Am29PDS322D 15

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ADVANCE INFORMATION

Sector/Sector Block Protection and Unprotection

(Note: For the following discussion, the term “sector” applies to both sectors and s ector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9).

Tabl e 8. Top Boot Sect or/Sector Block Addresses

for Protection/Unprotection

Sector Group Sectors A20–A12

SGA0 SA0 000000XXX 64 (1x64) Kbytes SGA1 SA1–SA3 00001XXXX 192 (3x64) Kbytes SGA2 SA4–SA7 0001XXXXX 256 (4x64) Kbytes SGA3 SA8–SA11 0010XXXXX 256 (4x64) Kbytes SGA4 SA12–SA15 0011XXXXX 256 (4x64) Kbytes SGA5 SA16–SA19 0100XXXXX 256 (4x64) Kbytes SGA6 SA20–SA23 0101XXXXX 256 (4x64) Kbytes SGA7 SA24–SA27 0110XXXXX 256 (4x64) Kbytes SGA8 SA28–SA31 0111XXXXX 256 (4x64) Kbytes

SGA9 SA32–SA35 1000XXXXX 256 (4x64) Kbytes SGA10 SA36–SA39 1001XXXXX 256 (4x64) Kbytes SGA11 SA40–SA43 1010XXXXX 256 (4x64) Kbytes SGA12 SA44–SA47 1011XXXXX 256 (4x64) Kbytes SGA13 SA48–SA51 1100XXXXX 256 (4x64) Kbytes SGA14 SA52–SA55 1101XXXXX 256 (4x64) Kbytes SGA15 SA56–SA59 1110XXXXX 256 (4x64) Kbytes SGA16 SA60–SA62 111100XXX 192 (3x64) Kbytes SGA17 SA63 111111000 8 Kbytes SGA18 SA64 111111001 8 Kbytes SGA19 SA65 111111010 8 Kbytes SGA20 SA66 111111011 8 Kbytes SGA21 SA67 111111100 8 Kbytes SGA22 SA68 111111101 8 Kbytes SGA23 SA69 111111110 8 Kbytes SGA24 SA70 111111111 8 Kbytes

Sector/

Sector Block Size

Table 9. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector Group Sectors A20–A12

SGA0 SA70 111111XXX 64 (1x64) Kbytes SGA1 SA69–SA67 11110XXXX 192 (3x64) Kbytes SGA2 SA66–SA63 1110XXXXX 256 (4x64) Kbytes SGA3 SA62–SA59 1101XXXXX 256 (4x64) Kbytes SGA4 SA58–SA55 1100XXXXX 256 (4x64) Kbytes SGA5 SA54–SA51 1011XXXXX 256 (4x64) Kbytes SGA6 SA50–SA47 1010XXXXX 256 (4x64) Kbytes SGA7 SA46–SA43 1001XXXXX 256 (4x64) Kbytes SGA8 SA42–SA39 1000XXXXX 256 (4x64) Kbytes

SGA9 SA38–SA35 0111XXXXX 256 (4x64) Kbytes SGA10 SA34–SA31 0110XXXXX 256 (4x64) Kbytes SGA11 SA30–SA27 0101XXXXX 256 (4x64) Kbytes SGA12 SA26–SA23 0100XXXXX 256 (4x64) Kbytes SGA13 SA22–SA19 0011XXXXX 256 (4x64) Kbytes SGA14 SA18–SA15 0010XXXXX 256 (4x64) Kbytes SGA15 SA14–SA11 0001XXXXX 256 (4x64) Kbytes SGA16 SA10–SA8 000011XXX 192 (3x64) Kbytes SGA17 SA7 000000111 8 Kbytes SGA18 SA6 000000110 8 Kbytes SGA19 SA5 000000101 8 Kbytes SGA20 SA4 000000100 8 Kbytes SGA21 SA3 000000011 8 Kbytes SGA22 SA2 000000010 8 Kbytes SGA23 SA1 000000001 8 Kbytes SGA24 SA0 000000000 8 Kbytes

Sector/Sector

Block Size

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previou sly protected sectors. Sector protection and unprotection can be implemented via two methods.

The primary method requires V

on the RESET# pin

only, and can be implemented either in-system or via programming equipment. Figure 3 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.

16 Am29PDS322D August 7, 2002

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ADVANCE INFORMATION

The alternate method intended only for programming equipment requires V

on address pin A9 and OE#.

This method is compatible with programmer routines written for earlier AMD flash devices. Contact an AMD representative for further details.

The device is shipped with all sectors unpr otected. AMD offers the option of pro grammin g and protectin g sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting certain boot sectors without using V WP#/ACC pin.

If the system asserts V vice disables program and erase functions in the two “outermost” 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Th e two outermost 8 Kbyte boot sectors are the two sectors containing th e lowest addresses in a bottom-b oot-configured devic e, or the two sectors containing the highest addresses in a top-boot-configured device.

If the system asserts V vice reverts to whether the two oute rmost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depe nds on w hethe r they we re las t protec ted or unprotected using the method described in “Sec- tor/Sector Block Protection and Unprotection”.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

. This function is one of two provided by the

on the WP#/ACC pin, the de-

block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9).

This feature al lows tempor ary unprotec tion of prev iously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V

(9.0 V – 11.0 V). During this mode,

formerly protected sectors can be progr ammed or erased by selecting the sector addresses. Once V

removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature.

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will rem ain protec ted ).

2. All previously protected sectors are protected once again.

Temporary Sector/Sector Block Unprotect

Figure 1. Temporary Sector Unprotect Operation

(Note: For the following discussion, the term “sector” applies to both sectors and s ector blocks. A sector

August 7, 2002 Am29PDS322D 17

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ADVANCE INFORMATION

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Group Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V the first or last sector will remain protected).

2. All previou sly prot ect ed sec tor gro ups are prote cte d once again.

Figure 2. Temporary Sector Group Unprotect

Operation

18 Am29PDS322D August 7, 2002

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ADVANCE INFORMATION

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors

protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Sector Unprotect

complete

Figure 3. In-System Sector Group Protect/Unprotect Algorithms

August 7, 2002 Am29PDS322D 19

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ADVANCE INFORMATION

SecSi (Secured Silicon) Sector Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 KBytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the fie ld.

AMD offers the device with the SecSi Sector either factory locked or customer lockable. The factory-locked version is alw ays protected when shipped from the factory, and has the SecSi (S ecured Silicon ) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allo wing customers to u tilize that sector in any manner they choose. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thu s, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked.

The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequ ence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the bo ot sectors ins tead of th e SecSi sector

Factory Locked: SecSi Sector Programmed and Protected at the Factory

In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is availab le preprogra mmed with on e of the following:

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

In devices th at have an ESN , a Bottom Bo ot device will have the 16-byte ESN in the low est addressable memory area at addresses 000000h–000007h. In the Top Boo t device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses 1F8000h–1F8007h.

Customers may opt to have their code pro grammed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the random ESN. The device s are then shippe d from AMD’s factory with the permane ntly locked . Contact an A MD representative for details on using AMD’s ExpressFlash service.

Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory

If the security feature is not required, the SecSi Sector can be treated as an additional Flash me mo ry s pa c e, exp an di ng t h e si ze of the available Flash array by 64 Kbytes. The SecSi Sector can be read, programmed, and erased as often as required. The SecSi Sector area can be protected using one of the following procedures:

■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 3, except that RESET# may be at either V

or VID. This

allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicabl e to the SecSi Sector.

■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection” sec- tion.

Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command seq uence to return to reading and wr iting the remainder of the array.

The SecSi Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data pro tection against inadvertent writes (refer to Table 10 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V and power-down transitions, or from system noise.

Low V

When V

Write Inhibit

is less than V

, the device does not ac-

LKO

cept any write cycles. This protects data during V power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent

power-up

20 Am29PDS322D August 7, 2002

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ADVANCE INFORMATION

writes are igno red unti l VCC is greater than V

LKO

. The system must provide the proper signals to the control pins to prevent unintentional writes when V greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

COMMAND DEFINITIONS

Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 defines the valid regis ter command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All dat a is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device powe r-up. No com mand s ar e requ ired t o retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information.

The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device i s in the autoselect mod e. See the next section, Reset Command, for more information.

See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 15 shows the timing diagram.

Reset Command

Writing the reset command resets the device to the read or erase-sus pend-read mod e. Address bi ts are don’t cares for this command.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Wri t e Inhibit

If WE# = CE# = V

and OE# = VIH during power up,

the device does not accept commands on the rising edge of WE#. The internal s tate machine is automatically reset to the read mode on power-up.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written betwee n the sequence cycles in a program c ommand sequence before programming begins. This resets the device to the read mode. If the pr ogram com mand sequ ence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be wr itten to r eturn to the read mode. If the de vice entered the autosel ect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Tab le 10 shows the address an d data require ments. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and requires V mand sequence may be written to an address that is either in the read or er ase-suspend- read mode. Th e autoselect command may not be wr itten while the device is actively programming or erasing.

The a utoselect comman d sequen ce is initia ted by wri ting two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode,

on address pin A9. The autosel ect com-

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ADVANCE INFORMATION

and the system may read any number of autoselect codes without reinitiating the command sequence.

Table 10 shows the address and data requirements for the command sequence. To determine sector protection information, the system must write to the appropriate sector group address (SGA). Tables 3 and 5 show the address range associated with each sector.

The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).

Enter SecSi Sector/Exit SecSi Sector Command Sequence

The SecSi Sector region provides a secured data area containing an 16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal op eration. Table 10 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash M emory Region” for further information. Note that a hardware reset (RESET#=V

) will reset the device to

reading array data.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program addr ess and data are wr itten next, which in tur n initiate the Embedd ed Program algorithm. The system is not required to pro vide furthe r controls or timings. The device automatically provides internally generated program pulses and verifies th e programmed cell margin. Table 10 shows the address and data requirements for the program command sequence.

When the Emb edded P rogram algori thm is c omple te, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits.

Any commands wr itten to the dev ice during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” On ly erase operations ca n convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program words to the device faster than using the standard program command s equence. The unlock bypass command s equence is in itiated by first w riting two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock b ypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 10 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypa ss Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to reading array data. See Figu re 4 for the unlock bypass algorithm.

The device offers accelerated program operations through the WP#/ACC pin. When the system asserts

on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The de vice us es the hig her voltag e on the WP#/ACC pin to acc elerate the ope ration. Note th at the WP#/ACC pin must not be at V

any operation

other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock

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ADVANCE INFORMATION

Increment

Address

Start

555h/AAh

2AAh/55h

555h/20h

XXXh/A0h

Program Address/Program Data

Data# Polling Device

Verify Byte?

Yes

Last Address

Yes

Set Unlock Bypass Mode

In Unlock Bypass Program

START

Write Program

Command Sequence

Data Poll

Embedded

algorithm

in progress

Increment Address

Program

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Note: See Table 10 for program command sequence.

Programming Completed

(BA) XXXh/90h

XXXh/F0h

Figure 4. Unlock Bypass Algorithm

Reset Unlock Bypass Mode

Figure 5. Program Operation

cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 10 shows the address and data requirements for the chip erase command sequence.

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ADVANCE INFORMATION

When the Embedded Erase algorithm is complete, the device returns to the read mode and add resses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately termina tes the erase operation. If tha t occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.

Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operation s tables in the AC Characteristics sectio n for parameters, and Figure 20 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 10 shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and v erifies the entire m emory for an all zero data pattern prior to electrica l erase. The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com mands may be written. Loading the sector e rase buf fer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all comm ands are accepted . The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than

Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command se-

quence and any additional addresses and commands. The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can determine the status of the erase o peration by readin g DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to the Write Operation Status section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the er ase operation. If that occurs, the sector erase command seq uence should be reinitiated once the device has returned to reading array data, to ensure data integrity.

Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operatio ns tables in the AC Characteristics sectio n for parameters, and Figure 20 section for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.

After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Note that unlock bypass programming is not allowed when the device is erase-suspended.

Reading at any add ress within e rase-suspe nded sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits.

After an eras e-sus pende d prog ram o pera tion is complete, the device returns to the erase-suspend-read

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mode. The system can determine the status of the program oper ation u sing the DQ7 or DQ6 s tatus bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information.

START

In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details.

To resume the sect or erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend com mand can be written after the chip has resumed erasing.

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Notes:

1. See Table 10 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Data = FFh?

Yes

Erasure Completed

Embedded Erase algorithm in progress

Figure 6. Erase Operation

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ADVANCE INFORMATION

Table 10. Am29PDS322D Command Definitions

Command Sequence

(Note 1)

Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001 Device ID (Note 9) 6 555 AA 2AA 55 555 90 X01 227E X0E 2206 X0F SecSi Sector Fa ctory

Protect (Note 10) Sector Group Protect Verify

Autoselect (Note 8)

(Note 11) Enter SecSi Sector Region 3 555 AA 2AA 55 555 88 Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass

Unlock Bypass Program (Note 12) Unlock Bypass Reset (Note 13) Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend (Note 14) 1 BA B0 Erase Resume (Note 15) 1 BA 30

Legend:

X = Don’t care RA = Address of the memory location to be read. RD = Data re ad from location RA duri ng read operation. PA = Addre ss of the me mo ry lo catio n to b e pr ogramme d. Addre sses

latch on the falling edge of the WE# or CE# pulse, whichever happens later.

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 555 AA 2AA 55 555 90 X03 80/00

4 555 AA 2AA 55 555 90

555 AA 2AA 55 555 20

XXX A0 PA PD

XXX 90 XXX 00

Bus Cycles (Notes 2–5)

2201/

2200

(SGA)

X02

PD = Data to be programmed at location PA. Data latches on the risi ng edge of WE# or CE# pulse, whichever happens first.

SGA = Address of the sector group to be verified (in autoselect mode) or erased. A ddress bits A20–A12 uniquely select any sector.

XX00/

XX01

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth and fifth cycle of the autoselect command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.

5. Unless otherwise noted, address bits A20–A12 are don’t cares in unlock sequence.

6. No unlock or command cycles required when device is in read mode.

7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information).

8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information.

9. The device ID must be read across the fourth, fifth and sixth cycles. The sixth cycle specifies 2201h for top boot or 2200h for bottom boot.

10. The data is 80h for factory locked and 00h for not factory locked.

11. The data is 00h for an unprotected sector group and 01h for a protected sector group.

12. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

13. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode.

14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase

15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.

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WRITE OPERATION STATUS

The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 1 1 and the following s ubsections descr i be the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Eras e operation is in progress or has been completed.

invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.

Table 11 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algorithm. Figure 22 in the AC Characteristics section shows the Data# Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the comma nd sequence .

During the Embedded Prog ram algorithm, the devi ce outputs on DQ7 the complement of t he datum pr ogr ammed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When t he Embedded Pr ogram algorit hm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status in formation on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode.

During the Embedd ed Erase algorith m, Data# Pollin g produces a “0” on DQ7. When the Embedde d Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to r ead valid statu s information on DQ7.

START

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

After an erase com mand sequen ce is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then

DQ7 = Data?

Yes

the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpr otected secto rs, and i gnores the se-

lected sectors that are protected. However, if the system reads DQ7 at an address withi n a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has com-

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

PASS

pleted the program or er ase operation and D Q7 has valid data, the data outputs on DQ0–DQ6 may be still

Figure 7. Data# Polling Algorithm

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RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

If the output is low (Busy), the device is active ly erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode.

Table 11 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in pro gress or complete, or whether the device has entered the Erase Suspend mo de. Toggle Bit I m ay be re ad at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and d uring the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are pr otect ed, DQ6 t oggles f or appr oximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected se ctors, and ignores the selected sectors that are prot ected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progre ss), DQ6 t oggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data.

Tabl e 11 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 23 in the “AC Characteristics” section shows the toggle bit timing diagrams. F igure 24 shows th e differences b etween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

START

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 a nd DQ2 for more information.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not Complete, Write Reset Command

Program/Erase

Operation Complete

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro-

Figure 8. Toggle Bit Algorithm

gram algorithm is complete.

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DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspe nded. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively era sing or is e rase-suspended. DQ6, by comparis on, indicates whether th e device is actively erasing, or is in Erase Suspend, but cannot distinguish wh ich sectors ar e selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 11 to compare outputs for DQ2 and DQ6.

Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 23 shows the toggle bit timing diagr am. Figure 24 shows the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the va lue of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the tog gle bit is still togg ling, the sys tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine ag ain whether the toggle bit is to ggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.

The remaining s cenario is that th e system initia lly determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or eras e time has exceeded a specified int ernal pulse cou nt limit. Under t hese conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timi ng limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determ ine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase com mand.) If additional sectors are selected for erasure, the entire time-out also applies afte r each a dditional se ctor eras e command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the tim e between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will acce pt additional sector eras e com mands. To ensure the com mand ha s been ac cepted, the sys tem software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the sec ond status ch eck, the last command might not have been accepted.

Table 11 shows the status of DQ3 relative to the other status bits.

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Table 11. Write Operation Status

DQ7

Status

Standard

Mode

Erase

Suspend

Mode

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to t he appro priate subsect ion f or fur ther detail s.

Embedded Program Algo rith m DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorith m 0 Toggle 0 1 Toggle 0

Erase

Erase-Suspend-

Read

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Suspended Sector Non-Erase

Suspended Sector

(Note 2) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

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ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . . . –0.5 V to +11 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +12.6 V

All other pins (Note 1). . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V Maximum DC voltage on input or I/O pins is V See Figure 9. During voltage transitions, input or I/O pins may overshoot to V Figure 10.

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on p in A9 is +12.5 V which m ay overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +12.6 V which may overshoot to +12.0 V for periods up to 20 ns.

3. No more than on e output ma y be shorted to ground at a time. Duration of the short c ircuit should n ot be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other co nditions above those i ndicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended per iod s may affe ct dev ice relia bili ty.

to –2.0 V for pe riods of up to 20 ns.

+2.0 V for periods up to 20 ns. See

+0.5 V

+0.5 V.

+0.8 V

–0.5 V –2.0 V

+2.0 V

+0.5 V

2.0 V

20 ns

Figure 9. Maximum Negative

Overshoot Waveform

20 ns

Figure 10. Maximum Positive

Overshoot Waveform

20 ns

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T

Supply Voltages

for standard voltage range . . . . . . .1.8 V to 2.2 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

August 7, 2002 Am29PDS322D 31

) . . . . . . . . . –40°C to +85°C

Page 33

ADVANCE INFORMATION

DC CHARACTERISTICS CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max U nit

Input Load Current VIN = VSS to VCC, VCC = VCC

= V

A9 Input Load Current

Output Leakage Curren t V VCC Active Inter-Page Read Current

(Notes 1, 2)

A9, OE#, RESET# = 11 V

= VSS to VCC, VCC = V

OUT

CE# = V

VCC Active Write Current (Notes 2, 3) CE# = V

;

CC max

OE# = VIH,

IL,

OE# = VIH 15 30 mA

IL,

max

CC max

1 MHz 2.5 3

10 MHz 24 28

VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 5 µA

VCC Reset Current (Note 2)

VCC Automatic Sleep Mode Curren t (Notes 2, 4)

VCC Active Read-While-Program Current (Notes 1, 2, 5)

VCC Active Read-While-Erase Current (Notes 1, 2, 5)

WP#/ACC = V RESET# = V

CE# = V

RESET# = V

= V

CE# = V

IL,

± 0.3 V,

± 0.3 V

± 0.3 V;

± 0.3 V,

± 0.3 V or V

OE# = V

, OE# = V

± 0.3 V

CC1

CC2

CC3

CC4

CC5

CC6

CC7

LIT

VCC Active

CC8

Program-While-Erase-Suspended

CE# = V

, OE# = V

Current (Note 2)

10 MHz 0.5 1

CC9

ACC

V V

VCC Active Intra-Page Read Current CE# = VIL, OE# = V

WP#/ACC Accelerate d Prog ram Current

Input Low Voltage –0.5 VCC x 0.2 V

Input High Voltage 0.8 x V

= V

CCMax

20 MHz 1 2

, WP#/ACC = V

ACCMax

Voltage for WP#/ACC Sector

ACC

Protect/Unprotect and Program

= 1.8–2.2 V 8.5 12.5 V

Acceleration

V V

LKO

Voltage for Autoselect and Temporary

Sector Unprotect Output Low Voltage IOL = 100 µA, VCC = V

Output High Voltage IOH = –100 µA V

= 1.8–2.2 V 9 11 V

0.1 V

CC min

Low VCC Lock-Out Voltage 1.2 1.5 V

Notes:

1. The I

2. Maximum I

3. I

current listed is typically less than 2 mA/MHz, with OE# at VIH.

specifications are tested with VCC = VCCmax.

active while Embedded Erase or Embedded Prog ram is in pr ogress.

4. Automatic sleep mode enables the low power mode when addresses remain stabl e for 150 ns.

5. Embedded algorithm (program or erase) is in progress (at 8 MHz).

0.1 5 µA

0.2 5 µA

30 55 mA

17 35 mA

12 20 mA

– 0.1 V

±1.0 µA

35 µA

±1.0 µA

VCC + 0.3 V

32 Am29PDS322D August 7, 2002

Page 34

DC CHARACTERISTICS Zero-Power Flash

Supply Current in mA

0 500 1000 1500 2000 2500 3000 3500 4000

ADVANCE INFORMATION

Time in ns

Note: Addresses are switching at 1 MHz

Figure 11. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

Supply Current in mA

2.0 V

13578

246

Frequency in MHz

Note: T = 25 °C

Figure 12. Typical I

vs. Frequency

CC1

August 7, 2002 Am29PDS322D 33

Page 35

TEST CONDITIONS

Device

Under

Test

ADVANCE INFORMATION

Table 12. Test Specifications

Test Condition 10 12 Unit

Output Load Capacitance, C (including jig capacitance)

Input Rise and Fall Times 5 ns Input Pulse Levels 0.0–2.0 V V

30 100 pF

Note: Diodes are IN3064 or equivalent

Figure 13. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Input timing measurement reference levels

Output timing measurement reference levels

Steady

Changing from H to L

Changing from L to H

1.0 V

KS000010-PAL

0.5 V

1.0 V

OutputMeasurement LevelInput

0.0 V

Figure 14. Input Waveforms and Measurement Levels

34 Am29PDS322D August 7, 2002

Page 36

AC CHARACTERISTICS Read-Only Operations

ADVANCE INFORMATION

Parameter

JEDEC Std 10 12 Unit

AVAV

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

Description Test Setup

Read Cycle Time (Note 1) Min 100 120 ns

Address to Output Delay CE#, OE# = V

ACC

Page Read Cycle Min 40 50 ns

PRC

Page Address to Output Delay CE#, OE# = V

PACC

Chip Enable to Output Delay OE# = V

Output Enable to Output Delay Max 35 50 ns

Chip Enable to Output High Z (Notes 1, 3) Max 16 ns

Output Enable to Output High Z (Notes 1, 3) Max 16 ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

Max 100 120 ns

Max 40 50 ns

Max 100 120 ns

Min 0 ns

Speed Option

Read Min 0 ns

Output Enable Hold

OEH

Time (Note 1)

Toggle and Data# Polling

Min 10 ns

Notes:

1. Not 100% tested.

2. See Figure 13 and Tabl e 12 f or t est spec ifi cations .

3. Measurements performed by placing a 50Ω termination on the data pin with a bias of V data bus driven to V

/2 is taken as tDF.

/2. The time from OE# high to the

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

ACC

OEH

HIGH Z

Output Valid

Figure 15. Conventional Read Operation Timings

HIGH Z

August 7, 2002 Am29PDS322D 35

Page 37

AC CHARACTERISTICS

ADVANCE INFORMATION

A20 to A2

A1 to A0

CE#

OE#

WE#

Output

Same page Addresses

Aa Ab Ac Ad

OEH

High-Z

ACC

PRC

PACC

Da Db Dc Dd

Figure 16. Page Mode Read Timings

PRC

PACC

36 Am29PDS322D August 7, 2002

Page 38

AC CHARACTERISTICS Hardware Reset (RESET#)

Parameter

ADVANCE INFORMATION

Description All Speed Options UnitJEDEC Std

Ready

RPD

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note)

Max 20 µs

Max 500 ns

RESET# Pulse Width Min 500 ns Reset High Time Before Read (See Note) Min 200 ns RESET# Low to Standby Mode Min 20 µs RY/BY# Recovery Time Min 0 ns

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

RY/BY#

CE#, OE#

RESET#

Figure 17. Reset Timings

August 7, 2002 Am29PDS322D 37

Page 39

ADVANCE INFORMATION

AC CHARACTERISTICS Erase and Program Operations

Parameter Speed Option

JEDEC Std Description 10 12 Unit

AVAV

AVWL

WLAX

DVWH

WHDX

GHWL

ELWL

WHEH

WLWH

WHDL

WHWH1

WHWH2

ASO

AHT

t t

CEPH

OEPH

GHWL

t t

WPH

SR/W

WHWH1

WHWH2

VCS

BUSY

Write Cycle Time (Note 1) Min 100 120 ns Address Setup Time Min 0 ns

Address Setup Time to OE# low during toggle bit polling Min 15 ns Address Hold Time Min 60 ns

Address Hold Time From CE# or OE# high during toggle bit polling

Data Setup Time Min 60 ns

Data Hold Time Min 0 ns

Chip Enable High during toggle bit polling Min 20 ns Output Enable High during toggle bit polling Min 20 ns Read Recovery Time Before Write

(OE# High to WE# Low) CE# Setup Time Min 0 ns

CE# Hold Time Min 0 ns

Write Pulse Width Min 60 ns

Write Pulse Width High Min 60 ns Latency Between Read and Write Operations Min 0 ns Programming Operation (Note 2) Typ 11 µs Accelerated Programming Operation (Note 2) Typ 5 µs Sector Erase Operation (Note 2) Typ 1 sec VCC Setup Time (Note 1) Min 50 µs Write Recovery Time from RY/BY# Min 0 ns

Program/Erase Valid to RY/BY# Delay Min 90 ns

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Min 0 ns

38 Am29PDS322D August 7, 2002

Page 40

AC CHARACTERISTICS

ADVANCE INFORMATION

Addresses

CE#

OE#

WE#

Data

RY/BY#

Program Command Sequence (last two cycles)

PA PA

WPH

555h

A0h

VCS

Read Status Data (last two cycles)

WHWH1

BUSY

Status

OUT

ote: PA = program address, PD = program data, D

Figure 18. Program Operation Timings

or V

ACC

IH V

VHH

Figure 19. Accelerated Program Timing Diagram

is the true data at the program address.

OUT

VHH

or V

August 7, 2002 Am29PDS322D 39

Page 41

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

ADVANCE INFORMATION

555h for chip erase

Addresses

2AAh SA

CE#

55h

WPH

30h

10 for Chip Erase

BUSY

WHWH2

Progress

Complete

OE#

WE#

Data

RY/BY#

VCS

Notes:

1. SA = sector address (for Sector Erase), V A = Valid Address for reading status data (see “Write Operation Status”).

Figure 20. Chip/Sector Erase Operation Timings

40 Am29PDS322D August 7, 2002

Page 42

AC CHARACTERISTICS

ADVANCE INFORMATION

Addresses

CE#

OE#

WE#

Data

WPH

Valid PA

Valid

OEH

Valid RA

ACC

SR/W

Valid

Out

Read Cycle

GHWL

Figure 21. Back-to-back Read/Write Cycle Timings

Valid PA

Valid

CE# Controlled Write CyclesWE# Controlled Write Cycle

CPH

Valid PA

Valid

Addresses

ACC

VA VA

CE#

OE#

OEH

WE#

DQ7

DQ0–DQ6

BUSY

Complement

Status Data

Complement

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 22. Data# Polling Timings (During Embedded Algorithms)

August 7, 2002 Am29PDS322D 41

Page 43

AC CHARACTERISTICS

ADVANCE INFORMATION

AHT

Addresses

ASO

CE#

OEH

WE#

OE#

DQ6/DQ2 Valid Data

RY/BY#

Valid Data

(first read) (second read) (stops toggling)

Valid

Status

OEPH

Valid

Status

CEPH

AHT

Valid

Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

WE#

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

42 Am29PDS322D August 7, 2002

Page 44

ADVANCE INFORMATION

AC CHARACTERISTICS Temporary Sector Unprotect

Parameter

Description All Speed Options UnitJEDEC Std

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

VHHVHH

RSP

Rise and Fall Time (See Note) Min 500 ns

RESET# Setup Time for Temporary Sector/Sector Block Unprotect

Min 4 µs

RRB

Note: Not 100% tested.

RESET#

VSS, VIL, or V

CE#

WE#

RY/BY#

RESET# Hold Time from RY/BY# High for Temporary Sector/Sector Block Unprotect

VIDR

Min 4 µs

Program or Erase Command Sequence

RSP

RRB

Figure 25. Temporary Sector Group Unprotect Timing Diagram

VIDR

VSS, VIL,

or V

August 7, 2002 Am29PDS322D 43

Page 45

AC CHARACTERISTICS

RESET#

ADVANCE INFORMATION

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector/Sector Block Protect or Unprotect Verify

Data

60h 60h 40h

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#

WE#

OE#

For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector Group Protect and Unprotect Timing Diagram

Status

44 Am29PDS322D August 7, 2002

Page 46

ADVANCE INFORMATION

AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations

Parameter Speed Option

JEDEC Std Description 10 12 Unit

AVAV

AVWL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

WHWH1

WHWH2

t t t

GHEL

CPH

WHWH1

WHWH2

Write Cycle Time (Note 1) Min 100 120 ns

Address Setup Time Min 0 ns

Address Hold Time Min 60 ns

Data Setup Time Min 60 ns

Data Hold Time Min 0 ns

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time Min 0 ns

WE# Hold Time Min 0 ns

CE# Pulse Width Min 60 ns

CE# Pulse Width High Min 60 ns Programming Opera tion (Note 2) Typ 16 µs Accelerated Programming Operation (Note 2) Typ 5 5 µs Sector Erase Operation (Note 2) Typ 1 sec

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Min 0 ns

August 7, 2002 Am29PDS322D 45

Page 47

AC CHARACTERISTICS

ADVANCE INFORMATION

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program 2AA for erase

PA for program SA for sector erase 555 for chip erase

GHEL

CPH

A0 for program 55 for erase

BUSY

PD for program 30 for sector erase 10 for chip erase

Data# Polling

WHWH1 or 2

DQ7# D

OUT

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = prog ram data .

3. DQ7# is the complement of the data wri tten to t he devic e. D

is the data written to the devic e.

OUT

4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

46 Am29PDS322D August 7, 2002

Page 48

ADVANCE INFORMATION

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 10 sec Chip Erase Time 93 sec

Word Program Time 16 360 µs

Excludes 00h programming

prior to erasure (Note 4)

Excludes system level

overhead (Note 5) Accelerated Word Program Time 5 µs Chip Program Time (Note 3) 20 100 sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 2.0 V V

, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 1.8 V , 1,000,000 cycle s.

3. The typical chip programming time is considerably less than t he maxi mum chip programmi ng time lis ted, s ince most words program faster than the maximum program t imes l isted .

4. In the pre-programming step of the Embedded Erase algorithm, all bits are pr ogrammed to 00h bef ore er asure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command defin ition s.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V (including A9, OE#, and RESE T#)

on all pins except I/O pins

–1.0 V 12.5 V

Input voltage with respect to V

Current –100 mA +100 mA

on all I/O pins –1.0 V VCC + 1.0 V

Note: Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.

DATA RETENTION

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10Years 125°C20Years

August 7, 2002 Am29PDS322D 47

Page 49

ADVANCE INFORMATION

PHYSICAL DIMENSIONS FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 12 mm package

xFBD 048

6.00 mm x 12.00 mm PACKAGE

0.20

0.84

0.94

12.00 BSC

6.00 BSC

5.60 BSC

4.00 BSC

0.25 0.30

0.35

0.80 BSC

Dwg rev AF; 1/2000

1.20

0.40 BSC

* For reference only. BSC is an ANSI standard for Basic Space Centering.

48 Am29PDS322D August 7, 2002

Page 50

ADVANCE INFORMATION

REVISION SUMMARY Revision A (December 4, 2000)

Initial release.

Revision A+1 (February 16, 2001)

Erase Suspend/Erase Resume Commands

Noted in the third paragraph that unlock bypass programming is not allowed when the device is erase suspended.

Ordering Information

Added “U” des ignator to package markin g. Deleted burn-in option.

Revision A+2 (August 31, 2001)

Autoselect Command Sequence

Modified sectio n to point to approp riate tables for autoselect functions.

Revision A+3 (February 18, 2002)

Global

Removed “Advance Information” designation from data sheet.

Revision A+4 (August 7, 2002)

Distinctive Characteristics

Removed “Supports Common Flash Memory Interface (CFI))

Table 10. Am29PDS322D Command Definitions

Changed the Command Cycle Device ID cycle from 6 to 4.

Trademarks

Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies

August 7, 2002 Am29PDS322D 49