Datasheet Am29LV160DT-120FI, Am29LV160DT-120FE, Am29LV160DT-120FC, Am29LV160DT-120EE, Am29LV160DT-120EC Datasheet (AMD Advanced Micro Devices)

Am29LV160D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-onl y Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3. 0 to 3.6 volt read and

write operations and for compatibility with high
performance 3.3 volt microprocessors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Manufactured on 0.23 µm process technology

— Fully compatible with 0.32 µm Am29L V160B device

■ High performance

— Access times as fast as 70 ns

■ Ultra low power consumption (typical values at

5MHz)

— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current

■ Flexible sector arc hitecture

— O ne 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

thirty-one 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

thirty-one 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to prevent

any program or erase operations within that sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect f eature allo ws code

changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall pr ogramming time when issuing

multiple program command sequences

■ Top or bottom boot block configurations

available

■ Minimum 1,000,000 write cycle guarantee

per sector

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package option

— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO

■ CFI (Common Flash Interface) compliant

— Provides device-specific information to the

system, allowing host software to easily
reconfigure for different Flash devices

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detec ting program

or erase operation completion

■ Ready/Busy# pin (RY/ BY#)

— Provides a hardware method of detecting

program or erase cycle completi on (not av ailable
on 44-pin SO)

■ Erase Suspend/Erase Resume

— Suspends an erase operation t o read data from,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the devic e to reading

array data

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.

Publication# 22358 Rev: B Amendment/+3
Issue Date: November 10, 2000

GENERAL DESCRIPTION

The Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes or 1,048,576
words. The device i s offered in 48-ba ll FBGA, 44-pin
SO, and 48-pin TSOP packages. The word-wide data

(x16) appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed in-system with the standard system 3.0
volt V
required for write or erase operations. The device can
also be programmed in standard
EPROM programmers.

The device offers access times of 70, 90, and 120 ns,
allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.

The Am29LV160D is entirely command set compatible
with the JEDEC single-power-supply Flash stan-
dard. Commands are written to the command register
using standard microprocessor write timings. Register
contents serve as input to an internal state-machine
that controls the erase and programming circuitry.
Write cycles also i nternally latch addresses and data
needed for the programming and erase operations.
Reading data ou t of the device is simil ar to reading
from other Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requir ing only two
write cycles to program data instead of four.

Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automati­cally preprograms the array (if it is not already pro­grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.

supply. A 12.0 V VPP or 5.0 VCC are not

CC

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cyc le has
been completed, the device is ready to read array data
or accept another command.

The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of
memory. This can be achieved in-system or via pro­gramming equipment.

The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. Tr ue background erase can
thus be achieved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bi t s w i th i n a
sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

2 Am29LV160D

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9

Table 1. Am29LV160D Device Bus Operations .... ............................9

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data .....................................9

Writing Commands/Command Sequences .............. ..............10

Program and Erase Operation Status .................................... 10

Standby Mode ....................... .................................................10

Automatic Sleep Mode ............................... .. ................... .......10

RESET#: Hardware Reset Pin ...............................................11

Output Disable Mode ..............................................................11

Table 2. Sector Address Tables (Am29LV160DT) ..........................12

Table 3. Sector Address Tables (Am29LV160DB) ..........................13

Autoselect Mode ..................................... .. ................. .. ...........14

Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14

Sector Protection/Unprotection ............................................... 14

Temporary Sector Unprotect ..................................................15

Figure 1. Temporary Sector Unprotect Operation........................... 15

Figure 2. In-System Sector Protect/Unprotect Algorithms.............. 16

Common Flash Memory Interface (CFI) . . . . . . .17

Table 5. CFI Query Identification String ..........................................17

Table 6. System Interface String .....................................................18

Table 7. Device Geometry Definition ..............................................18

Hardware Data Protection ......................................................19

Table 8. Primary Vendor-Specific Extended Query ........................19

Low VCC Write Inhibit ..............................................................19

Write Pulse “Glitch” Protection ...............................................19

Logical Inhibit ..........................................................................19

Power-Up Write Inhibit ............................................................19

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20

Reading Array Data ................................................................20

Reset Command .................................... ........................... ......20

Autoselect Command Sequence ......................... ............. ......20

Word/Byte Program Command Sequence .............................20

Unlock Bypass Command Sequence ............ .........................21

Figure 3. Program Operation.......................................................... 21

Chip Erase Command Sequence ...........................................21

Sector Erase Command Sequence ........................................22

Erase Suspend/Erase Resume Commands ...........................22

Figure 4. Erase Operation............................................................... 23

Command Definitions ............................................................. 24

Table 9. Am29LV160D Command Definitions ................................24

Write Operation Status . . . . . . . . . . . . . . . . . . . . .25

DQ7: Dat a# Po ll i n g ............ ............ .. ............ ... ............ .. .......... 25

Figure 5. Data# Polling Algorithm ................................................... 25

RY/BY#: Ready/Busy# ...........................................................26

DQ6: Toggle Bit I ....................................................................26

DQ2: Toggle Bit II ...................................................................26

Reading Toggle Bits DQ6/DQ2 ...............................................26

Figure 6. Toggle Bit Algorithm........................................................ 27

DQ3: Sector Erase Timer .......................................................28

Table 10. Write Operation Status ...................................................28

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29

Figure 7. Maximum Negative Overshoot Waveform...................... 29

Figure 8. Maximum Positive Overshoot Waveform........................ 29

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 29

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 9. I

Automatic Sleep Currents)................................................. ........... . 31

Figure 10. Typical I

Current vs. Time (Showing Active and

CC1

vs. Frequency........................................... 31

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. Test Setup..................................................................... 32

Table 11. Test Specifications ......................................................... 32

Figure 12. Input Waveforms and Measurement Levels ................. 32

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Read Operations ............ ................ ............. ...........................33

Figure 13. Read Operations Timings ............................................. 33

Hardware Reset (RESET#) ....................................................34

Figure 14. RESET# Timings.......................................................... 34

Word/Byte Configuration (BYTE#) ........................................ 35

Figure 15. BYTE# Timings for Read Operations............................ 35

Figure 16. BYTE# Timings for Write Operations............................ 35

Erase/Program Operations ..................................................... 36

Figure 17. Program Operation Timings.......................................... 37

Figure 18. Chip/Sector Erase Operation Timings .......................... 38

Figure 19. Data# Polling Timings (During Embedded Algorithms). 39

Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 39

Figure 21. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations............................................................ 40

Figure 22. Temporary Sector Unprotect/Timing Diagram .............. 40

Figure 23. Sector Protect/Unprotect Timing Diagram.................... 41

Figure 24. Alternate CE# Controlled Write Operation Timings ...... 43

Erase and Programming Performance . . . . . . . 44

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 44

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 44

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 45

TS 048—48-Pin Standard TSOP ............................................45

TSR048—48-Pin Reverse TSOP ...........................................46

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

8 x 9 mm ................................................................................47

SO 044—44-Pin Small Outline Package .............. ..................48

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49

Revision A (January 1999) .....................................................49

Revision A+1 (April 19, 1999) .................................................49

Revision B (November 23, 1999) ............................................49

Revision B+1 (February 22, 2000) ..........................................49

Revision B+2 (November 7, 2000) ......................................... 49

Revision B+3 (November 10, 2000) ....................................... 49

Am29LV160D 3

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV160D

Speed Option Voltage Range: V

Max access time, ns (t
Max CE# access time, ns (t
Max OE# access time, ns (t

)7090120

ACC

)7090120

CE

) 303550

OE

= 2.7–3.6 V -70 -90 -120

CC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

RY/BY#

V

CC

V

SS

RESET#

WE#

BYTE#

CE#

OE#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

DQ0

–

DQ15 (A-1)

Input/Output

Buffers

Latch

Data

A0–A19

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

4 Am29LV160D

CONNECTION DIAGRAMS

A15
A14
A13
A12
A11
A10

A9
A8

A19

NC

WE#

RESET#

NC
NC

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

A16

BYTE#

V

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE#

V

CE#

SS

CC

SS

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard TSOP

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#
A0

A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1

Am29LV160D 5

CONNECTION DIAGRAMS

RESET#

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V

SS

OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

FBGA

Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6 G6 H6

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

A3 B3 C3 D3 E3 F3 G3 H3

A2 B2 C2 D2 E2 F2 G2 H2

A1 B1 C1 D1 E1 F1 G1 H1

Special Handling Instructions

Special handling is required for Flash Memory products
in FBGA packages.

BYTE#A16A15A14A12A13

DQ15/A-1 V

SS

DQ13 DQ6DQ14DQ7A11A10A8A9

V

CC

DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

CE#A0A1A2A4A3

OE# V

SS

Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.

6 Am29LV160D

PIN CONFIGURATION

A0–A19 = 20 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin
RY/BY# = Ready/Busy output

(N/A SO 044)

= 3.0 volt-only single power supply

V

CC

(see Product Selector Guide for speed

options and voltage supply toleranc es)

LOGIC SYMBOL

20

A0–A19

CE#
OE#

WE#
RESET#
BYTE# RY/BY#

16 or 8

DQ0–DQ15

(A-1)

(N/A SO 044)

V

SS

= Device ground

NC = Pin not connected internally

Am29LV160D 7

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

Am29LV160D T -70 E C

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40
E = Extended (–55

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
WC = 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV160D
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

°C to +85°C)

°C to +125°C)

Valid Combinations For TSOP and SO Packages

Am29LV160DT-70,
Am29LV160DB-70

Am29LV160DT-90,
Am29LV160DB-90

Am29LV160DT-120,
Am29LV160DB-120

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

EC, EI, EE,

FC, FI, FE,
SC, SI, SE

Valid Combinations for FBGA Packages

Order Number Package Marking

Am29LV160DT-70,
Am29LV160DB-70

Am29LV160DT-90,
Am29LV160DB-90

Am29LV160DT-120,
Am29LV160DB-120

WCC,

WCI,
WCE

L160DT70V,
L160DB70V

L160DT90V,
L160DB90V

L160DT12V,
L160DB12V

C, I, E

8 Am29LV160D

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29LV160D Device Bus Operations

Operation CE# OE# WE# RESET#

Read L L H H A

Write L H L H A

±

V

Standby
Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V

Temporary Sector
Unprotect

CC

0.3 V

XX

XXX V

V

CC

0.3 V

±

ID

ID

ID

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.

DQ8–DQ15

Addresses

(Note 1)

IN
IN

X High-Z High-Z High-Z

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Address,
A6 = H, A1 = H,

A0 = L

A

IN

DQ0–

DQ7

D

OUT

D

IN

D

IN

D

IN

D

IN

BYTE#

= V

IH

D

OUT

D

IN

XX

XX

D

IN

BYTE#

= V

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z

IL

Legend:

L = Logic Low = V

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

IL

= Data Out

OUT

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V

), A19:A-1 in byte mode (BYTE# = VIL).

IH

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the by te or word configur a­tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con­trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac­tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-

. CE# is the power

IL

main at V
vice outputs array data in word s or b yt e s.

The internal state machine is set for reading array
data upon device po wer-u p , or after a hardw are res et.
This ensure s that no sp urious alteration of the mem­ory content occurs dur ing the power transition. No
command is nece ssary in this mode to ob tain array
data. Standard microprocessor read cycles that as­sert valid addresses on the de vice addr ess inputs pro­duce valid dat a on the de vice da ta outputs . The de vice
remains enabled for read access until the command
register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 13 for the timing diagram. I

the DC Characteristics table represents the active cur­rent specification for reading array data.

. The BYTE# pin determines whether the de-

IH

CC1

in

Am29LV160D 9

Writing Commands/Command Sequences

To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

For program operations, the BYT E# pin determin es
whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more
information.

The device f eatures an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of f our. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.

An erase operation can erase one sect or, multiple sec­tors, or the entire device. Tables 2 and 3 i ndicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.

After the system writes the autoselect command
sequence, the devi ce enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Sta ndard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more
information.

I

CC2

tive current specification for the w rite mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

, and OE# to VIH.

IL

in the DC Characteristics table represents the ac-

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifica tions apply. Refer to “Write Ope ration
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is gr eatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when the

0.3 V.

CE# and RESET# pins are both held at V

CC

±

(Note that this is a more restricted voltage range than
V

.) If CE# and RESET# ar e held at VIH, but not within

IH

0.3 V, the device will be in the standby mode, b ut

±

V

CC

the standby current will be grea ter. The device req uires
standard access time (t

) for read access when the

CE

device is in either of these standby modes, before it is
ready to read data.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The de vice automatically enables
this mode when addresses remain stable f or t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard addres s
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I

CC4

Characteristics table represents the automatic sleep
mode current specification.

+ 30

ACC

in the DC

10 Am29LV160D

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to readi ng arr ay data. When the system
drives the RESET# pin to V
the device immediately terminates any operati on in
progress, tristates all data output pins, and ignores all
read/wri te attempts for the durati on of the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

draws CMOS standby current (I

but not within VSS±0.3 V, the standby current will

at V

IL

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

for at least a p eriod of tRP,

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase op­eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine
whether the reset oper ation is c omplete . If RESE T# is
asserted when a program or erase oper ation is not e x­ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin retur n s to V

(not during Embed-

READY

.

IH

RH

after

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

Am29LV160D 11

Table 2. Sector Address T ables (Am29LV160DT)

Sector Size

(Kbytes/

Sector A19 A18 A17 A16 A15 A14 A13 A12

SA0 0 0 0 0 0 X X X 64/32 000000–00FFFF 00000–07FFF
SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF
SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF
SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF
SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF
SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF
SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF
SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF
SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF

SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF
SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF
SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF
SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF
SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF
SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF
SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF
SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF
SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF
SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF
SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF
SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF
SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF
SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF
SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF
SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF
SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF
SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF
SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF
SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF
SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF
SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF
SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF
SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF
SA33 1 1 1 1 1 1 0 1 8/4 1FA000–1FBFFF FD000–FDFFF
SA34 1 1 1 1 1 1 1 X 16/8 1FC000–1FFFFF FE000–FFFFF

Kwords)

Address Range (in hexadecimal)

Byte Mode (x8) Word Mode (x16)

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.

12 Am29LV160D

Table 3. Sector Address Tables (Am29LV160DB)

Sector Size

(Kbytes/

Sector A19 A18 A17 A16 A15 A14 A13 A12

SA00000000X 16/8 000000–003FFF 00000–01FFF

SA100000010 8/4 004000–005FFF 02000–02FFF

SA200000011 8/4 006000–007FFF 03000–03FFF

SA3000001XX 32/16 008000–00FFFF 04000–07FFF

SA400001XXX 64/32 010000–01FFFF 08000–0FFFF

SA500010XXX 64/32 020000–02FFFF 10000–17FFF

SA600011XXX 64/32 030000–03FFFF 18000–1FFFF

SA700100XXX 64/32 040000–04FFFF 20000–27FFF

SA800101XXX 64/32 050000–05FFFF 28000–2FFFF

SA900110XXX 64/32 060000–06FFFF 30000–37FFF

SA1000111XXX 64/32 070000–07FFFF 38000–3FFFF
SA1101000XXX 64/32 080000–08FFFF 40000–47FFF
SA1201001XXX 64/32 090000–09FFFF 48000–4FFFF
SA1301010XXX 64/32 0A0000–0AFFFF 50000–57FFF
SA1401011XXX 64/32 0B0000–0BFFFF 58000–5FFFF
SA1501100XXX 64/32 0C0000–0CFFFF 60000–67FFF
SA1601101XXX 64/32 0D0000–0DFFFF 68000–6FFFF
SA1701110XXX 64/32 0E0000–0EFFFF 70000–77FFF
SA1801111XXX 64/32 0F0000–0FFFFF 78000–7FFFF
SA1910000XXX 64/32 100000–10FFFF 80000–87FFF
SA2010001XXX 64/32 110000–11FFFF 88000–8FFFF
SA2110010XXX 64/32 120000–12FFFF 90000–97FFF
SA2210011XXX 64/32 130000–13FFFF 98000–9FFFF
SA2310100XXX 64/32 140000–14FFFF A0000–A7FFF
SA2410101XXX 64/32 150000–15FFFF A8000–AFFFF
SA2510110XXX 64/32 160000–16FFFF B0000–B7FFF
SA2610111XXX 64/32 170000–17FFFF B8000–BFFFF
SA2711000XXX 64/32 180000–18FFFF C0000–C7FFF
SA2811001XXX 64/32 190000–19FFFF C8000–CFFFF
SA2911010XXX 64/32 1A0000–1AFFFF D0000–D7FFF
SA3011011XXX 64/32 1B0000–1BFFFF D8000–DFFFF
SA3111100XXX 64/32 1C0000–1CFFFF E0000–E7FFF
SA3211101XXX 64/32 1D0000–1DFFFF E8000–EFFFF
SA3311110XXX 64/32 1E0000–1EFFFF F0000–F7FFF
SA3411111XXX 64/32 1F0000–1FFFFF F8000–FFFFF

Kwords)

Address Range (in hexadecimal)

Byte Mode (x8) Word Mode (x16)

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.

Am29LV160D 13

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in

Description Mode CE# OE# WE#

(11.5 V to 12.5 V) on address pin

ID

Table 4. Am29LV160D Autoselect Codes (High Voltage Method)

A19

to

A12

Ta ble 4. In addition, when verifying s ector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care .
When all necessary bits have been set as required, the
programming equipment may then read the corre­sponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9. This method
does not require V

. See “Command Definitions” for

ID

details on using the autoselect mode.

A11

to

A10 A9

A8

to

A7 A6

A5

to

A2 A1 A0

DQ8

to

DQ15

DQ7

to

DQ0

Manufacturer ID: AMD L L H X X V
Device ID:

Am29LV160D
(Top Boot Block)

Device ID:
Am29LV160D
(Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.

Word L L H

XXV

Byte L L H X C4h

Word L L H

XXV

Byte L L H X 49h

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sect or. The hard­ware sector unprotection feature re-enables both pro­gram and erase operations in previously protected
sectors.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Sector protection/unprotection can be implemented via

XLXLL X 01h

ID

XLXLH

ID

XLXLH

ID

XLXHL

ID

The primary method requires V
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo­rithms and Figure 23 shows the timing diagram. This
method uses standard m icroprocessor bus cycle tim­ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sect or unprotect write
cycle.

The alternate method intended o nly for programming
equipment requires V

on address pin A9 and OE#.

ID

This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. De­tails on this method are pro vided in a supplement, pub­lication number 21468. Contact an AMD representativ e
to request a copy.

two methods.

22h C4h

22h 49h

X

X

on the RESET# pin

ID

01h

(protected)

00h

(unprotected)

14 Am29LV160D

Temporary Sector Unprotect

This feature allows temporary unpr otection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE­SET# pin to V
sectors can be programmed or erased by sele cting the
sector addresses. Once V
SET# pin, all the previously protected sectors are
protected again. Figure shows the algorithm, and Fig­ure 22 shows the timing diagrams, for this feature.

. During this mode, formerly protected

ID

is removed from the RE-

ID

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

ID

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

IH

Figure 1. Temporary Sector Unprotect Operation

Am29LV160D 15

Temporary Sector

Unprotect Mode

No

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

START

Protect all sectors:

The indicated portion

of the sector protect

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

ID

No

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

Yes

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Yes

Protect another

sector?

No

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

No

All sectors

protected?

Yes

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Reset

PLSCNT = 1

Increment

PLSCNT

No

Yes

ID

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector
address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Set up

next sector

address

No

ID

Algorithm

Write reset

command

Figure 2. In-System Sector Protect/Unprotect Algorithms

16 Am29LV160D

Sector Unprotect

complete

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Inte rface (CFI) specification out­lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. S oftware support can then be de vice-indepen­dent, JEDEC ID-independent, and forward- and back­ward-compatible for t he specified flash device families.
Flash vendors can standardize t heir existing interf ac es
for long-term compatibility.

This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h in word mode (or address A Ah in byte
mode), any time the dev ice is ready to read arr ay data.

Table 5. CFI Query Identification String

The system can read CFI information at the addresses

given in Tables 5–8. In word mode, the upper address
bits (A7–MSB) must be all zeros. To terminate reading
CFI data, the system must write the reset command.

The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the autoselect mode.

For further information, please refer to the CFI Specifi­cation and CFI Publication 100, a vailable via the W orld
Wide Web at http://www.amd.com/products/nvd/over­view/cfi.html. Alternatively, contact an AMD repres en­tative for copies of these documents.

Addresses

(Word Mode)

10h
11h
12h

13h
14h

15h
16h

17h
18h

19h
1Ah

Addresses

(Byte Mode) Data Description

20h
22h
24h

26h
28h

2Ah

2Ch
2Eh

30h
32h

34h

0051h
0052h
0059h

0002h
0000h

0040h
0000h

0000h
0000h

0000h
0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Am29LV160D 17

Table 6. System Interface String

Addresses

(Word Mode)

1Bh 36h 0027h

1Ch 38h 0036h

1Dh 3Ah 0000h V
1Eh 3Ch 0000h V

Addresses

(Byte Mode) Data Description

Min. (write/erase)

V

CC

D7–D4: volt, D3–D0: 100 millivolt

Max. (write/erase)

V

CC

D7–D4: volt, D3–D0: 100 millivolt

Min. voltage (00h = no VPP pin present)

PP

Max. voltage (00h = no VPP pin present)

PP

1Fh 3Eh 0004h Typical timeout per single byte/word write 2
20h 40h 0000h Typical timeout for Min. size buffer write 2
21h 42h 000Ah Typical timeout per individual block erase 2
22h 44h 0000h Typical timeout for full chip erase 2
23h 46h 0005h Max. timeout for byte/word write 2
24h 48h 0000h Max. timeout for buffer write 2

N

25h 4Ah 0004h Max. timeout per individual block erase 2
26h 4Ch 0000h Max. timeout for full chip erase 2

Table 7. Device Geometry Definition

N

µs

N

µs (00h = not supported)

N

ms

N

ms (00h = not supported)

N

times typical

times typical

N

times typical

N

times typical (00h = not supported)

Addresses

(Word Mode)

27h 4Eh 0015h Device Size = 2
28h

29h
2Ah

2Bh

Addresses

(Byte Mode) Data Description

N

byte

50h
52h

54h
56h

0002h
0000h

0000h
0000h

Flash Device Interface description (refer to CFI publication 100)

Max. number of byte in multi-byte write = 2

(00h = not supported)
2Ch 58h 0004h Number of Erase Block Regions within device
2Dh

2Eh
2Fh
30h

31h
32h
33h
34h

35h
36h
37h
38h

39h
3Ah
3Bh
3Ch

5Ah
5Ch
5Eh

60h
62h

64h
66h
68h

6Ah
6Ch
6Eh

70h
72h

74h
76h
78h

0000h
0000h
0040h
0000h

0001h
0000h
0020h
0000h

0000h
0000h
0080h
0000h

001Eh
0000h
0000h
0001h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

N

18 Am29LV160D

Table 8. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

40h
41h
42h

43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII

45h 8Ah 0000h

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

4Ah 94h 0000h

4Bh 96h 0000h

Addresses

(Byte Mode) Data Description

80h
82h
84h

0050h
0052h
0049h

Query-unique ASCII string “PRI”

Address Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 98h 0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent wri tes (refer to Table 9 for com­mand definitions). In additio n, the following hardware
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.

Low V

When V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

power-up and

CC

CC

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a wr ite cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

Am29LV160D 19

COMMAND DEFINITIONS

Writing speci fic address and data commands or
sequences into the command register initiates device
operations. Table 9 defines the v al id regis ter c ommand
sequences. Writing incorrect address and data
values or writing them in the improper sequence
resets the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend com­mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera­tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.

must

The system
able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Figure 13 shows the timing diagram.

issue the reset command to re-en-

Reset Command

Writing the reset command to the devi ce resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

must

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
T ab le 9 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requi res V
on address bit A9.

The autoselect command sequence is initiated by writ­ing two unlock cycles, followed by the autoselect com­mand. The device then enters the autoselect m ode,
and the system may read at any address any number
of times, without initiating anot her command sequence.

A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if it
is unprotected. Refer to Tables 2 and 3 for valid sector
addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

ID

Word/Byte Program Command Sequence

The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program­ming is a fou r-b us -cyc le oper at ion . The prog ram com­mand sequence is initiated by writing tw o unloc k write
cycles, f ollo wed b y the progr am set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The

not

system is
timin gs. The device automatic ally generates the pro­gram pulses and verifies the programmed cell margin.
Table 9 shows the address and data requirements for
the byte program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation b y using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in­formation on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a

required to provide fur ther controls or

20 Am29LV160D

hardware reset immediately terminates the program-

ming operation. The Byte Program command se­quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the op eration was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro­gram bytes or words to the de vice f aster than using the
standard program command sequence. The unloc k b y­pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de­vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the prog ram
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program­ming time. Table 9 shows the requirements for th e com­mand sequence.

During the unlock bypass mode, o nly the Unlock By­pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com­mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Add resses are
don’t care for both cycles. The device then returns to
reading array data.

Figure 3 illustrates the algorithm for the program oper­ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See Table 9 for program command sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

No

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle opera tion. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. Table 9 shows
the address and data requirements for the chip erase
command sequence.

require the system to

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a ha rd ware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.

The system can determine the status of the erase op­eration by using DQ7, DQ6, DQ2, or RY/BY#. See

Am29LV160D 21

“Write Operation Status” for information on these sta­tus bits. When the Embedded Erase algorithm is com­plete, the device returns to reading array data and
addresses are no longer latched.

no longer latched. The system can determine the sta­tus of the erase operation b y using DQ7, DQ6, DQ2, or
RY/BY#. ( Refer to “Write Ope ration St atus” f or info rma­tion on these status bits.)

Figure 4 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 9 shows the address and data
requirements for the sector eras e command sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begi ns. During the time-out per iod,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all secto rs. The time be­tween these additional cycl es must be less than 50 µs ,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .

Once the sector erase operation has begun, onl y the
Erase Suspend command is valid. All other commands
are ignored. Note th at a hardware reset during the
sector erase operation immediately terminates the op­eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addresses are

require the system to preprogram

Figure 4 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters , and to
Figure 18 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows t he syste m to in­terrupt a sector erase ope ration and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase c ommand sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasu re. (The de vice “er ase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “Write Operation Status” for more informa­tion.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another

22 Am29LV160D

valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operat ion. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Data = FFh?

Erasure Completed

Embedded
Erase
algorithm
in progress

Yes

Notes:

1. See Table 9 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

Am29LV160D 23

Command Definitions

Table 9. Am29LV160D Command Definitions

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0

Manufacturer ID
Device ID,

Top Boot Block
Device ID,

Bottom Boot Block

Sector Protect Verify

Autoselect (Note 8)

(Note 9)

CFI Query (Note 10)

Program

Unlock Bypass
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 12) 2 XXX 90 XXX 00
Chip Erase

Sector Erase
Erase Suspend (Note 13) 1 XXX B0

Erase Resume (Note 14) 1 XXX 30

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

555

4

555

4

555

4

555

4

55

1

555

4

555

3

555

6

555

6

AA

AA

AA

AA

98

AA

AA

AA

AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

Bus Cycles (Notes 2–5)

55

55

55

55

55

55

55

55

555

555

555

555

555

555

555

555

90 X00 01

X01 22C4

90

X02 C4

X01 2249

90

X02 49

XX00

(SA)

X02

(SA)

X04

555

555

XX01

00
01

AA

AA

90

A0 PA PD

20

80

80

2AA

2AA

555

55

55 SA 30

PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.

10

Notes:

1. See Table 1 for description of bus operations.

9. The data is 00h for an unprotected sector and 01h for a

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the
autoselect command sequence, all bus cycles are write

10. Command is valid when device is ready to read array data or

cycles.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

11. The Unlock Bypass command is required prior to the Unlock

command cycles.

5. Address bits A19–A11 are don’t cares for unlock and

12. The Unlock Bypass Reset command is required to return to

command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array
data.

13. The system may read and program in non-erasing sectors, or

7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).

8. The fourth cycle of the autoselect command sequence is a

14. The Erase Resume command is valid only during the Erase

read cycle.

24 Am29LV160D

protected sector. See “Autoselect Command Sequence” for
more information.

when device is in autoselect mode.

Bypass Program command.

reading array data when the device is in the unlock bypass
mode.

enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.

Suspend mode.

WRITE OPERATION STATUS

The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6,
DQ7, and RY/BY#. Table 10 and the following subsec­tions describe the functions of these bits. DQ7,
RY/BY#, and DQ6 e ach offer a method f or determining
whether a program or erase oper ation is c omplete or in
progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or wh ether the device is in Erase Sus­pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading

array data.

Ta ble 10 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.

START

Read DQ7–DQ0

Addr = VA

Yes

No

DQ7 = Data?

No

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.

After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 i s activ e for approx imately 100 µs , then
the device returns to reading array data. If not all
selected sectors are protected, the Embedd ed Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is as serted low. Figure 19, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Yes

PASS

Figure 5. Data# Polling Algorithm

Am29LV160D 25

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to V
availab l e on the 44-pin SO package.)

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

T ab le 10 shows the outputs f or R Y/BY#. Figures 13, 14,
17 and 18 shows R Y/BY# for read, reset, prog ram, and
erase operations, respectively.

. (The RY/BY# pin is not

CC

DQ6: Toggle Bit I

To ggle Bit I on DQ6 indi cates whether an Embe dded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.

Table 10 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm in flowchar t
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. Figure 20 in t he “A C Char ac ter­istics” section shows the toggle bit timing d iagrams.
Figure 21 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for era­sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for sector and
mode information. Refer to Table 10 to compare
outputs for DQ2 and DQ6.

During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. (The system may us e either OE#
or CE# to control the read cycles.) When the operation
is complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for er asing are protected, DQ6 toggles

for appro ximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro­tected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a pro tected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.

Figure 6 shows the toggle bit algorithm in flowchar t
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20 shows the toggle bit timing dia­gram. Figure 21 shows the differences between DQ2
and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog­gle bit after the first read. After the second read, the
system would compare t he new value of th e togg le bi t
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol­lowing read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and

26 Am29LV160D

the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may contin ue to monitor the
toggle bit and DQ5 through successive read cy cles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 6).

No

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

(Note 1)

No

(Notes
1, 2)

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

No

Program/Erase

Operation Complete

Figure 6. Toggle Bit Algorithm

Am29LV160D 27

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s previously pro­grammed to “0.” Only an era se operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, t he system must issue the

reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determin e whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0” to
“1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the “Sector Erase Command Sequence” section.

After the sector erase command sequenc e is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Sus pend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should che ck the s tatus
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 10 shows the outputs for DQ3.

Table 10. Write Operation Status

DQ7

Operation

Standard
Mode

Erase
Suspend
Mode

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 2) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

28 Am29LV160D

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V

CC

A9, OE#, and RESET# (Note 2). .–0.5 V to +12.5 V

All other pins (Note 1). . . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, input or I/O pins may overshoot V
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

V

DC voltage on input or I/O pins is
voltage transitions, input or I/O pins may overshoot to V
+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is -0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot V
20 ns. See Figure 7. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

to –2.0 V for periods of up to

SS

+0.5 V. During

CC

CC

+0.5 V

to

SS

CC

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

Figure 7. Maximum Negative

Overshoot Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

Supply Voltages

V

CC

for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

V

CC

Operating ranges define those limits between which the
functionality of the device is guaranteed.

) . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . –55°C to +125°C

A

Am29LV160D 29

DC CHARACTERISTICS
CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit

I

I

LIT

I

I

CC1

I

CC2

I

CC3

I

CC4

I

CC5

V
V

V

LI

LO

Input Load Current

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current
(Notes 1, 2)

VCC Active Write Current
(Notes 2, 3, 5)

VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±
VCC Standby Current During Reset

(Notes 2, 4)
Automatic Sleep Mode

(Notes 2, 4, 6)

IL

IH

ID

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 x V
Voltage for Autoselect and

Temporary Sector Unprotect

VIN = VSS to VCC,

= VCC

V

CC

V

OUT

V

CC

CE# = V
Byte Mode

CE# = V
Word Mode

CE# = V

max

; A9 = 12.5 V 35 µA

CC max

= VSS to VCC,

= V

CC max

OE#

IL,

= VIH,

OE#

IL,

= VIH,

OE# = V

IL,

5 MHz 9 16
1 MHz 2 4
5 MHz 9 16
1 MHz 2 4

IH

20 30 mA

0.3 V 0.2 5 µA

0.3 V 0.2 5 µA

RESET# = V

VIH = V

CC

V

= V

IL

SS

= 3.3 V 11.5 12.5 V

V

CC

SS

0.3 V;

±

0.3 V

±

±

0.2 5 µA

CC

1.0 µA

±

1.0 µA

±

mA

VCC + 0.3 V

V
V

V

V

OL

OH1

OH2

LKO

Output Low Voltage IOL = 4.0 mA, VCC = V

I

= -2.0 mA, VCC = V

Output High Voltage

OH

IOH = -100 µA, VCC = V

Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V

0.45 V

CC min

0.85 x V

CC min

VCC–0.4

CC min

Notes:

1. The I

2. Maximum I

3. I

4. At extended temperature range (>+85

current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.

CC

specifications are tested with VCC = VCCmax.

CC

active while Embedded Erase or Embedded Program is in progress.

CC

°

C), typical current is 5 µA and maximum current is 10 µA.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t
current is 200 nA.

6. Not 100% tested.

CC

+ 30 ns. Typical sleep mode

ACC

V

30 Am29LV160D

DC CHARACTERISTICS (Continued)
Zero Power Flash

25

20

15

10

Supply Current in mA

5

0

0 500 1000 1500 2000 2500 3000 3500 4000

Note: Addresses are switching at 1 MHz

Time in ns

Figure 9. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

3.6 V

8

2.7 V

6

4

Supply Current in mA

2

0

12345

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I

Am29LV160D 31

vs. Frequency

CC1

TEST CONDITIONS

3.3 V

Table 11. Test Specifications

Test Condition -70 -90, -120 Unit

Device

Under

Test

C

L

Note: Diodes are IN3064 or equivalent

6.2 k

Ω

Figure 11. Test Setup

Key to Switching Waveforms

WAVEFORM INPUTS OUTPUTS

2.7 k

Ω

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

L

30 100 pF

1.5 V

1.5 V

3.0 V

0.0 V

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

1.5 V 1.5 V

Figure 12. Input Waveforms and Measurement Levels

OutputMeasurement LevelInput

32 Am29LV160D

AC CHARACTERISTICS
Read Operations

Parameter

JEDEC Std Test Setup -70 -90 -120 Unit

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

Description

t

Read Cycle Time (Note 1) Min 70 90 120 ns

RC

t

Address to Output Delay

ACC

t

Chip Enable to Output Delay OE# = V

CE

t

Output Enable to Output Delay Max 30 35 50 ns

OE

t

Chip Enable to Output High Z (Note 1) Max 25 30 30 ns

DF

t

Output Enable to Output High Z (Note 1) Max 25 30 30 ns

DF

CE# = V
OE# = V

IL

Max 70 90 120 ns

IL

Max 70 90 120 ns

IL

Speed Options

Read Min 0 ns

Output Enable

OEH

Hold Time (Note 1)

Toggle and
Data# Polling

Output Hold Time From Addresses, CE# or

t

OH

OE#, Whichever Occurs First (Note 1)

Min 10 ns

Min 0 ns

t

AXQX

t

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 11 for test specifications.

t

RC

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 13. Read Operations Timings

t

DF

t

OH

HIGH Z

Am29LV160D 33

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

t

READY

t

READY

RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pulse Width Min 500 ns

t

RP

RESET# High Time Before Read (See Note) Min 50 ns

t

RH

RESET# Low to Standby Mode Min 20 µs

t

RPD

RY/BY# Recovery Time Min 0 ns

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t

RP

t

Ready

Max 20 µs

Max 500 ns

t

RH

RY/BY#

CE#, OE#

RESET#

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 14. RESET# Timings

t

RB

34 Am29LV160D

AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)

Parameter Speed Options

JEDEC Std Description -70 -90 -120 Unit

t

ELFL/tELFH

t

FLQZ

t

FHQV

BYTE#

Switching

from word

to byte

mode

CE# to BYTE# Switching Low or High Max 5 ns
BYTE# Switching Low to Output HIGH Z Max 25 30 30 ns
BYTE# Switching High to Output Active Min 70 90 120 ns

CE#

OE#

BYTE#

t

DQ0–DQ14

DQ15/A-1

ELFL

t

ELFH

Data Output

(DQ0–DQ14)

DQ15

Output

t

FLQZ

Data Output

(DQ0–DQ7)

Address

Input

BYTE#

BYTE#

Switching

from byte

to word

DQ0–DQ14

Data Output
(DQ0–DQ7)

mode

DQ15/A-1

Address

Input

t

FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(tAS)

t

HOLD

(tAH)

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 16. BYTE# Timings for Write Operations

Data Output

(DQ0–DQ14)

DQ15

Output

Am29LV160D 35

AC CHARACTERISTICS
Erase/Program Operations

Parameter Speed Options

JEDEC Std Description -70 -90 -120 Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

WHWH1

t

WHWH2

t

VCS

t

RB

t

BUSY

Write Cycle Time (Note 1) Min 70 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 50 ns
Data Setup Time Min 35 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 35 35 50 ns
Write Pulse Width High Min 30 ns

Byte Typ 5

Programming Operation (Note 2)

µs

Word Typ 7
Sector Erase Operation (Note 2) Typ 0.7 sec
VCC Setup Time (Note 1) Min 50 µs
Recovery Time from RY/BY# Min 0 ns
Program/Erase Valid to RY/BY# Delay Min 90 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

36 Am29LV160D

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t

WC

Addresses

CE#

555h

t

CH

OE#

t

WP

WE#

t

CS

t

DS

t

DH

Data

A0h

RY/BY#

t

VCS

V

CC

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

Read Status Data (last two cycles)

t

AS

PA PA

t

AH

t

t

WPH

PD

t

BUSY

is the true data at the program address.

OUT

PA

WHWH1

Status

D

OUT

t

RB

Figure 17. Program Operation Timings

Am29LV160D 37

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

t

AS

555h for chip erase

VA

t

AH

VA

Addresses

t

WC

2AAh SA

CE#

t

t

WP

t

DS

55h

CH

t

WPH

t

DH

30h

10 for Chip Erase

t

BUSY

t

WHWH2

In

Progress

Complete

t

RB

OE#

WE#

Data

t

CS

RY/BY#

t

VCS

V

CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (s ee “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

38 Am29LV160D

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

WE#

DQ7

OEH

t

ACC

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note: VA = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Am29LV160D 39

AC CHARACTERISTICS

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.

Erase

Erase

Suspend

Erase Suspend

Enter Erase

Suspend Program

Read

Erase
Suspend
Program

Erase Suspend

Read

Figure 21. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations

Erase

Resume

Erase

Complete

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

Erase

t

VIDR

t

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

CE#

WE#

RY/BY#

VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector

Unprotect

t

VIDR

Min 4 µs

t

VIDR

Program or Erase Command Sequence

t

RSP

Figure 22. Temporary Sector Unprotect/Timing Diagram

40 Am29LV160D

AC CHARACTERISTICS

V

ID

V

RESET#

IH

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

Data

60h 60h 40h

1 µs

Sector Protect: 150 µs

Sector Unprotect: 15 ms

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

Status

Am29LV160D 41

AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations

Parameter Speed Options

JEDEC Std Description -70 -90 -120 Unit

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHEL

t

WS

t

WH

t

CP

t

CPH

Write Cycle Time (Note 1) Min 70 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 50 ns
Data Setup Time Min 35 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)
WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 35 35 50 ns
CE# Pulse Width High Min 30 ns

Byte Typ 5

t

WHWH1

t

WHWH2

t

WHWH1

t

WHWH2

Programming Operation (Note 2)

Word Typ 7

Sector Erase Operation (Note 2) Typ 0.7 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Min 0 ns

µs

42 Am29LV160D

AC CHARACTERISTICS

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program
2AA for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
555 for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

RY/BY#

Notes:

1. P A = program address, PD = program data, DQ7# = complement of the data written to the device, D
device.

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

= data written to the

OUT

Am29LV160D 43

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s
Chip Erase Time 25 s
Byte Programming Time 5 150 µs

Word Programming Time 7 210 µs
Chip Programming Time

(Note 3)

Byte Mode 11 33 s

Word Mode 7.2 21.6 s

Excludes 00h programming
prior to erasure (Note 4)

Excludes system level
overhead (Note 5)

Notes:

°

1. Typical program and erase times assume the following conditions: 25

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V
(including A9, OE#, and RESE T#)

on all pins except I/O pins

SS

–1.0 V 12.5 V

Input voltage with respect to V

Current –100 mA +100 mA

V

CC

on all I/O pins –1.0 V VCC + 1.0 V

SS

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

Control Pin Capacitance VIN = 0 7.5 9 pF

= 0 8.5 12 pF

OUT

C

C

C

IN

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

44 Am29LV160D

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

Am29LV160D 45

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

46 Am29LV160D

Dwg rev AA; 10/99

PHYSICAL DIMENSIONS

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8x9mm

Dwg rev AF; 10/99

Am29LV160D 47

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

48 Am29LV160D

REVISION SUMMARY
Revision A (January 1999)

The Am29LV160D is fully form, fit, and function com­patible with the Am29LV160B device, with the f ollo wing
differences:

A 70 ns device at full voltage range is now available.
The 80 ns speed option has been deleted.

Byte and word programming times, and byte- and
word-mode chip programming times are now reduced.

At extended temperatures (>+85°C), sleep and
standby currents increase.

Revision A+1 (April 19, 1999)

Global

Reclassified the document f rom advance i nformation to
preliminary.

The 70 ns speed option is now also available with the
industrial and extended temperature r ange ratings.

Revision B (November 23, 1999)

AC Characteristics—Figure 17. Program
Operations Timing and Figure 18. Chip/Sector
Erase Operations

Deleted t
high.

and changed OE# waveform to start at

GHWL

Physical Dimensions

Replaced figures with more detailed illustrations.

Revision B+1 (February 22, 2000)

Global

Added dash to speed options.

Ordering Information

Added dash to OPN.

Revision B+2 (November 7, 2000)

Global

Deleted Preliminary status from data sheet. Deleted
burn-in option. Added table of contents.

Revision B+3 (November 10, 2000)

Command Definitions

Reset Command:

RESET# Timings, which applies only to hardware
reset.

Deleted reference to Figure 14,

Trademarks

Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV160D 49