Datasheet AM29LV116BT-90EC, AM29LV116BT-80RFIB, AM29LV116BT-80RFI, AM29LV116BT-80RFEB, AM29LV116BT-80RFE Datasheet (AMD Advanced Micro Devices)

PRELIMINARY

Am29LV116B

16 Megabit (2 M x 8-Bit)
CMOS 3.0 Volt-onl y Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3. 6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3. 6 volt read

and write operations and for compatibility with
high performance 3.3 volt microprocessors

■ Manufactured on 0.35 µm process technology

■ High performance

— Full voltage range: ac cess times as f ast as 90 ns
— Regulated voltage range: access times as fast

as 80 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 15 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

thirty-one 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

T emporary Sector Unprotect feat ure allows code

changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall progr amming time when

issuing multiple program command sequences

■ Top or bottom boot block configurations

available

■ Embedded Al gorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Minimum 1,000,000 write cycle guarantee per

sector

■ Package option

— 40-pin TSOP

■ CFI (Common Flash Interface) compliant

— Provides device-specific information to the

system, allowing host software to easily
reconfigure for different Flash devices

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operati on to read dat a from,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the de vi ce to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed
product without notice.

Publication# 21359 Rev: C Amendment/+2
Issue Date: March 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV116B is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)

data appears on DQ7–DQ0. All read, program, and
erase operations are accomplished using only a single
power supply. The device can also be programmed in
standard EPROM programmers.

The standard device off ers access times of 80, 90, and
120 ns, allowing high speed microprocessors to
operate without wait s tates. To eliminate bus conten­tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.

The device requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co n­tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requir ing only two
write cycles to program data instead of four.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre­programs the array (if it is not already progr ammed) be­fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.

The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This can be achieved in-system or via program­ming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases a ll bit s within
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

Am29LV116B 2

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV116B

Speed Options

Max access time, ns (t
Max CE# access time, ns (tCE) 80 90 120
Max OE# access time, ns (tOE) 30 35 50

Regulated Voltage Range: VCC =3.0–3.6 V 80R

Full Voltage Range: VCC = 2.7–3.6 V 90 120

) 80 90 120

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ7

Input/Output

Buffers

Data

Latch

V

CC

V

SS

RESET#

WE#

CE#

OE#

RY/BY#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A20

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21359C-1

3 Am29LV116B

CONNECTION DIAGRAMS

PRELIMINARY

A16
A15
A14
A13
A12
A11

A9
A8

WE#

RESET#

NC

RY/BY#

A18

A7
A6
A5
A4
A3
A2
A1

A17
V

SS

A20
A19

A10
DQ7
DQ6
DQ5
DQ4

V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0

OE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40-Pin Standard TSOP

40-Pin Reverse TSOP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A17
V

SS

A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0
OE#

V

SS

CE#
A0

A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1

21359C-2

Am29LV116B 4

PRELIMINARY

PIN CONFIGURATION

A0–A20 = 21 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy output

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin not connected internally

(see Product Selector Guide for speed

options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

21

A0–A20

CE#
OE#

WE#
RESET#

8

DQ0–DQ7

RY/BY#

21359C-3

5 Am29LV116B

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in s everal packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

CE80RAm29LV116B T

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

Am29LV116BT80R,
Am29LV116BB80R

Am29LV116BT90,
Am29LV116BB90

Am29LV116BT120,
Am29LV116BB120

Valid Combinations

EC, EI, EE,

FC, FI, FE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

DEVICE NUMBER/DE SCR IP TIO N

Am29LV116B
16 Megabit (2 M x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations list configurations planned to be sup-

EC, FC

ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Valid Combinations

Am29LV116B 6

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory loc ation.
The register is composed of latches that store the com­mands, along with the address and data information
needed to execute the command. The contents of the

Table 1. Am29LV116B Device Bus Operations

Operation CE# OE# WE# RESET# Addresses DQ0–DQ7

Read L L H H A
Write L H L H A

Standby
Output Disable L H H H X High-Z

Reset X X X L X High-Z
Sector Protect (See Note) L H L V

Sector Unprotect (See Note) L H L V
Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

IL

VCC ±

0.3 V

XX

register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. Table 1 lists the device bus operations, the in­puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.

D

D

D

, D

IN

D

, D

IN

D

= Data Out

OUT

OUT

IN

OUT

OUT

IN

VCC ±

0.3 V

ID

ID

ID

IN
IN

X High-Z

Sector Addresses,

A6 = L, A1 = H, A0 = L

Sector Addresses

A6 = H, A1 = H, A0 = L

A

IN

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the dev ice. OE# is the output con­trol and gates array data to the output pins. WE#
should remain at V

.

IH

The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con­tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address input s produc e valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 13 for the timing diagram. I

the DC Characteristics table represents the active cur­rent specification for reading array data.

. CE# is the power

IL

CC1

in

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re­quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sec­tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad­dress” consists of the address b its requ ired to uni quely
select a sector. The “Command D efinitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this

, and OE# to VIH.

IL

7 Am29LV116B

PRELIMINARY

mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write m ode. The “AC

Characteristics” section contains timing specification
tables and timing diagrams for w r ite operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pin s are both held at V

CC

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held a t VIH, but not within

V

IH

± 0.3 V, the device will be in the standb y mode, b ut

V

CC

the standby current will be greater. The device requires
standard access time (t

) for read access when the

CE

device is in either of these standby modes, before it is
ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, “RE­SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

in the DC Characteristics table represents the

I

CC3

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addres ses remain stable for

+ 30 ns. The automatic sleep mode is

t

ACC

independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new
data when addresses are chan ged. While in sleep
mode, output data is latched and always available to
the system. I

in the DC Characteristics table

CC5

represents the automatic sleep mode current
specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardw are method of reset­ting the device to reading array data. When the RE­SET# pin is driven low for at least a period of t

RP

, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby c urrent (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operatio n is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V

(not during Embe dded Algo-

READY

.

IH

RH

after the RE-

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

Am29LV116B 8

PRELIMINARY

Table 2. Am29LV116BT Top Boot Sector Address Table

Sector Size

Sector A20 A19 A18 A17 A16 A15 A14 A13

SA000000XXX 64 000000–00FF FF
SA100001XXX 64 010000–01FFFF
SA200010XXX 64 020000–02FFFF
SA300011XXX 64 030000–03FFFF
SA400100XXX 64 040000–04FFFF
SA500101XXX 64 050000–05FFFF
SA600110XXX 64 060000–06FFFF
SA700111XXX 64 070000–07FFFF
SA801000XXX 64 080000–08FFFF

SA901001XXX 64 090000–09FFFF
SA1001010XXX 64 0A0000–0AFFFF
SA1101011XXX 64 0B0000–0BFFFF
SA1201100XXX 64 0C0000–0CFFFF
SA1301101XXX 64 0D0000–0DFFFF
SA1401110XXX 64 0E0000–0EFFFF
SA1501111XXX 64 0F0000–0FFFFF
SA1610000XXX 64 100000–10FFFF
SA1710001XXX 64 110000–11FFFF
SA1810010XXX 64 120000–12FFFF
SA1910011XXX 64 130000–13FFFF
SA2010100XXX 64 140000–14FFFF
SA2110101XXX 64 150000–15FFFF
SA2210110XXX 64 160000–16FFFF
SA2310111XXX 64 170000–17FFFF
SA2411000XXX 64 180000–18FFFF
SA2511001XXX 64 190000–19FFFF
SA2611010XXX 64 1A0000–1AFFFF
SA2711011XXX 64 1B0000–1BFFFF
SA2811100XXX 64 1C0000–1CFFFF
SA2911101XXX 64 1D0000–1DFFFF
SA3011110XXX 64 1E0000–1EFFFF
SA31111110XX 32 1F0000–1F7FFF
SA3211111100 8 1F8000–1F9FFF
SA3311111101 8 1FA000–1FBFFF
SA341111111X 16 1FC000–1FFFFF

(Kbytes)

Address Range

(in hexadecimal)

9 Am29LV116B

PRELIMINARY

Table 3. Am29LV116BB Bottom Boot Sector Address Table

Sector Size

Sector A20 A19 A18 A17 A16 A15 A14 A13

SA0 0000000X 16 000000–003FFF
SA1 00000010 8 004000–005FFF
SA2 00000011 8 006000–007FFF
SA3 0 0 0 0 0 1 X X 32 008000–00FFFF
SA4 0 0 0 0 1 X X X 64 010000–01FFFF
SA5 0 0 0 1 0 X X X 64 020000–02FFFF
SA6 0 0 0 1 1 X X X 64 030000–03FFFF
SA7 0 0 1 0 0 X X X 64 040000–04FFFF
SA8 0 0 1 0 1 X X X 64 050000–05FFFF

SA9 0 0 1 1 0 X X X 64 060000–06FFFF
SA10 0 0 1 1 1 X X X 64 070000–07FFFF
SA11 0 1 0 0 0 X X X 64 080000–08FFFF
SA12 0 1 0 0 1 X X X 64 090000–09FFFF
SA13 0 1 0 1 0 X X X 64 0A0000–0AFFFF
SA14 0 1 0 1 1 X X X 64 0B0000–0BFFFF
SA15 0 1 1 0 0 X X X 64 0C0000–0CFFFF
SA16 0 1 1 0 1 X X X 64 0D0000–0DFFFF
SA17 0 1 1 1 0 X X X 64 0E0000–0EFFFF
SA18 0 1 1 1 1 X X X 64 0F0000–0FFFFF
SA19 1 0 0 0 0 X X X 64 100000–10FFFF
SA20 1 0 0 0 1 X X X 64 110000–11FFFF
SA21 1 0 0 1 0 X X X 64 120000–12FFFF
SA22 1 0 0 1 1 X X X 64 130000–13FFFF
SA23 1 0 1 0 0 X X X 64 140000–14FFFF
SA24 1 0 1 0 1 X X X 64 150000–15FFFF
SA25 1 0 1 1 0 X X X 64 160000–16FFFF
SA26 1 0 1 1 1 X X X 64 170000–17FFFF
SA27 1 1 0 0 0 X X X 64 180000–18FFFF
SA28 1 1 0 0 1 X X X 64 190000–19FFFF
SA29 1 1 0 1 0 X X X 64 1A0000–1AFFFF
SA30 1 1 0 1 1 X X X 64 1B0000–1BFFFF
SA31 1 1 1 0 0 X X X 64 1C0000–1CFFFF
SA32 1 1 1 0 1 X X X 64 1D0000–1DFFFF
SA33 1 1 1 1 0 X X X 64 1E0000–1EFFFF
SA34 1 1 1 1 1 X X X 64 1F0000–1FFFFF

(Kbytes)

Address Range

(in hexadecimal)

Am29LV116B 10

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in

(11.5 V to 12.5 V) on address pin

ID

Table 4. In addition, when verifying sector protec tion,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care .
When all necessary bits have been set as required, the
programming equipment may then read the corre­sponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9. This method
does not require V
details on using the autoselect mode.

Table 4. Am29LV116B Autoselect Codes (High Voltage Method)

A20

A12

to

to

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID: Am29LV1 16B

(Top Boot Block)
Device ID: Am29LV1 16B

(Bottom Boot Block)

LLHXXV

LLHXXVIDXLXLH 4Ch

A13

A10 A9

. See “Command Definitions” for

ID

A8

to

A7 A6

XLXLL 01h

ID

XLXLH C7h

ID

A5

to

A2 A1 A0

DQ7

to

DQ0

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sect or. The hard­ware sector unprotection feature re-enables both pro­gram and erase operations in previously protected
sectors. Sector protection/unprotecti on can be imple­mented via two methods.

The primary method requires V
only, and c an be implemented either in-system or via

on the RESET# pin

ID

lication number 21586 contains further details; contact
an AMD representative to request a copy.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

XLXHL

ID

programming equipment. Figure 1 shows the algo­rithms and Figure 21 shows the timing diagram. This
method uses standard m icroprocessor bus cycle tim­ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unpro tect write
cycle.

The alternate method intended on ly for programming
equipment requires V

on address pin A9 and OE#.

ID

This method is compatible with programmer routines
written for earlier 3.0 v olt-only AMD flash de vices. Pub-

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE­SET# pin to V
sectors can be programmed or erased b y selecting the
sector addresses. Once V
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 20 shows the tim ing diagrams, for this feature.

01h

(protected)

00h

(unprotected)

. During this mode, formerly protected

ID

is removed from the RE-

ID

11 Am29LV116B

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

Yes

No

START

Protect all sectors:

The indicated portion

of the sector protect

ID

Reset

PLSCNT = 1

Yes

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

No

PLSCNT
= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

No

All sectors
protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

ID

Algorithm

Write reset

command

Sector Unprotect

complete

Figure 1. In-System Sector Protect/Unprotect Algorithms

Am29LV116B 12

21359C-4

PRELIMINARY

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

ID

IH

21359C-5

against inadverten t writes (refer to Table 9 for com­mand definitions). In addition, the following hardwar e
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V

power-up

CC

and power-down transitions, or from system noise.

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Figure 2. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

13 Am29LV116B

PRELIMINARY

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Inte rface (CFI) specification out­lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software suppor t can then be device-inde­pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can s tandardize their existing
interfaces for long-term compatibility.

This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, any time the de vice is ready to read array

data. The system can read CFI information at the

addresses given in Tables 5–8. To terminate reading
CFI data, the system must write the reset command.

The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the autoselect mode.

For further information, please refer to the CFI Specifi­cation and CFI Publication 100, a vailable via the World
Wide Web at http://www.amd.com/products/nvd/over­view/cfi.html. Alternatively, contact an AMD represent­ative for copies of these documents.

Table 5. CFI Query Identification String

Addresses Data Description

10h
11h
12h

13h
14h

51h
52h
59h

02h
00h

Query Unique ASCII string “QRY”

Primary OEM Command Set

15h
16h

17h
18h

19h

1Ah

40h
00h

00h
00h

00h
00h

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 6. System Interface String

Addresses Data Description

Min. (write/erase)

V

1Bh 27h

1Ch 36h

1Dh 00h VPP Min. voltage (00h = no VPP pin present)
1Eh 00h V

1Fh 04h Typical timeout per single byte/word write 2
20h 00h Typical timeout for Min. size buffer write 2
21h 0Ah Typical timeout per individual block erase 2
22h 00h Typical timeout for full chip erase 2
23h 05h Max. timeout for byte/word write 2
24h 00h Max. timeout for buffer write 2
25h 04h Max. timeout per individual block erase 2
26h 00h Max. timeout for full chip erase 2

CC

D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

Max. voltage (00h = no VPP pin present)

PP

N

N

N

times typical

N

times typical (00h = not supported)

N

µs

N

µs (00h = not supported)

N

ms

ms (00h = not supported)

times typical

N

times typical

Am29LV116B 14

PRELIMINARY

Table 7. Device Geometry Definiti on

Addresses Data Description

N

27h 15h Device Size = 2

byte

28h
29h

2Ah
2Bh

2Ch 04h Number of Erase Block Regions within device
2Dh

2Eh

2Fh
30h

31h
32h
33h
34h

35h
36h
37h
38h

39h
3Ah
3Bh
3Ch

00h
00h

00h
00h

00h
00h
40h
00h

01h
00h
20h
00h

00h
00h
80h
00h

1Eh

00h
00h
01h

Flash Device Interface description (refer to CFI publication 100)

Max. number of byte in multi-byte write = 2
(00h = not supported)

Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

N

Table 8. Primary Vendor-Specific Extended Query

Addresses Data Description

40h

41h

42h

43h 31h Major version number, ASCII

44h 30h Minor version number, ASCII

45h 00h

46h 02h

47h 01h

48h 01h Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported

49h 04h

4Ah 00h Simultaneous Operation: 00 = Not Supported, 01 = Supported
4Bh 00h Burst Mode Type: 00 = Not Supported, 01 = Supported

4Ch 00h

50h
52h
49h

Query-unique ASCII string “PRI”

Address Sensitive Unlock
0 = Required, 1 = Not Required

Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect
0 = Not Supported, X = Number of sectors in per group

Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode

Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page

15 Am29LV116B

PRELIMINARY

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. Table 9 de fines the valid registe r command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same exception. See “Erase Sus­pend/Erase Resume Commands” for more information
on this mode.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (a lso applies during Erase Suspend).

must

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
T ab le 9 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requi res V
on address bit A9.

The autoselect command sequence is initiated by writ­ing two unlock cycles, followed by the autoselect com­mand. The device then enters the autoselect m ode,
and the system may read at any address any number
of times, without initiating another command sequenc e.
A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Tables 2
and 3 for valid sector addresses.

ID

must

The system
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parame­ters, and Figure 13 shows the timing diagram.

issue the reset command to re-ena-

Reset Command

Writing the reset command to the devi ce resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

The device programs one byte of data for each pro­gram operation. The command sequence requires four
bus cycles, and is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The

not

system is
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
9 shows the address and data re quirements for the
byte program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program­ming operation. The Byte Program command se-

required to provide further controls or tim-

Am29LV116B 16

PRELIMINARY

quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the op eration was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro­gram bytes to t he de vice f aster than using the standard
program command sequence. The unlock b ypass com­mand sequence is initiated by first writin g two unlock
cycles. This is followed b y a third write cycle containing
the unlock bypass command, 20h. The de v ice then en­ters the unlock bypass mode. A two-cycle unlo ck by­pass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com­mand, A0h; the second cycle contains the progr am ad­dress and data. Additional data is programmed in the
same manner. This mode dispenses wit h the init ial t wo
unlock cycles required in the standard program com­mand sequence, resulting in faster total programming
time. Table 9 shows the requ irements f or t he command
sequence.

Embedded

Program

algorithm

in progress

Increment Address

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

No

Last Address?

Programming

Completed

No

Yes

Yes

During the unlock bypass mode, o nly the Unlock By­pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com­mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Add resses are
don’t cares for both cycles. The device then returns to
reading array data.

Figure 3 illustrates the algorithm for the program oper­ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams

21359C-6

Note: See Table 9 for program command sequence.

Figure 3. Program Operation

17 Am29LV116B

PRELIMINARY

Chip Erase Command Sequence

Chip erase is a six bus cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and ve rifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. Table 9 shows
the address and data requirements for the chip erase
command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a har dware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, t o ensure data int eg rity.

The system can determine the status of the erase op­eration by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these sta­tus bits. When the Embedded Erase algorithm is com­plete, the device returns to reading array data and
addresses are no longer latched.

require the system to

ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Eras e command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the s ector

erase timer has timed out. (See the “DQ3 : Sector Erase
Timer” section.) The tim e-out begins from the rising
edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, on ly the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op­eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched. The system can determine the sta­tus of the erase operation b y using DQ7, DQ6, DQ2, or
RY/BY#. ( Refer to “Write Ope ration St atus” f or info rma­tion on these status bits.)

Figure 4 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad­ditional unlock write cycles are then f ollow ed b y the ad­dress of the sector to be erased, and the sector erase
command. Table 9 shows the address and data re­quirements for the sector erase command sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. Du ring the time-out per iod,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all secto rs. The time be­tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to

require the system to preprogram

Figure 4 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows t he syste m to in­terrupt a sector erase ope ration and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs
during the sector erase c ommand sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasu re. (The de vice “er ase

Am29LV116B 18

PRELIMINARY

suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determ ine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system can once again read arra y data within
non-suspended sectors. The system ca n determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operat ion. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Notes:

1. See Table 9 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

21359C-7

Figure 4. Erase Operation

19 Am29LV116B

PRELIMINARY

Table 9. Am29LV116B Command Definitions

Command Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID,

Top Boot Block
Device ID,

Bottom Boot Block
Sector Protect

Autoselect (Note 7)

Verify (Note 8)

Byte Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program

(Note 9)
Unlock Bypass Reset

(Note 10)
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 5 55 AA 2AA 55 55 5 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 11) 1 XXX B0
Erase Resume (Note 12) 1 XXX 30

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 555 AA 2AA 55 555 90 X01

4 555 AA 2AA 55 555 90

2 XXX A0 PA PD

2 XXX 90 XXX 00

Bus Cycles (Notes 2–4)

SA

X02

C7

4C
00

01

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses are latched on the falling edge of the WE# or CE#
pulse.

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus
cycles are write operations.

4. Address bits A20–A11 are don’t care for unlock and
command cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in
read mode.

6. The Reset command is required to return to the read
mode when the device is in the autoselect mode or if DQ5
goes high.

7. The fourth cycle of the autoselect command sequence is
a read cycle.

PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.

SA = Address of the sector to be erased or verified. Address
bits A20–A13 uniquely select any sector.

8. The data is 00h for an unprotected sector and 01h for a
protected sector.

9. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.

10. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the Unlock
Bypass mode.

11. The system may read and program functions in non­erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation.

12. The Erase Resume command is valid only during the
Erase Suspend mode.

Am29LV116B 20

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to deter mine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the functions of thes e bits . DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys­tem whether an Embedded Algorithm is in progress or
completed, or whether the devic e is in Er as e Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se­quence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 1 µs, then the device returns to reading

array data.

No

START

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is as serted low. Figure 17, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.

DQ7 = Data?

No

FAIL

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Yes

PASS

21359C-8

Figure 5. Data# Polling Algorithm

Table 10 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.

21 Am29LV116B

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, se v­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
ble on the 44-pin SO package.)

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 10 shows the outputs for RY/BY#. Figures 13, 15
and 16 shows RY/BY# for reset, program, and erase
operations, respectively.

. (The RY/BY# pin is not availa-

CC

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whethe r an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the sector erase time-out.

T ab le 10 shows the outputs f or Toggle Bit I on DQ6. Fig­ure 6 shows the toggle bit algorithm in flowchart form,
and the section “Reading Toggle Bits DQ6/DQ2” ex­plains the algorithm. Figure 18 in the “AC Characteris­tics” section shows the toggle bit timing dia grams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sectors that have been selected for eras­ure. (The system may use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which s ectors are selected for erasure.
Thus, both status bits are requ ired f or sector and mode
information. Refer to Table 10 to compare outputs for
DQ2 and DQ6.

During an Embedded Program or Erase algorithm op­eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# o r CE#
to control the read cy cles). When the oper at ion is c om­plete, DQ6 stops toggling.

After an erase command sequence is written, if all s ec­tors selected for eras ing are protected , DQ6 toggles for
approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the Em­bedded Erase algorithm erases the unprotected sec­tors, and ignores the selected sectors that are
protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: D ata# Polling).

If a program address falls within a pro tected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

Figure 6 shows the toggle bit algorithm in flowchar t
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 18 shows the toggle bit timing dia­gram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. Whe n­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically , the
system would note and store the value of the t oggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com­pleted the program or eras e operation. The system can
read array data on DQ7–DQ0 on the following read cy­cle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system

Am29LV116B 22

PRELIMINARY

must write the reset command to return to readin g
array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perfor m other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).

T ab le 10 shows the outputs f or Toggle Bit I on DQ6. Fig­ure 6 shows the toggle bit algorithm. Figure 18 in the

“AC Characteristics” section sho ws the toggle bit timing
diagrams. Figure 19 shows the differences between
DQ2 and DQ6 in graphical for m. See also the subsec­tion on DQ2: Toggle Bit II.

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

(Note 1)

No

No

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

(Notes
1, 2)

No

Program/Erase

Operation Complete

21359C-9

23 Am29LV116B

Figure 6. Toggle Bit Algorithm

PRELIMINARY

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the
device halts the oper ation, and when th e operati on has

exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue

the reset command to return the device to reading
array data.

DQ3: Sector Erase Timer

After writing a sector erase comm and sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time­out also applies after each additional sector erase com­mand. When the time-out is complete, DQ3 switches
from “0” to “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the “Sector Erase Command Sequence” sec­tion.

After the sector erase command sequenc e is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Sus pend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should che ck the s tatus
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 10 shows the outputs for DQ3.

Table 10. Write Operation Status

DQ7

Operation

Standard
Mode

Erase
Suspend
Mode

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 2) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Am29LV116B 24

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V

CC

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1). . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, input or I/O pins may undershoot V
to –2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage on input or I/O pins is
During voltage transitions, input or I/O pins may overshoot
to V

+2.0 V for periods up to 20 ns. See Figure 8.

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

to –2.0 V for periods of up

SS

CC

V

CC

+0.5 V

SS

+0.5 V.

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

Figure 7. Maximum Negative Overshoot Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

20 ns

Figure 8. Maximum Positive Ov ershoot Waveform

21359C-10

21359C-11

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

VCC Supply Voltages

for regulated voltage range. . . . . .+3.0 V to 3.6 V

V

CC

for full v oltage range. . . . . . . . . . .+2.7 V to 3.6 V

V

CC

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

25 Am29LV116B

) . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . –55°C to +125°C

A

PRELIMINARY

DC CHARACTERISTICS
CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit

= VSS to VCC,

V

IN

V

= VCC

CC

= VSS to VCC,

V

OUT

V

= V

CC

VCC = V
CE# = V

max

; A9 = 12.5 V 35 µA

CC max

CC max

CC max

OE#

IL,

;

= VIH

5 MHz 9 16
1 MHz 2 4

±1.0 µA

±1.0 µA

I

I

I

CC1

I

LI

LIT

LO

Input Load Current

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current
(Note 1)

mA

V
V

V

I

CC2

I

CC3

I

CC4

I

CC5

V

V

V

V

IL

IH

ID

OL

OH1

OH2

LKO

VCC Active Write Current
(Notes 2 and 4)

VCC Standby Current

VCC Reset Current

Automatic Sleep Mode (Note 3)

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 x V
Voltage for Autoselect and

Temporary Sector Unprotect
Output Low Voltage IOL = 4.0 mA, VCC = V

Output High Voltage

Low VCC Lock-Out Voltage
(Note 4)

VCC = V
CE# = V

= V

V

CC

CE#, RESET# = V
VCC = V

RESET# = V

= V

V

CC

V

= V

IL

CC max

IL,

CC max

CC max

CC max

± 0.3 V

SS

OE#

SS

;

= VIH

;

CC

;

± 0.3 V

; VIH = V

±0.3 V

± 0.3 V;

CC

VCC = 3.3 V 11.5 12.5 V

0.45 V

CC min

I

= –2.0 mA, VCC = V

OH

IOH = –100 µA, VCC = V

0.85 V

CC min

VCC–0.4

CC min

2.3 2.5 V

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC = 3.0 V.

CC

active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

4. Not 100% tested.

CC

CC

ACC

15 30 mA

0.2 5 µA

0.2 5 µA

0.2 5 µA

VCC + 0.3 V

V

+ 30 ns.

Am29LV116B 26

DC CHARACTERISTICS (Continued)
Zero Power Flash

25

20

15

10

Supply Current in mA

5

0

0 500 1000 1500 2000 2500 3000 3500 4000

PRELIMINARY

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

8

6

4

Supply Current in mA

2

0

12345

21359C-12

3.6 V

2.7 V

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I

vs. Frequency

CC1

27 Am29LV116B

21359C-13

TEST CONDITIONS

PRELIMINARY

Table 11. Test Specifications

3.3 V

Test Condition 80R 90, 120 Unit

Device

Under

Test

C

L

6.2 kΩ

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

2.7 kΩ

21359C-14

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

L

30 100 pF

1.5 V

1.5 V

3.0 V

0.0 V

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

1.5 V 1.5 V

Figure 12. Input Waveforms and Measurement Levels

KS000010-PAL

OutputMeasurement LevelInput

21359C-15

Am29LV116B 28

AC CHARACTERISTICS
Read Operations

PRELIMINARY

Parameter

JEDEC Std Test Setup 80R 90 120 Unit

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

Description

t

Read Cycle Time (Note 1) Min 80 90 120 ns

RC

t

Address to Output Delay

ACC

t

Chip Enable to Output Delay OE# = V

CE

t

Output Enable to Output Delay Max 30 35 50 ns

OE

t

Chip Enable to Output High Z (Note 1) Max 25 30 30 ns

DF

t

Output Enable to Output High Z (Note 1) Max 25 30 30 ns

DF

CE# = V
OE# = V

IL

Max 80 90 120 ns

IL

Max 80 90 120 ns

IL

Speed Option

Read Min 0 ns

Output Enable

OEH

Hold Time (Note 1)

Toggle and
Data# Polling

Output Hold Time From Addresses, CE# or OE#,

t

OH

Whichever Occurs First (Note 1)

Min 10 ns

Min 0 ns

t

AXQX

t

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 11 for test specifications.

t

RC

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 13. Read Operations Timings

t

OH

t

DF

HIGH Z

21359C-16

29 Am29LV116B

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

PRELIMINARY

t

READY

t

READY

RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

t

RESET# Pulse Width Min 500 ns

RP

RESET# High Time Before Read (See Note) Min 50 ns

t

RH

RESET# Low to Standby Mode Min 20 µs

t

RPD

RY/BY# Recovery Time Min 0 ns

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t

RP

t

Ready

Max 20 µs

Max 500 ns

t

RH

RY/BY#

CE#, OE#

RESET#

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 14. RESET# Timings

t

RB

21359C-17

Am29LV116B 30

AC CHARACTERISTICS
Erase/Program Operations

Parameter

PRELIMINARY

80R 90 120JEDEC Std. Description Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

VCS

t

RB

t

BUSY

Write Cycle Time (Note 1) Min 80 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 50 ns
Data Setup Time Min 35 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time (Note 1) Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 35 35 50 ns
Write Pulse Width High Min 30 ns
Programming Operation (Note 2) Typ 9 µs

Sector Erase Operation (Note 2) Typ 0.7 sec
VCC Setup Time (Note 1) Min 50 µs
Recovery Time from RY/BY# Min 0 ns
Program/Erase Valid to RY/BY# Delay Min 90 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

31 Am29LV116B

AC CHARACTERISTICS

PRELIMINARY

Program Command Sequence (last two cycles)

t

WC

Addresses

555h

CE#

t

GHWL

OE#

t

WP

WE#

t

CS

t

DS

t

Data

A0h

RY/BY#

t

VCS

V

CC

Notes:

1. PA = program address, PD = program data, D

Figure 15. Program Operation Timings

t

AS

PA PA

t

AH

t

CH

t

WPH

DH

PD

t

BUSY

is the true data at the program address.

OUT

Read Status Data (last two cycles)

PA

t

WHWH1

Status

D

OUT

t

RB

21359C-18

Erase Command Sequence (last two cycles) Read Status Data

t

AS

555h for chip erase

VA

t

AH

VA

Addresses

t

WC

2AAh SA

CE#

t

GHWL

t

t

WP

t

DS

55h

CH

t

WPH

t

DH

30h

10 for Chip Erase

t

BUSY

t

WHWH2

In

Progress

Complete

t

RB

OE#

WE#

Data

t

CS

RY/BY#

t

VCS

V

CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

21359C-19

Figure 16. Chip/Sector Erase Operation Timings

Am29LV116B 32

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

WE#

DQ7

OEH

t

ACC

t

t
VA

CE

t

RC

OE

PRELIMINARY

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

21359C-20

Figure 17. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note: V A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.

21359C-21

Figure 18. Toggle Bit Timings (During Embedded Algorithms)

33 Am29LV116B

PRELIMINARY

AC CHARACTERISTICS

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.

Erase

Erase

Suspend

Erase Suspend

Enter Erase

Suspend Program

Read

Figure 19. DQ2 vs. DQ6

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std. Description Unit

Erase

Complete

21359C-22

t

VIDR

t

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

CE#

WE#

RY/BY#

VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector

Unprotect

t

VIDR

Min 4 µs

t

VIDR

Program or Erase Command Sequence

t

RSP

21359C-23

Figure 20. Temporary Sector Unprotect Timing Diagram

Am29LV116B 34

AC CHARACTERISTICS

V

ID

V

RESET#

IH

PRELIMINARY

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

Data

60h 60h 40h

1 µs

Sector Protect: 100 µs

Sector Unprotect: 10 ms

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 21. Sector Protect/Unprotect Timing Diagram

Status

21359C-24

35 Am29LV116B

PRELIMINARY

AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations

Parameter

80R 90 120JEDEC Std. Description Unit

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

t

WHWH2

Write Cycle Time (Note 1) Min 80 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 50 ns
Data Setup Time Min 35 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 n s

WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 35 35 50 ns
CE# Pulse Width High Min 30 ns
Programming Operation (Note 2) Typ 9 µs

Sector Erase Operation (Note 2) Typ 0.7 sec

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29LV116B 36

AC CHARACTERISTICS

PRELIMINARY

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program
2AA for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
555 for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

RY/BY#

Note: PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
the device. Figure indicates the last two bus cycles of the command sequence.

Figure 22. Alternate CE# Controlled Write Operation Timings

= data written to

OUT

21359C-25

37 Am29LV116B

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s
Chip Erase Time 25 s
Byte Programming Time 9 300 µs

Chip Programming Time (Note 3) 18 54 s

Excludes 00h programming
prior to erasure (Note 4)

Excludes system level
overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles per sector.

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V
(including A9, OE#, and RESE T#)

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

on all pins except I/O pins

SS

–1.0 V 12.5 V

Current –100 mA +100 mA

V

CC

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

Control Pin Capacitance VIN = 0 7.5 9 pF

= 0 8.5 12 pF

OUT

C

C

C

IN

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

Am29LV116B 38

PRELIMINARY

PHYSICAL DIMENSIONS*

TS 040—40-Pin Standard TSOP (measured in millimeters)

Pin 1 I.D.

1

40

0.95

1.05

9.90

10.10

0.50 BSC

20

18.30

18.50

19.80

20.20

1.20

MAX

0.25MM (0.0098") BSC

21

0˚
5˚

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

TSR040—40-Pin Reverse TSOP (measured in millimeters)

Pin 1 I.D.

1

40

0.08

0.20

0.10

0.21

9.90

10.10

0.05

0.15

16-038-TSOP-1_AC
TS 040
4-25-96 lv

1.05

20

18.30

18.50

19.80

20.20

1.20

MAX

0˚

0.25MM (0.0098") BSC

5˚

* For reference only. BSC is an ANSI standard for Basic Space Centering.

39 Am29LV116B

21

0.50

0.70

0.08

0.20

0.10

0.21

0.50 BSC

0.05

0.15

16-038-TSOP-1_AC
TSR040
4-25-96 lv

REVISION SUMMARY

PRELIMINARY

Revision B

Global

Deleted SO package from data sheet.

Revision C

Alternate CE# Controlled Erase/Program Operations

Changed t

from 45 to 35 ns on 80R and 90 speed

CP

options.

Revision C+1

Global

Changed data sheet status to Preliminary.

Reset Command

Deleted the last paragraph in this section.

Revision C+2

Figure 1, In-System Sector Protect/Unprotect Algorithms

In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the path from “Protect ano ther sec­tor?” back to setting up the next sec tor address.

AC Characteristics

Erase/Program Operations; Altern ate CE# Controlled
Erase/Program Operations:

ence for t

WHWH1

and t

100% tested. Corrected the note reference for t

Corrected the notes refer-

WHWH2

. These parameters are

VCS

This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for t

. This parameter is not

VIDR

100% tested.

Figure 21, Sector Protect/Unpro tect Timing Diagram

A valid address is not required for the first write cycle;
only the data 60h.

Erase and Programming Performance

In Note 2, the wor st case enduranc e is now 1 million
cycles.

.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV116B 40