Datasheet AM29LV002T-90RFIB, AM29LV002T-90RFI, AM29LV002T-90RFEB, AM29LV002T-90RFE, AM29LV002T-90RFC Datasheet (AMD Advanced Micro Devices)

PRELIMINARY

Am29LV002

2 Megabi t (256 K x 8-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single p ower su pply operation

— Full vol t ag e r ange : 2. 7 t o 3.6 v o l t re ad an d w r ite

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with
high performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

ns

— Regulated voltage range: access times as fast

as 90 ns

■ Embedded Algorithms

— Embedded Erase a lgorithms au tomatically

preprogram and erase the entire chip or any
combination of designated sectors

— Embedded Program algorithms automatically

write and veri fy bytes or w ords at specified
addres ses

■ Typical 1,000,000 write cycles per sector

(100,000 cycles minimum guaranteed)

■ Package option

— 40-pin TSOP

■ Ultra low power consumption (typical values at

5 MHz)

— Automatic Sleep Mode: 200 nA
— Standby mode: 200 nA
— Read mode: 10 mA
— Program/erase mode: 20 mA

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyt e sectors

— Supports control code and data storage on a

single device

— Sector Protection features:

A hardware method of locking a sector to
preve nt any prog ram or erase operations within
that sector

T empor ary Sect or Unprote ct featu re allows c ode
changes in previously locked sectors

■ Top or bottom boot block confi gurations

available

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation compl etion

■ Ready/Bu sy # pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Su s pe nd/E r as e Resume featur e

— Suspends an erase operation to read data from,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to the read

mode

Issu e Date: March 1998

.Publication# 21191 Rev: C Amendment/+2

1

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV002 is a 2 Mbit, 3.0 Volt-only Flash
memory organized as 262,144 bytes. The device is
offered in a 40-pin TSOP package. The byt e-wide (x8)

data appears on DQ7– DQ0. All read, program, an d
erase operations are accomplished using only a single
power supply. The device can also be programmed in
standard EPROM programmers.

The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. T o eliminate bus conten­tion the d evice ha s separat e chip en able (CE #), writ e
enable (WE#) and output enable (OE#) controls .

The device requires only a single 3.0 volt power sup-
ply for both rea d an d write functions. Inte rna l ly g en er ­ated and r egulated voltages a re provided for th e
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using
standard microprocessor write timings. Register con­tents serve as input to an internal state-machine that
controls the er ase and programming ci rcuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data ou t of the de vice is si milar to r eading fr om othe r
Flash or EPR O M dev ic es.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matical ly time s the program pulse widths and ver ifies
proper cell margin.

Device erasure occurs by executing the erase com­mand se quence. T his init iates th e Embedded Erase
algorithm—an internal algorithm that automatically pre­programs the array (if it is not already programmed) be­fore executing the erase operation. During erase, the
device au tom atically time s th e e ra se pulse widths an d
verifies proper cell margin.

The host system can detect whether a program or
erase op eratio n is co mpl ete by o bse rving th e RY/B Y#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been com p lete d, the device i s re ad y to rea d a rra y
data o r accept another command.

The sector erase architecture allow s memo ry s ector s
to be er ased and reprog rammed withou t affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

detector that au tomatically inhibits write opera-

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operat ions in any combina tion of the s ectors of m em­ory. This is achieved via programming eq uipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates a ny operatio n
in progress and resets the internal state machine to
reading array data. The RESET# pin may b e ti ed to t he
system reset circuitry. A system reset would thus als o
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When
addres ses have be en stable for a s p ec if ied a mo un t o f
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power co nsumpt ion is greatly reduc ed in bot h
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bits w ithin
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

2 Am29LV002

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV002
Ordering Part Number: VCC = 3.0–3.6 V (regulated voltage range) -90R

VCC = 2.7–3.6 V (full voltage range) -100 -120 -150
Max access time (ns) 90 100 120 150
CE# access time (ns) 90 100 120 150
OE# access time (ns) 40 40 50 55

BLOCK DIAGRAM

V

CC

V

SS

RESET#

WE#

CE
OE

A0–A17

RY/BY#

State

Control

Command

Register

PGM Voltage

Generator

TimerVCC Detector

Sector

Switches

Erase Voltage

Generator

Output Enable

STB

Chip Enable

Logic

Y-Decoder

Address Latch

Input/Output

STB

DQ0–DQ7

Buffers

Data Latch

Y-Gating

Cell MatrixX-Decoder

21191C-1

Am29LV002 3

CONNECTION DIAGRAMS

PRELIMINARY

A16
A15
A14
A13
A12
A11

A9
A8

WE#

RESET#

NC

RY/BY#

NC

A7
A6
A5
A4
A3
A2
A1

A17
V

SS

NC
NC

A10
DQ7
DQ6
DQ5
DQ4

V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0

OE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Standard 40-Pin TSOP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A17
V

SS

NC
NC
A10
DQ7
DQ6
DQ5
DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0
OE#

V

SS

CE#
A0

A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
NC
A7
A6
A5
A4
A3
A2
A1

Reverse 40-Pin TSOP

4 Am29LV002

21191C-2

PRELIMINARY

PIN CONFIGURATION

A0–A17 = 18 add re ss e s
DQ0–DQ7 = 8 data inputs/o utputs
CE# = Chip enable
WE# = Write enable
OE# = Output enable
RESET# = Reset pin
RY/BY# = Ready/Busy# pin
V

= 3.0 volt-only single power supply

CC

V

SS

NC = Pin not connected internally

(see Product Selector Guide for speed

options and voltage supply tolerances)

= Device ground

LOGIC SYMBOL

18

A0–A17

CE#
OE#

WE#
RESET# RY/BY#

8

DQ0–DQ7

21191C-3

Am29LV002 5

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.

CE-90RAM29LV002 T

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

AM29LV002T-90R,
AM29LV002B-90R

V

= 3.0–3.6 V

CC

AM29LV002T-100,
AM29LV002B-100

AM29LV002T-120,
AM29LV002B-120

AM29LV002T-150,
AM29LV002B-150

Valid Combinations

EC, EI, FC, FI

EC, EI, EE,

FC, FI, FE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

DEVICE NUMBER/DE SCRIP TION

Am29LV002
2 Megabit (256 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Program and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

6 Am29LV002

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memo ry location.
The reg iste r is co mposed of lat che s that store the co m­mands, along with the address and data information
needed to execu te the com mand . The co nte nts of th e

Table 1. Am29LV002 Device Bus Operations

Operation CE# OE# WE# RESET# Addresses DQ0–DQ7

Read L L H H A
Write L H L H A

±

V

Standby
Output Disable L H H H X High-Z

Reset X X X L X High-Z
Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

IL

CC

0.3 V

XX

register serve a s input s to the inter nal sta te mac hine.
The state machine outputs dictate the function of the
device. Table 1 lists the devi ce bus op erat ions , the in­puts and control levels they require, and the resulting
output. The following subsections describe eac h of
these operations in further detail.

D

D

D

= Data Out

OUT

OUT

VCC ±

0.3 V

ID

IN
IN

X High-Z

A

IN

IN

IN

Requirements for Reading Array Data

To read arra y data from the ou tputs, the sys tem must
drive the CE# and OE # pins to V

. CE# is the power

IL

control an d sel ects the de vice . OE# is th e outpu t con­trol and gates array data to the output pins. WE#
should remain at V

.

IH

The int er na l st a te ma c hin e i s s et f or re ad i ng ar ra y da ta
upon d evic e p ower-up, or a fter a ha rd w ar e res et. This
ensures that no spurious alteration of the memory con­tent oc cur s du ring the pow er tra nsi tion . N o comma nd i s
necessary in this mod e to obtain array da ta. Stand ard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered .

See “R ead ing Ar ray Data” fo r more info rmatio n. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 12 for the timing waveforms. I

CC1

in

the DC Characteristics table represents the active cur­rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory ), the sy stem m ust drive WE# an d
CE# to V

, and OE# to VIH.

IL

An eras e op e ra tio n ca n er ase on e s ect or, multipl e s ec­tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad­dress” consist s of the address bits required to uniquely
select a sector. See the “Command Definitions” section
for d eta i ls o n er asi n g a se c t or o r th e e nt ire c h ip, or su s­pending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can th en re ad aut ose lect codes fr om th e inter ­nal register (which is separate from the memory array)
on DQ7– DQ0 . St anda rd r ead cycle ti ming s ap ply in this
mode. Re fer to th e “ Autoselect Mode” and “Auto sel e ct
Command Sequence” sections for more information.

I

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The AC
Charac ter isti cs se ctio n co ntai ns tim ing speci fi cati on ta­bles and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specificati ons apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

CC

Am29LV002 7

PRELIMINARY

Standby Mode

When th e sy st em is not read ing or wr itin g to the dev ice,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The dev ice en ter s t he CM OS st an dby mode wh en th e
CE# and RESET# pins are both held at V

CC

± 0.3 V.
(Note th at thi s is a mor e res trict ed vol tage rang e tha n
V

.) If CE# and RESET# are held at VIH, but no t wit hin

IH

V

± 0.3 V, the device will be in the standby mode, but

CC

the standby current will be greater. The device requires
standard access time (t

) for read access when the

CE

device is i n e ith er of these stand by modes, b efore it is
ready to read data.

If the device i s desele cte d during erasur e or pro gram ­ming, the device draws active current until the
operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specifications.

Automatic Sleep Mode

The au tomatic sl eep mode m inimizes F lash devi ce
energy co nsumption. The device automatically
enables this mode when addresses remain stable for
t

+ 30 ns. The automatic sleep mode is

ACC

independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
the system. I

in the D C Characteris tics table

CC5

represents the automatic sleep mode current
specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset­ting the device to reading array data. When the system

drives the RESET# pin to V

for at le ast a per iod of tRP,

IL

the device immediately terminates any operation in
progress , tri states all da ta output p ins, and igno res all
read/write atte mpts for the durati on of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The oper ation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET #
pulse. When RESET# is held at V

draws CMOS standby current (I
at V

but no t wi t hin VSS±0.3 V, the standby current will

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system rese t would thus also res et th e Flas h
memory, enabling the system to read the boot-up
firmware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operation is complete, whi ch requires a
time of t

(durin g Embedde d Algorit hms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY # pin is “1 ”), the re set oper ation is c omplet ed
within a time of t
rithms). The system can read data t
SET# pin returns to V

(not during Embedded Algo-

READY

.

IH

RH

after the RE-

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabl e d . Th e o ut p ut pi n s ar e pl a c ed i n t he h igh i m ped­ance state.

8 Am29LV002

PRELIMINARY

Table 2. Secto r Add re ss Tables (Am29LV002T)

Sector A17 A16 A15 A14 A13 Sector Size Address Range

SA0 0 0 X X X 64 Kbytes 00000h–0FFFFh
SA1 0 1 X X X 64 Kbytes 10000h–1FFFFh
SA2 1 0 X X X 64 Kbytes 20000h–2FFFFh
SA3 1 1 0 X X 32 Kbytes 30000h–37FFFh
SA411100 8 Kbytes 38000h–39FFFh
SA511101 8 Kbytes 3A000h–3BFFFh
SA61111X 16 Kbytes 3C000h–3FFFFh

Table 3. Sector Add ress Tables (Am29LV002B)

Sector A17 A16 A15 A14 A13 Sector Size Address Range

SA00000X 16 Kbytes 00000h–03FFFh
SA100010 8 Kbytes 04000h–05FFFh
SA200011 8 Kbytes 06000h–07FFFh
SA3 0 0 1 X X 32 Kbytes 08000h–0FFFFh
SA4 0 1 X X X 64 Kbytes 10000h–1FFFFh
SA5 1 0 X X X 64 Kbytes 20000h–2FFFFh
SA6 1 1 X X X 64 Kbytes 30000h–3FFFFh

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to auto mati ca lly match a de vice to b e pr ogra mmed with
its corresponding programming al gorithm. However,
the aut osel ect co des can also be a cces sed in -sy stem
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12. 5 V) on addr ess pin

ID

A9. Addre ss pins A6, A1, and A0 must be as sho wn i n
Table 4. In addition, when verifying sector protection,

the sector ad dress must app ear on the appro priate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care.
When all necessary bits have been set as required, the
programming equipment may then read the corre­sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V

. See “Command Definitions” for

ID

details on using the autoselect mode.

Am29LV002 9

PRELIMINARY

Table 4. Am29LV002 Autoselect Codes (High Voltage Method)

Description CE# OE# WE#

A17

to

A13

A12

to

A10 A9

A8

to

A7 A6

A5

to

A2 A1 A0

DQ7

to

DQ0

Manufacturer ID: AMD L L H X X V
Device ID: Am29LV002T

(Top Boot Block)
Device ID: Am29LV002B

(Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

LLHXXV

LLHXXV

XLXLL 01h

ID

XLXLH 40h

ID

XLXLH C2h

ID

XLXHL

ID

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hard­ware sector unprotection feature re-enables both pro­gram and eras e operat ions in p reviou sly prot ected
sectors.

Sector protection/unprotection must be implemented
using programming equipment. The procedure
requires a high voltage (V
OE#. D eta ils o n this method ar e pr ovid ed i n a sup pl e ­ment, publication number 21224. Contact an AMD rep­resentative to request a copy.

The device is shipped with all secto rs unprotected .
AMD offers the option of progra mming and prote cting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.

) on address pin A9 and

ID

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

ID

IH

01h

(protected)

00h

(unprotected)

It is p ossi ble t o det ermi ne wh ethe r a s ector is p rotec ted
or unprotected. See “Autoselect Mode” for details .

Notes:

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

ously protected sectors to change data in-system. The
Sector U n pr ote ct m od e i s a cti va ted by s e tting th e R E­SET# pin t o V

. During thi s mod e, form erly pr otecte d

ID

Figure 1. Temporary Sector Un protec t Operation

sector s can b e pr o gr amm ed or er as ed by s ele ct i ng t he
sector addres ses. Once V

is remove d fro m the RE -

ID

SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 19 shows the timing waveforms, for this feature.

10 Am29LV002

21191C-4

again.

PRELIMINARY

Hardware Data Protection

The command sequence requir ement of unlock cycle s
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com­mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or prog ramm ing, w hich m ig ht othe rwis e be ca use d by
spurious system level signals during V

power-up

CC

and power-down transition s, or from system noise.

Low V

When V
cept any write cycles. This protects data during V

Write I nhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater t han V

. The system must p rovide the

LKO

CC

COMMAND DEFINITIONS

Writing specific ad dress and data commands or se­quences into the command register initiates device op­erations. Table 5 defines the valid register command
sequences. W riting incor rect ad dress and da ta val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after d evice power- up. N o comm ands ar e requ ired t o
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend command,
the dev ice enters the Erase Susp end m ode . The sys ­tem can read ar ray data using th e standa rd read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outpu ts status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.

The system
ble the device for reading array data if DQ5 goes high,
or while in the a utoselect mode. Se e the “R eset C om ­mand” section, next.

must

iss ue t he r eset comm a nd t o re-ena -

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =
V

, CE# = VIH or WE# = VIH. To initiate a write cycle ,

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during po wer up, the

IL

device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.

See also “Requirements for Reading Array Data” in the
“Devic e B u s Op er at io ns ” section f or m ore in for ma t ion .
The Read Operations table provides the read parame­ters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the de­vice to r ea di n g a rr ay da ta. A dd re ss bits are do n’ t car e
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This reset s the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is compl ete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programmi ng begins. This resets the device to
reading a rray data (a lso applie s to programm ing in
Erase Su spend mode ). Once p rogrammin g begins,
however, the device ignores r eset co m mand s until th e
operat ion i s comp l et e.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
be written to re turn to re ading ar ray data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the res et comm and r eturn s th e devic e to re ad­ing array data (also applies during Erase Suspend).

See “AC Characteristics” for parameters, and to Figure
13 for the timing diagram.

must

Am29LV002 11

PRELIMINARY

Autoselect Command Sequence

The autoselect comm and sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Tab le 5 shows th e address a nd data require ments.
This meth od is an alternative to that show n i n Table 4,
which is intended for PROM programmers and requires
V

on address bi t A9.

ID

The auto sel e c t comm an d se qu enc e i s ini ti a te d by wr i t­ing two unlock cycles, followed by the autos elect com ­mand. The device then enters the autoselect mode,
and the s yste m may r ead at any addre ss any n um ber
of time s, witho ut initia ting ano ther comma nd sequen ce.

A read cycle at address XX00h retrieves the manufac­turer code. A read cy cle a t address X X0 1h r eturn s th e
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protect ed, or 00 h i f it is un pr ote cte d. R e fe r to Tables 2
and 3 for valid sector addresses.

The system must wr ite the reset comma nd to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-up
comman d. T he pr ogra m ad dres s an d dat a are wr itten
next, which in turn initiate the Embedded Program a l­gorithm. The system is
controls or timin gs. The device automat ically provides
intern ally ge ne r at ed p r og ra m pu l se s a nd v e rif y th e pr o­grammed cell marg in. Table 5 shows th e add res s and
data requirements for the byte program command se­quence .

When th e Embe dded Pr ogra m algor ithm is compl ete,
the devic e then returns to readi ng array data a nd ad­dresses a re no l ong er latc hed. The sys tem can de ter­mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately t erminate s the pro gram­ming opera tion. The Byte Prog ram command se­quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.

not

required to provide further

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the oper ation and set DQ5 to “1,” or cau se the Data #
Polling algorithm to indicate the operation was suc­cessful. However , a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Figure 2 illustrates the algorithm for the program oper­ation. S e e th e E ras e a nd Program O per ations tabl e in
“AC Characteristics” for parameters, and to Figure 14
for timing diagrams

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See Table 5 for program command sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

No

Figure 2. P rogram Operation

12 Am29LV002

PRELIMINARY

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase
command s equence i s initiate d by writin g two unloc k
cycles, followed by a set-up command. Two additional
unlock wri t e cyc l es ar e t he n fo ll owe d by th e ch ip era se
command, which in turn invokes the Embedded Erase
algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm aut omatically preprograms and verifies the entire
memo ry for an all zero d ata pa ttern prio r to ele ctric al
erase. The system is not required to pro vide any con­trols or timings during these operations. Table 5 shows
the addr ess and data requirem ents for the chip eras e
command sequence .

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a hard ware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.

The syste m can deter mine the stat us of the e ras e op­eration by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these sta­tus bits. When the Embedded Erase algorithm is com­plete, the device returns to reading array data and
addresses are no longer latched.

Figure 3 illustr ates the algor ithm for the e rase opera­tion. See the Read Operations tables in “AC Character­istics” for parameters, and to Figure 15 for timing
diagrams.

not

require the system to

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is i nitiated by writing two
unlock c ycl es , f o ll owed by a s et- up co mm an d. Two ad­ditional unlock write cycles are then followed by the ad­dress o f th e sector to be er as e d, an d t he s ec tor e ras e
command. Ta ble 5 shows the addre ss and data re­quirements for the sector erase command sequence.

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additi onal secto r addresses and secto r erase com ­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sectors. The time be­tween th es e add it i onal cyc l e s must be less th an 50 µs,
otherwise the last address and command might not be
accepted , and era sur e ma y beg in. It i s re comm ende d
that processor interrupts be disabled during this time to

not

require the system to prepro gram

ensure all commands are accepted. The interrupts can
be re-e nabled after the la st Sec tor Er ase com man d is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector
Erase T imer” sectio n.) The t ime-out begins f rom the ri s­ing edge of the final WE# pulse in the command se­quence .

Once the sector erase operation has begun, only the
Erase Sus p en d co mma nd is v al id. A ll o the r c o mman ds
are ignored. Note that a hardware reset during the
sector er as e op er atio n i m me diately termi n ate s the op­eration . Th e S ec tor E ras e c o mm an d sequence should
be reinitiated once the device has retu rned to rea ding
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latch ed. The system can determ ine the sta ­tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY #. ( Ref er t o “W rit e Oper ati on Stat us” for i nfo rma­tion on these status bits.)

Figure 3 illustr ates the algor ithm for the e rase opera­tion. Refer to the Read Operations tables in the “AC
Characte ristic s” sect ion for pa ramete rs, and to Figure
15 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in­terrupt a sector e rase operation a nd then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip eras e o pera tion o r Em bedd ed P rogr am a lgo­rithm. Writing the Erase Suspend command dur ing the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad­dresses are “don’t- cares” when writing the E r ase Sus­pend command.

When the Era s e Su sp end c o mma nd is written du ring a
sector erase operation, the device requires a maximum
of 20 µs to su spend the er ase operation. H owever,
when the Erase Suspend command is written during
the sector erase tim e-out, th e device imm ediate ly ter­minates the time-out period and suspends the erase
operat ion.

After the erase op eration has been su spended, the
system can read array data from or program data to

Am29LV002 13

PRELIMINARY

any sector not selected for erasure. (The device “erase
suspends” all sec tors selected for erasure.) N ormal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use D Q7 , or DQ6 and DQ2 toge ther, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Op eration St atus” for informat ion on thes e
status bits.

After an erase-suspended program operation is com­plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” f or more information.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows r eading autoselect codes
even at addresses within erasing s ectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Su spend mode, an d is ready for ano ther
valid op er ati o n. Se e “A ut os e lec t Comm an d Se qu en c e”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode an d co nt in ue th e se ct or e ra se op era ti on. Fu rt h er
writes of the Re sume comman d are ig nored. A nothe r
Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

21191C-5

Figure 3. Erase Operation

14 Am29LV002

PRELIMINARY

Table 5. Am29LV002 Command Definitions

Command Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID,

Top Boot Block
Device ID,

Bottom Boot Block
Sector Protect

Autoselect (Note 7)

Verify (Note 8)

Byte Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 555 AA 2AA 55 555 90 X01

4 555 AA 2AA 55 555 90

Bus Cycles (Notes 2–4)

SA

X02

40

C2

00
01

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.

SA = Address of the sector to be erased or verified. Address
bits A17–A13 uniquely select any sector.

Addresses are latched on the falling edge of the WE# or CE#
pulse.

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

4. Address bits A17–A11 are don’t care for unlock and

command cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in

read mode.

6. The Reset command is required to return to the read

mode when the device is in the autoselect mode or if DQ5
goes high.

7. The fourth cycle of the autoselect command sequence is

a read cycle.

8. The data is 00h for an unprotected sector and 01h for a
protected sector.

9. The system may read and program functions in non­erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation.

10. The Erase Resume command is valid only during the
Erase Suspend mode.

Am29LV002 15

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write op eratio n: DQ2, DQ 3, DQ5, DQ6 , DQ7,
and RY/BY#. Table 6 and the following subsections de­scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys­tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edg e of the final
WE# pulse in the program or erase command se­quence .

During the Embedded Program algorithm, the device
outputs on DQ7 the c ompleme nt of the da tum pro­grammed to D Q7. T his DQ 7 status also applies to pro­gramming during Erase Suspend. When the
Embedde d Pro gram al gorith m is co mplete , the devic e
outputs the datum programmed to DQ7. The system
must provide the program addr ess to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 1 µs, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is comp lete, o r if the de vice en ters t he Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the sys tem det ects DQ7 h as changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on t h e
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 16, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.

following

read cycles. This is because DQ7

Ta ble 6 shows th e outputs fo r Data# Polling o n DQ7.
Figure 4 shows the Data# Polling algorithm.

START

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

No

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

21191C-6

Figure 4. Data# Po lling Algorithm

16 Am29LV002

PRELIMINARY

RY/ BY#: Read y/Bu sy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the fina l WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
ble on the 44-pin SO package.)

If the output is low (Busy), the device is actively erasing
or programming. (T his includes programm ing in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. Figures 12, 13,
14 and 15 shows RY/BY# for read, reset, program, and
erase operat ions, respectively.

. (The RY/BY# pin is not availa-

CC

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded
Progra m or Era se alg ori thm is i n progre ss or comple te,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at an y address, and is
valid aft er th e risi n g ed ge of the fin al WE # pu l se in th e
command sequence (prior to the program or erase op­erati on), and during the sector erase time-ou t.

Table 6 shows the outputs for Toggle Bit I on DQ6. Fig­ure 5 shows the toggle bit algorithm in flowchart form,
and the section “Reading Toggle Bits DQ6/DQ2” ex­plains t he a lgor ithm. Figure 17 in th e “ AC Ch ar ac t er is­tics” section shows the toggle bit timing diagrams.
Figure 18 sho ws the differences b etween DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a particular sector is actively erasi ng
(that is, the Embedded Erase algorithm is in progress),
or whet her t hat secto r is eras e-sus pen ded. Toggle Bi t
II is valid after the rising edge of the final WE# pulse in
the command sequence.

DQ2 toggles when the system reads at addresses
within those sectors that have been selected for eras­ure. (The system may use either OE# or CE# to control
the read cycles.) B ut DQ2 ca nnot dist inguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 6 to compare outputs for
DQ2 and DQ6.

During an Embe dded Prog ram or Eras e algor ithm op ­eration, succe ssive read cycles to any a ddress c ause
DQ6 to toggle (The system may use either OE# or CE#
to cont ro l the re ad cy cl es ) . Wh en the op er at i on i s com­plete, DQ6 stops toggling.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array
data. If n ot all selected se cto rs ar e pro te cted , the Em­bedded Erase algorithm erases the unprotected sec­tors, and ignores the selected sector s that are
protect ed.

The system can use DQ6 an d DQ2 togethe r to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is actively erasing (that
is, th e Em be dd e d Er as e alg or i t hm is i n pr og re s s ), D Q6
toggles. When the device enters the Erase Suspend
mode, DQ6 stop s to ggling . Ho wever, the system must
also use DQ2 to deter mine whic h sector s are eras ing
or erase-suspende d. Alter na tively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a protected sector,
DQ6 togg les f or ap proxi mat ely 1 µs afte r the prog ram
comman d s eq uence is wr itten, then re tur ns to r ea di n g
array data.

DQ6 also toggles during the erase-suspend-program
mode, and sto ps toggling once the E mbedded Pro­gram algorithm is complete.

Figure 5 shows the toggle bit algorithm i n flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the “DQ6: Toggle Bit I”
subsecti on. Figur e 17 shows the togg le bit timi ng dia­gram. Figure 18 shows the differences between DQ2
and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When­ever the system initially begins readin g toggle bit sta­tus, it mus t read DQ7–D Q0 at least twice in a ro w to
determine whether a toggle bit is toggling. Typically, the
syste m woul d no te and st o re the v al u e of th e t og gle bi t
after the f irst rea d. After th e second read, th e system
would compare the new value of the toggle bit w ith the
first. If the toggle bit is not toggling, the device has com­pleted the prog ram or er ase oper atio n. Th e syst em can
read array data on DQ7–DQ0 on the following read cy­cle.

However, if after the initial two read cycles, the system
determines that t he toggle bit is still toggling, t he sys ­tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have s top ped toggling j u st a s
DQ5 went high. If the toggle bit is no longer toggling,
the device has su cce ssfu lly comp let ed the prog ram o r
erase operation. If it is still t oggling, t he de vice did not
completed the operation successfully, and the system

Am29LV002 17

PRELIMINARY

must write the reset command to return to reading
array data.

The remaining sc enario is that the system initially de ­termi n es th at th e tog gl e b it i s to gg l i ng a nd D Q 5 ha s n ot
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de­termining the status as des cribed in the previous para­graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

Table 6 shows the outputs for Toggle Bit I on DQ6. Fig­ure 5 sh ows the toggle bi t algorit hm. Fi gure 17 in the

“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 18 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec­tion on “DQ2: Toggle Bit II”.

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

(Note 1)

No

DQ5: Exceeded Timing Limits

DQ5 indi ca te s w h eth er th e p ro gr am or e ra se t i me ha s
exceeded a specified in ternal pulse count lim it. Under
these co ndi tions DQ5 p roduc es a “1.” This is a fa ilur e
condition that indicates the program or erase cycle was
not successfully completed.

The DQ5 failure condition may appear i f the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has

exceeded the timing limits, DQ5 prod uces a “1.”
Under both these conditions, the system must issue

the re set comman d to retur n the dev ice to read ing
array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has b egun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selected for erasure, the entire time­out also applies after each additional sector erase com­mand. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the sys­tem can guarantee that the time between additional
sector erase commands will always be less than 50
µs. See also the “Sector Erase Command Sequence”
section.

After the sector erase command sequence is written,
the sys t em sho ul d re ad th e s t at u s on D Q 7 ( Dat a# Pol l­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all furt he r com man ds (o t he r tha n E ra se S usp en d)

No

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

(Notes
1, 2)

No

Program/Erase

Operation Complete

21191C-7

Figure 5. Toggle Bit Algor ithm

are ignored until the erase opera tion is complete. If
DQ3 is “0”, the device will accept additional se ctor
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prio r to and f ollo wing each su bsequ ent se cto r
erase c omman d. If DQ3 is high on the s econd status
check, the last command might not have been ac­cepted. Table 6 shows the outputs for DQ3.

18 Am29LV002

PRELIMINARY

Table 6. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 2) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Am29LV002 19

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Voltage wit h Respect to Ground

V

(Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

CC

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +13.0 V

All other pins (Note 1) . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot V
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I /O pin s is V
During voltage transitions, input or I/O pins may overshoot
to V

+2.0 V for periods up to 20 ns. See Figure 7.

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for peri ods
up to 20 ns.

3. No mo re tha n on e ou tput may be s horted to ground at a
time. Durat ion of the s hort c ircuit sho uld not be gre ater
than one second.

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any oth er con ditions above tho se indica ted in th e
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

to –2.0 V for periods of up

SS

CC

CC

+0.5 V

SS

+0.5 V.

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

Figure 6. Maximum Negative Overshoot

Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

Figure 7. Maximum Positive Overshoot

Waveform

21191C-8

21191C-9

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) De vices

Ambient Temperature (T

Extended (E) De vices

Ambient Temperature (T

V

Supply Voltages

CC

V

for regulated voltage range. . . . . .+3.0 V to 3.6 V

CC

V

for full voltage range . . . . . . . . . . .+2.7 V to 3.6 V

CC

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

20 Am29LV002

) . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . –55°C to +125°C

A

PRELIMINARY

DC CHARACTERISTICS
CMOS Compatible

Parameter Parameter Description Test Conditions Min Typ Max Unit

V

= VSS to VCC,

I

I

LIT

I

LO

I

CC1

LI

Input Load Current

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current
(Note 1)

IN

V

= VCC

CC

= VSS to VCC,

V

OUT

V

= V

CC

VCC = V
CE# = V

max

; A9 = 12.5 V 35 µA

CC max

CC max

CC max

OE#

IL,

;

= VIH

5 MHz 10 16 mA
1 MHz 2 4 mA

±1.0 µA

±1.0 µA

I

I

I

I

V
V
V

V

CC2

CC3

CC4

CC5

V
V

V

OL

OH1

OH2

LKO

VCC Active Write Current
(Notes 2, 4)

VCC Standby Current

VCC Standby Current During
Reset

Automatic Sleep Mode (Note 3)

IL

IH

ID

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 x V
Voltage for Autoselect and

Temporary Sector Unprotect
Output Low Voltage IOL = 4.0 mA, VCC = V

Output High Voltage

Low VCC Lock-Out Voltage (Note

4)

VCC = V
CE# = V

= V

V

CC

CE#, RESET# = V
VCC = V

RESET# = V

= V

V

CC

V

= V

IL

= 3.3 V 11.5 12.5 V

V

CC

I

= –2.0 mA, VCC = V

OH

IOH = –100 µA, VCC = V

CC max

IL,

CC max

CC max

CC max

± 0.3 V

SS

OE#

SS

;

= VIH

;

CC

;

± 0.3 V

; VIH = V

±0.3 V

± 0.3 V;

CC

0.45 V

CC min

0.85 V

CC min

VCC–0.4

CC min

2.3 2.5 V

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.

CC

active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

4. Not 100% tested.

CC

CC

+ 30 ns.

ACC

20 30 mA

0.2 5 µA

0.2 5 µA

0.2 5 µA

VCC + 0.3 V

V

Am29LV002 21

PRELIMINARY

DC CHARACTERISTICS (Continued)
Zero-Power Fl a s h

25

20

15

10

Supply Current in mA

5

0

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 8. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

15

10

5

Supply Current in mA

0

1 2345

3

Frequency in MHz

V

6

.

V

7

.

2

21191C-10

Note: T = 25 °C

Figure 9. Typical I

CC1

22 Am29LV002

21191C-11

vs. Frequency

TE S T CONDITIONS

Device

Under

Test

C

L

6.2 kΩ

PRELIMINARY

3.3 V

2.7 kΩ
Output Load 1 TTL gate

Output Load Capacitance, C
(including jig capacitance)

Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V

Table 7. Test Specifications

-90R,

Test Condition

-100

L

-120,

-150 Unit

30 100 pF

Note: Diodes are IN3064 or equivalent

Figure 10 . Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

21191C-12

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

1.5 V

1.5 V

KS000010-PAL

3.0 V

0.0 V

1.5 V 1.5 V

Figure 11. Input Waveforms and Measuremen t Levels

Am29LV002 23

OutputMeasurement LevelInput

21191C-13

AC CHARACTERISTICS
Read Operations

PRELIMINARY

Parameter

JEDEC Std Test Setup -90R -100 -120 -150 Unit

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

Read Cycle Time (Note 1) Min 90 100 120 150 ns

RC

t

Address to Output Delay

ACC

t

Chip Enable to Output Delay OE# = V

CE

t

Output Enable to Output Delay Max 40 40 50 55 ns

OE

t

Chip Enable to Output High Z (Note 1) Max 30 30 30 40 ns

DF

t

Output Enable to Output High Z (Note 1) Max 30 30 30 40 ns

DF

Description

CE# = V
OE# = V

IL

Max 90 100 120 150 ns

IL

Max 90 100 120 150 ns

IL

Speed Option

Read Min 0 ns

Output Enable

t

t

AXQX

OEH

Hold Time (Note 1)

Output Hold Time From Addresses, CE# or

t

OH

OE#, Whichever Occurs First (Note 1)

Toggle and
Data# Polling

Min 10 ns

Min 0 ns

Notes:

1. Not 100% tested.

2. See Figure 10 and Table 7 for test specifications.

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

t

RC

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 12. Read Operations Timings

t

OH

t

DF

HIGH Z

21191C-14

24 Am29LV002

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std. Test Setup Unit

PRELIMINARY

t

READY

t

READY

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

t

RESET# Pulse Width Min 500 ns

RP

t

RESET# High Time Before Read (See Note) Min 50 ns

RH

t

RY/BY# Recovery Time Min 0 ns

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

Max 20 µs

Max 500 ns

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

RY/BY#

CE#, OE#

RESET#

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 13. RESET# Timings

t

RB

21191C-15

Am29LV002 25

AC CHARACTERISTICS
Erase and Program Operations

Parameter

PRELIMINARY

-90R -100 -120 -150JEDEC Std Description Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

VCSVCC

t

RB

t

BUSY

Write Cycle Time (Note 1) Min 90 100 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 50 50 50 65 ns
Data Setup Time Min 50 50 50 65 ns
Data Hold Time Min 0 ns
Output Enable Setup Time (Note 1) Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 50 50 50 65 ns
Write Pulse Width High Min 30 30 30 35 ns
Programming Operation (Note 2) Typ 9 µs

Sector Erase Operation (Note 2) Typ 1 sec

Setup Time (Note 1) Min 50 µs
Recovery Time from RY/BY# Min 0 ns
Program/Erase Valid to RY/BY# Delay Min 90 ns

Notes:

1. Not 100% tested.

2. See the Erase and Programming Performance table for more information.

26 Am29LV002

AC CHARACTERISTICS

PRELIMINARY

Program Command Sequence (last two cycles)

t

WC

Addresses

555h

CE#

t

GHWL

OE#

t

WP

WE#

t

CS

t

DS

t

Data

A0h

RY/BY#

t

VCS

V

CC

Notes:

1. PA = program address, PD = program data, D

Figure 14. Program O peration Timings

t

AS

PA PA

t

AH

t

CH

t

WPH

DH

PD

t

BUSY

is the true data at the program address.

OUT

Read Status Data (last two cycles)

PA

t

WHWH1

Status

D

OUT

t

RB

21191C-16

Erase Command Sequence (last two cycles) Read Status Data

t

AS

555h for chip erase

VA

t

AH

VA

Addresses

t

WC

2AAh SA

CE#

t

GHWL

t

OE#

WE#

Data

t

CS

CH

t

WP

t

WPH

t

DS

t

DH

55h

30h

10 for Chip Erase

t

BUSY

t

WHWH2

In

Progress

Complete

t

RB

RY/BY#

t

VCS

V

CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

21191C-17

Figure 15. Chip/Sector Erase Operation Timings

Am29LV002 27

AC CHARACTERISTICS

Z

Addresses

t

ACC

CE#

t

CH

OE#

t

OEH

WE#

DQ7

PRELIMINARY

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

21191C-18

Figure 16. Data# Polling Timings (During Embedded Al gorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note: VA = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.

21191C-19

Figure 17. Toggle Bit Timings (During Embedded Algorithms)

28 Am29LV002

AC CHARACTERISTICS

PRELIMINARY

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Erase

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.

Figure 18. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std. Description Unit

t

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector

t

RSP

Unprotect

Min 4 µs

Erase

Complete

21191C-20

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

12 V

0 or 3 V

t

VIDR

Program or Erase Command Sequence

t

RSP

Figure 19. Temporary Sector Unprotect Timing Diagram

t

VIDR

0 or 3 V

21191C-21

Am29LV002 29

AC CHARACTERISTICS
Erase and Program Operations

Alternate CE# Controlled Writes

Parameter

PRELIMINARY

-90R -100 -120 -150JEDEC Std Description Unit

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

t

WHWH2

Write Cycle Time (Note 1) Min 90 100 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 50 50 50 65 ns
Data Setup Time Min 50 50 50 65 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 50 50 50 65 ns
CE# Pulse Width High Min 30 30 30 35 ns
Programming Operation (Note 2) Typ 9 µs

Sector Erase Operation (Note 2) Typ 1 sec

Notes:

1. Not 100% tested.

2. See the Erase and Programming Performance table for more information.

30 Am29LV002

AC CHARACTERISTICS

o

555 for program
2AA for erase

PRELIMINARY

PA for program
SA for sector erase
555 for chip erase

Data# Polling

Addresses

WE#

OE#

CE#

Data

RESET#

RY/BY#

PA

t

WC

t

WH

t

WS

t

RH

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

PD for program
30 for sector erase
10 for chip erase

BUSY

t

WHWH1 or 2

DQ7# D

OUT

Note: PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
the device. Figure indicates the last two bus cycles of the command sequence

Figure 20. Alternate CE# Controlled Write Operation Timings

= data written t

OUT

21191C-22

Am29LV002 31

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s
Chip Erase Time 2.8 s
Byte Programming Time 9 300 µs

Chip Programming Time (Note 3) 2.3 6.8 s

Excludes 00h programming
prior to erasure (Note 4)

Excludes system level
overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 100,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.

6. The device has a typical erase and program cycle endurance of 100,000 cycles per sector. 100,000 cycles are guaranteed.

LATCHUP CHARACTERISTICS

Min Max

Input voltage with respect to V
(including A9, OE#, and RESET#)

Input voltage with respect to V
V

Current –100 mA +100 mA

CC

on all pins except I/O pins

SS

on all I/O pins –1.0 V VCC + 1.0 V

SS

–1.0 V 13.0 V

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

C

IN

C

OUT

C

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

= 0 8.5 12 pF

OUT

Control Pin Capacitance VIN = 0 7.5 9 pF

32 Am29LV002

PRELIMINARY

PHYSICAL DIMENSIONS*

TS 040—40-Pin (measured in millimeters)

Pin 1 I.D.

1

20

18.30

18.50

19.80

20.20

1.20

MAX

0.95

1.05

40

9.90

10.10

0.50 BSC

21

0.05

0.15

0.08

0.20

0.10

0

0.21

5

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

TSR040—40-Pin (measured in millimeters)

Pin 1 I.D.

1

20

18.30

18.50

19.80

20.20

1.20

MAX

0
5

40

21

16-038-TSOP-1_AE
TS 040
2-27-97 lv

0.95

1.05

9.90

10.10

0.50 BSC

0.05

0.15

0.08

0.20

0.10

0.21

0.50

0.70

16-038-TSOP-1_AE
TSR040
2-27-97 lv

Am29LV002 33

PRELIMINARY

REVISION SUMMARY FOR AM29LV002
Revision C+1

Global

Revised form atting to b e con siste nt w ith ot her c urren t

3.0 volt-only data sheets.

Absolute Maximum Ratings

The vo ltage with res pect to gr ound for V
+4.0 V.

should be

CC

Revision C+2

AC Characteristics

Erase/Program Operations; Erase and Program Oper­ations Alternate CE# Controlled Writes:

notes reference for t

WHWH1

and t

WHWH2

eters are 100% tested. Corrected the note reference
for t

. This parameter is not 100% tested.

VCS

Temporary Sector Unprotec t Table

Added note reference for t

. This para meter i s not

VIDR

100% test ed .

Correcte d th e

. These pa ram-

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

34 Am29LV002