Datasheet AM29LV001BT-90FI, AM29LV001BT-90FEB, AM29LV001BT-90FE, AM29LV001BT-90FCB, AM29LV001BT-90FC Datasheet (AMD Advanced Micro Devices)

PRELIMINARY

Am29LV001B

1 Megabit (128 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sec tor Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3. 6 volt read and write

operations for battery-powered applications

— Regulated voltage r ange: 3.0 to 3.6 v olt read and

write operations and for compatibility with high
performance 3.3 volt microprocessors

■ Manufactured on 0.35 µm process technology

■ High performance

— Full voltage range: ac cess times as f ast as 55 ns
— Regulated voltage range: access times as fast

as 45 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current

■ Flexible sector architecture

— One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte
— Supports full chip erase
— Sector Protection features:

Hardware method of loc king a sector to prevent
any program or erase operat ions within that
sector

Sectors can be locked in-system or via
programming equipment

T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors

■ Unlock Bypass Mode Program Co mmand

— Reduces overall programming time when

issuing multiple program command sequences

■ Top or bottom boot block configurations

available

■ Embedded Al gorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Minimum 1,000,000 write cycle guarantee per

sector

■ Package option

— 32-pin TSOP
— 32-pin PLCC

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Erase Suspend/Erase Resume

— Supports reading data from or programming

data to a sector that is not being erased

■ Hardware reset pin (RESET#)

— Hardware method for resetting the device to

reading array data

Publication# 21557 Rev: C Amendment/0
Issue Date: April 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash
memory devic e organized as 131,072 bytes. T he
Am29LV001B has a boot sector architecture.

The device is offered in 32-pin PLCC and 32-pin TSOP

packages. The byte-wide (x8) data appears on DQ7–
DQ0. All read, erase, and program operations are
accomplished using only a single power supply. The
device can also be programmed in s tandard EPROM
programmers.

The standard Am29LV001B offers access times of 45,
55, 70, and 90 ns, allowing high speed m icroproces­sors to operate without wait states. To eliminate bus
contention, the device has separate chip enab le (CE#),
write enable (WE#) and output enable (OE#) controls.

The device requires only a single power supply (2.7
V–3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.

The Am29LV001B is entirely command set compatible
with the JEDEC single-power-supply Flash
standard. Commands are written to t he command reg­ister using standard microprocessor write timings. Reg­ister contents ser ve as input to an internal state­machine that controls the erase and programming cir­cuitry. Write cycles also internally latch addresses and
data needed for the programming and erase op era­tions. Reading data out of the device is similar to
reading from other Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requir ing only two
write cycles to program data instead of four.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an in ternal algorithm that autom atically
preprograms the array (if it is not already prog rammed)
before e xecuting the erase operation. During erase, the

device automatically tim es the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.

The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measur es include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This can be achieved in-system or via program­ming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achie ved.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device off ers two power-sa ving f eatures. When ad­dresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bi t s w i th i n a
sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

Am29LV001B 2

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV001B

Speed Options

Max access time, ns (t
Max CE# access time, ns (tCE) 45 55 70 90
Max OE# access time, ns (tOE) 25 30 30 35

Regulated Voltage Range: VCC =3.0–3.6 V -45R

Full Voltage Range: VCC = 2.7–3.6 V -55 -70 -90

) 45 55 70 90

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ7

V

RESET#

WE#

CC

V

SS

CE#

OE#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Input/Output

Buffers

Data

Latch

A0–A16

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21557C-1

3 Am29LV001B

CONNECTION DIAGRAMS

PRELIMINARY

A11

A9

A8
A13
A14

NC

WE#

V

CC

RESET#

A16
A15
A12

A7

A6

A5

A4

OE#

A10

CE#

DQ7
DQ6
DQ5
DQ4

DQ3

V

DQ2
DQ1
DQ0

SS

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-Pin Standard TSOP

32-Pin Reverse TSOP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE#
A10
CE#

DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

A11
A9
A8
A13
A14
NC
WE#
V

CC

RESET#
A16
A15
A12
A7
A6
A5
A4

A7
A6
A5

A4
A3
A2
A1
A0

DQ0

CC

WE#

RESET#

5
6

7

8
9
10

11
12
13

14

A12

A15

Am29LV001

15

DQ1

DQ2

A16

13130234

PLCC

17

SS

V

DQ3

32

18

V

19 2016

DQ4

DQ5

NC

29
28
27

26
25
24
23
22
21

DQ6

A14
A13

A8

A9
A11
OE#

A10
CE#
DQ7

Am29LV001B 4

21557C-2

PRELIMINARY

PIN CONFIGURATION

A0–A16 = 17 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin not connected internally

(see Product Selector Guide for speed
options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

17

A0–A16

CE#
OE#

WE#
RESET#

8

DQ0–DQ7

21557C-3

5 Am29LV001B

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

CE-45RAm29LV001B T

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

Am29LV001BT-45R,
Am29LV001BB-45R,

Am29LV 00 1B T-55,
Am29LV 00 1B B-5 5,

Am29LV 00 1B T-70,
Am29LV 00 1B B-7 0,

Am29LV 00 1B T-90,
Am29LV 00 1B B-9 0,

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29LV001B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

EC, FC, JC

EC, EI, EE,
FC, FI, FE,

JC, JI, JE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Am29LV001B 6

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29LV001B Device Bus Operations

Operation CE# OE# WE# RESET# Addresses (Note 1) DQ0–DQ7

Read L L H H A
Write L H L H A
Standby VCC ± 0.3 V X X VCC ± 0.3 V X High-Z
Output Disable L H H H X High-Z
Reset X X X L X High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V
Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Notes:

1. Addresses are A16–A0.

2. The in-system method of sector protection/unprotection is available. Sector protection/unprotection can be implemented by
using programming equipment. See the “Sector Protection/Unprotection” section.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

IL

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.

IN
IN

ID

ID

ID

Sector Address, A6 = L,

A1 = H, A0 = L

Sector Address, A6 = H,

A1 = H, A0 = L

A

IN

D

D

IN

D

IN

= Data Out

OUT

OUT

D

, D

, D
D

IN

OUT

OUT

IN

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con­trol and gates arra y data to the output pins . WE# should
remain at V

.

IH

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con­tent occurs dur ing the power transi tion. No com mand
is necessary in this mode to o btai n array data. Stand­ard microprocessor read cycles that assert valid ad­dresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 13 for the timing diagram. I

the DC Characteristics table represents the active c ur­rent specification for reading array data.

. CE# is the power

IL

CC1

in

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

The device f eatures an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re­quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sec­tors, or the entire device. Table 2 indicate the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de­tails on erasing a sector or the entire chip, or suspend­ing/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-

, and OE# to VIH.

IL

7 Am29LV001B

PRELIMINARY

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the w rite mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for w r ite operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the de­vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs ar e placed in the high impedance
state, independent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pin s are both held at V
(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held a t VIH, but not within

V

IH

± 0.3 V, the device will be in the standb y mode, but

V

CC

the standby current will be greater. The device requires
standard access time (t

) for read access when the

CE

device is in either of these standby modes, before it is
ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, RE­SET#: Hardware Reset Pin.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

CC

± 0.3 V.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The de vice automatically enables
this mode when addresses remain stable f or t

ACC

+ 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard addres s
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I

CC5

in the DC
Characteristics table represents the automatic sleep
mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardw are method of reset­ting the device to reading array data. When the RE­SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby c urrent (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.The system may use
the RESET# pin to force the device into the standby
mode. Refer to the “ Standby Mode” section for more in­formation.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 14 for the timing diagram.

RP

, the

in the DC Characteristics table represents the

I

CC3

standby current specification.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

Am29LV001B 8

PRELIMINARY

Table 2. Am29LV001B Top Boot Sector Architecture

Sector Size

Sector A16 A15 A14 A13 A12

SA0 0 0 0 X X 16 Kbytes 00000h–03FFFh
SA1 0 0 1 X X 16 Kbytes 04000h–07FFFh
SA2 0 1 0 X X 16 Kbytes 08000h–0BFFFh
SA3 0 1 1 X X 16 Kbytes 0C000h–0FFFFh
SA4 1 0 0 X X 16 Kbytes 10000h–13FFFh
SA5 1 0 1 X X 16 Kbytes 14000h–17FFFh
SA6 1 1 0 X X 16 Kbytes 18000h–1BFFFh
SA7 1 1 1 0 0 4 Kbytes 1C000h–1CFFFh
SA8 1 1 1 0 1 4 Kbytes 1D000h–1DFFFh
SA9 1 1 1 1 X 8 Kbytes 1E000h–1FFFFh

(Kbytes)

Address Range

(in hexadecimal)

Table 3. Am29LV001B Bottom Boot Sector Architecture

Sector Size

Sector A16 A15 A14 A13 A12

SA0 0 0 0 0 X 8 Kbytes 00000h–01FFFh
SA1 0 0 0 1 0 4 Kbytes 02000h–02FFFh
SA2 0 0 0 1 1 4 Kbytes 03000h–03FFFh
SA3 0 0 1 X X 16 Kbytes 04000h–07FFFh
SA4 0 1 0 X X 16 Kbytes 08000h–0BFFFh
SA5 0 1 1 X X 16 Kbytes 0C000h–0FFFFh
SA6 1 0 0 X X 16 Kbytes 10000h–13FFFh
SA7 1 0 1 X X 16 Kbytes 14000h–17FFFh
SA8 1 1 0 X X 16 Kbytes 18000h–1BFFFh
SA9 1 1 1 X X 16 Kbytes 1C000h–1FFFFh

(Kbytes)

Address Range (in

hexadecimal)

9 Am29LV001B

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in

(11.5 V to 12.5 V) on address pin

ID

Table 4. In addition, when verifying sector protection,
the sector addres s must appear on the appropriate
highest order address bits (see Table 2). Table 4 s hows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V
details on using the autoselect mode.

Table 4. Am29LV001B Autoselect Codes

A16

A11

to

to

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID: Am29LV001B T

(Top Boot Block)
Device ID: Am29LV001B B

(Bottom Boot Block)

LLHXXV

LLHXXVIDXLXLH 6Dh

A12

A10 A9

. See “Command Definitions” for

ID

A8

to

A7 A6

XLXLL 01h

ID

XLXLH EDh

ID

A5

to

A2 A1 A0

DQ7

to

DQ0

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sect or. The hard­ware sector unprotection feature re-enables both pro­gram and erase operations in previously protected
sectors. Sector protection/unprotecti on can be imple­mented via two methods.

The primary method requires V
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo­rithms and Figure 21 shows the timing diagram. This
method uses standard m icroprocessor bus cycle tim­ing. For sector unprotect, all unprotec ted sectors must
first be protected prior to the first sector unpro tect write
cycle.

The alternate method intended on ly for programming
equipment requires V

on address pin A9, OE#, and

ID

RESET#. This method is compatible with programmer

on the RESET# pin

ID

The device is shipped with all s ectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE­SET# pin to V
sectors can be programmed or erased b y selecting the
sector addresses. Once V
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 20 shows the tim ing diagrams, for this feature.

XLXHL

ID

routines written for earlier 3.0 volt-only AMD flash de­vices. Publication number 2 2134 contains fur ther de­tails; contact an AMD representati ve to r equest a cop y.

01h

(protected)

00h

(unprotected)

. During this mode, formerly protected

ID

is removed from the RE-

ID

Am29LV001B 10

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

Yes

No

START

Protect all sectors:

The indicated portion

of the sector protect

ID

Reset

PLSCNT = 1

Yes

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

No

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

No

All sectors
protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector
address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

ID

Algorithm

Write reset

command

Figure 1. In-System Sector Protect/Unprotect Algorithms

11 Am29LV001B

Sector Unprotect

complete

21557C-4

PRELIMINARY

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

ID

IH

21557C-5

Figure 2. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection

against inadverten t writes (refer to Table 5 for com­mand definitions). In addition, the following hardwar e
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V

power-up and

CC

power-down transitions, or from system noise.

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up W rite Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. Table 5 de fines the valid register co mmand
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend com­mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-su spended sectors, the device outputs
status data. After completing a programming o pera­tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.

must

The system

issue the reset command to re-ena­ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements f o r Reading A rr ay Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parame­ters, and Figure 13 shows the timing diagram.

Am29LV001B 12

PRELIMINARY

Reset Command

Writing the reset command to the devi ce resets the de-

vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

See “AC Characteristics” for parameters, and to Figure
14 for the timing diagram.

must

Autoselect Command Sequence

The autoselect comm and sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
T ab le 5 shows the address and data requirements . This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires V
on address bit A9.

The autoselect command sequence is initiated by writ­ing two unlock cycles, followed by the autoselect com­mand. The device then enters the autoselect m ode,
and the system may read at any address any num ber
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protected, or 00h if it is unprot ected. Refer t o Table 2 f or
valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

ID

Byte Program Command Sequence

The device progr ams one byte of data f or each progr am
operation. The command sequence requires four bus
cycles, and is initiated by wr iting two unlock write cy ­cles, followed by the program set-up command. The

program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is
ings. The device automatically provides internally gen­erated program pulses and verify the programmed cell
margin. Table 5 shows the address and data require­ments for the byte prog ram command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the prog ram oper ation b y using DQ7
or DQ6. See “Wr ite Operation Status” for information
on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the prog r am­ming operation. The Byte Program command se­quence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indic ate the operation was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro­gram bytes to the dev ice fast er than using the standard
program command sequence. The unlock b ypass com­mand sequence is initiated by first writin g two unlock
cycles. This is followed b y a third write cycle containing
the unlock bypass command, 20h. The de vi ce then en­ters the unlock bypass mode. A two-cycle unlo ck by­pass program command sequence is all that is required
to program in this mode. The first cycle in this se­quence contains the unlock bypass program com­mand, A0h; the sec ond cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with t he i nitial
two unlock cycles required in the standard program
command sequence, resulting in faster total program­ming time. Table 5 shows the requirements for the com­mand sequence.

During the unlo ck bypass mode, only the Unlock By­pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com­mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Add resses are
don’t cares for both cycles. The device then returns to
reading array data.

Figure 3 illustrates the algorithm for the program oper­ation. See the Erase/Program Operations table in “AC

not

required to provide further controls or tim-

13 Am29LV001B

PRELIMINARY

Characteristics” for parameters, and to Figure 15 for
timing diagrams.

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note:

See Table 5 for program command sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

No

21557C-6

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and ve rifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a har dware

require the system to

reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.

The system can determine the status of the erase op­eration by using DQ7, DQ6, or DQ2. See “Write Oper­ation Status” for inf ormation on these status bits. When
the Embedded Erase algorithm is complete, the de vi ce
returns to r eading array data and addr esses are no
longer latched.

Figure 4 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase co mmand sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sector s. The time be­tween these additional cycl es must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase comm and is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the s ector

erase timer has timed out. (See the “DQ3 : Sector Erase
Timer” section.) The tim e-out begins from the rising
edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, on ly the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the

require the system to preprogram

Am29LV001B 14

PRELIMINARY

sector erase operation immediately terminates the op­eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addresses are
no longer latched. The system can determine the sta­tus of the erase operation b y usi ng DQ7, DQ6, or DQ2.

(Refer to “Write Operation Status” for information on
these status bits.)

Figure 4 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the s yst em to in­terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend comm and is ignored if written dur ing
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during
a sector erase operation, the device requires a maxi­mum of 20 µs to suspend the eras e operation. How­ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi­ately terminates the t ime-out p eriod and sus pends the
erase operation.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When th e
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

No

from System

Data = FFh?

Yes

Embedded
Erase
algorithm
in progress

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure . (The devi ce “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system can once again read arra y data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “Write Operation Status” for more infor ma­tion.

15 Am29LV001B

Erasure Completed

21557C-7

Figure 4. Erase Operation

PRELIMINARY

Table 5. Am29LV001B Command Definitions

Command Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Manufacturer ID 4 555 AA 2A A 55 555 90 X0 0 01
Device ID, Top Boot

Block
Device ID, Bottom

Boot Block
Sector Protect

Autoselect (Note 7)

Verify (Note 8)

Byte Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program

(Note 9)
Unlock Bypass Reset

(Note 10)
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 5 5 55 5 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 11) 1 XXX B0
Erase Resume (Note 12) 1 XXX 30

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 555 AA 2AA 55 555 90 X01

4 555 AA 2AA 55 555 90

2 XXX A0 PA PD

2 XXX 90 XXX 00

Bus Cycles (Notes 2–4)

SA

X02

ED

6D
00

01

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses are latched on the falling edge of the WE# or CE#
pulse.

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus
cycles are write operations.

4. Address bits A16–A11 are don’t care for unlock and
command cycles, unless SA or PA required.

5. No unlock or command cycles required when device is in
read mode.

6. The Reset command is required to return to the read
mode when the device is in the autoselect mode or if DQ5
goes high.

7. The fourth cycle of the autoselect command sequence is
a read cycle.

PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.

SA = Address of the sector to be erased or verified. Address
bits A16–A12 uniquely select any sector.

8. The data is 00h for an unprotected sector and 01h for a
protected sector. The complete bus address in the fourth
cycle is composed of the sector address (A16–A12),
A1 = 1, and A0 = 0.

9. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.

10. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the Unlock
Bypass mode.

11. The system may read and program functions in non­erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation.

12. The Erase Resume command is valid only during the
Erase Suspend mode.

Am29LV001B 16

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 6 and the following subsections describe
the functions of these bits. DQ7, and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys­tem whether an Embedded Algorithm is in progress or
completed, or whether the devic e is in Er as e Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se­quence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 1 µs, then the device returns to reading

array data.

No

START

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is as serted low. Figure 17, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.

DQ7 = Data?

No

FAIL

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Yes

PASS

21557C-8

Figure 5. Data# Polling Algorithm

Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.

17 Am29LV001B

PRELIMINARY

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whethe r an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the sector erase time-out.

During an Embedded Program or Erase algor ithm op­eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# o r CE#
to control the read cy cles). When the oper at ion is c om­plete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are pro tected,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: D ata# Polling).

If a program address falls within a pro tected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

Table 6 shows the outputs f or Toggle Bit I on DQ6. Fig­ure 6 shows the toggle bit algorithm in flowchart form,
and the section “Reading Toggle Bits DQ6/DQ2” ex­plains the algorithm. Figure 18 in the “AC Characteris­tics” section shows the toggle bit timing dia grams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Er ase alg orithm is in pr og ress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.

DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The

system may use either OE# or CE# to control the read
cycles.) But DQ2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. DQ6, by com­parison, indicates whether the device is actively erasing,
or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sector and mode information. Refer to
Table 6 to compare outputs for DQ2 and DQ6.

Figure 6 shows the toggle bit algorithm in flowchar t
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 18 shows the toggle bit timing dia­gram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and s tore the value of the tog­gle bit after the firs t read. After the second read, the
system would compare t he new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–D Q0 on the fol­lowing read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to readi ng
array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successi ve read cycles , de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perform other
system tasks . In this ca se, the sy ste m must sta rt at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).

Table 6 shows the outputs fo r Toggle Bit I on DQ6. Fig­ure 6 shows the toggle bit algorithm. Figure 18 in the
“AC Characteristics” section shows the toggle bit ti ming
diagrams. Figure 19 shows the differences between
DQ2 and DQ6 in graphical for m. See also the subsec­tion on DQ2: Toggle Bit II.

Am29LV001B 18

PRELIMINARY

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

No

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

(Note 1)

No

(Notes
1, 2)

No

Program/Erase

Operation Complete

21557C-9

Figure 6. Toggle Bit Algorithm

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” T his is a failure
condition that indicates the pro gram or er ase cycle w as
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro­grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, t he system must issue the

reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine w hether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0” to
“1.” If the time between additional sector erase com­mands from the system can be assumed to be less than
50 µs, the system need not monitor DQ3. See also the
“Sector Erase Command Sequence” section.

After the sector erase command sequenc e is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Sus pend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should che ck the s tatus
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 6 shows the outputs for DQ3.

19 Am29LV001B

PRELIMINARY

Table 6. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle
Embedded Erase Algorithm 0 Toggle 0 1 Toggle
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A

(Note 2) DQ6

1 No toggle 0 N/A Toggle

Data Data Data Data Data

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

DQ5

(Note 1) DQ 3

DQ2

(Note 2)

Am29LV001B 20

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground
All pins except A9, OE# and RESET#

V

CC

CC

+0.5 V

SS

+0.5 V.

(Note 1) . . . . . . . . . . . . . . . . . . . –0.5 V to V

(Note 1). . . . . . . . . . . . . . . . . . . .–0.5 V to +3.6 V

V

CC

A9, OE#, and RESET# (Note 2) . . .–0.5 V to +12.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot V
to –2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage on inp ut or I/ O pins is
During voltage transitions, input or I/O pins may overshoot
to V

+2.0 V for periods up to 20 ns. See Figure 8.

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.

3. No more than on e output may be shor te d to ground at a
time. Duration of the short circuit should not be greater
than one second.

4. Stresses above those listed under “Absolute Maximum
Ratings” may cause per manent damage to the device.
This is a stress rating only; functional operation of the de­vice at these or any other conditions above those indi­cated in the operational section s of this data sheet is not
implied. Exposure of the device to absolute maximum rat­ing conditions for extended pe r io ds may affect device re­liability.

to –2.0 V for periods of up

SS

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

21557C-10

Figure 7. Maximum Negative Overshoot Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

21557C-1

Figure 8. Maximum Positive Ov ershoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

VCC Supply Voltages

for regulated voltage range. . . . . .+3.0 V to 3.6 V

V

CC

for full v oltage range. . . . . . . . . . .+2.7 V to 3.6 V

V

CC

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

21 Am29LV001B

) . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . –55°C to +125°C

A

PRELIMINARY

DC CHARACTERISTICS
CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit

= VSS to VCC,

V

IN

V

= VCC

CC

= VSS to VCC,

V

OUT

V

= V

CC

CE# = V

max

; A9 = 12.5 V 35 µA

CC max

CC max

5 MHz 7 12

OE#

IL,

= VIH

1 MHz 2 4

±1.0 µA

±1.0 µA

I

I

I

CC1

I

LIT

LO

LI

Input Load Current

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current
(Note 1)

mA

V
V

V

I

CC2

I

CC3

I

CC4

I

CC5

V

V

V

V

IL

IH

ID

OL

OH1

OH2

LKO

VCC Active Write Current
(Notes 2 and 4)

VCC Standby Current

VCC Reset Current

Automatic Sleep Mode (Note 3)

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 x V
Voltage for Autoselect and

Temporary Sector Unprotect
Output Low Voltage IOL = 4.0 mA, VCC = V

Output High Voltage

Low VCC Lock-Out Voltage
(Note 4)

CE# = V

V

CC

CE#, RESET# = V
VCC = V

RESET# = V
V

IH

V

IL

= V

= V

= V

IL,

CC max

CC max

CC

± 0.3 V

SS

OE#

= VIH

;

;

± 0.3 V

SS

± 0.3 V;

CC

±0.3 V

VCC = 3.3 V 11.5 12.5 V

0.45 V

CC min

I

= –2.0 mA, VCC = V

OH

IOH = –100 µA, VCC = V

0.85 V

CC min

VCC–0.4

CC min

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH.

CC

active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t
current is 200 nA.

4. Not 100% tested.

15 30 mA

0.2 5 µA

0.2 5 µA

0.2 5 µA

CC

CC

VCC + 0.3 V

2.3 2.5 V

+ 30 ns. Typical sleep mode

ACC

V

Am29LV001B 22

DC CHARACTERISTICS (Continued)
Zero Power Flash

20

15

10

5

Supply Current in mA

0

0 500 1000 1500 2000 2500 3000 3500 4000

PRELIMINARY

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

8

6

4

Supply Current in mA

2

0

12345

21557C-12

3.6 V

2.7 V

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I

vs. Frequency

CC1

23 Am29LV001B

21557C-13

TEST CONDITIONS

Device

Under

Test

C

L

6.2 kΩ

PRELIMINARY

3.3 V

2.7 kΩ

Table 7. Test Specifications

-45R,

Test Condition

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V

-55

L

30 100 pF

-70,

-90 Unit

Note:

Diodes are IN3064 or equivalent

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

21557C-14

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

1.5 V

1.5 V

21557C-15

3.0 V

0.0 V

1.5 V 1.5 V

Figure 12. Input Waveforms and Measurement Levels

Am29LV001B 24

OutputMeasurement LevelInput

21557C-16

AC CHARACTERISTICS
Read Operations

PRELIMINARY

Parameter

JEDEC Std. Test Setup -45R -55 -70 -90 Unit

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

Description

t

Read Cycle Time (Note 1) Min 45 55 70 90 ns

RC

t

Address to Output Delay

ACC

t

Chip Enable to Output Delay OE# = V

CE

t

Output Enable to Output Delay Max 25 30 30 35 ns

OE

t

Chip Enable to Output High Z (Note 1) Max 10 15 25 30 ns

DF

t

Output Enable to Output High Z (Note 1) Max 10 15 25 30 ns

DF

CE# = V
OE# = V

IL

Max45557090ns

IL

Max45557090ns

IL

Speed Option

Read Min 0 ns

Output Enable

t

t

AXQX

OEH

Hold Time (Note 1)

Output Hold Time From Addresses, CE# or

t

OH

OE#, Whichever Occurs First (Note 1)

Toggle and
Data# Polling

Min 10 ns

Min 0 ns

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

Addresses

CE#

OE#

WE#

Outputs

RESET#

n/a Am29F002NB

t

RC

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 13. Read Operations Timings

t

DF

t

OH

HIGH Z

21557C-17

25 Am29LV001B

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std. Test Setup Unit

PRELIMINARY

t

READY

t

READY

t

RP

t

RH

t

RPD

Note:

Not 100% tested.

CE#, OE#

RESET#

n/a Am29F002NB

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

Max 20 µs

Max 500 ns

RESET# Pulse Width Min 500 ns
RESET# High Time Before Read (See Note) Min 50 ns
RESET# Low to Standby Mode Min 20 µs

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

RESET#

n/a Am29F002NB

t

RP

Figure 14. RESET# Timings

21557C-18

Am29LV001B 26

AC CHARACTERISTICS
Erase/Program Operations

Parameter

t

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

GHWL

t

t

Write Cycle Time (Note 1) Min 45 55 70 90 ns

WC

t

Address Setup Time Min 0 ns

AS

t

Address Hold Time Min 35 45 45 45 ns

AH

t

Data Setup Time Min 20 20 35 45 ns

DS

t

Data Hold Time Min 0 ns

DH

Output Enable Setup Time (Note 1) Min 0 ns

OES

Read Recovery Time Before Write
(OE# High to WE# Low)

t

CE# Setup Time Min 0 ns

CS

t

CE# Hold Time Min 0 ns

CH

t

Write Pulse Width Min 25 30 35 35 ns

WP

Write Pulse Width High Min 30 ns

WPH

Programming Operation (Note 2) Typ 9 µs

Sector Erase Operation (Note 2) Typ 0.7 sec

VCSVCC

Setup Time (Note 1) Min 50 µs

PRELIMINARY

-45R -55 -70 -90JEDEC Std. Description Unit

Min 0 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” Section for more information.

27 Am29LV001B

AC CHARACTERISTICS

PRELIMINARY

Program Command Sequence (last two cycles)

t

WC

Addresses

CE#

555h

t

GHWL

t

OE#

t

WP

WE#

t

CS

t

DS

t

DH

Data

V

CC

t

VCS

A0h

Notes:

1. PA = program addre ss, PD = program data, D

Figure 15. Program Operation Timings

Read Status Data (last two cycles)

t

AS

PA PA

t

AH

CH

t

t

WPH

PA

WHWH1

PD

is the true data at the program address.

OUT

Status

D

OUT

21557C-19

Am29LV001B 28

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

PRELIMINARY

t

AS

555h for chip erase

VA

t

AH

VA

Addresses

t

WC

2AAh SA

CE#

t

GHWL

t

OE#

WE#

Data

V

CC

t

VCS

t

CS

CH

t

WP

t

WPH

t

DS

t

DH

55h

30h

10 for Chip Erase

t

WHWH2

In

Progress

Complete

Note:

SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

Figure 16. Chip/Sector Erase Operation Timings

21557C-20

29 Am29LV001B

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

OEH

WE#

DQ7

t

ACC

PRELIMINARY

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

Status Data

Status Data

True

Valid Data

High Z

Note:

V A = Vali d address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

21557C-21

Figure 17. Data# Polling Timings (Durin g Emb e dded Algo ri thm s)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

t

CH

t

OEH

High Z

t

ACC

t

CE

VA

t

VA VA

OE

t

DF

t

OH

Valid Status

(first read) (second read) (stops toggling)

VA

Valid DataValid StatusValid Status

Note:

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.

21557C-22

Figure 18. Toggle Bit Timings (During Embedded Algorithms)

Am29LV001B 30

PRELIMINARY

AC CHARACTERISTICS

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Note:

The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an erase-suspended
sector.

Erase

Erase

Suspend

Erase Suspend

Enter Erase

Suspend Program

Read

Figure 19. DQ2 vs. DQ6

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

21557C-23

Temporary Sector Unprotect

Parameter

t

VIDR

t

RSP

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

All Speed OptionsJEDEC Std. Description Unit

VID Rise and Fall Time Min 500 ns
RESET# Setup Time for Temporary Sector

Unprotect

Min 4 µs

12 V

0 or 3 V

t

VIDR

t

VIDR

0 or 3 V

Program or Erase Command Sequence

t

RSP

21557C-24

Figure 20. Temporary Sector Unprotect Timing Diagram

31 Am29LV001B

AC CHARACTERISTICS

V

ID

V

ESET#

IH

PRELIMINARY

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

Data

60h 60h 40h

1 µs

Sector Protect: 100 µs

Sector Unprotect: 10 ms

CE#

WE#

OE#

Note:

For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 21. In-System Sector Protect/Unprotect Timing Diagram

Status

21557C-25

Am29LV001B 32

PRELIMINARY

AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations

Parameter

-45 -55 -70 -90JEDEC Std. Description Unit

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

t

WHWH2

Write Cycle Time (Note 1) Min 45 55 70 90 ns
Address Setup Time Min 0 ns
Address Hold Time Min 35 45 45 45 ns
Data Setup Time Min 20 20 35 45 ns
Data Hold Time Min 0 ns
Output Enable Setup Time (Note 1) Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 25 30 35 35 ns
CE# Pulse Width High Min 30 ns
Programming Operation (Notes 1, 2) Typ 9 µs

Sector Erase Operation (Notes 1, 2) Typ 0.7 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” Section for more information.

33 Am29LV001B

AC CHARACTERISTICS

PRELIMINARY

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program
2AA for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
555 for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

PD for program
30 for sector erase
10 for chip erase

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

Notes:

1. Figure indicates the last two bus cycles of the program or erase command sequence.

2. PA program address, SA = Sector Address, PD = program data, DQ7# = complement of the data written to the device,

= data written to the device.

D

OUT

21557C-26

Figure 22. Alternate CE# Controlled Write Operation Timings

Am29LV001B 34

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s
Chip Erase Time 7 s
Byte Programming Time 9 300 µs

Chip Programming Time (Note 3) 1.1 3.3 s

Excludes 00h programming
prior to erasure (Note 4)

Excludes system level
overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V (3.0 V for -45R), 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 5 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V
(including A9, OE#, and RESE T#)

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

on all pins except I/O pins

SS

–1.0 V 13.0 V

Current –100 mA +100 mA

V

CC

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

= 0 8.5 12 pF

OUT

Control Pin Capacitance VIN = 0 7.5 9 pF

C

C

C

IN

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

PLCC PIN CAPACITANCE

Parameter Symbol Parameter Description Test Setup Typ Max Unit

C

IN

C

OUT

C

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

Input Capacitance VIN = 0 4 6 pF
Output Capacitance V

= 0 8 12 pF

OUT

Control Pin Capacitance VPP = 0 8 12 pF

= 25°C, f = 1.0 MHz.

A

35 Am29LV001B

PRELIMINARY

PHYSICAL DIMENSIONS
PL 032

32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485
.495

.009
.015

.125
.140

.080
.095

SEATING

PLANE

.050 REF.

.585
.595

.447
.453

Pin 1 I.D.

.547
.553

.026
.032

TOP VIEW

.013
.021

.400

REF.

SIDE VIEW

.042
.056

.490
.530

16-038FPO-5
PL 032
DA79
6-28-94 ae

Am29LV001B 36

PRELIMINARY

PHYSICAL DIMENSIONS*
TS 032

32-Pin Standard Thin Small Outline Package (measured in millimeters)

Pin 1 I.D.

1

7.90

8.10

0.95

1.05

0.50 BSC

18.30

18.50

19.80

20.20

1.20

MAX

* For reference only. BSC is an ANSI standard for Basic Space Centering

0.05

0.15

0.08

0.20

0.10

0˚
5˚

0.50

0.70

0.21

16-038-TSOP-2
TS 032
DA95
3-25-97 lv

37 Am29LV001B

PRELIMINARY

PHYSICAL DIMENSIONS*
TSR032

32-Pin Reverse Thin Small Outline Package (measured in millimeters)

Pin 1 I.D.

1

7.90

8.10

0.95

1.05

0.50 BSC

18.30

18.50

19.80

20.20

1.20

MAX

0.25MM (0.0098") BSC

0°
5°

* For reference only. BSC is an ANSI standard for Basic Space Centering

REVISION SUMMARY FOR AM29LV001B

Distinctive Characteristics

Changed process technology to 0.33 µm.

Revision B

Split the Am29LV001B/Am29LV010B data sheet, with
the elimination of all references to Am29LV010B.

Revision C

Global

Deleted 120 ns speed option; added 90 ns speed
option.

Temporary Sector Unprotect

Entered timing specifications for t

Erase and Programming Performance

Changed endurance in Note 2 to 1 million cycles;
added worst case voltage for -45R speed option.

0.50

0.70

0.08

0.20

0.10

0.21

16-038-TSOP-2
TSR032
DA95
4-4-95 ae

and t

VIDR

0.05

0.15

RSP

.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV001B 38