Datasheet AM29F400AT-90FIB, AM29F400AT-90FI, AM29F400AT-90FCB, AM29F400AT-90FC, AM29F400AT-90EIB Datasheet (AMD Advanced Micro Devices)

5.0 V-only Flash

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PRELIMINARY

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Am29F400AT/Am29F400AB

4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

Compatible with JEDEC-standards

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

Package options

— 44-pin SO
— 48-pin TSOP

Minimum 100,000 write/erase cycles guaranteed
High performance

— 60 ns maximum access time

Sector erase architecture

— One 16 Kbyte, two 8 Kbytes , one 32 Kbyte, and

seven 64 Kbytes

— Any combination of sectors can be erased. Also

supports full chip erase.

Sector protection

— Hardware method that disables any combination

of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.

Embedded Erase  Algorithms

— Automatically preprograms and erases the chip

or any sector

Embedded Program  Algorithms

— Automatically programs and verifies data at

specified address

Data

Polling and Tog gle Bit feature for detection

of program or erase cycle completion
Ready/Busy output (RY/BY)

— Hardware method for detection of program or

erase cycle completion

Erase Suspend/Resume

— Supports reading data from a sector not being

erased

Low power consumption

— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current

Enhanced power management for standby
mode

—1 µ A typical standby current

Boot Code Sector Architecture

— T = Top sector
— B = Bottom sector

Hardware RESET

— Resets internal state machine to the read mode

pin

GENERAL DESCRIPTION

The Am29F400A is a 4 Mbit, 5.0 V olt-only Flash memory
organized as 512 Kbytes of 8 bits each or 256 Kwords
of 16 bits each. The 4 Mbits of data is divided into 11
sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte,
and seven 64 Kbytes, for flexible erase capability. The
8 bits of data will appear on DQ0–DQ7 or 16 bits on
DQ0–DQ15. The Am29F400A is offered in 44-pin SO
and 48-pin TSOP packages. This device is designed
to be programmed in-system with the standard system

5.0 Volt V
program or erase operations. The de vice can also be re­programmed in standard EPROM programmers .

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

supply. 12.0 Volt V

CC

is not required for

PP

The standard Am29F400A offers access times of
60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has sepa­rate chip enable (CE
enable (OE) controls.

The Am29F400A is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con­tents serve as input to an internal state-machine
which controls the erase and programming circuitry.

), write enable (WE) and output

Publication# 20380 Rev: B Amendment/0
Issue Date: April 1997

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PRELIMINARY

Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.

The Am29F400A is programmed by executing the pro­gram command sequence. This will invoke the Embed­ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase , the de vice automat­ically times the erase pulse widths and verifies proper
cell margin.

This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re­programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F400A is erased when
shipped from the factory.

The Am29F400A device also features hardw are sector
protection. This feature will disable both program and
erase operations in any combination of eleven sectors
of memory.

AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from a sector that was not being
erased. Thus, true backg round erase can be achieved.

The device features single 5.0 Volt power supply oper­ation for both read and write functions. Internally gen­erated and regulated voltages are provided for the
program and erase operations. A low V

detector au-

CC

tomatically inhibits write operations during power tran­sitions. The end of program or erase is detected by the

pin. Data Polling of DQ7, or by the Toggle Bit

RY/BY
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.

The Am29F400A also has a hardware RESET pin.
When this pin is driven low, execution of any Embed­ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto­matically reset to the read mode and will have errone­ous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the sys­tem’s microprocessor to read the boot-up firmware
from the Flash memory.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The Am29F400A memory electrically erases all
bits within a sector simultaneously via
Fowler-Nordhiem tunneling. The bytes/words are pro­grammed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.

Flexible Sector-Erase Architecture

One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbyte sectors

Individual-sector or multiple-sector erase capability
Sector protection is user definable

(x8) (x16)

7FFFFh 3FFFFh
7BFFFh 3DFFFh
79FFFh 3CFFFh
77FFFh 3BFFFh
6FFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
00000h 00000h

20380B-1

(x8) (x16)

7FFFFh 3FFFFh
6BFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
07FFFh 03FFFh
05FFFh 02FFFh
03FFFh 01FFFh
00000h 00000h

20380B-2

SA10

SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

SA10

SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

16 Kbyte

8 Kbyte

8 Kbyte
32 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte

Am29F400AT Sector Architecture

64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte

8 Kbyte

8 Kbyte
16 Kbyte

Am29F400AB Sector Architecture

2 Am29F400AT/Am29F400AB

5.0 V-only Flash

%

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part No: Am29F400A

Ordering Part No:V

Max Access Time (ns) 60 70 90 120 150
CE

(E) Access (ns) 60 70 90 120 150

OE (G) Access (ns) 30 30 35 50 55

= 5.0 V ±

CC

V

= 5.0 V ± 10%

CC

5

-65

-70 -90 -120 -150

BLOCK DIAGRAM

DQ0–DQ15

V
V

WE

BYTE

RESET

A0-A17

A-1

CC
SS

CE
OE

RY/BY

Buffer

State

Control

Command

Register

V

Detector

CC

RY/BY

PGM V oltage

Generator

Timer

Erase V oltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

Address Latch

STB

Input/Output

Buffers

Data

Latch

Y-Gating

Cell MatrixX-Decoder

20380B-3

Am29F400AT/Am29F400AB 3

CONNECTION DIAGRAMS

PRELIMINARY

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

NC

RY/BY

A17

A7
A6
A5
A4
A3
A2
A1
A0

CE

V

SS

OE
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

20380B-4

4 Am29F400AT/Am29F400AB

5.0 V-only Flash

CONNECTION DIAGRAMS

PRELIMINARY

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE

RESET

NC
NC

RY/BY

NC

A17

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Standard TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16

BYTE

V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0

OE

V

SS

CE

A0

20380B-5

A16

BYTE

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE

V

SS

CE

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC

WE
RESET

NC
NC
RY/BY
NC

A17
A7
A6
A5
A4
A3
A2
A1

20380B-6

Am29F400AT/Am29F400AB 5

PRELIMINARY

PIN CONFIGURATION

A1, A0–A17 = 18 Addresses
BYTE
CE = Chip Enable
DQ0–DQ15 = 16 Data Inputs/Outputs
NC = Pin Not Connected Internally
OE = Output Enable
RESET = Hardware Reset Pin, Active Low
RY/BY = Ready/Busy Output
V

SS

V

SS

WE

= Selects 8-bit or 16-bit mode

= +5.0 V olt Single-Power Supply

( ± 10% for -90, -120, -150) or ( ± 5% for -75)
= Device Ground
= Write Enable

LOGIC SYMBOL

A-1

18

A0–A17

CE

(E)

(G)

OE
WE

(W)

RESET
BYTE

16 or 8

DQ0–DQ15

RY/BY

20380B-7

6 Am29F400AT/Am29F400AB

5.0 V-only Flash

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the following:

AM29F400A -65 E C

T

DEVICE NUMBER/DESCRIPTION

Am29F400A
4 Megabit (512K x 8-Bit/256K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

B

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

TEMPERATURE RANGE

C = Commercial (0
I = Industrial (-40

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and
Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector

°C to +70°C)

°C to +85°C)

AM29F400AT/B-65 EC, EI, FC, FI, SC, SI
AM29F400AT/B-70
AM29F400AT/B-90
AM29F400AT/B-120
AM29F400AT/B-150

Valid Combinations

EC, EI, EE, EEB,

FC, FI, FE, FEB,
SC, SI, SE, SEB

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Am29F400AT/Am29F400AB 7

PRELIMINARY

±

Table 1. Am29F400A User Bus Operations (BYTE = V

Operation CE

Autoselect, AMD Manuf. Code (Note 1) L L H L L L V
Autoselect Device Code (Note 1) L L H H L L V
Read L L H A0 A1 A6 A9 D
Standby H XXXXXXHIGH Z H
Output Disable L H H XXXXHIGH Z H
Write L H L A0 A1 A6 A9 D
Verify Sector Protect (Note 2) L LHLHLV
Temporary Sector Unprotect XXXXXXX X V
Hardware Reset XXXXXXXHIGH Z L

OE WE A0 A1 A6 A9 DQ0–DQ15 RESET

Table 2. Am29F400A User Bus Operations (BYTE

Operation CE

Autoselect, AMD Manuf. Code
(Note 1)

Autoselect Device Code (Note 1) L L H H L L V
Read L L H A0 A1 A6 A9 D
Standby H XXXXXXHIGH Z HIGH Z H
Output Disable L H H XXXXHIGH Z HIGH Z H
Write L H L A0 A1 A6 A9 DIN HIGH Z H
Verify Sector Protect (Note 2) L LHLHLVIDCode HIGH Z H
Temporary Sector Unprotect XXXXXXX X HIGH Z V
Hardware Reset XXXXXXXHIGH Z HIGH Z L

OE WE A0 A1 A6 A9 DQ0–DQ7 DQ8–DQ15 RESET

LLHLLLV

ID

ID

)

IH

ID

ID

ID

= V

)

IL

Code HIGH Z H

Code HIGH Z H

OUT

Code H
Code H

OUT

IN

Code H

HIGH Z H

H

H

ID

ID

Legend:

L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels.

Notes:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.

2. Refer to the section on Sector Protection.

Read Mode

The Am29F400A has two control functions which must
be satisfied in order to obtain data at the outputs. CE
the power control and should be used for de vice selec­tion. OE is the output control and should be used to
gate data to the output pins if a device is selected.

Address access time (t

) is equal to the delay from

ACC

stable addresses to valid output data. The chip enable
access time (t
and stable CE

) is the delay from stable addresses

CE

to valid data at the output pins.
The output enable access time is the delay from the
falling edge of OE to valid data at the output pins (as-

is

suming the addresses have been stable for at least
t

-t

OE

time).

ACC

Standby Mode

There are two ways to implement the standb y mode on
the Am29F400A device, both using the CE

A CMOS standby mode is achieved with the CE input
held at V
typically reduced to less than 5 µ A. A TTL standby
mode is achieved with the CE
this condition the current is typically reduced to 1 mA.

In the standby mode the outputs are in the high imped­ance state, independent of the OE

0.5 V. Under this condition the current is

CC

pin held at V

input.

8 Am29F400AT/Am29F400AB

pin.

IH

. Under

PRELIMINARY

5.0 V-only Flash

Output Disable

With the OE input at a logic high level (VIH), output from
the device is disabled. This will cause the output pins to
be in a high impedance state.

Autoselect

The autoselect mode allows the reading of a binary
code from the device and will identify its manufacturer
and type. This mode is intended for use by program­ming equipment for the purpose of automatically
matching the device to be programmed with its corre­sponding programming algorithm. This mode is func­tional over the entire temperature range of the device.

To activate this mode, the programming equipment
must force V
Two identifier bytes may then be sequenced from the
device outputs by toggling address A0 from VIL to VIH.
All addresses are don’t cares except A0, A1, and A6
(see T ab le 3).

The manufacturer and device codes may also be read
via the command register, for instances when the

(11.5 V to 12.5 V) on address pin A9.

ID

Table 3. Am29F400A Sector Protection Verify Autoselect Codes

Am29F400A is erased or programmed in a system
without access to high voltage on the A9 pin. The com­mand sequence is illustrated in Table 4 (see Autoselect
Command Sequence).

Byte 0 (A0 = V

) represents the manufacturer’s code

IL

(AMD=01H) and byte 1 (A0 = VIH) the device identifier
code (Am29F400AT = 23H and Am29F400AB = ABH
for x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode). These two bytes/words are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as
the parity bit. In order to read the proper device codes
when executing the Autoselect, A1 must be V
(see Tables 3 and 4).

The autoselect mode also facilitates the determination
of sector protection in the system. By perf orming a read
operation at the address location XX02H with the
higher order address bits A12–A17 set to the desired
sector address, the device will return 01H for a pro­tected sector and 00H for a non-protected sector.

IL

Type A12-A17 A6 A1 A0 Code (HEX)

Manufacturer Code-AMD X V

Am29F400AT

Am29F400A Device

Am29F400AB

Sector Protection

*Outputs 01H at protected sector addresses

Byte

XVILV

Word 2223H

Byte

XVILV

Word 22ABH

Sector

Address

IL

V

IL

V

IL

IL

IL

V

IH

V

IL

V

IH

V

IH

V

IL

01H
23H

ABH

01H*

Table 4. Expanded Autoselect Code Table

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

23H

A-10HI-Z0HI-Z1HI-Z0HI-Z0HI-Z0HI-Z1HI-Z0000011000000111

A-10HI-Z0HI-Z1HI-Z0HI-Z0HI-Z0HI-Z1HI-Z0110011001100111

ABH

0

1

1

(W)

(W)

Code

2223H

22ABH

Type

Manufacturer Code-AMD 01H 0000000000000001

Am29F400AT(B)

Am29F400A
Device

Sector Protection 01H 0000000000000001

Am29F400AB(B)

B) - Byte mode
(W) - Word mode

Am29F400AT/Am29F400AB 9

PRELIMINARY

Table 5. Sector Address Tables (Am29F400AT)

(x8) Address

A17 A16 A15 A14 A13 A12

SA0 0 0 0 X X X 00000h-0FFFFh 00000h-07FFFh
SA1 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh
SA2 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh
SA3 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh
SA4 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh
SA5 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh
SA6 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh
SA71110XX70000h-77FFFh 38000h-3BFFFh
SA811110078000h-79FFFh 3C000h-3CFFFh
SA91111017A000h-7BFFFh 3D000h-3DFFFh

SA10 11111X7C000h-7FFFFh 3E000h-3FFFFh

Range

(x16) Address

Range

Table 6. Sector Address Tables (Am29F400AB)

(x8) Address

A17 A16 A15 A14 A13 A12

SA000000X00000h-03FFFh 00000h-01FFFh
SA100001004000h-05FFFh 02000h-02FFFh
SA200001106000h-07FFFh 03000h-03FFFh
SA30001XX08000h-0FFFFh 04000h-07FFFh
SA4 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh
SA5 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh
SA6 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh
SA7 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh
SA8 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh
SA9 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh

SA10 1 1 1 X X X 70000h-7FFFFh 38000h-3FFFFh

Range

(x16) Address

Range

Write

Device erasure and programming are accomplished via
the command register. The contents of the register serve
as inputs to the internal state machine. The state ma­chine outputs dictate the function of the device.

The command register itself does not occupy any ad­dressable memory location. The register is a latch used
to store the commands, along with the address and data
information needed to execute the command. The com­mand register is written to by bringing WE

to VIL, while
CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later;
while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write
timings are used.

10 Am29F400AT/Am29F400AB

Refer to AC Write Characteristics and the Erase/Pro­gramming Waveforms for specific timing parameters.

Sector Protection

The Am29F400A features hardware sector protection.
This feature will disable both program and erase opera­tions in any combination of ten sectors of memory. The
sector protect feature is enabled using programming
equipment at the user’s site. The device is shipped with
all sectors unprotected. Alternatively , AMD ma y program
and protect sectors in the factory prior to shipping the
device (AMD’ s ExpressFlash  Service).

PRELIMINARY

5.0 V-only Flash

It is possible to determine if a sector is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where
the higher order address bits A12–A17 is the desired
sector address, will produce a logical “1” at DQ0 for a
protected sector. See Table 3 for Autoselect codes.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors of the Am29F400A device in
order to change data in-system. The Sector Unprotect
mode is activated by setting the RESET pin to high v olt­age (12 V). During this mode, formerly protected sec­tors can be programmed or erased by selecting the
sector addresses. Once the 12 V is taken away from

the RESET pin, all the previously protected sectors will
be protected again. Refer to Figures 16 and 17.

Command Definitions

Device operations are selected by writing specific ad­dress and data sequences into the command register.

Writing incorrect address and data values
or writing them in the improper sequence will reset
the device to the read mode. Table 7 defines the valid

register command sequences. Note that the
Erase Suspend (B0H) and Erase Resume (30H) com­mands are valid only while the Sector Erase operation
is in progress. Moreover, both Reset/Read commands
are functionally equivalent, resetting the device to the
read mode.

Am29F400AT/Am29F400AB 11

PRELIMINARY

Table 7. Am29F400A Command Definitions (Notes 1–7)

Bus
Command
Sequence
Read/Reset

Reset/Read 1 XXXXH F0H
Reset/

Read

Autoselect

Program

Chip Erase

Sector
Erase

Erase Suspend 1 XXXXH B0H
Erase Resume 1 XXXXH 30H

Write

Cycles

Req’ d

Word
Byte AAAAH 5555H AAAAH
Word 3 5555H AAH 2AAAH 55H 5555H 90H 01H 2223H

Byte AAAAH 5555H AAAAH 23H

Word
/Byte

Word 4 5555H AAH 2AAAH 55H 5555H A0H PA PD
Byte AAAAH 5555H AAAAH
Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Byte AAAAH 5555H AAAAH AAAAH 5555H AAAAH
Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H
Byte AAAAH 5555H AAAAH AAAAH 5555H

First Bus

Write Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

5555H AAH 2AAAH 55H 5555H

3

Second Bus

Write Cycle

Third Bus

Write Cycle

F0H RA RD

Fourth Bus

Read/Write Cycle

(T Device ID)
22ABH
(B Device ID)

(T Device ID)
ABH
(B Device ID)

01H (T/B

00H

Manuf. ID)

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Notes:

1. Bus operations are defined in Tables 1 and 2.

2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE
SA = Address of the sector to be erased. The combination of A17–A12 will uniquely select any sector.

3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE

4. Reading from non-erasing sectors is allowed in the Erase Suspend mode.

5. Address bits A17–A15 are don’t care for unlock and command cycles.

6. The system should generate the following address patterns:

Word Mode: 5555H or 2AAAH to addresses A0–A14
Byte Mode: AAAAH or 5555H to addresses A-1–A14.

Read/Reset Command

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg­ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.

The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en­sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific

.

timing parameters.

pulse.

12 Am29F400AT/Am29F400AB

PRELIMINARY

5.0 V-only Flash

Autoselect Command

Flash memories are intended for use in applications
where the local CPU can alter memory contents. As
such, manufacture and device codes must
be accessible while the device resides in the target
system. PR OM prog r ammers typically access the sig­nature codes by raising A9 to a high voltage. How ev er ,
multiplexing high voltage onto the address lines is not
generally a desirable system design practice.

The device contains an autoselect command operation
to supplement traditional PROM programming method­ology. The operation is initiated by writing the autose­lect command sequence into the command register.
Following the command write, a read cycle from ad­dress XX00H retrieves the manuf acture code of 01H. A
read cycle from address XX01H returns the device
code (Am29F400AT = 23H and Am29F400AB = ABH
for x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode) (see Tables 3 and 4).

All manufacturer and device codes will exhibit odd par­ity with DQ7 defined as the parity bit.

Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector addresses
(A17, A16, A15, A14, A13, and A12) while (A6, A1, A0)
= (0, 1, 0) will produce a logical “1” at device output
DQ0 for a protected sector.

To terminate the operation, it is necessary to write the
read/reset command sequence into the register.

Byte/Word Programming

The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These
are followed by the program setup command and data
write cycles. Addresses are latched on the falling edge
of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichev er hap­pens first. The rising edge of CE or WE (whichev er hap­pens first) begins programming using the Embedded
Program Algorithm. Upon executing the algorithm, the
system is
ings. The device will automatically pro vide adequate in­ternally generated program pulses and verify the
programmed cell margin.

The automatic programming operation is completed
when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time
the device returns to the read mode and addresses are
no longer latched (see Table 8, Write Operation Sta­tus). Theref ore , the device requires that a v alid address
to the device be supplied by the system at this particu­lar instance of time for Data Polling operations. Data
Polling must be performed at the memory location
which is being programmed.

not

required to provide further controls or tim-

Any commands written to the chip during the Embed­ded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the
data at that particular location will be corrupted.

Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success according
to the data polling algorithm but a read from reset/read
mode will show that the data is still “013”. Only erase
operations can convert “0”s to “1”s.

Figure 1 illustrates the Embedded Programming Algo­rithm using typical command strings and
bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the chip erase command.

Chip erase does
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
erase is performed sequentially on all sectors at the
same time (see Table “Erase and Programming Perfor­mance”). The system is not required to provide any
controls or timings during these operations.

The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi­nates when the data on DQ7 is “1” (see Write Operation
Status section) at which time the device returns to read
the mode.

Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.

not

require the user to program the

Sector Erase

Sector erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed b y the sector erase command. The sector
address (any address location within the
desired sector) is latched on the falling edge of WE,
while the command (30H) is latched on the rising edge
of WE. After a time-out of 100 µs from the rising edge
of the last sector erase command, the sector erase op­eration will begin.

Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
sequentially erased. The time between writes must be
less than 100 µs otherwise that command will not be

Am29F400AT/Am29F400AB 13

PRELIMINARY

accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command
is written. A time-out of 100 µs from the rising edge of
the last WE will initiate the execution of the Sector
Erase command(s). If another falling edge of the WE
occurs within the 100 µs time-out window the timer is
reset. (Monitor DQ3 to determine if the sector erase
timer window is still open, see section DQ3, Sector
Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this period will reset the de­vice to the read mode, ignoring the previous command
string. In that case, restart the erase on those sectors
and allow them to complete.

(Refer to the Write Operation Status section for DQ3,
Sector Erase Timer operation.) Loading the sector
erase buffer may be done in any sequence and with
any number of sectors (0 to10).

not

Sector erase does

require the user to program the
device prior to erase. The device automatically pro­grams all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not af­fected. The system is

not

required to provide any con-

trols or timings during these operations.
The automatic sector erase begins after the 100 µs

time out from the rising edge of the WE pulse for the
last sector erase command pulse and terminates when
the data on DQ7, Data Polling, is “1” (see Write Opera­tion Status section) at which time the device returns to
the read mode. Data Polling must be performed at an
address within any of the sectors being erased.

Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.

Erase Suspend

The Erase Suspend command allows the user to inter­rupt a Sector Erase operation and then perform data
reads from a sector not being erased. This command is
applicable ONLY during the Sector Erase operation
which includes the time-out period for sector erase. The
Erase Suspend command will be ignored if written dur­ing the Chip Erase operation or Embedded
Program Algorithm. Writing the Erase Suspend com­mand during the Sector Erase time-out results in imme­diate termination of the time-out period and suspension
of the erase operation.

Any other command written during the Erase Suspend
mode will be ignored except the Erase
Resume command. Writing the Erase Resume com­mand resumes the erase operation. The addresses are
“don’t-cares” when writing the Erase Suspend or Erase
Resume command.

When the Erase Suspend command is written during
the Sector Erase operation, the device will take a max­imum of 15 µs to suspend the erase operation. When
the device has entered the erase-suspended mode,
DQ6 will stop toggling. The user must use the address
of a sector being erased for reading DQ6 to determine
if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the
device defaults to the erase-suspend-read mode.
Reading data in this mode is the same as reading from
the standard read mode except that the data must be
read from sectors that have not been
erase-suspended.

To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. An­other Erase Suspend command can be written after the
chip has resumed erasing.

Write Operation Status

Table 8. Write Operation Status

Status DQ7 DQ6 DQ5 DQ3

In Progress

Exceeded

Time Limits

Notes:

1. D8–D15 = Don’t Care for x16 mode.

2. DQ4 for AMD internal use only.

14 Am29F400AT/Am29F400AB

Auto-Programming DQ7 Toggle 0 0
Program/Erase in Auto-Erase 0 Toggle 0 1
Auto-Programming DQ7 Toggle 1 0
Program/Erase in Auto-Erase 0 Toggle 1 1

PRELIMINARY

5.0 V-only Flash

DQ7
Data Polling

The Am29F400A device features Data Polling as a
method to indicate to the host that the embedded algo­rithms are in progress or completed. During
the Embedded Program Algorithm an attempt to read
the device will produce the complement of the data last
written to DQ7. Upon completion of the Embedded Pro­gram Algorithm, an attempt to read the device will pro­duce the true data last written to DQ7. During the
Embedded Erase Algorithm, an attempt to read
the device will produce a “0” at the DQ7 output.
Upon completion of the Embedded Erase Algorithm an
attempt to read the device will produce a “1” at the DQ7
output. The flowchart for Data
in Figure 2.

For chip erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse se­quence. For sector erase, the Data Polling is valid after
the last rising edge of the sector erase WE pulse. Data
Polling must be performed at sector addresses within
any of the sectors being erased and not a protected
sector. Otherwise, the status may not be valid.

Just prior to the completion of Embedded Algorithm
operations DQ7 may change asynchronously while
the output enable (OE) is asserted low. This means
that the device is driving status information on DQ7 at
one instant of time and then that byte’s valid data at
the next instant of time. Depending on when the sys­tem samples the DQ7 output, it may read the status or
valid data. Even if the device has completed the Em­bedded Algorithm operations and DQ7 has a valid
data, the data outputs on DQ0–DQ6 may be still in­valid. The valid data on DQ0–DQ7 will be read on the
successive read attempts.

The Data Polling feature is only active during the Em­bedded Programming Algorithm, Embedded Erase Al­gorithm, or sector erase time-out (see Table 7).

See Figure 10 for the Data P olling timing specifications
and diagrams.

DQ6
Toggle Bit

The Am29F400A also features the “Toggle Bit” as a
method to indicate to the host system that the embed­ded algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cy­cle, successive attempts to read (OE toggling) data
from the device at any address will result in DQ6 tog­gling between one and zero. Once the Embedded Pro­gram or Erase Algorithm cycle is completed, DQ6 will
stop toggling and valid data will be read on
successive attempt. During programming, the Toggle
Bit is valid after the rising edge of the fourth WE pulse
in the four write pulse sequence. For chip erase, the

Polling (DQ7) is shown

the next

Toggle Bit is valid after the rising edge of the sixth WE
pulse in the six write pulse sequence. F or Sector erase,
the Toggle Bit is valid after the last rising edge of the
sector erase WE pulse. The Toggle Bit is active during
the sector time-out.

Either CE or OE toggling will cause DQ6 to toggle. In
addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See Figure 11 for the Toggle Bit
timing specifications and diagrams.

DQ5
Exceeded Timing Limits

DQ5 will indicate if the program or erase time has ex­ceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a “1”. This is
a failure condition which indicates that the program or
erase cycle was not successfully completed. Data
ing is the only operating function of the device under
this condition. The CE circuit will partially power down
the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output dis­able functions as described in Table 1.

The DQ5 failure condition will also appear if a user tries
to program a 1 to a location that is previously pro­grammed to 0. In this case the device locks out and
never completes the Embedded Program Algorithm.
Hence, the system never reads a valid data on DQ7 bit
and DQ6 never stops toggling. Once the de vice has e x­ceeded timing limits, the DQ5 bit will indicate a “1.”
Please note that this is not a device failure condition
since the device was incorrectly used. If this occurs,
reset the device.

DQ3
Sector Erase Timer

After the completion of the initial sector erase com­mand sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete. Data
Polling and Toggle Bit are valid after the initial sector
erase command sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, DQ3 may be
used to determine if the sector erase timer window is
still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent
commands (other than Erase Suspend) to the device
will be ignored until the erase operation is completed as
indicated by Data Polling or Toggle Bit. If DQ3 is low
(“0”), the device will accept additional sector erase
commands. To insure the command has been ac­cepted, the system software should check the status of
DQ3 prior to and following each subsequent sector
erase command. If DQ3 were high on the second sta­tus check, the command may not have been accepted.

Refer to Table 8: Write Operation Status.

Poll-

Am29F400AT/Am29F400AB 15

PRELIMINARY

RY/BY

Ready/Busy

The Am29F400A provides a RY/BY open-drain output
pin as a way to indicate to the host system that the Em­bedded Algorithms are either in progress or have been
completed. If the output is low, the device is busy with
either a program or erase operation. If the output is
high, the device is ready to accept any read/write or
erase operation. When the R Y/BY pin is low, the device
will not accept any additional program or erase com­mands with the exception of the Erase Suspend com­mand. If the Am29F400A is placed in an Erase
Suspend mode, the RY/BY

During programming, the RY/BY pin is driven low after
the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising
edge of the sixth WE pulse. The RY/BY pin should be
ignored while RESET is at VIL. Refer to Figure 12 for a
detailed timing diagram.

Since this is an open-drain output, sever al RY/BYpins
can be tied together in parallel with a pull-up resistor
to VCC.

RESET
Hardware Reset

The Am29F400A device may be reset by driving the
RESET pin to VIL. The RESET pin must be kept low
(VIL) for at least 500 ns. Any operation in progress will
be terminated and the internal state machine will be
reset to the read mode 20 µs after the RESET pin is
driven low. Furthermore, once the RESET pin goes
high, the device requires an additional 50 ns before it
will allow read access. When the RESET pin is low, the
device will be in the standby mode for the duration of
the pulse and all the data output pins will be tri-stated.
If a hardware reset occurs during a program or erase
operation, the data at that particular location will
be indeterminate.

The RESET pin may be tied to the system reset input.
Therefore, if a system reset occurs during the Embed­ded Program or Erase Algorithm, the device will be au­tomatically reset to read mode and this will enable the
system’s microprocessor to read the boot-up firmware
from the Flash memory.

output will be high.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word
(16 bit) mode for the Am29F400A device. When this
pin is driven high, the device operates in the word (16

bit) mode. The data is read and programmed
at DQ0–DQ15. When this pin is driven low, the de­vice operates in byte (8 bit) mode. Under this mode,
the DQ15/A-1 pin becomes the lowest address bit
and DQ8–DQ14 bits are tri-stated. However, the
command bus cycle is always an 8-bit operation and
hence commands are written at DQ0–DQ7 and the
DQ8–DQ15 bits are ignored. Refer to Figures 14 and
15 for the timing diagram.

Data Protection

The Am29F400A is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that ma y e xist during power transi­tions. During power up the device automatically resets
the internal state machine in the Read mode. Also , with
its control register architecture, alteration of the mem­ory contents only occurs after successful completion of
specific multi-bus cycle command sequences.

The device also incorporates several features to pre­vent inadvertent write cycles resulting from V
power-up and power-down tr ansitions or system noise.

CC

Low VCC Write Inhibit

To av oid initiation of a write cycle during VCC power-up
and power-down, the Am29F400A locks out write cy­cles for VCC < V
voltages). When VCC < V
disabled, all internal program/erase circuits
are disabled, and the device resets to the read mode.
The Am29F400A ignores all writes until VCC > V
The user must ensure that the control pins are in the
correct logic state when VCC > V
tentional writes.

(see DC Characteristics section for

LKO

, the command register is

LKO

to prevent unin-

LKO

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL,CE
= VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

Power -Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE =
VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.

.

16 Am29F400AT/Am29F400AB

5.0 V-only Flash

EMBEDDED ALGORITHMS

PRELIMINARY

Start

Increment Address

Program Command Sequence (Address/Command):

Write Program Command Sequence

(see below)

Data

Poll Device

No

Last Address

?

Yes

Programming Completed

5555H/AAH

2AAAH/55H

5555H/A0H

Program Address/Program Data

20380B-8

Figure 1. Embedded Programming Algorithm

Am29F400AT/Am29F400AB 17

EMBEDDED ALGORITHMS

PRELIMINARY

Start

Write Erase Command Sequence

Chip Erase Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

(see below)

Polling or Toggle Bit

Data

Successfully Completed

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/10H

2AAAH/55H

Sector Address/30H

Sector Address/30H

Sector Address/30H

Additional sector
erase commands
are optional

20380B-9

Note:

To insure the command has been accepted, the system software should check the status of DQ3 prior to and f ollowing each sub­sequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted.

Figure 2. Embedded Erase Algorithm

18 Am29F400AT/Am29F400AB

PRELIMINARY

5.0 V-only Flash

Start

No

Read Byte

(DQ0-DQ7)

Addr=VA

DQ7=Data

?

No

DQ5=1

?

Yes

Read Byte

(DQ0-DQ7)

Addr=VA

DQ7=Data

?

No

VA=Byte address for programming

=any of the sector addresses within the

sector being erased during sector erase

operation

=Valid address equals any non-protected

sector group address during chip erase

Yes

Yes

Pass

Note:

DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Fail

20380B-10

Figure 3. Data Polling Algorithm

Am29F400AT/Am29F400AB 19

PRELIMINARY

Start

Read Byte

(DQ0–DQ7)

Addr=Don’t Care

DQ6=Toggle

No

?

Yes

No

DQ5=1

?

Yes

Read Byte

(DQ0–DQ7)

Addr=Don’t Care

DQ6=Toggle

No

?

Yes

Pass

Fail

Note:

DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.

20380B-11

Figure 4. Toggle Bit Algorithm

20 ns

+0.8 V

-0.5 V

-2.0 V
20 ns

20 ns

Figure 5. Maximum Negative Overshoot Waveform

20 ns

+ 2.0 V

V

CC

V

+ 0.5 V

CC

2.0 V
20 ns 20 ns

Figure 6. Maximum Positive Overshoot Waveform

20 Am29F400AT/Am29F400AB

20380B-12

20380B-13

PRELIMINARY

5.0 V-only Flash

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . -65°C to +125°C

Ambient T emper ature

with Power Applied. . . . . . . . . . . . . . -55°C to +125°C

Voltage with Respect to Ground
All pins except A9, OE and RESET

(Note 1) . . . . . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V

A9, OE, and RESET (Note 2). . . . . . -2.0 V to +13.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC v oltage on input or I/O pins is -0.5 V. During
voltage transitions, input or I/O pins ma y undershoot V
to -2.0 V f or periods of up to 20 ns. Maximum DC voltage
on input or I/O pins is
transitions, input or I/O pins may ov ershoot to V
for periods up to 20 ns. See Figure 7 and Figure 8.

2. Minimum DC input v oltage on pins A9, OE

-0.5 V. During voltage transitions, A9, OE
may undershoot V
Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns. See
Figure 7 and Figure 8.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this data sheet is
not implied. Exposure of the de vice to absolute maximum
rating conditions for extended periods may affect device
reliability.

V

+0.5 V. During voltage

CC

, and RESET is

, and RESET

to -2.0 V for periods of up to 20 ns.

SS

CC

SS

+2.0 V

OPERATING RANGES

Commercial (C) Devices

Ambient T emper ature (TA). . . . . . . . . . . . 0˚C to +70˚C

Industrial (I) Devices

Ambient T emper ature (TA). . . . . . . . . . -40˚C to +85˚C

Extended (E) Devices

Ambient T emper ature (TA). . . . . . . . . -55˚C to +125˚C

VCC Supply Voltages

VCC for Am29F400T/B-65, . . . . . . +4.75 V to +5.25 V

VCC for Am29F400T/B-70, -90,

-120, -150 . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

Am29F400AT/Am29F400AB 21

PRELIMINARY

DC CHARACTERISTICS
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

I

LI

I

LIT

I

LO

I

CC1

I

CC2

I

CC3

V

IL

V

IH

V

ID

V

OL

V

OH

V

LKO

Notes:

1. The I
The frequency component typically is less than 2 mA/MHz, with OE

active while Embedded Program or Erase Algorithm is in progress.

2. I

CC

3. Not 100% tested.

Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
A9, OE, RESET Input Load Current VCC = VCC Max, A9, OE, RESET = 12.5 V 50 µA
Output Leakage Current V

= VSS to VCC, VCC = VCC Max ±1.0 µA

OUT

Byte 40

VCC Active Read Current (Note 1) CE = VIL, OE = V

VCC Active Program/Erase Current
(Notes 2, 3)

CE

= VIL, OE = V

VCC Standby Current VCC = VCC Max, CE = VIH, OE = V

IH

IH

Word 50

IH

60 mA

1.0 mA
Input Low Voltage –0.5 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
Voltage for Autoselect and

Temporary Sector Unprotect

= 5.0 V 11.5 12.5 V

V

CC

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
Output High Voltage IOH = -2.5 mA, VCC = VCC Min 2.4 V
Low VCC Lock-Out Voltage 3.2 4.2 V

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

CC

at VIH.

mA

22 Am29F400AT/Am29F400AB

PRELIMINARY

5.0 V-only Flash

DC CHARACTERISTICS (continued)
CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

LI

I

LIT

I

LO

I

CC1

I

CC2

I

CC3

V

V

IH

V

ID

V

OL

V

OH1

V

OH2

V

LKO

Notes:

1. The I
The frequency component typically is less than 2 mA/MHz, with OE

active while Embedded Program or Erase Algorithm is in progress.

2. I

CC

3. Not 100% tested.

4. I

CC3

Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

V

A9, OE, RESET Input Load
Current

Output Leakage Current V

= VCC Max, A9, OE,

CC

= 12.5 V

RESET

= VSS to VCC, VCC = VCC Max ±1.0 µA

OUT

Byte 20 40

VCC Active Read Current (Note 1) CE = VIL, OE = V

VCC Active Program/Erase
Current (Notes 2, 3)

VCC Standby Current (Note 4)

Input Low Voltage -0.5 0.8 V

IL

CE

= VIL, OE = V

= VCC Max, CE = VIH,

V

CC

OE

= V

IH

Input High Voltage

Voltage for Autoselect and
Temporary Sector Unprotect

V

= 5.0 V 11.5 12.5 V

CC

IH

IH

Word 28 50

30 50 mA

15µA

0.7 x
V

CC

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

Output Low Voltage

IOH = –2.5 mA, VCC = VCC Min

0.85
V

CC

IOH = –100 µA, VCC = VCC Min VCC -0.4 V

Low VCC Lock-Out Voltage 3.2 4.2 V

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

CC

at VIH.

= 20 µA max at extended temperatures (> +85°C).

50 µA

VCC +

0.3

mA

V

V

Am29F400AT/Am29F400AB 23

PRELIMINARY

AC CHARACTERISTICS
Read-Only Operations Characteristics

Parameter

Symbols Speed Option (Notes 1 and 2)

JEDEC Standard Description Test Setup -65 -70 -90 -120 -150 Unit

t

AVAV

t

AVQV

t

ELQV

t

GLQVtOE

t

EHQZtDF

t

GHQZtDF

t

AXQXtOH

t

RC

t

ACC

t

CE

t

Ready

t

ELFL

t

ELFH

Notes:

1. Test Conditions (for -65 only)
Output Load: 1 TTL gate and 30 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels:0.0 V to 3.0 V
Timing Measurement Reference Level: 1.5 V input
and output

2. Test Conditions (for -70, -90, -120, -150)
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns

Read Cycle Time (Note 4) Min 60 70 90 120 150 ns

= V

CE

Address to Output Delay

OE = V

IL

Max 60 70 90 120 150 ns

IL

Chip Enable to Output Delay OE = VILMax 60 70 90 120 150 ns
Output Enable to Output

Delay
Chip Enable to Output High Z

(Notes 3, 4)
Output Enable to Output

High Z (Notes 3, 4)

Max 30 30 35 50 55 ns

Max 20 20 20 30 35 ns

Max 20 20 20 30 35 ns

Output Hold Time From
Addresses, CE

or OE,

Min00000ns

Whichever Occurs First
RESET Pin Low to Read

Mode (Note 4)
CE to BYTE Switching Low

or High

Max 20 20 20 20 20 µs

Max55555ns

Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2.0 V
input and output

3. Output Driver Disable Time

4. Not 100% tested.

5.0 V

IN3064

Device

or Equivalent

2.7 kΩ

Under

Test

C

L

6.2 kΩ

Notes:

For -65: C
For all others: C

= 30 pF including jig capacitance

L

= 100 pF including jig capacitance

L

Figure 7. Test Conditions

24 Am29F400AT/Am29F400AB

IN3064 or Equivalent

IN3064 or Equivalent

IN3064 or Equivalent

20380B-14

5.0 V-only Flash

AC CHARACTERISTICS
Write (Erase/Program) Operations

PRELIMINARY

Parameter Symbols

JEDEC Standard -65 -70 -90 -120 -150 Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHDL

t

WC

t

AS

t

AH

t

DS

t

DH

t

OEH

t

GHWL

t

CS

t

CH

t

WP

t

WPH

Description

Write Cycle Time Min 60 70 90 120 150 ns
Address Setup Time Min 00000ns
Address Hold Time Min 45 45 45 50 150 ns
Data Setup Time Min 30 30 45 50 50 ns
Data Hold Time Min 00000ns

Output
Enable
Hold Time

Read Recovery Time Before Write
(OE

High to WE Low)

Read (Note 2) Min 00000ns
Toggle and Data

(Note 2)

Polling

Min 10 10 10 10 10 ns

Min00000ns

CE Setup Time Min 00000ns
CE Hold Time Min 00000ns
Write Pulse Width Min 35 35 45 50 50 ns
Write Pulse Width High Min 20 20 20 20 20 ns

Speed Option (Notes 1 and 2)

Byte Typ 77777µs

t

WHWH1tWHWH1

Programming Operation

Word Typ1414141414µs

Typ 1.0 1.0 1.0 1.0 1.0 sec

t

WHWH2tWHWH2

t

VCS

t

VIDR

t

OESP

t

RP

t

FLQZ

t

BUSY

t

RESSP

Sector Erase Operation (Note 1)

Max88888sec
VCC Setup Time (Note 2) Min 50 50 50 50 50 µs
Rise Time to VID (Notes 2, 3) Min 500 500 500 500 500 ns
OE Setup Time to WE Active

(Notes 2, 3)

Min44444µs

RESET Pulse Width Min 500 500 500 500 500 ns
BYTE Switching Low to Output High Z

(Notes 3, 4)
Program/Erase Valid to RY/BY Delay

(Note 2)

Max 20 20 30 30 30 ns

Min 30 30 35 50 55 ns

RESET Setup Time to WE Active Min 44444µs

Notes:

1. This does not include the preprogramming time.

2. Not 100% tested.

3. These timings are for Temporary Sector Unprotect operation.

4. Output Driver Disable Time.

Am29F400AT/Am29F400AB 25

KEY TO SWITCHING WA VEFORMS

WAVEFORM INPUTS OUTPUTS

PRELIMINARY

SWITCHING W A VEFORMS

Addresses

Must Be
Steady

May
Change
from H to L

May
Change
from L to H

Don’t Care,
Any Change
Permitted

Does Not
Apply

t

RC

Addresses Stable

Will Be
Steady

Will Be
Changing
from H to L

Will Be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

KS000010

CE

OE

WE

Outputs

t

ACC

t

OE

t

OEH

(tCE)

(tOH)

High Z High Z

Output Valid

(tDF)

Figure 8. AC Waveforms for Read Operations

20380B-15

26 Am29F400AT/Am29F400AB

5.0 V-only Flash

SWITCHING W A VEFORMS

3rd Bus Cycle

PRELIMINARY

Data Polling

Addresses

5555H

t

WC

PA

t

AH

t

AS

CE

t

GHWL

OE

t

WHWH1

WE

Data

t

t

CS

DS

A0H

t

WPH

t

WP

t

DH

PD

5.0 V

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7

4. D

is the output of the complement of the data written to the device.

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles of four bus cycle sequence.

6. These waveforms are for the x16 mode.

Figure 9. Program Operation Timings

DQ7

PA

t

RC

t

t

OE

D

OUT

t

CE

DF

t

OH

20380B-16

Addresses

Notes:

1. SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase.

2. These waveforms are for the x16 mode.

CE

OE

WE

Data

V

CC

t

VCS

t

GHWL

t

AH

5555H 5555H

t

WP

t

t

CS

t

DS

WPH

t

DH

AAH

2AAAH

t

AS

55H

5555H

AAH

Figure 10. AC Waveforms Chip/Sector Erase Operations

Am29F400AT/Am29F400AB 27

2AAAH

55H80H 10H/30H

SA

20380B-17

SWITCHING W A VEFORMS

t

CE

OE

CH

t

OEH

PRELIMINARY

t

OE

t

DF

WE

DQ7

DQ0-DQ6

t

CE

t

WHWH 1 or 2

DQ7

DQ0-DQ6=Invalid

Note:

*DQ7=Valid Data (The device has completed the Embedded operation).

Figure 11. AC Waveforms for Data Polling During Embedded Algorithm Operations

CE

t

OEH

WE

*

t

OH

DQ7=

Valid Data

DQ0-DQ6
Valid Data

High Z

20380B-18

OE

Data

(DQ0-DQ7)

DQ6=T oggle

DQ6=T oggle

Note:

*DQ6 stops toggling (The device has completed the Embedded operation).

Figure 12. AC Waveforms for Toggle Bit During Embedded Algorithm Operations

28 Am29F400AT/Am29F400AB

*

t

OE

DQ6=

Stop T oggling

DQ0-DQ7

Valid

20380B-19

5.0 V-only Flash

SWITCHING W A VEFORMS

CE

PRELIMINARY

The rising edge of the last WE

WE

RY/BY

Entire programming
or erase operations

t

BUSY

Figure 13. RY/BY Timing Diagram During Program/Erase Operations

RESET

t

RP

t

Ready

Figure 14. RESET

Timing Diagram

signal

20380B-20

20380B-21

Am29F400AT/Am29F400AB 29

SWITCHING W A VEFORMS

CE

OE

BYTE

DQ0-DQ14

t

ELFL

t

ELFH

PRELIMINARY

Data Output

(DQ0-DQ14)

Data Output

(DQ0-DQ7)

DQ15/A-1

Figure 15. BYTE Timing Diagram for Read Operation

CE

WE

BYTE

Figure 16. BYTE

Address

Input

t

FLQZ

DQ15

Output

The falling edge of the last WE signal

t

SET

(tAS)

t

HOLD

(tAH)

Timing Diagram for Write Operations

20380B-22

20380B-23

30 Am29F400AT/Am29F400AB

PRELIMINARY

5.0 V-only Flash

Start

RESET = V

(Note 1)

Perform Erase or

Program Operations

RESET

Temporary Sector Group

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 17. Temporary Sector Unprotect Algorithm

= V

ID

IH

20380B-24

5 V

RESET

RY/BY

CE

WE

12 V

t

VIDR

Program or Erase Command Sequence

Figure 18. Temporary Sector Unprotect Timing Diagram

20380B-25

Am29F400AT/Am29F400AB 31

AC CHARACTERISTICS
Write/Erase/Program Operations

Alternate CE Controlled Writes

PRELIMINARY

Parameter Symbols

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

OEH

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

FLQZ

Speed Option (Notes 1 and 2)

Description

UnitJEDEC Standard -65 -70 -90 -120 -150

Write Cycle Time (Note 2) Min 60 70 90 120 150 ns
Address Setup Time Min 00000ns
Address Hold Time Min 45 45 45 50 50 ns
Data Setup Time Min 30 30 45 50 50 ns
Data Hold Time Min 00000ns
Output Enable Setup Time Min 00000ns

Read (Note 2) Min 00000ns

Output Enable
Hold Time

Toggle and Data
Polling (Note 2)

Min 10 10 10 10 10 ns

Read Recover Time Before Write Min 00000ns
WE Setup Time Min 00000ns
WE Hold Time Min 00000ns
CE Pulse Width Min 35 35 45 50 50 ns
CE Pulse Width High Min 20 20 20 20 20 ns

Byte T yp 77777µs

Programming Operation

Word Typ1414141414µs

Typ 1.0 1.0 1.0 1.0 1.0 sec

Sector Erase Operation (Note 1)

Max88888sec

BYTE Switching Low to Output High Z
(Note 2)

Max 20 20 30 30 30 ns

Notes:

1. This does not include the preprogramming time.

2. Not 100% tested.

32 Am29F400AT/Am29F400AB

5.0 V-only Flash

SWITCHING W A VEFORMS

PRELIMINARY

Data Polling

Addresses

5555H

t

WC

PA

t

AH

t

AS

WE

t

GHEL

OE

t

CP

CE

Data

t

WS

t

DS

A0H

t

CPH

t

DH

PD

5.0 V olt

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7

4. D

is the output of the complement of the data written to the device.

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles of four bus cycle sequence.

6. These waveforms are for the x16 mode.

Figure 19. Alternate CE Controlled Program Operation Timings

t

WHWH1

DQ7

PA

D

OUT

20380B-26

ERASE AND PROGRAMMING PERFORMANCE

Sector Erase Time 1.0 8 sec Excludes 00H programming prior to erasure
Chip Erase Time 11 88 sec Excludes 00H programming prior to erasure
Byte Programming Time 7 300 (Note 3) µs Excludes system-level overhead (Note 4)
Word Programming Time 14 600 µs Excludes system-level overhead (Note 4)
Chip Programming Time 3.6 10.8 (Notes 3, 5) sec Excludes system-level overhead (Note 4)

Notes:

1. 25

2. Although Embedded Algorithms allow for longer chip prog r am and erase time , the actual time will be consider ab ly less since
bytes program or erase significantly faster than the worst case byte.

3. Under worst case condition of 90

4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each
byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.

5. The Embedded Algorithms allow for 2.5 ms b yte program time. DQ5 = “1” only after a b yte takes the theoretical maximum time
to program. A minimal number of bytes ma y require significantly more progr amming pulses than the typical byte . The majority
of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming Times
listed above.

Parameter

°

C, 5.0 V VCC, 100,000 cycles.

Limits

°

C, 4.5 V VCC, 100,000 cycles.

Am29F400AT/Am29F400AB 33

Unit CommentsTyp (Note 1) Max

PRELIMINARY

LATCHUP CHARACTERISTICS

Min Max

Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

C

IN

C

OUT

C

IN2

Input Capacitance VIN = 0 6 7.5 pF
Output Capacitance V

= 0 8.5 12 pF

OUT

Control Pin Capacitance VIN = 0 8 10 pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

C

IN

C

OUT

C

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

A

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

= 0 8.5 12 pF

OUT

Control Pin Capacitance VPP = 0 8 10 pF

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

34 Am29F400AT/Am29F400AB

150°C 10 Years
125°C 20 Years

PRELIMINARY

5.0 V-only Flash

REVISION SUMMARY

Distinctive Characteristics:

High Performance:

is now 60 ns.

Enhanced power management for standby mode:

Changed typical standby current to 1µA.

General Description:

First paragraph, first sentence should read, “...orga­nized as 512 Kbytes of 8 bits each or 256
bits each.” Added 60 ns speed option.

Product Selector Guide:

Added -65 column (60 ns, ±5% V
±10% VCC) and deleted -75 speed option.

Ordering Information, Standard Products:

The -65 speed option is now listed in the example.

Valid Combinations:

75 speed options.

Tables 1 and 2, User Bus Operations:

Corrected WE for read operations; was don’t care (X),
is now H.

Standby Mode:

Corrected standby mode current; was 100 µA, is now
5 µA.

Table 5, Sector Address Tables (Am29F400AB):

Corrected x16 starting address for SA5; was 1C000h,
is now 28000h.

The fastest speed option available

Kwords

). Added -70 (70 ns ,

CC

Added -65 and -70, and deleted -

of 16

Erase Suspend:

Third paragraph, third sentence: Deleted the word “NOT.”

Operating Ranges:

VCC Supply Voltages:

options in the list. Changed A9 maximum to +13.0 V.

DC Characteristics:

CMOS Compatible:

Note 4 (refers to I

AC Characteristics:

Read Only Operations Characteristics:

column and test conditions.
Replaced -75 column with -70 column.

Test Conditions, Figure 7:

Changed speed option in first C
to -65.

AC Characteristics:

Added -65 and deleted -75 speed

Revised ICC specifications. Added

).

CC3

Added the -65

statement from -75

L

Write/Erase/Program Operations, Alternate CE Con­trolled Writes:

column with -70 column. Revised sector erase and
programming specifications.

Erase and Programming Performance:

Revised specifications in table. Clarified tab le and notes.

Table 7, Command Definitions

Revised Note 5 to cover all upper address bits that are
don’t care.

Deleted Note 6.

Added the -65 column. Replaced -75

Am29F400AT/Am29F400AB 35