Datasheet AM29F200AT-55SCB, AM29F200AT-55SC, AM29F200AT-55FIB, AM29F200AT-55FI, AM29F200AT-55FEB Datasheet (AMD Advanced Micro Devices)
...Page 1
PRELIMINARY
Publication# 20637 Rev: B Amendment/+3
Issue Date: March 1998
Am29F200A
2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
■ High performance
— Access times as fast as 55 ns
■ Low power consumption
— 20 mA typical active read current (byte mode)
— 28 mA typical active read current for
(word mode)
— 30 mA typical program/erase current
—1 µA typical standby current
■ Sector erase architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
three 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 100,000 write/ erase cyc les guaranteed
■ Package options
— 44-pin SO
— 48-pin TSOP
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■ Data# Polling and Toggle Bit
— Detects program or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Hardware method for detection of program or
erase cycle completion
■ Erase Suspend/Erase Resume
— Supports reading data from a sector not being
erased
■ Hardware RESET# pin
— Resets internal state machine to the reading
array data
Page 2
2 Am29F200A
PRELIMINARY
GENERAL DESCRIPTION
The Am29F200A is a 2 Mbit, 5.0 Volt-only Flash memory organized as 262,144 byte s or 131,072 words. The
8 bits of data a ppear on DQ0–DQ7; the 16 bits on DQ0–
DQ15. The Am29F200A is offered in 44-pin SO and
48-pin TSOP packages. This device is designed to be
programmed in-system with the standard system 5.0
volt V
CC
supply. A 12.0 volt VPP is not required for
program or erase operation s. The device can also be
reprogrammed in standard EPROM programmers.
The standard device offers access times of 55, 70,
90, 120, and 150 ns, allowing operation of
high-speed microp ro cess ors withou t w ai t stat es. To
eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co ntrols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase co mmand sequence. This initiates the Embedded Erase
algorithm—an inter nal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6/
DQ2 (toggle) status bits. After a program or eras e
cycle has been completed, the device is ready to read
array data or accept another command.
The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically in hibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory . This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the devi ce into the standb y mode.
Pow er cons umption is g reatly r educed in this mode .
AMD’s Flash technology combines years of Flas h memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device
electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is
program me d using hot electron in je ct i on.
Page 3
Am29F200A 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
BLOCK DIAGRAM
Family Part Number Am29F200A
Speed Option
V
CC
= 5.0 V ± 5% -55
V
CC
= 5.0 V ± 10% -70 -90 -120 -150
Max access time, ns (t
ACC
) 55 70 90 120 150
Max CE# access time, ns (tCE) 55 70 90 120 150
Max OE# access time, ns (tOE) 3030355055
Erase Voltage
Generator
Input/Output
Buffers
Data
Latch
Y-Gating
Cell MatrixX-Decoder
Y-Decoder
Address Latch
Chip Enable
Output Enable
Logic
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
WE#
CE#
OE#
A0–A16
STB
STB
DQ0–DQ15
RY/BY#
Buffer
RY/BY#
BYTE#
RESET#
A-1
V
CC
V
SS
20637B-1
Page 4
4 Am29F200A
PRELIMINARY
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
RY/BY#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
20637B-2
Page 5
Am29F200A 5
PRELIMINARY
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A1
NC
A7
A6
A5
A4
A3
A2
20637B-3
Standard TSOP
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A1
NC
A7
A6
A5
A4
A3
A2
20637B-4
Reverse TSOP
Page 6
6 Am29F200A
PRELIMINARY
PIN CONFIGURATION
A0–A16 = 17 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
V
CC
= +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
V
SS
= Device ground
NC = Pin not connected internally
LOGIC SYMBOL
20637B-5
17
16 or 8
DQ0–DQ15
(A-1)
A0–A16
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
Page 7
Am29F200A 7
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29F200A
2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
CE-55Am29F200A T
Valid Combinations
AM29F200AT-55,
AM29F200AB-55
EC, EI, FC, FI, SC, SI
AM29F200AT-70,
AM29F200AB-70
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
AM29F200AT-90,
AM29F200AB-90
AM29F200AT-120,
AM29F200AB-120,
AM29F200AT-150,
AM29F200AB-150,
Page 8
8 Am29F200A
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory loc ation.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F200A Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D
OUT
= Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the by te or word configur ation. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at V
IH
. On x16 (word-wide) devices, the BYTE# pin
determines whether the device outputs array data in
words or bytes.
The internal state machin e is set for reading array
data upon device power-up, or after a ha rdware reset. This ensures that no spurious alteration of the
memory content occ urs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to VIH.
On x16 (word-wide) devices, for program op erations,
the BYTE# pin dete rmines whether the device a ccepts program data in bytes or words. Refer to
“Word/Byte Configuration” for more information.
Operation CE# OE# WE# RESET# A0–A16 DQ0–DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read L L H H A
IN
D
OUT
D
OUT
High-Z
Write L H L H A
IN
D
IN
D
IN
High-Z
CMOS Standby V
CC
± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
(See Note)
XXX V
ID
A
IN
D
IN
D
IN
X
Page 9
Am29F200A 9
PRELIMINARY
An erase operation can erase one sect or, multiple sectors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Characteristics section in the appropriate data sheet f or t iming
diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standb y mode when CE#
and RESET# pins are both held at V
CC
± 0.5 V. (Note
that this is a more restrict ed voltage range than V
IH
.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
IH
. The device re-
quires standard access time (t
CE
) for read access
when the device is in either of these s tandby modes,
before it is ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, I
CC3
represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardw are method of resetting the device to readin g arr ay data. When the system
drives the RESET# pin low for at least a period of t
RP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
IL
, the device enters
the TTL standby mode; if RESET# is held at V
SS
±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embe dded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
Page 10
10 Am29F200A
PRELIMINARY
Table 2. Am29F200T Top Boot Block Sector Address Tabl e
Table 3. Am29F200B Bottom Boot Block Sector Address Table
Note for Tables 2 and 3: Address range is A16:A-1 in byte mode and A16:A0 in word mode. See “Word/Byte Configuration”
section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Com mand Definitions ta ble shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require V
ID
. See “Autoselect Command Sequence” for details on using the
autoselect mode.
Sector A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
SA0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 1 1 0 X X 32/16 30000h–37FFFh 18000h–1BFFFh
SA4 1 1 1 0 0 8/4 38000h–39FFFh 1C000h–1CFFFh
SA5 1 1 1 0 1 8/4 3A000h–3BFFFh 1D000h–1DFFFh
SA6 1 1 1 1 X 16/8 3C000h–3FFFFh 1E000h–1FFFFh
Sector A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
SA0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh
SA1 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh
SA2 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh
SA3 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh
SA4 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
Page 11
Am29F200A 11
PRELIMINARY
Table 4. Am29F200A Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20551. Contact an
AMD representative to obtain a cop y of the appropriate
document.
The device is shipped with all s ectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system.
The Sector Unprotect mode is acti v ated b y setti ng the
RESET# pin to V
ID
. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V
ID
is removed
from the RESET# pin, all the previously protected
sectors are protec ted again. Figure 1 shows the algorithm, and the Temporar y Sector Unprotect diagram
(Figure 18 ) shows the tim ing waveforms, for this feature.
Figure 1. Temporary Sector Unprotect Operati on
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or pro-
Description Mode CE# OE# WE#
A16
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
ID
XLXLL X 01h
Device ID:
Am29F200A
(Top Boot Block)
Word L L H
XXVIDXLXLH
22h 51h
Byte L L H X 51h
Device ID:
Am29F200A
(Bottom Boot Block)
Word L L H
XXVIDXLXLH
22h 57h
Byte L L H X 57h
Sector Protection V erification L L H SA X V
ID
XLXHL
X
01h
(protected)
X
00h
(unprotected)
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20637B-6
Page 12
12 Am29F200A
PRELIMINARY
gramming, which might otherwise be caused by spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
IL
, CE# = VIH or WE# = VIH. To initiate a writ e cycle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = VIH during powe r
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
COMMAND DEFINITIONS
Writing specific addre ss and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Embedded Erase algorithm.
After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.
The system
must
issue the reset command to re-enable the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
howeve r, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (a lso applies during Erase Suspend).
Autoselect Command Sequence
The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table show s the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage
Page 13
Am29F200A 13
PRELIMINARY
Method) table, which is intended for PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Ref e r t o the Se cto r Ad dre ss tables for valid
sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is
not
required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell
margin. The Command Definitions take shows the address and data requirements f or the byte prog ram command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Ope ration Status”
for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The program command sequence
should be reinitiated once the de vi ce has reset t o reading array data, to ensure data integrity.
Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bu s-cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a ha rd ware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20637B-7
Page 14
14 Am29F200A
PRELIMINARY
The system can deter mine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#.
See “Write Op eration Status” for information on
these status bits. When the Embedded Erase algorithm is complete, the device return s to reading
array data and addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for parameters , and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then f ollow ed b y the address of the sector to be erased, and the sector erase
command. The Command Definitions table shows the
address and data requirements for the sector erase
command sequence.
The device does
not
require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. Du ring the time-ou t period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all secto rs. The time between these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .
Once the sector erase operation has begun, onl y the
Erase Suspend command is valid. All other commands
are ignored. Note th at a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched. The system can determine the status of the erase operation b y using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for information on these status bits.
Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagr am for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows t he syste m to interrupt a sector erase ope ration and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase c ommand sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the er ase oper at ion. Addresses are “don’t-cares” when writing the Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasu re. (The de vice “er ase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is complete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can dete rmine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
Page 15
Am29F200A 15
PRELIMINARY
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operat ion. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device has resumed erasing.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
20637B-8
Page 16
16 Am29F200A
PRELIMINARY
Table 5. Am29F200A Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A16–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Data bits DQ15–DQ8 are don’t ca res for unlock and
command cycles.
5. Address bits A16–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array
data.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).
8. The fourth cycle of the autose lect command sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
11. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID
Word
4
555
AA
2AA
55
555
90 X00 01
Byte AAA 555 AAA
Device ID,
Top Boot Block
Word
4
555
AA
2AA
55
555
90
X01 2251
Byte AAA 555 AAA
X02
51
Device ID,
Bottom Boot Block
Word
4
555
AA
2AA
55
555
90
X01 2257
Byte AAA 555 AAA
X02
57
Sector Protect Verify
(Note 9)
Word
4
555
AA
2AA
55
555
90
(SA)
X02
XX00
XX01
Byte AAA 555 AAA
(SA)
X04
00
01
Program
Word
4
555
AA
2AA
55
555
A0 PA PD
Byte AAA 555 AAA
Chip Erase
Word
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase
Word
6
555
AA
2AA
55
555
80
555
AA
2AA
55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 10) 1 XXX B0
Erase Resume (Note 11) 1 XXX 30
Cycles
Autoselect (Note 8)
Page 17
Am29F200A 17
PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 9 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, in dicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the ris ing edge of the final WE# pulse in the program or
erase command sequence.
During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 2 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all s ectors selected for erasing are protected, Data# Polling
on DQ7 is active for appro ximately 100 µs , t hen th e device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the
following
read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Table 9 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
DQ7 = Data?
Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
20637B-9
Figure 4. Data# Polling Algorithm
Page 18
18 Am29F200A
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, se veral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
CC
.
If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 9 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whethe r an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are pro tected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a pro tected sector,
DQ6 toggles for approx imately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Tog gle Bit Timings figu re in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.
DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 9 to compare outputs
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows t he differences between DQ2 and DQ6 in graphical f orm.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle
bit after th e fi rs t r ead . After the s ec on d read, the sy stem would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have s topped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and
Page 19
Am29F200A 19
PRELIMINARY
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, determining the status as described in the previous paragraph. Alterna tively, it may choose to perfor m other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the oper ation, and when th e operati on has
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to det ermine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selec ted for er asure, th e entire timeout also applies after each add itional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guar antee t hat the time betw een additional sector erase commands will always be less
than 50 µs. See also the “Sec tor Erase Command Sequence” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Su spend)
are ignored u ntil the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should ch eck the s tatus
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been accepted. Table 9 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
20637B-10
Figure 5. Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
Page 20
20 Am29F200A
PRELIMINARY
Table 9. Write Operation Status
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Operation
DQ7
(Note 1) DQ6
DQ5
(Note 2) DQ3
DQ2
(Note 1) RY/BY#
Standard
Mode
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector
1 No toggle 0 N/A Toggle 1
Reading within Non-Erase
Suspended Sector
Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Page 21
Am29F200A 21
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
V
CC
(Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot V
SS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pin s is V
CC
+0.5 V.
During voltage transitions, input or I/O pins may overshoot
to V
CC
+2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
SS
to –2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.
3. No more than on e output may be shor te d to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Abs olute Maximum Ratings” may cause perm anent d amage to the de vice. This is a
stress rating only; funct iona l ope rat ion of the de vic e at the se
or any other conditions ab ove those indicated in the ope rational sections o f this dat a sheet is not im plied. Exp osure of
the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 6. Maximum Negative Overshoot
Waveform
Figure 7. Maximum Posi tive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (T
A
) . . . . . . . . –55°C to +125°C
V
CC
Supply Voltages
VCC for ± 5% devices. . . . . . . . . . .+4.75 V to +5.25 V
V
CC
for± 10% de vices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20637B-11
20 ns
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
20637B-12
Page 22
22 Am29F200A
PRELIMINARY
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. The I
CC
current is typically less than 2 mA/MHz, with OE# at VIH.
2. I
CC
active while Embedded Program or Erase Algorithm is in progress.
3. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Min M ax Unit
I
LI
Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
I
LIT
A9, OE#, RESET# Input Load
Current
VCC = VCC Max,
A9, OE
#, RESET# = 12.5 V
50 µA
I
LO
Output Leakage Current V
OUT
= VSS to VCC, VCC = VCC Max ±1.0 µA
I
CC1
VCC Active Read Current (Note 1) CE# = VIL, OE# = V
IH
Byte 40
mA
Word 50
I
CC2
VCC Active Program/Erase Current
(Notes 2, 3)
CE
# = V
IL
, OE# = V
IH
60 mA
I
CC3
VCC Standby Current VCC = VCC Max, CE# = VIH, OE# = V
IH
1.0 mA
V
IL
Input Low Voltage –0.5 0.8 V
V
IH
Input High Voltage 2.0 VCC + 0.5 V
V
ID
Voltage for Autoselect and
Temporary Sector Unprotect
V
CC
= 5.0 V 11.5 12.5 V
V
OL
Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
V
OH
Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
V
LKO
Low VCC Lock-Out Voltage 3.2 4.2 V
Page 23
Am29F200A 23
PRELIMINARY
DC CHARACTERISTICS (continued)
CMOS Compatible
Notes:
1. The I
CC
current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. I
CC
active while Embedded Program or Erase Algorithm is in progress.
3. Not 100% tested.
4. I
CC3
for extended temperature is 20 µA max.
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
I
LI
Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
I
LIT
A9, OE#, RESET# Input
Load Current
VCC = VCC Max;
A9, OE
#, RESET# = 12.5 V
50 µA
I
LO
Output Leakage Current V
OUT
= VSS to VCC, VCC = VCC Max ±1.0 µA
I
CC1
VCC Active Read Current
(Note 1)
CE# = VIL, OE# = V
IH
Byte 20 40
mA
Word 28 50
I
CC2
VCC Active Program/Erase
Current (Notes 2, 3)
CE
# = V
IL
, OE# = V
IH
30 50 mA
I
CC3
VCC Standby Current
Note (Note 4)
VCC = VCC Max,
CE
# = V
CC
± 0.5 V, OE# = V
IH
15µA
V
IL
Input Low Voltage –0.5 0.8 V
V
IH
Input High Voltage 0.7 x V
CC
VCC + 0.3 V
V
ID
Voltage for Autoselect and
Temporary Sector Unprotect
V
CC
= 5.0 V 11.5 12.5 V
V
OL
Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
V
OH1
Output Low Voltage
IOH = –2.5 mA, VCC = VCC Min 0.85 V
CC
V
V
OH2
IOH = –100 µA, VCC = VCC Min VCC – 0.4 V
V
LKO
Low VCC Lock-Out Voltage 3.2 4.2 V
Page 24
24 Am29F200A
PRELIMINARY
TEST CONDITIONS
Table 6. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
C
L
6.2 kΩ
5.0
Device
Under
Test
20637B-13
Figure 8. Test Setup
Note:
Diodes are IN3064 or equivalents.
Test Condition -55
All
others Unit
Output Load 1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30 100 pF
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels
1.5 0.8, 2.0 V
Output timing measurement
reference levels
1.5 0.8, 2.0 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
Page 25
Am29F200A 25
PRELIMINARY
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 6 for test specifications
Figure 9. Read Operations Timings
Parameter
Description
Speed Option
JEDEC Std Test Setup -55 -70 -90 -120 -150 Unit
t
AVAV
t
RC
Read Cycle Time (Note 1) Min 55 70 90 120 150 ns
t
AVQVtACC
Address to Output Delay
CE# = V
IL
OE# = V
IL
Max 55 70 90 120 150 ns
t
ELQV
t
CE
Chip Enable to Output Delay OE# = V
IL
Max 55 70 90 120 150 ns
t
GLQV
t
OE
Output Enable to Output Delay
(Note 1)
Max 30 3 0 35 50 55 ns
t
EHQZ
t
DF
Chip Enable to Output High Z
(Note 1)
Max 20 2 0 20 30 35 ns
t
GHQZ
t
DF
Output Enable to Output High Z
(Note 1)
Max 20 2 0 20 30 35 ns
t
OEH
Output Enable
Hold Time
(Note 1)
Read Min 0 ns
Toggle and
Data# Polling
Min 10 ns
t
AXQX
t
OH
Output Hold Time From Addresses,
CE# or OE#, Whichever Occurs
First (Note 1)
Min 0 ns
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
OE
0 V
RY/BY#
RESET#
t
DF
t
OH
Page 26
26 Am29F200A
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
t
READY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max 20 µs
t
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max 500 ns
t
RP
RESET# Pulse Width Min 500 ns
t
RH
RESET# High Time Before Read (See Note) Min 50 ns
t
RB
RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#, OE#
t
RH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
20637B-14
Figure 10. RESET# Timings
Page 27
Am29F200A 27
PRELIMINARY
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
-55 -70 -90 -120 -150JEDEC Std. Description Unit
t
ELFL/tELFH
CE# to BYTE# Switching Low or High Max 5 ns
t
FLQZ
BYTE# Switching Low to Output HIGH Z Max 20 20 20 30 35 ns
t
FHQV
BYTE# Switching High to Output Active Max 55 70 90 120 150 ns
DQ15
Output
Data Output
(DQ0–DQ7)
CE#
OE#
BYTE#
t
ELFL
DQ0–DQ14
Data Output
(DQ0–DQ14)
DQ15/A-1
Address
Input
t
FLQZ
BYTE#
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
BYTE#
t
ELFH
DQ0–DQ14
Data Output
(DQ0–DQ14)
DQ15/A-1
Address
Input
t
FHQV
BYTE#
Switching
from byte
to word
mode
20637B-15
Figure 11. BYTE# Timings for Read Operations
Note:
Refer to the Erase/Program Operations table for t
AS
and tAH specifications.
20637B-16
Figure 12. BYTE# Timings for Write Operations
CE#
WE#
BYTE#
The falling edge of the last WE# signal
t
HOLD
(tAH)
t
SET
(tAS)
Page 28
28 Am29F200A
PRELIMINARY
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
-55 -70 -90 -120 -150JEDEC Std. Description Unit
t
AVAV
t
WC
Write Cycle Time (Note 1) Min 55 70 90 120 150 ns
t
AVWL
t
AS
Address Setup Time Min 0 ns
t
WLAX
t
AH
Address Hold Time Min 45 45 45 50 50 ns
t
DVWH
t
DS
Data Setup Time Min 25 30 45 50 50 ns
t
WHDX
t
DH
Data Hold Time Min 0 ns
t
OES
Output Enable Setup Time Min 0 ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min 0 ns
t
ELWL
t
CS
CE# Setup Time Min 0 ns
t
WHEH
t
CH
CE# Hold Time Min 0 ns
t
WLWH
t
WP
Write Pulse Width Min 30 35 45 50 50 ns
t
WHWL
t
WPH
Write Pulse Width High Min 20 ns
t
WHWH1tWHWH1
Programming Operation (Note 2)
Byte Typ 7
µs
Word Typ 14
t
WHWH2tWHWH2
Sector Erase Operation (Note 2) Typ 1 sec
t
VCS
VCC Setup Time (Note 1) Min 50 µs
t
RB
Recovery Time from RY/BY# Min 0 ns
t
BUSY
Program/Erase Valid to RY/BY# Delay Min 30 30 35 50 55 ns
Page 29
Am29F200A 29
PRELIMINARY
AC CHARACTERISTICS
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA PA
Read Status Data (last two cycles)
A0h
t
GHWL
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
Notes:
1. PA = program address, PD = program data, D
OUT
is the true data at the program address.
2. Illustration shows device in word mode.
20637B-17
Figure 13. Program Operation Timing s
Page 30
30 Am29F200A
PRELIMINARY
AC CHARACTERISTICS
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh SA
t
GHWL
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
t
RB
t
BUSY
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
20637B-18
Figure 14. Chip/Sector Erase Operation Timings
Page 31
Am29F200A 31
PRELIMINARY
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note:
20637B-19
Figure 15. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
RY/BY#
t
BUSY
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
t
ACC
t
RC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note:
20637B-20
Figure 16. Toggle Bit Timings (During Embedded Algorithms)
Page 32
32 Am29F200A
PRELIMINARY
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std. Description Unit
t
VIDR
VID Rise and Fall Time (See Note) Min 500 ns
t
RSP
RESET# Setup Time for Temporary Sector
Unprotect
Min 4 µs
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.
20637B-21
Figure 17. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
t
VIDR
12 V
0 or 5 V
CE#
WE#
RY/BY#
t
VIDR
t
RSP
Program or Erase Command Sequence
0 or 5 V
20637B-22
Figure 18. Tem pora ry Sector Unprotect Timi ng Diagram
Page 33
Am29F200A 33
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
-55 -70 -90 -120 -150JEDEC Std. Description Unit
t
AVAV
t
WC
Write Cycle Time (Note 1) Min 55 70 90 120 150 ns
t
AVEL
t
AS
Address Setup Time Min 0 ns
t
ELAX
t
AH
Address Hold Time Min 45 45 45 50 50 ns
t
DVEH
t
DS
Data Setup Time Min 25 30 45 50 50 ns
t
EHDX
t
DH
Data Hold Time Min 0 ns
t
OES
Output Enable Setup Time Min 0 ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min 0 ns
t
WLEL
t
WS
WE# Setup Time Min 0 ns
t
EHWH
t
WH
WE# Hold Time Min 0 ns
t
ELEH
t
CP
CE# Pulse Width Min 30 35 45 50 50 ns
t
EHEL
t
CPH
CE# Pulse Width High Min 20 ns
t
WHWH1
t
WHWH1
Programming Operation
(Note 2)
Byte Typ 7
µs
Word Typ 14
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2) Typ 1 sec
Page 34
34 Am29F200A
PRELIMINARY
AC CHARACTERISTICS
t
GHEL
t
WS
OE#
CE#
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7# D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
RY/BY#
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
t
BUSY
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D
OUT
= Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
20637B-23
Figure 19. Alternate CE# Controlled Write Operation Timings
Page 35
Am29F200A 35
PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 5.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V
CC
= 4.5 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Limits
CommentsTyp (Note 1) Max (Note 2) Unit
Sector Erase Time 1 8 sec
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time 7 56 sec
Byte Programming Time 7 300 µs
Excludes system-level overhead
(Note 5)
Word Programming Time 14 600 µs
Chip Programming Time (Note 3) 1.8 5.4 sec
Parameter Description Min Max
Input Voltage with respect to V
SS
on all I/O pins –1.0 V VCC + 1.0 V
V
CC
Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
C
IN
Input Capacitance VIN = 0 6 7.5 pF
C
OUT
Output Capacitance V
OUT
= 0 8.5 12 pF
C
IN2
Control Pin Capacitance VIN = 0 8 10 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time
150°C 10 Years
125°C 20 Years
Page 36
36 Am29F200A
PRELIMINARY
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package (measured in millimeters)
44
23
1
22
13.10
13.50
15.70
16.30
1.27 NOM.
28.00
28.40
2.17
2.45
0.35
0.50
0.10
0.35
2.80
MAX.
SEATING
PLANE
16-038-SO44-2
SO 044
DF83
8-8-96 lv
0.10
0.21
0.60
1.00
0°
8°
END VIEW
SIDE VIEW
TOP VIEW
Page 37
Am29F200A 37
PRELIMINARY
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)
48
25
1
24
18.30
18.50
19.80
20.20
11.90
12.10
0.05
0.15
0.50 BSC
0.95
1.05
16-038-TS48-2
TS 048
DT95
8-8-96 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0.25MM (0.0098") BSC
0°
5°
0.08
0.20
Page 38
38 Am29F200A
PRELIMINARY
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)
48
25
1
24
18.30
18.50
19.80
20.20
11.90
12.10
SEATING PLANE
0.05
0.15
0.50 BSC
0.95
1.05
16-038-TS48
TSR048
DT95
8-8-96 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0.25MM (0.0098") BSC
0°
5°
0.08
0.20
Page 39
Am29F200A 39
PRELIMINARY
REVISION SUMMARY
Revision B
Global: Made formatting and layout consistent with
other data sheets. Used updated common tables and
diagrams
Revision B+1
Minor formatting changes only.
Revision B+2
Connection Diagrams
Swapped standard and reversed TSOP drawings in
online version (data book version is correct).
Revision B+3
DC Characteristics, CMOS Compatible
Corrected the I
CC3
CE# test condition to VCC±0.5 V.
AC Characteristics
Read-Only Operations:
Corrected parameter descrip-
tions to match parameters.
Erase/Program Operations; Altern ate CE# Controlled
Erase/Program Operations:
Corrected the notes refer-
ence for t
WHWH1
and t
WHWH2
. These parameters are
100% tested. Corrected the note reference for t
VCS
.
This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for t
VIDR
. This parameter is not
100% tested.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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