Datasheet AM29F017B-90FIB, AM29F017B-90FI, AM29F017B-90FEB, AM29F017B-90FE, AM29F017B-90FCB Datasheet (AMD Advanced Micro Devices)

PRELIMINARY

Am29F017B

16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Optimized for memory card applications

— Backwards-compatible with the Am29F016C

■ 5.0 V ± 10%, single power supply operation

— Minimizes system level power requirements

■ Manufactured on 0.35 µm process technology

■ High performance

— Access times as fast as 70 ns

■ Low power consumption

— 25 mA typical active read current
— 30 mA typical program/erase current
—1 µA typical standby current (standard access

time to active mode)

■ Flexible sector architecture

— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:

A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group

Temporary Sector Group Unprotect allows code
changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Minimum 1,000,000 progr am/erase cycles per

sector guaranteed

■ Package options

— 48-pin TSOP

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase cycle completion

■ Ready/Busy# output (RY/BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase oper ation to read da ta

from, or program data to, a non-erasing sector,
then resumes the erase operation

■ Hardware reset p in (RESET#)

— Resets internal state machine to the read mode

Publication# 21195 Rev: B Amendment/+2
Issue Date: April 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29F017B is a 16 Mbit, 5.0 v olt-only Flash mem­ory organized as 2,097,152 bytes. The 8 bits of data

appear on DQ0–DQ7. The Am29F017B is offered in a
48-pin TSOP package. This d evice is designed to be
programmed in-system with the standard system 5.0
volt V
gram or erase operations. The device can also be pro­grammed in standard EPROM programmers.

This device is manufactured using AMD’s 0.35

process technology, and offers all the f eatures and ben­efits of the Am29F016C, which was manufactured
using 0.5

The standard device of fers access t imes of 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to
operate without wait states. To elim inate bus conten ­tion, the device has separate c hip enable (CE#), write
enable (WE#), and output enable (OE#) controls.

The device requires only a si ngle 5.0 volt power sup-
ply for both read and w rite functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set c ompatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con­trols the erase and programming circuitry. Write cycles
also internally latch addresses and data n eeded f o r the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an inter nal algorithm that automatically
preprograms the array (if it is not already progr ammed)

supply. A 12.0 volt VPP is not required for pro-

CC

µm process technology.

µm

before e xecutin g the erase operatio n. During erase, t he
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by obser ving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the de vice is ready to read array data
or accept another command.

The sector erase ar chitecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any com bination of the sectors of mem­ory. This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achie ved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin ma y be t ied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost
effectiveness. The device electrically erases all
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.

2 Am29F017B

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29F017B
Speed Options (V
Max Access Time (ns) 70 90 120 150
CE# Access (ns) 70 90 120 150
OE# Access (ns) 40 40 50 75

= 5.0 V ± 10% -70 -90 -120 -150

CC

Note: See the AC Characteristics section for more information.

BLOCK DIAGRAM

–

DQ7

DQ0

V

CC

V

SS

RY/BY#

RESET#

WE#

CE#
OE#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Input/Output

Buffers

Data

Latch

A0–A20

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21195B-1

Am29F017B 3

CONNECTION DIAGRAMS

PRELIMINARY

NC

NC
A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

NC

RESET#

A11
A10

A9
A8
A7
A6
A5

A4
NC
NC

NC
NC

A20

NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0

A0
A1
A2

A3
NC
NC

1
2

3
4
5
6
7
8
9

10
11
12

CC

13
14
15
16
17
18
19
20
21
22

48-Pin Standard TSOP

23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
NC

21195B-2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

48-Pin Reverse TSOP

23

24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NC
NC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC

21195B-3

4 Am29F017B

PRELIMINARY

PIN CONFIGURATION

A0–A20 = 21 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
VCC = +5.0 V single power supply

(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)

V

SS

NC = Pin Not Connected Internally

= Device Ground

LOGIC SYMBOL

21

A0–A20

CE#
OE#

WE#
RESET# RY/BY#

8

DQ0–DQ7

21195B-4

Am29F017B 5

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Am29F017B -70 E I

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40 °C to +85 °C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Am29F017B-70
Am29F017B-90
Am29F017B-120
Am29F017B-150

DEVICE NUMBER/DE SCR IP TIO N

Am29F017B
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sec tor Erase Fla sh Mem or y

5.0 V Read, Program, and Erase

Valid Combinations

EC, EI, EE, FC, FI, FE

Valid Combinations

Valid Combinations list configurations planned to be support­ed in volume for this device. Cons ult the loc al AM D sale s of­fice to confirm availab ility of specific valid com binations and
to check on newly released combinations.

6 Am29F017B

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29F017B Device Bus Operations

Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.

Read L L H H A
Write L H L H A
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z

TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect

(See Note)

Legend:

L = Logic Low = V

Note:

See the sections on Sector Protection and Temporary Sector Unprotect for more information.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D

IL

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re­main at V

.

IH

The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that as­sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enable d for read access until the
command register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

in the DC Characteristics

CC1

table represents the active current specification for
reading array data.

. CE# is the power

IL

XXX V

ID

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

An erase operation can erase one sect or, multiple sec­tors, or the entire de vice. The Sector Address Tabl es in­dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the en­tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

I

CC2

tive current specification for the write mode. The “AC
Characteristics” section contains timing specification

, and OE# to VIH.

IL

in the DC Characteristics table represents the ac-

OUT

IN

IN

A

IN

= Data Out, AIN = Address In

D

OUT

D

D

IN

IN

tables and timing diagrams for write operations.

Am29F017B 7

PRELIMINARY

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more infor mation, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standb y mode when CE#
and RESET# pins are both held at V
that this is a more restrict ed voltage range than V

± 0.5 V. (Note

CC

IH

The device enters the TTL standby mode when CE#
and RESET# pins are both held at V

. The device re-

IH

quires standard access time (tCE) for read access when
the device is in either of these standb y modes, bef ore it
is ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, “RE­SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program ­ming, the device draws active current until the
operation is completed.

In the DC Charac teristics tables, I

represents the

CC3

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to readi ng arr ay data. When the system

drives the RESET# pin low for at least a period of t
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

, the device enters

IL

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

.)

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operatio n is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V

(not during Embe dded Algo-

READY

.

IH

RH

Refer to the AC Characteristics tables for RESET# pa­rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

RP

SS

after the RE-

,

±

8 Am29F017B

PRELIMINARY

Table 2. Sector Address Table

Sector A20 A19 A18 A17 A16 Address Range

SA0 0 0 0 0 0 000000h-00FFFFh
SA1 0 0 0 0 1 010000h-01FFFFh
SA2 0 0 0 1 0 020000h-02FFFFh
SA3 0 0 0 1 1 030000h-03FFFFh
SA4 0 0 1 0 0 040000h-04FFFFh
SA5 0 0 1 0 1 050000h-05FFFFh
SA6 0 0 1 1 0 060000h-06FFFFh
SA7 0 0 1 1 1 070000h-07FFFFh
SA8 0 1 0 0 0 080000h-08FFFFh

SA9 0 1 0 0 1 090000h-09FFFFh
SA10 0 1 0 1 0 0A0000h-0AFFFFh
SA11 0 1 0 1 1 0B0000h-0BFFFFh
SA12 0 1 1 0 0 0C0000h-0CFFFFh
SA13 0 1 1 0 1 0D0000h-0DFFFFh
SA14 0 1 1 1 0 0E0000h-0EFFFFh
SA15 0 1 1 1 1 0F0000h-0FFFFFh
SA16 1 0 0 0 0 100000h-10FFFFh
SA17 1 0 0 0 1 110000h-11FFFFh
SA18 1 0 0 1 0 120000h-12FFFFh
SA19 1 0 0 1 1 130000h-13FFFFh
SA20 1 0 1 0 0 140000h-14FFFFh
SA21 1 0 1 0 1 150000h-15FFFFh
SA22 1 0 1 1 0 160000h-16FFFFh
SA23 1 0 1 1 1 170000h-17FFFFh
SA24 1 1 0 0 0 180000h-18FFFFh
SA25 1 1 0 0 1 190000h-19FFFFh
SA26 1 1 0 1 0 1A0000h-1AFFFFh
SA27 1 1 0 1 1 1B0000h-1BFFFFh
SA28 1 1 1 0 0 1C0000h-1CFFFFh
SA29 1 1 1 0 1 1D0000h-1DFFFFh
SA30 1 1 1 1 0 1E0000h-1EFFFFh
SA31 1 1 1 1 1 1F0000h-1FFFFFh

Note: All sectors are 64 Kbytes in size.

Am29F017B 9

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin

ID

A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. I n addi­tion, when verifying sector protection, the sector ad-

Table 3. Am29F017B Autoselect Codes (High Voltage Method)

Description CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 DQ7-DQ0

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad­dress Tables. The Comm and Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the C ommand Defini­tions table. This method does not require V
“Command Definitions” for details on using the autose­lect mode.

. See

ID

Manufacturer ID:
AMD

Device ID:
Am29F017B

Sector Group
Protection
Ve r ific atio n

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

LLH X X V

LLH X X VIDXVILXVILV

Sector

LLH

Group

Address

XVIDXVILXVIHV

Sector Group Protection/Unprotection

The hardware sector group protection feature dis­ables both program and erase operations in any sec­tor. Each sector group consists o f four ad jacent
sectors. Table 4 shows how the sectors are goruped,
and the address range that each sector group con­tains. The hardware sector group unprotection fea­ture re-enables both program and erase operations in
previously protected sectors.

Sector group protection/unprotection must be imple­mented using programming equipment. The procedure
requires a high voltage (V
control pins. Details on this method are provided in a
supplement, publication number 21544. Contact an
AMD representative to obtain a cop y of the appropriate
document.

The device is shipped with all sector grou ps unpro­tected. AMD offers t he optio n of prog r amming a nd pro­tecting sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector group is
protected or unprotected. See
details.

) on address pin A9 and the

ID

“Autoselect Mode” for

XVILXVILV

ID

Table 4. Sector Group Addresses

Sector
Group A20 A19 A18 Sectors

SGA0 0 0 0 SA0
SGA1 0 0 1 SA4
SGA2 0 1 0 SA8
SGA3 0 1 1 SA12
SGA4 1 0 0 SA16
SGA5 1 0 1 SA20
SGA6 1 1 0 SA24
SGA7 1 1 1 SA28

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ­ously protected sector s groups t o change dat a in-sys­tem. The Sector Group Unprotect mode is activated
by setting the RESET# pin to V
formerly protected sector g roups can be programmed
or erased by selecting the sector group addresses.
Once V
previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector/Sector Group Unprotect dia-

is removed from the RESET# pin, all the

ID

gram shows the timing waveforms, for this feature.

IL

IH

IL

01h

3Dh

01h (protected)

00h (unprotected)

–
–

–

–
–
–
–
–

. During this mode,

ID

SA3
SA7

SA11

SA15
SA19
SA23
SA27
SA31

10 Am29F017B

PRELIMINARY

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector Group

Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected
once again.

ID

IH

21195B-5

Figure 1. Temporary Sector Group Unprotect

Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi­nitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or pro­gramming, which might otherwise be caused by spuri­ous system level signals during V
power-down transitions, or from system noise.

Low V

When V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

power-up and

CC

.

LKO

CC

CC

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

Am29F017B 11

PRELIMINARY

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect

address and data values or writing them in the im-
proper sequence resets the device to reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend m ode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same ex ception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.

must

The system
able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Read Operation Tim ings diagram shows the
timing diagram.

issue the reset command to re-en-

Reset Command

Writing the reset command to the devi ce resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

must

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes ,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is in tended for PROM program­mers and requires V

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Ad dr e ss ta bles for valid sector addres s es.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

on address bit A9.

ID

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-up
command. The program address and data are wr itten
next, which in turn initiate the Embedded Program al-

not

gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and v erify the pro­grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation b y using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in­formation on these status bits.

required to provide further

12 Am29F017B

PRELIMINARY

Any commands written to the device dur ing the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program­ming operation. The program command sequenc e
should be reinitiated once the de vi ce has reset t o read­ing array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

START

Write Program

Command Sequence

preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. The Command
Definitions table show s the address and data require­ments for the chip erase command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a ha rd ware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.

The system can deter mine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no long er latched.

Figure 3 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for p arameters , and to the Chip/Sector
Erase Operation Timings for t i ming waveforms.

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See the appropriate Command Definitions table for
program command sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

No

21195B-6

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does

require the system to

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command . The Command Definitions table
shows the address and data requirement s for the sec­tor erase command sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sector s. The time be­tween these additional cycl es must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

require the system to preprogram

Am29F017B 13

PRELIMINARY

time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .

Once the sector erase operation has begun, onl y the
Erase Suspend command is valid. All other commands
are ignored. Note th at a hardware reset during the
sector erase operation immediately ter m inates the op­eration. The Sector Erase command sequence s hould
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addresses are
no longer latched. The system can determine the sta­tus of the erase operation b y usi ng DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa­tion on these status bits.

Figure 3 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section f or par amet ers , and to
the Sector Erase Operations Ti ming diagr am for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the s yst em to in­terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only dur ing the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend comm and is ignored if written dur ing
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately ter minates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasu re. (The de vice “er ase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “Write Operation Status” for more informa­tion.

The system may also write the autos elect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

14 Am29F017B

START

Write Erase

Command Sequence

Data Poll

from System

No

Data = FFh?

Erasure Completed

PRELIMINARY

Embedded
Erase
algorithm
in progress

Yes

21195B-7

Notes:

1. See the appropriate Command Definitions table for erase
command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

Am29F017B 15

PRELIMINARY

Table 5. Am29F017B Command Definitions

Bus Cycles (Notes 2–4)

Command
Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Manufacturer ID 4 XXX AA XXX 55 XXX 90 X00 01

Autoselect

(Note 7)

Program 4 XXX AA XXX 55 XXX A0 PA PD
Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 XXX 10
Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30

Device ID 4 XXX AA XXX 55 XXX 90 X01 3D

Sector Group Protect
Verify (Note 8)

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Cycles

XXX

4

XXX XXX XXX XX01

AA

XXX

55

XXX

90

SGA

X02

XX00

PD = Data to be programmed at location PA. Data latches on
the rising edge of WE# or CE# pulse, whichever happens
first.

SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A20–A16 select a unique sector.

SGA = Address of the sector group to be verified. Address
bits A20–A18 select a unique sec tor group.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus
cycles are write operations.

4. Address bits A20–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading
array data.

6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is
a read cycle.

8. The data is 00h for an unprotected sector group and 01h
for a protected sector group. See “Autoselect Command
Sequence” for more information.

9. The system may read and program in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.

10. The Erase Resume command is valid only during the
Erase Suspend mode.

16 Am29F017B

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Tab le 6 and the f ollo wing subsecti ons de­scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for deter mining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, in dicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# P olling is v alid after the rising
edge of the final WE# pulse in the program or erase
command sequence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 2 µs, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algor ithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

No

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll­ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.

Am29F017B 17

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21195B-8

Figure 4. Data# Polling Algorithm

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia­grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.

CC

.

DQ6: Toggle Bit I

Toggle Bit I on D Q6 indicates whether a n Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the s ector erase time-out.

The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure show s the differences be­tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for era­sure. (The system may use either OE# or CE# to con­trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for s ector and
mode information. Refer to Tabl e 6 to compare o utputs
for DQ2 and DQ6.

During an Embedded Program or Erase algorithm op­eration, successive read cyc les to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog­gles for appro xi mately 100 µ s , t hen returns to read ing

array data. If not all selected sectors are pro tected,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), D Q6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a pro tected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows t he dif­ferences between DQ2 and DQ6 in graphical f orm.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the follow ing discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typica lly, a
system would note a nd store th e val ue of the to ggle bit
after the first read. After the second read, the system
would compare the ne w v alue of the toggle bit with the
first. If the toggle bit is not to ggling, the device has
completed the program or erase operation. The sys­tem can read arra y data on DQ7–DQ0 on the f ollo wing
read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and

18 Am29F017B

PRELIMINARY

the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perform o ther
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s previously pro­grammed to “0.” Only an era se operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 6 shows the outputs for DQ3.

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

(Note 1)

No

Under both these conditions, t he system must issue the
reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to det ermine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selec ted for er asure, th e entire time­out also applies after each add itional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guar antee t hat the time betw een ad­ditional sector erase commands will always be less
than 50 µs. Se e also th e “S ector Er ase Command Se­quence” section.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Su spend)
are ignored u ntil the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should ch eck the s tatus
of DQ3 prior to and following each subsequent s ector

No

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

(Notes
1, 2)

No

Program/Erase

Operation Complete

21195B-9

Figure 5. Toggle Bit Algorithm

Am29F017B 19

PRELIMINARY

Table 6. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 1) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

DQ5

(Note 2) DQ3

DQ2

(Note 1) RY/BY#

20 Am29F017B

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

V

CC

A9, OE#, RESET# (Note 2). . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, inputs may overshoot V
for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on output and I/O pins is V
voltage transitions, outputs may overshoot to V
for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V . During voltage transitions, A9, OE#, RESET# pins
may overshoot V
See Figure 6. Maximum DC input voltage on A9, OE#,
and RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.

3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.

to –2.0 V for periods of up to 20 ns.

SS

+ 0.5 V. During

CC

to –2.0 V

SS

+ 2.0 V

CC

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

Figure 6. Maximum Negative Overshoot

Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

21195B-10

Stresses greater than those listed in this section may cause
permanent da mage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections
of this specification is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods
may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Case Temperature (TC) . . . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Case Temperature (T

Extended (E) Devices

Ambient Temperature (T

Supply Voltages

V

CC

VCC for± all devices . . . . . . . . . . . . . .+4.5 V to +5.5 V

Operating rang es define those limits between which the
functionality of the device is guaranteed.

) . . . . . . . . . . . –40°C to +85°C

C

) . . . . . . . . –55°C to +125°C

A

21195B-11

Figure 7. Maximum Positive Overshoot

Waveform

Am29F017B 21

PRELIMINARY

DC CHARACTERISTICS
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

I
I

I

CC1

I

CC2

I

CC3

I

CC4

V

V
V
V

V

V

I

LI

LIT

LO

OL
OH

LKO

Input Load Current VIN = V

A9 Input Load Current V
Output Leakage Current V

CC
OUT

VCC Read Current (Note 1) CE# = V
VCC Write Current (Notes 2, 3) CE# = V
V

Standby Current

CC

(CE# Controlled)
V

Standby Current

CC

(RESET# Controlled)
Input Low Level –0.5 0.8 V

IL

Input High Level 2.0 V

IH

Voltage for Autoselect and Sector

ID

Protect

VCC = VCC Max, CE# = VIH,
RESET#

V

CC

V

CC

Output Low Voltage IOL = 12 mA, V
Output High Level IOH = –2.5 mA V

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

to VCC, V

SS

OE# = V

IL,

OE# = V

IL,

= VIH

= V

Max, RESET# = V

CC

= VCC Max ±1.0 µA

CC

= VCC Max ±1.0 µA

CC

IH

IH

25 40 mA
40 60 mA

0.4 1.0 mA

IL

0.4 1.0 mA

= 5.0 V 11.5 12.5 V

= V

CC

CC

Min 0.45 V

CC

= V

Min 2.4 V

CC

Low VCC Lock-out Voltage 3.2 4.2 V

+ 0.5 V

CC

CMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

I

LI

I

LIT

I

LO

I

CC1

I

CC2

I

CC3

I

CC4

V

V
V
V

OL

V

OH1

V

OH2

V

LKO

Notes for DC Characteristics (both tables):

1. The I

2. I

CC

3. Not 100% tested.

Input Load Current VIN = V
A9 Input Load Current V
Output Leakage Current V
V

Read Current (Note 1) CE# = V

CC

V

Write Current (Notes 2, 3) CE# = V

CC

V

Standby Current

CC

(CE# Controlled)
V

Standby Current

CC

(RESET# Controlled)
Input Low Level –0.5 0.8 V

IL

Input High Level 0.7x V

IH

Voltage for Autoselect

ID

and Sector Protect

CC
OUT

V

CC = VCC

RESET# = V
V

CC

RESET# = V

V

CC

Output Low Voltage IOL = 12 mA, V

I

Output High Voltage

Low V

current is typically less than 1 mA/MHz, with OE# at VIH.

CC

Lock-out Voltage 3.2 4.2 V

CC

OH

IOH = –100 µA, V

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

to VCC, V

SS

OE# = V

IL,

OE# = V

IL,

Max, CE# = V

CC

= V

Max,

CC

SS

CC

IH
IH

± 0.5 V

± 0.5 V

= V

Max ±1.0 µA

CC

= V

CC

Max ±1.0 µA

CC

25 40 mA
30 40 mA

± 0.5 V,

CC

15µA

15µA

CC

= 5.0 V 11.5 12.5 V

= V

CC

= –2.5 mA, V

Min 0.45 V

CC

= V

CC
CC

Min 0.85 V

CC

= V

Min VCC – 0.4 V

CC

CC

active while Embedded Program or Embedded Erase algorithm is in progress.

V

CC

+ 0.3 V

V

22 Am29F017B

TEST CONDITIONS

Device

Under

Test

C

L

6.2 kΩ

PRELIMINARY

5.0 V

2.7 kΩ
Output Load 1 TTL gate

Output Load Capacitance, C
(including jig capacitance)

Input Rise and Fall Times 20 ns
Input Pulse Levels 0.45–2.4 V

Table 7. Test Specifications

All speed

Test Condition

L

options Unit

100 pF

Note: Diodes are IN3064 or equivalent

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

21195B-12

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

0.8 V

2.0 V

KS000010-PAL

Am29F017B 23

AC CHARACTERISTICS
Read-only Operations

PRELIMINARY

Parameter Symbol

Parameter Description

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

t

ACC

t
t

Read Cycle Time (Note 1) Min 70 90 120 150 ns

RC

Address to Output Delay

Chip Enable to Output Delay OE# = VILMax 70 90 120 150 ns

CE

Output Enable to Output Delay Max 40 40 50 55 ns

OE

Read Min0000ns

t

OEH

Output Enable Hold
Time (Note 1)

Toggle and
Data# Polling

t

EHQZ

t

GHQZ

t

AXQX

t
t

t

OH

t

Ready

Chip Enable to Output High Z (Note 1) Max 20 20 30 35 ns

DF

Output Enable to Output High Z (Note 1) Max 20 20 30 35 ns

DF

Output Hold Time From Addresses CE#
or OE# Whichever Occurs First

RESET# Pin Low to Read Mode
(Note 1)

Notes:

1. Not 100% tested.

2. Refer to Figure 1 and Table 6 for test specifications.

CE# = V
OE# = V

Test

Setup

Speed Options

UnitJEDEC Standard -70 -90 -120 -150

IL

Max 70 90 120 150 ns

IL

Min10101010ns

Min0000ns

Max20202020µs

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

t

RC

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 9. Read Operation Ti mi ng s

t

OH

t

DF

HIGH Z

21195B-13

24 Am29F017B

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

PRELIMINARY

t

READY

t

READY

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pulse Width Min 500 ns

t

RP

RESET# High Time Before Read (See Note) Min 50 ns

t

RH

RY/BY# Recovery Time Min 0 ns

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t

RP

t

Ready

Max 20 µs

Max 500 ns

t

RH

RY/BY#

CE#, OE#

RESET#

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 10. RESET# Timings

t

RB

21195B-14

Am29F017B 25

AC CHARACTERISTICS
Erase/Program Operations

PRELIMINARY

Parameter

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

CS

t

CH

t

WP

t

WPH

Speed Options

Parameter Description

UnitJEDEC Std -70 -90 -120 -150

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 50 50 ns
Data Setup Time Min 40 45 50 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recover Time Before Write

(OE# high to WE# low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 40 45 50 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 7 µs

Typ 1 sec

Sector Erase Operation (Note 2)

Max 8 sec

t

VCS

t

BUSY

VCC Set Up Time (Note 1) Min 50 µs
WE# to RY/BY# Valid Min 40 40 50 60 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

26 Am29F017B

AC CHARACTERISTICS

PRELIMINARY

Program Command Sequence (last two cycles)

t

WC

Addresses

CE#

555h

t

GHWL

t

CH

OE#

t

WP

WE#

t

WPH

t

DH

Data

t

CS

t

DS

A0h

RY/BY#

t

VCS

V

CC

Note: PA = program address, PD = program data, D

Figure 11. Program Operation Timings

Read Status Data (last two cycles)

t

AS

PA PA

t

AH

t

PD

t

BUSY

is the true data at the program address.

OUT

PA

WHWH1

Status

D

OUT

t

RB

21195B-15

Am29F017B 27

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

PRELIMINARY

t

AS

555h for chip erase

Addresses

t

WC

2AAh SA

CE#

t

GHWL

t

t

WP

t

DS

55h

CH

t

WPH

t

DH

10 for Chip Erase

OE#

WE#

Data

t

CS

RY/BY#

t

VCS

V

CC

Note:

SA = Sector Address. VA = Valid Address for reading status data.

Figure 12. Chip/Sector Erase Operation Timings

VA

t

AH

t

WHWH2

30h

t

BUSY

In

Progress

VA

Complete

t

RB

21195B-16

28 Am29F017B

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

WE#

DQ7

OEH

t

ACC

PRELIMINARY

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note:

V A = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

21195B-17

Figure 13. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note:

V A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.

21195B-18

Figure 14. Toggle Bit Timings (During Embedded Algorithms)

Am29F017B 29

AC CHARACTERISTICS

PRELIMINARY

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Erase

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.

21195B-19

Figure 15. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std. Description Unit

t

t

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector

RSP

Unprotect

Min 4 µs

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

12 V

0 or 5 V

t

VIDR

Program or Erase Command Sequence

t

RSP

Figure 16. Temporary Sector Group Unprotect Timing Diagram

t

VIDR

0 or 5 V

21195B-20

30 Am29F017B

AC CHARACTERISTICS
Erase and Program Operations

Alternate CE# Controlled Writes

PRELIMINARY

Parameter Symbol

Parameter Description

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 50 50 ns
Data Setup Time Min 40 45 50 50 ns
Address Hold Time Min 0 ns
Read Recover Time Before Write Min 0 ns
CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 4 0 45 50 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 7 µs

Typ 1 sec

t

WHWH2

t

WHWH2

Sector Erase Operation (Note 2)

Max 8 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Speed Options

UnitJEDEC Standard -70 -90 -120 -150

Am29F017B 31

AC CHARACTERISTICS

PRELIMINARY

Addresses

WE#

OE#

CE#

Data

RESET#

XXX for program
XXX for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
XXX for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence.

Figure 17. Alternate CE# Controlled Write Operation Timings

= Array Data.

OUT

21195B-21

32 Am29F017B

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 sec
Chip Erase Time 32 256 sec
Byte Programming Time 7 300 µs

Chip Programming Time (Note 3) 14.4 43.2 sec

Excludes 00h programming prior to
erasure (Note 4)

Excludes system-level overhead
(Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further
information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTIC

Input Voltage with respect to V

Current –100 mA +100 mA

V

CC

on I/O pins –1.0 V VCC + 1.0 V

SS

S

Min Max

Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Input Capacitance VIN = 0 6 7.5 pF

IN

Output Capacitance V
Control Pin Capacitance VIN = 0 7.5 9 pF

= 0 8.5 12 pF

OUT

C

C

C

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

Am29F017B 33

PRELIMINARY

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

24

18.30

18.50

19.80

20.20

48

11.90

12.10

0.50 BSC

25

0.05

0.15

16-038-TS48-2
TS 048
DT95
8-8-96 lv

1.20

MAX

0.25MM (0.0098") BSC

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

24

18.30

18.50

19.80

20.20

48

11.90

12.10

0.50 BSC

25

0.05

0.15

SEATING PLANE

1.20

MAX

0.25MM (0.0098") BSC

34 Am29F017B

16-038-TS48

0.08

0.20

TSR048
DT95
8-8-96 lv

0.10

0°

0.21

5°

0.50

0.70

PRELIMINARY

REVISION SUMMARY FOR AM29F017B
Revision B

Global

Made formatting and layout consistent with other data
sheets. Used updated common tables and diagr ams.

The online version has slightly modified formatting.

Revision B+1

Reset Command

Deleted paragraph referring to RESET# waveforms.

AC Characteristics—Read-only Operations

Deleted note referring to output driver disable time.

Figure 16—Temporary Sector Group Unprotect Timings

Corrected title to indicate “sector group. ”

Revision B+2

Global

Added -70 speed option, deleted -75 speed option.

Distinctive Characteristics

Changed minimum 100K wr ite/erase cycles guaran­teed to 1,000,000.

DC Characteristics, CMOS Compatible

Corrected the CE# and RESET# test conditions for
I

CC3

and I

to VCC ±0.5 V.

CC4

AC Characteristics

Erase/Program Operations; Erase and Program Oper­ations Alternate CE# Controlled Writes:

notes reference f or t

WHWH1

and t

WHWH2

Corrected the

. These param-

eters are 100% tested. Corrected the note ref erence for

. This parameter is not 100% tested.

t

VCS

Temporary Sector Unprotect Table

Added note reference for t

. This parameter is not

VIDR

100% tested.

Erase and Programming Performance

Changed mini mum 100K program a nd erase cycles
guaranteed to 1,000,000.

Ordering Information

Added extended temperature availability.

Operating Ranges

Added extended temperature range.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29F017B 35