Datasheet AM28F256A-70PI, AM28F256A-70PEB, AM28F256A-70PE, AM28F256A-70PCB, AM28F256A-70PC Datasheet (AMD Advanced Micro Devices)

FINAL

Am28F256A

256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

DISTINCTIVE CHARACTERISTICS

■ High performance

— Access times as fast as 70 ns

■ CMOS low power consumption

— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption

■ Compatible with JEDEC-standard byte-wide

32-Pin EPROM pinouts

— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP

■ 100,000 write/erase cycles minimum

■ Write and erase voltage 12.0 V ±5%

■ Latch-up protected to 100 mA from –1 V to

+1 V

V

CC

■ Embedded Erase Electrical Bulk Chip-Erase

— 1.5 seconds typical chip-erase including

pre-programming

■ Embedded Program

— 14 µs typical byte-program including time-out
— 0.5 second typical chip program

■ Command register architecture fo r

microprocessor/microcontroller compatible
write interface

■ On-chip address and data latches

■ Advanced CMOS flash memory technology

— Low cost single transistor memory cell

■ Embedded

self-timed write/erase operations

algorithms fo r completely

GENERAL DESCRIPTION

The Am28F256A is a 256 K Flash memory organized
as 32 Kbytes of 8 bits each. AMD’s Flash memories
offer the most cost-effective and reliable read/write
non- volatile rand om access memory . The Am28F256A
is packaged in 32-pin PDIP, PLCC, and TSOP versions .
It is designed to be reprogrammed and erased in-sys­tem or in standard EPROM programmers. The
Am28F256A is erased when shipped from the factory.

The standard Am28F256A offers access times as fast
as 70 ns, allowing operation of high-spee d micropro­cessors without wait states. To eliminate bus conten­tion, the Am28F256A has separate chip enable (CE#)
and output enable (OE#) controls.

AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256A uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command registe r
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.

AMD’s Flash technology reliably stores me mory con­tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and

programming mechanisms. In addition, the combina­tion of advanced tunnel o xide processing and l ow inter­nal electric fields for erase and programming
operations produces reliable cycling. The Am28F256A
uses a 12.0V ± 5% V
the erase

The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro­tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to V

and programming functions.

high voltage i nput to perfor m

PP

+1 V.

CC

Embedded Program

The Am28F256A is byte programmable using the
Embedded Program ming algorithm. The Em bedded
Programming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F256A is one half second.

Embedded Erase

The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are

Erase algorithm

Publication# 18879 Rev: C Amendment/+2
Issue Date: May 1998

controlled internal to the device. Typical erasure at room
temperature is acco mplished in 1 .5 seconds, including
preprogramming.

Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms

AMD’s Am28F256A is entirely pin and software com­patible with AMD’s Am28F020A, Am28F256A and
Am28F512A Flash memories.

Embedded
Programming
Algorithm vs.
Flashrite
Programming
Algorithm

Embedded Erase
Algorithm vs.
Flasherase Erase
Algorithm

Am28F256A with

Embedded Algorithms

AMD’s Embedded Programming algorithm
requires the user to only write a program
set-up command and a program command
(program data and address). The device
automatically times the programming
pulse width, verifies the programming, and
counts the number of sequences. A status
bit, Data
the programming operation status.

AMD’s Embedded Erase algorithm
requires the user to only write an erase set­up command and erase command. The
device automatically pre-programs and
verifies the entire array. The device then
automatically times the erase pulse width,
verifies the erase operation, and counts
the number of sequences. A status bit,
Data
erase operation status.

# Polling, provides the user with

# Polling, provides the user with the

Am28F256 using AMD Flashrite

and Flasherase Algorith ms

The Flashrite Programming algorithm requires the
user to write a program set-up command, a program
command, (program data and address), and a
program verify command, followed by a read and
compare operation. The user is required to time the
programming pulse width in order to issue the
program verify command. An integrated stop timer
prevents any possibility of overprogramming.

Upon completion of this sequence, the data is read
back from the device and compared by the user with
the data intended to be written; if there is not a
match, the sequence is repeated until there is a
match or the sequence has been repeated 25 times.

The Flasherase Erase algorithm requires the device
to be completely programmed prior to executing an
erase command.

To invoke the erase operation, the user writes an
erase set-up command, an erase command, and an
erase verify command. The user is required to time
the erase pulse width in order to issue the erase
verify command. An integrated stop timer prevents
any possibility of overerasure.

Upon completion of this sequence, the data is read
back from the device and compared by the user with
erased data. If there is not a match, the sequence is
repeated until there is a match or the sequence has
been repeated 1,000 times.

Commands are written to the command register using
standard microprocessor write timings. Register con­tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
address and data needed for the programming and
erase operations. For system design simplification, the
Am28F256A is designed to support either WE# or CE#
controlled writes. During a system write cycle,
addresses are latched on the falling edge of WE# or
CE# whichever occurs last. Data is latched on the rising

the following discussion, the WE# pin is used as the
write cycle control pin throughout the rest of this text. All
setup and hold times are with respect to the WE# signal.

AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest lev els
of quality, reliability, and cost effectiveness. The
Am28F256A electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.

edge of WE# or CE# whichever occurs first. To simplify

2 Am28F256A

BLOCK DIAGRAM

V

CC

V

SS

V

PP

Erase

Voltage

Switch

DQ0–DQ7

Input/Output

Buffers

WE#

CE#
OE#

Low V
Detector

A0–A14

CC

State

Control

Command

Register

Embedded
Algorithms

Program/Erase

Pulse Timer

Program

Voltage

Switch

To Array

Address

Latch

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Data

Latch

Y-Gating

262,144

Bit

Cell Matrix

18879C-1

PRODUCT SELECTOR GUIDE

Family Part Number Am28F256A
Speed Options (V
Max Access Time (ns) 70 90 120 150 200

# (E#) Access (ns) 70 90 120 150 200

CE

# (G#) Access (ns) 35 35 50 55 55

OE

= 5.0 V ±10%) -70 -90 -120 -150 -200

CC

Am28F256A 3

CONNECTION DIAGRAMS

PDIP

PLCC

V

NC
NC

A12

DQ0
DQ1
DQ2

V

PP

A7
A6
A5

A4
A3
A2

A1
A0

SS

1
2
3
4
5

6
7

8
9
10
11
12

13
14
15
16

32
31
30
29
28

27
26

25
24
23
22

21
20

19
18
17

Note: Pin 1 is marked for orientation.

V

CC

WE# (W#)
NC
A14

A13
A8
A9
A11

(G#)

OE#
A10
CE# (E#)

DQ7
DQ6

DQ5
DQ4

DQ3

18879C-2

A7
A6
A5

A4
A3
A2
A1
A0

DQ0

5
6

7

8
9
10

11
12
13

14

A12

4

DQ1

15

NC

3

DQ2

PP

CC

NC

V

1

32

2

17

18

SS

V

DQ3

WE# (W#)

V

31 30

19 2016

DQ4

DQ5

NC

29
28
27

26
25
24
23
22
21

DQ6

A14
A13

A8

A9
A11
OE# (G#)

A10
CE# (E#)
DQ7

18879B-3

4 Am28F256A

CONNECTION DIAGRAMS (continued)

A11

A13
A14

V

V

A12

OE#

A10

CE#

D7
D6
D5
D4
D3

V

SS

D2
D1
D0

A0
A1
A2
A3

A9
A8

NC

WE

CC

PP

NC
NC

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-Pin — Standard Pinout

32-Pin — Reverse Pinout

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE#
A10
CE#
D7
D6
D5
D4
D3
V

SS

D2
D1
D0
A0
A1
A2
A3

A11
A9
A8
A13
A14
NC
WE#
V

CC

V

PP

NC
NC
A12
A7
A6
A5
A4

18879C-4

LOGIC SYMBOL

15

A0–A14

CE# (E#)
OE# (G#)

WE# (W#)

8

DQ0–DQ7

18879C-5

Am28F256A 5

ORDERING INFORMATION
Standard Products

AM28F256A -70 J C

DEVICE NUMBER/DES CR IPT IO N

Am28F256A
256 Kilobit (32 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms

B

OPTIONAL PROCESSING

Blank = Standard Pro ces sin g
B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

AM28F256A-70
AM28F256A-90
AM28F256A-120
AM28F256A-150
AM28F256A-200

Valid Combinations

PC, PI, PE,

EC, EI, EE,

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

JC, JI, JE,

FC, FI, FE

6 Am28F256A

PIN DESCRIPTION

A0–A14

Address Inputs for memory locations. Internal latches
hold addresses during write cycles.

CE# (E#)

Chip Enable active lo w input activates the chip’ s control
logic and input buffers. Chip Enable high will deselect
the device and operates the chip in stand-by mode.

DQ0-DQ7

Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.

NC

No Connect-corresponding pin is not connected
internally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the
device through the data buffers during memory read
cycles. Output Enable is high during command
sequencing and program/erase operations.

V

CC

Pow er supply f or de vice operat ion. (5.0 V ± 5% or 10%)

V

PP

Program voltage input. VPP must be at high voltage in
order to write to the command register. The command
register controls all functions required to alt er the mem­ory array contents. Memory contents cannot be a ltered
when V

V

SS

Ground.

PP

≤ V

CC

+2 V.

WE# (W)

Write Enable active low input controls the write function
of the command register to the memory array . The target
address is latche d on the falling edge of the Write En­able pulse and the appropriate data is latched on the ris­ing edge of the pulse. Write Enable high inhibits wr iting
to the device.

Am28F256A 7

BASIC PRINCIPLES

This section contains descriptions about the device
read, erase, and program operations, and write opera­tion status of the Am29FxxxA, 12.0 volt f amily of Flash
devices. References to some tables or figures may be

given in generic form, such as “Command Definitions
table”, rather than “ Table 1”. Refer to the corresponding
data sheet for the actual table or figure.

The Am28FxxxA family uses 100% TTL-level control
inputs to manage the comman d register. Erase and
reprogramming operations use a fixed 12.0 V ± 5%
high voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a
read only memory and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, out put disable, and Auto select modes.

Command Register

The command register is enabled only when high volt­age is applied to the V
gramming operations are only accessed via the
register. In addit i on, two-cycle commands are required
for erase and reprogramming operations. The tradi­tional read, standby, output disable, and Auto select
modes are available via the register.

The device’s command register is written using standard
microprocessor write timings. The register controls an
intern al state machi ne that manag es all device opera­tions. For system design simplification, the device is de­signed to support either WE# or CE # controlled writes.
During a system write cycle, addresses are latched on
the falling edge of WE# o r CE# whichever occurs last .
Data is latched on the rising edge of WE# or CE# which­ever occur first. To simplify the following discussion, the
WE# pin is used as the write cycle control pin throughout
the rest of this text. All setup and hold times are with re­spect to the WE# signal.

pin. The erase and repro-

PP

OVERVIEW OF ERASE/PROGRAM OPERATIONS

Embedded

AMD now makes erasure extremely simple and reli­able. The Embedded Erase algorithm requires the user
to only write an erase setup command and erase com­mand. The device will automatica lly pre-program and
verify the entire array. The device automatically times
the erase pulse width, provides the erase verify and
counts the number of sequences. A status bit, Data#
Polling, provides feedback to the user as to the status
of the erase operation.

Erase Algorithm

Embedded Programming Algorithm

AMD now makes programming extremely simple and
reliable. The Embedded Programming algorithm re­quires the user to only write a program setup command
and a program command. The device automatically
times the programming pulse width, provides the pro­gram verify and counts the number of sequences. A
status bit, Data# Polling, provides feedback to the user
as to the status of the programming operation.

DATA PROTECTION

The device is designed to offer protection against acci­dental erasur e or programming ca used by spurious
system level signals that ma y e xist during power t ransi­tions. The device po wers up in its read only state . Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple­tion of specific command sequences.

The device also incor porates several features to pre­vent inadvertent wr ite cycles resulting from V
power-up and power-down trans itions or system noise.

CC

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up
and power-down, the device locks out write cycles for

< V

V

CC

ages). When V
abled, all internal program/erase circuits are disabled,
and the device resets to the read mode. The dev ic e ig­nores all writes until V
that the control pins are in the correct logic state when

> V

V

CC

(see DC characteristics section for volt-

LKO

LKO

< V

CC

to prevent unintentional writes.

, the command register is dis-

LKO

> V

CC

. The user must ensure

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE# = VIL,
CE# =V
and WE# must be a logical zero while OE# is a logical
one.

or WE# = VIH. To initiate a write cycle CE#

IH

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = VIL and
OE# = V
edge of WE#. The internal state machine is automati­cally reset to the read mode on power-up.

will not accept commands on the rising

IH

8 Am28F256A

FUNCTIONAL DESCRIPTION
Description Of User Modes

Table 1. Am28F256A Device Bus Operations (Notes 7 and 8)

Read-Only

Read/Write

CE#

Operation

(E#)

Read V
Standby V
Output Disable V
Auto-select Manufacturer

Code (Note 2)
Auto-select Device

Code (Note 2)
Read V

Standby (Note 5) V
Output Disable V
Write V

V

V

OE#
(G#)

IL

IH

IL

IL

IL

IL

IH

IL

IL

V

V

V

V

V

V
V

WE#
(W#)

IL

XV

XXV

V

IH

IL

IL

IL

IH

V

IH

V

IH

V

IH

XXV

V

IH

IH

IH

V

IL

V

PP

(Note 1) A0 A9 I/O

PPL

PPL

V

PPL

V

PPL

V

PPL

V

PPH

PPH

V

PPH

V

PPH

A0 A 9 D

X X HIGH Z
X X HIGH Z

V

V

IL

V

IH

ID

(Note 3)

V

ID

(Note 3)

A0 A9

X X HIGH Z
X X HIGH Z

A0 A9

Legend:

X = Don’t care, where Don’t Care is either V

of V

. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

PPH

or VIH levels. V

IL

= VPP < VCC + 2 V. See DC Characteristics for voltage levels

PPL

Notes:

1. V

may be grounded, connected with a resistor to ground, or < VCC + 2.0 V . V

PPL

the device. Refer to the DC characteristics. When V

PP

= V

, memory contents can be read but not written or erased.

PPL

is the programming voltage specified for

PPH

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

4. Read operation with V

5. With V

6. Refer to Table 3 for valid D

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V
addresses except A

8. If V

< 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

ID

= V

PP

at high voltage, the standby current is ICC + IPP (standby).

PP

and A0 must be held at VIL.

9

≤

1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP

CC

may access array data or the Auto select codes.

PPH

during a write operation.

IN

or VIH levels. In the Auto select mode all

IL

rise time and fall time specification of 500 ns minimum.

OUT

CODE

(01h)

CODE

(2Fh)
D

OUT

(Note 4)

D

IN

(Note 6)

Am28F256A 9

READ-ONLY MODE

When VPP is less than V
is inactive. The device can either read array or autose­lect data, or be standby mode.

+ 2 V , the command register

CC

Read

The device functions as a read only memory when V
< V

+ 2 V. The de vice has two control functi ons. Both

CC

must be satisfied in order to output data. CE# controls
power to the device. This pin should be used for spe­cific device selection. OE# controls the device outputs
and should be used to gate data to the output pins if a
device is selected.

Address access time t

is equal to the delay from

ACC

stable addresses to valid output data. The chip enable
access time t

is the delay from st able addres ses and

CE

stable CE# to valid data at the output pins. The output
enable access time is the delay from the f alling edge of
OE# to valid data at the output pins (assuming the ad­dresses have been stable at least t

ACC

- tOE).

PP

Standby Mode

The device has two standby modes. The CMOS
standby mode (CE# input held at V

sumes less than 100 µA of current. TTL standby mode
(CE# is held at V

) reduces the current requirements

IH

to less than 1 mA. When in the standby mode the out­puts are in a high impedance state, independent of the
OE# input.

If the device is deselected during erasure, program­ming, or program/erase verification, the device will
draw activ e current until the operation is terminated.

± 0.5 V), con-

CC

Output Disable

Output from the device is disabled whe n OE# is at a
logic high level. When disabled, output pins are in a
high impedance state.

Auto Select

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol­dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.

The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer and
type. This mode is intended for the purpos e of autom ati­cally matching the device to be programmed with its cor­responding p rogramming algorithm . This mode is
functional over the entire temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment
must force V
identifier bytes ma y then be sequenced from the device
outputs by toggling address A0 f rom V
address lines must be held at V
less than or equal to V
select mode. Byte 0 (A0 = V
turer code and byte 1 (A0 = V
code. For t he device t he two b ytes are given in the table
2 of the device data sheet. All identifiers for manufac­turer and device codes will exhibit odd parity with the
MSB (DQ7) defined as the parity bit.

(11.5 V to 13.0 V) on address A9. Two

ID

to VIH. All other

IL

, and VPP must be

+ 2.0 V while using this Auto

CC

IL

) represents the manufac-

IL

) the device identifier

IH

Table 2. Am28F256A Auto Select Code

Type A0

Manufacturer Code V
Device Code V

10 Am28F256A

Code

(HEX)

IL

IH

01
2F

ERASE, PROGRAM, AND READ MODE

When VPP is equal to 12.0 V ± 5%, the command reg-

ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.

Write Operations

High voltage must be applied to the VPP pin in order to
activate the command register. Data written to the reg­ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.

The command register does not occupy an address­able memory location. The register is a latch that stores
the command, along with the address and data infor­mation needed to execute the command. The register
is written by bringing WE# and CE# to V
is at V

. Addresses are latched on the falling edge of

IH

WE#, while data is latched on the rising edge of the
WE# pulse. Standard microprocessor write timings are
used.

The device requires the OE# pin to be V
erations. This condition eliminates the possi bility for
bus contention during programming operations. In
order to write, OE# must be V
must be V

. If any pin is not in the correct state a write

IL

, and CE# and WE#

IH

command will not be executed.

, while OE#

IL

for write op-

IH

Refer to AC Write Characteristics and the Erase/Pro­gramming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h
(Read Mode) in the abs ence of hi gh v oltage applie d to
the V
memory. High voltage on the V

pin. The device operates as a read only

PP

pin enables the

PP

command register. Device operations are selected by
writing specific data codes i nto the command regi ster.
Tabl e 3 in the de vice data sheet def ines these regis ter
commands.

Read Command

Memory contents can be accessed via the read com­mand when V
00h into the command register. Standard microproces­sor read cycles access data from the memory. The de­vice will remain in the read mode until the command
register contents are altered.

The command register defaults to 00h (read mode)
upon V

PP

fault helps ensure that inadvertent alteration of the
memory contents does not occur during the V
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.

is high. To read from the device, write

PP

power-up. The 00h (Read Mode) register de-

power

PP

Table 3. Am28F256A Command Definitions

First Bus Cycle Second Bus Cycle

Operation

Command

Read Memory (Note 4) Write X 00h/FFh Read RA RD
Read Auto select Write X 80h or 90h Read 00h/01h 01h/2Fh
Embedded Erase Set-up/

Embedded Erase
Embedded Program Set-up/

Embedded Program
Reset (Note 4) Write X 00h/FFh Write X 00h/FFh

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE

X = Don’t care.

3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE

4. Please reference Reset Command section.

(Note 1)

Write X 30h Write X 30h

Write X 10h or 50h Write PA PD

Address

(Note 2)

#

pulse.

Data

(Note 3)

Operation

(Note 1)

#

.

Address

(Note 2)

Data

(Note 3)

Am28F256A 11

FLASH MEMORY PROGRAM/ERASE OPERATIONS

Embedded Erase Algorithm

The automatic chip erase does not require the device
to be entirely pre-programmed prior to executing the
Embedded set-up erase comm and and Embedded
erase command. Upon ex ecuting the Embedded erase
command the device automatically will program and
verify the entire memor y for an all zero data patter n.

not

The system is
timing during these operations.

required to provide any controls or

has been achiev ed f or the memory arra y ( no eras e v er­ify command is required). The margin voltages are in­ternally generated in the same manner as when the
standard erase verify command is used.

The Embedded Erase Set-Up command is a command
only operation that stages the device for automatic
electrical erasure of all bytes in the array. Embedded
Erase Setup is performed by writing 30h to the com­mand register.

When the device is automatical ly verified to contain an
all zero pattern, a self-timed chip erase and verify be­gin. The erase and ve rify oper ation are c omplete when

the data on DQ7 is “1" (see Write Operation Status sec­tion) atwhich time the device returns to Read mode.
The system is not required to provide any control or
timing during these operations.

When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin

Apply V

Write Embedded Erase Setup Command

Write Embedded Erase Command

Data# Poll from Device

To commence automatic chip erase, the command 30h
must be written again to the command register . The au­tomatic erase begins on the rising edge of the WE and
terminates when the data on DQ7 is “1" (see Write Op­eration Status section) at which time the device returns
to Read mode.

Figure 1 and Table 4 illustrate the Embedded Erase al­gorithm, a typical command string and bus operation.

START

PPH

Erasure Completed

Figure 1. Embedded Erase Algorithm

Table 4. Embedded Erase Algorithm

Bus Operations Command Comments

Standby Wait for V

Write

Read Data
Standby Compare Output to FFh
Read Available for Read Operations

Note: See AC and DC Characteristics for values of V
switchable. When V
to Functional Description.

Embedded Erase Setup Command Data = 30h
Embedded Erase Command Data = 30h

parameters. The V

is switched, V

PP

may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer

PPL

PP

Ramp to V

PP

# Polling to Verify Erasure

power supply can be hard-wired to the device or

PP

(see Note)

PPH

12 Am28F256A

18879C-6

Embedded Programming Algorithm

The Embedded Program Setup is a command only op­eration that stages the device for automatic program­ming. Embedde d Program Setup is performed by
writing 10h or 50h to the command register.

Once the Embedded Setup Progr am ope r ation is per­formed, the next WE# pulse causes a transition to an
active prog ramming operati on. Ad dresses are latched
on the falling edge of CE# or WE# pulse, whichever
happens later. Data is latched on the rising edge of
WE# or CE#, whiche ver happens first. The ris ing edge

of WE# also begins the programming operation. The
system is not required to provide further controls or
timings. The device will automatically provide an ade­quate internally generated program pulse and verify
margin. The automatic programming operation is
completed when the data on DQ7 is equiva lent to data
written to this bit (see Write Oper at io n Stat us s ecti on)
at which time the device returns to Read mode.

Figure 2 and Table 5 illustrate the Embedded Program
algorithm, a typical command string, and bus operation.

START

Increment Address

Apply V

Write Embedded Setup Program Command

Write Embedded

Data# Poll Device

No

Last Address

Programming Completed

PPH

Program Command (A/D)

Yes

Figure 2. Embedded Programming Algorithm

Table 5. Embedded Programming Algorithm

Bus Operations Command Comments

18879C-7

Standby Wait for V
Write Embedded Program Setup Command Data = 10h or 50h
Write Embedded Program Command Valid Address/Data
Read Data
Read Available for Read Operations

Note: See AC and DC Characteristics for values of V
switchable. When V
to Functional Description. Device is either powered-down, erase inhibit or program inhibit.

is switched, V

PP

may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer

PPL

parameters. The V

PP

Ramp to V

PP

PPH

# Polling to Verify Completion

power supply can be hard-wired to the device or

PP

Am28F256A 13

(see Note)

Write Operation Status

Data Polling—DQ7

The device features Data# Polling as a method to indi­cate to the host system that the Embedded algorithms
are either in progress or completed.

While the Embedded Programming algorithm is in oper­ation, an attempt to read the device at a valid address
will produce the complement of expected Valid data on
DQ7. Upon completion of the Embedded Program algo­rithm an attempt to read the device at a valid address will
produce Valid data on DQ7. The Data# Polling feature is
valid after the rising edge of the se cond WE# pulse of
the two write pulse sequence.

START

While the Embedded Erase algorithm is in operation,

DQ7 will read “0"

until the erase operation is com­pleted. Upon completion of the eras e operation, the
data on DQ7 will read “1.” The Data# Polling feature is
valid after the rising edge of the second WE# pulse of
the two Write pulse sequence.

The Data# Polling feature is only active during Embed­ded Programming or erase algorithms.

See Figures 3 and 4 for the Data# Polling timing spec­ifications and diagrams. Data# Polling is the standard
method to check the write operation status, however,
an alternative method is available using Toggle Bit.

No

Read Byte

(DQ0–DQ7)

Addr = VA

DQ7 = Data

?

No

DQ5 = 1

?

Yes

Read Byte

(DQ0–DQ7)

Addr = VA

DQ7 = Data

?

No

VA = Byte address for programming

= XXXXh during chip erase

Yes

Yes

Fail

Note:

DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5 or after DQ5.

Pass

Figure 3. Data# Polling Algorithm

14 Am28F256A

18879C-8

CE#

t

CH

t

t

OE

DF

OE#

t

OEH

WE#

DQ7

t

CE

t

WHWH 3 or 4

DQ7#

DQ0–DQ6 = InvalidDQ0–DQ6

*DQ7 = Valid Data (The device has completed the Embedded operation.)

Figure 4. AC Waveforms for Data# Polling during Embedded Algorithm Operations

*

DQ7 =

Valid Data

t

OH

DQ0–DQ7
Valid Data

High Z

18879C-9

Am28F256A 15

Toggle Bit—DQ6

The device also f eatures a “Toggle Bit” as a method to
indicate to the host system that the Embedded algo­rithms are either in progres s or completed.

Successive attempts to read data from the device at a
valid address, while the Embedded Program algorithm
is in progress, or at any address while the Embedded
Erase algorithm is in progress, will result in D Q6 tog­gling between one and zero. Once the Embedded Pro­gram or Erase algor ithm is completed, D Q6 will stop

START

toggling to indicate the completion of either Embedded
operation. Only on the next read cycl e will valid data be
obtained. The toggle bit is valid after the rising edge of
the first WE# pulse of the two write pulse seq uence, un­like Data# Polling which is valid after the rising edge of
the second WE# pulse. This feature allows the user to
determine if the device is partially through the two write
pulse sequence.

See Figures 5 and 6 for the Toggle Bit timing specifica­tions and diagrams.

Read Byte

(DQ0–DQ7)

Addr = VA

DQ6 = Toggle

No

DQ5 = 1

Read Byte

(DQ0–DQ7)

Addr = VA

DQ6 = Toggle

VA = Byte address for programming

= XXXXh during chip erase

No

?

Yes

?

Yes

No

?

Yes

Fail

Note:

DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.

Pass

Figure 5. Toggle Bit Algorithm

16 Am28F256A

18879C-10

CE#

t

OEH

WE#

OE#

Data

DQ0–DQ7

Note:

*DQ6 stops toggling (The device has completed the Embedded operation.)

DQ6 = DQ6 =

Figure 6. AC Waveforms for Toggle Bit during Embedded Algorithm Operations

*

t

OE

DQ6

Stop Toggling

DQ0–DQ7

Valid

18879C-11

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has
exceeded the specified limits. This is a failure condi­tion and the device may not be used again (internal
pulse count exceeded). Under these conditions DQ5

will produce a “1.” The program or er ase cycle was not
successfully completed. Data# Polling is the only op­erating function of the de vice under this conditi on. The
CE# circuit will partially power down the device under
these conditions (to approximately 2 m A). The OE#
and WE# pins will control the output disable functions
as described in the Command Definitions table in the
corresponding device data sheet.

Parallel Device Erasure

The Embedded Erase algorithm greatly simplifies par­allel device erasure. Sinc e the erase process is internal
to the device, a single eras e command can be given to
multiple devices concurrently. By implementing a paral­lel erase algorithm, total erase time may be minimized.

Note that the Flash memories may erase at different
rates. If this is the case, when a device is completely
erased, use a masking code to prevent further erasure
(over-erasure). The other de vices will continue t o erase
until verified. The masking code applied could be the
read command (00h).

Power-Up/Power-Down Sequence

The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if V

1.0 Volt, the voltage difference between V

and V

PP

CC

≤

CC

should not exceed 10.0 Volts. Also, the device has a
rise V

rise time and fall time specification of 500 ns

PP

minimum.

Reset Command

The Reset command initializes the Flash memory de­vice to the Read mode. In addition, it also provides the
user with a safe method to abor t any device operation
(including program or erase).

The Reset must be written two cons ecutive times after
the Setup Program command (10h or 50h). This will
reset the device to the Read mode.

Following any other Flash comm and, write the Reset
command once to the device. This wi ll safely abort any
previous operation and initializ e the de vice to the Read
mode.

The Setup Program command (10h or 50h) is the only
command that requires a two-sequence reset cycle. The
first Reset command is interpreted as program data.
However , FFh data is considered as null data during pro­gramming operations (memor y cells are only pro­grammed from a logica l “1" to “0"). The second Reset
command safely aborts the programming operation and
resets the device to the Read mode.

Memory contents are not altered in any case.

Am28F256A 17

This detailed information i s for your reference. It may
prove easier to always issue the Reset command two
consecutive times. This elim inates the need to deter ­mine if you are in the Setup Program state or not.

In-System Programming Considerations

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol­dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the circuit board.

Auto Select Command

AMD’s Flash memories are designed for use in appli­cations where the local CPU alters memory contents.
In order to correctly program any Flash memor ies

in-system, manufacturer and device codes must be
accessible while the device resides in the target
system. PROM programmers typically access the sig­nature codes by r aising A9 to a hig h voltage . How ev er ,
multiplexing high voltage onto address lines is not a
generally desired system design practice.

The device contains an Auto Select operation to supple­ment traditional PROM programming methodologies.
The operation is initiated by writing 80h or 90h into the
command register. Following this c ommand, a read
cycle address 0000h retrieves the manufacturer code of
01h (AMD). A read cycle from address 0001h returns
the device code (see the Auto Select Code table of the
corresponding device data sheet). To terminate the op­eration, it is necessary to write another valid command,
such as Reset (00h or FFh), into the register.

18 Am28F256A

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . –65°C to +150°C

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C

Voltage with Respect To Ground
All pins except A9 and V

(Note 1) . . . . . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

V

(Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

CC

(Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

A9

(Note 2). . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

V

PP

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, inputs may overshoot V
periods of up to 20 ns. Maximum DC voltage on input and
I/O pins is V
and I/O pins may overshoot to V
to 20ns.

2. Minimum DC input voltage on A9 and V
During voltage transitions, A9 and V
V

to –2.0 V for periods of up to 20 ns. Maximum DC

SS

input voltage on A9 and V
overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the op­erational sections of this specification is not implied. Expo­sure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.

+ 0.5 V. During voltage transitions, input

CC

PP

+ 2.0 V for periods up

CC

PP

may overshoot

PP

is +13.0 V which may

PP

to –2.0 V for

SS

pins is –0.5 V.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

V

Supply Voltages

CC

. . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

V

CC

Voltages

V

PP

Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V

Program, Erase , and Verify. . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

) . . . . . . . . . . .0°C to +70°C

A

) . . . . . . . . .–40°C to +85°C

A

) . . . . . . . .–55°C to +125°C

A

Am28F256A 19

MAXIMUM OVERSHOOT

V

CC

+0.8 V

–0.5 V

+ 0.5 V

2.0 V

V

CC

20 ns

–2.0 V

20 ns

Maximum Negative Input Overshoot

20 ns

+ 2.0 V

20 ns 20 ns

20 ns

18879C-12

V

CC

18879C-13

Maximum Po sitive Input Overshoot

20 ns

14.0 V

13.5 V

+ 0.5 V

20 ns 20 ns

18879C-14

Maximum VPP Overshoot

20 Am28F256A

DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1-4)
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

I

I

I

I

I

I

I

V

V

V

V

I

LI

I

LO

CCS

CC1

CC2

CC3

PPS

PP1

PP2

PP3

V

IL

V

IH

OL

OH1

V

ID

I

ID

PPL

PPH

Input Leakage Current V
Output Leakage Current VCC = VCC Max, V
VCC Standby Current VCC = VCC Max, CE# = V

VCC Active Read Current

VCC Programming Current

VCC Erase Current

V

Standby Current V

PP

V

Read Current

PP

V

Programming Current

PP

V

Erase Current

PP

= V

CC

V

CC = VCC

I

OUT

CE#

Max, VIN = V

CC

Max, CE# = V

= 0 mA, at 6 MHz

= VIL

OUT

or V

CC

SS

= VCC or V

IH

OE# = V

IL,

Programming in Progress (Note 4)

#

CE

= VIL

Erasure in Progress (Note 4)

= V

PP

PPL

V

= V

PP

PPH

= V

V

PP

PPL

= V

V

PP

PPH

Programming in Progress (Note 4)
V

= V

PP

PPH

Erasure in Progress (Note 4)

SS

±1.0 µA
±1.0 µA

0.2 1.0 mA

IH

20 30 mA

20 30 mA

20 30 mA

±1.0 µA

70 200

µA

±1.0

10 30 mA

10 30 mA

Input Low Voltage –0.5 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
A9 Auto Select Voltage A9 = V

ID

11.5 13.0 V
A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
V

during Read-Only

PP

Operations
V

during Read/Write

PP

Operations

Note: Erase/Program are inhibited
when V

PP

= V

PPL

0.0 VCC +2.0 V

11.4 12.6 V

V

LKO

Low VCC Lock-out Voltage 3.2 3.7 V

Notes:

1. Caution: The Am28F256A must not be removed from (or inserted into) a socket when V
volt, the voltage difference between V

and VCC should not exceed 10.0 volts. Also, the Am28F256A has a VPP rise time

PP

and fall time specification of 500 ns minimum.

2. I

3. Maximum active power usage is the sum of I

is tested with OE# = VIH to simulate open outputs.

CC1

CC

and IPP.

4. Not 100% tested.

Am28F256A 21

or VPP is applied. If VCC ð 1.0

CC

DC CHARACTERISTICS
CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

I

I

I

I

I

I

I

V
V
V

V

V

I

LI

I

LO

CCS

CC1

CC2

CC3

PPS

PP1

PP2

PP3

V

IL

V

IH

OL

OH1

OH2

V

ID

I

ID

PPL

PPH

Input Leakage Current V

Output Leakage Current VCC = VCC Max, V
VCC Standby Current VCC = VCC Max, CE#

V

Active Read Current

CC

VCC Programming Current

VCC Erase Current

V

Standby Current V

PP

V

Read Current V

PP

V

Programming Current

PP

V

Erase Current

PP

= V

CC

V

CC

I

OUT

CE# = V

Max, VIN = V

CC

= V

Max, CE# = V

CC

= 0 mA, at 6 MHz

IL

OUT

or V

CC

SS

= VCC or V

±0.5 V 15 100 µA

= VCC

OE# = V

IL,

Programming in Progress (Note 4)

# = V

CE

IL

Erasure in Progress (Note 4)

= V

PP

PPL

= V

PP

PPH

V

= V

PPH

PP

Programming in Progress (Note 4)

= V

V

PP

PPH

Erasure in Progress (Note 4)

SS

±1.0 µA
±1.0 µA

IH

20 30 mA

20 30 mA

20 30 mA

±1.0 µA

70 200 µA

10 30 mA

10 30 mA

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 V

CC

V

CC

+ 0.5 V

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

Output High Voltage

IOH = –2.5 mA, VCC = VCC Min 0.85 V
IOH = –100 µA, V

A9 Auto Select Voltage A9 = V

CC

CC = VCC

ID

Min VCC –0.4

11.5 13.0 V

V

A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
V

during Read-Only

PPL

Operations
V

during Read/Write

PP

Operations

Note: Erase/Program are inhibited
when V

PP

= V

PPL

0.0 VCC + 2.0 V

11.4 12.6 V

V

LKO

Low VCC Lock-out Voltage 3.2 3.7 V

Notes:

1. Caution: The Am28F256A must not be removed from (or inserted into) a socket when V

the voltage difference between V

and VCC should not exceed 10.0 volts. Also, the Am28F256A has a VPP rise time and fall

PP

time specification of 500 ns minimum.

2. I

3. Maximum active power usage is the sum of I

is tested with OE# = VIH to simulate open outputs.

CC1

CC

and IPP.

4. Not 100% tested.

22 Am28F256A

or VPP is applied. If VCC ð 1.0 volt,

CC

25

20

15

Active in mA

10

CC

I

5

0

0123456789101112

Frequency in MHz

55°C
0°C
25°C
70°C
125°C

Figure 7. Am28F256A—Average ICC Active vs. Frequency

TEST CONDITIONS

Device

Under

Test

C

L

Note: Diodes are IN3064 or equivalent

Figure 8. Test Setup

6.2 kΩ

= 5.5 V, Addressing Pattern = Minmax

V

CC

Data Pattern = Checkerboard

5.0 V

2.7 kΩ

18879C-16

Test Condition - 70 All others Unit

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times ≤10 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement
reference levels

Output timing measurement
reference levels

Table 6. Test Specifications

L

30 100 pF

1.5 0.8, 2.0 V

1.5 0.8, 2.0 V

18879C-15

Am28F256A 23

SWITCHING TEST WAVEFORMS

s

2.4 V

0.45 V

2.0 V
Test Points

0.8 V

Input

2.0 V

0.8 V
Output

AC T esting (all speed options except -70): Inputs are driven at

2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise
and fall times are

≤

10 ns.

3 V

1.5 V

0 V

Input

Test Points

Output

AC Testing for -70 devices: Inputs are driven at 3.0 V for a

logic “1” and 0 V for a logic “0”. Input pulse rise and fall time
are ≤10 ns.

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

AC Characteristics—Read Only Operation

Parameter Symbols

t

AVAV

t

ELQV

t

AVQV

t

GLQV

t

ELQX

t
t

t

ACC

t

t

RC

CE

OE

LZ

Parameter Description

Read Cycle Time (Note 2) Min 70 90 120 150 200 ns
Chip Enable Access Time Max 70 90 120 150 200 ns
Address Access Time Max 70 90 120 150 200 ns
Output Enable Access Time Max 35 35 50 55 55 ns
Chip Enable to Output in Low Z

(Note 2)

Min00000ns

Am28F256A Speed Options

1.5 V

18879C-17

UnitJEDEC Standard -70 -90 -120 -150 -200

t

EHQZ

t

GLQX

t

GHQZ

t

AXQX

t

VCS

t

t

t

t

DF

OLZ

DF

OH

Chip Disable to Output in High Z
(Note 1)

Output Enable to Output in Low Z
(Note 2)

Output Disable to Output in High Z
(Note 2)

Output Hold from first of Address,
CE

#, or OE# Change (Note 2)

VCC Setup Time to Valid Read
(Note 2)

Notes:

1. Guaranteed by design not tested.

2. Not 100% tested.

Max2020303535ns

Min00000ns

Max2020303535ns

Min00000ns

Min 50 50 50 50 50 µs

24 Am28F256A

AC Characteristics—Write/Erase/Program Operations

Parameter Symbols

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

OEH

t

GHWL

t

ELWLE

t

WHEH

t

WLWH

t

WHWL

t

WHWH3

t

WHWH4

t

VPEL

t

WC

t

AS

t

AH

t

DS

t

DH

t

CSE

t

CH

t

WP

t

WPH

Am28F256A Speed Options

Parameter Description

UnitJEDEC Standard -70 -90 -120 -150 -200

Write Cycle Time (Note 4) Min 70 90 120 150 200 ns
Address Setup Time Min00000ns
Address Hold Time Min 45 45 50 60 75 ns
Data Setup Time Min 45 45 50 50 50 ns
Data Hold Time Min 10 10 10 10 10 ns
Output Enable Hold Time for

Embedded Algorithm only

Min 10 10 10 10 10 ns

Read Recovery Time before WriteMin00000µs

Chip Enable Embedded Algorithm
Setup Time

Min 20 2 0 20 20 20 ns

Chip Enable Hold Time Min00000ns
Write Pulse Width Min 45 45 50 60 60 ns
Write Pulse Width HIGH Min 20 20 20 20 20 ns
Embedded Programming Operation

(Note 2)

Min 14 14 14 14 14 µs

Embedded Erase Operation (Note3)Typ55555sec
VPP Setup Time to Chip Enable LOW

(Note 4)

Min 100 100 100 100 100 ns

t

VCS

t

VPPR

t

VPPF

t

LKO

VCC Setup Time to Chip Enable LOW
(Note 4)

VPP Rise Time 90% V
VPP Fall Time 90% V
VCC < V

to Reset (Note 4) Min 100 100 100 100 100 ns

LKO

(Note 4) Min 500 500 500 500 500 ns

PPH

(Note 4) Min 500 500 500 500 500 ns

PPL

Min 50 50 50 50 50 µs

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.

2. Embedded program operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the

minimum time for one pass through the programming algorithm.

3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and 1 sec array erase time. This is a typical
time for one embedded erase operation.

4. Not 100% tested.

Am28F256A 25

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

SWITCHING WAVEFORMS

Power-up, Standby

Device and

Address Selection

Outputs
Enabled

Steady

Changing from H to L

Changing from L to H

Data
Valid

Standby, Power-down

Addresses

CE#

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V
V

CC

0 V

t

VCS

Addresses Stable

t

(tRC)

AVAV

t

EHQZ

(tDF)

t

WHGL

t

(tOE)

GLQV

t

(tCE)

ELQV

t

t

(t

OLZ

)

GLQX

t

(tLZ)

High Z High Z

ELQX

t

AVQV

(t

)

ACC

AXQX (tOH

Output Valid

t

GHQZ

(tDF)

)

Figure 9. AC Waveforms for Read Operations

26 Am28F256A

18879C-18

SWITCHING WAVEFORMS

Addresses

CE#

OE#

WE#

Data

V

CC

t

GHWL

t

t

VCS

CSE

Embedded

Erase Setup

t

WC

t

WP

t

DS

Embedded

Erase

t

AS

t

WPH

t

t

DH

AH

30h

Erase Standby

t

WHWH3 OR 4

Data# Polling

DQ7#30h

DQ7#

Read

t

RC

t

t

OE

t

CE

DF

t

OH

V

PP

t

VPEL

Note:

DQ7# is the complement of the data written to the device.

Figure 10. AC Waveforms for Embedded Erase Operation

18879C-19

Am28F256A 27

SWITCHING WAVEFORMS

Addresses

CE#

OE#

WE#

Data

V

CC

Embedded

Program Setup

t

CSE

t

VCS

t

WC

t

WP

t

t

DH

50h

DS

t

GHWL

t

Embedded

WPH

Program

PA

t

AS

t

AH

IN

t

WHWH3 OR 4

Data# Polling

PA

DQ7#D

DQ7# D

OUT

Read

t

RC

t

t

DF

OH

t

OE

t

CE

V

PP

t

VPEL

Notes:

D

is data input to the device.

IN

#

is the complement of the data written to the device.

DQ7

is the data written to the device.

D

OUT

Figure 11. AC Waveforms for Embedded Programming Operation

18879C-20

28 Am28F256A

AC CHARACTERISTICS—WRITE/ERASE/PROGRAM OPERATIONS
Alternate CE

Parameter Symbols

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

OEH

t

GHEL

t

WLEL

t

EHWK

t

ELEH

t

EHEL

t

EHEH3

t

EHEH4

t

VPEL

# Controlled Writes

Parameter Description

t

t
t
t

t
t

t

t

CPH

WC

AS

AH

DS

t

WS

WH

CP

Write Cycle Time (Note 4) Min 70 90 120 150 200 ns
Address Setup Time Min 0 0 0 0 0 ns
Address Hold Time Min 45 45 50 60 75 ns
Data Setup Time Min 45 45 50 50 50 ns
Data Hold Time Min 10 10 10 10 10 ns

g

Output Enable Hold Time for
Embedded Algorithm only

Read Recovery Time Before Write Min 0 0 0 0 0 µs

WE# Setup Time by CE# Min00000ns
WE# Hold Time Min 0 0 0 0 0 ns
Write Pulse Width M in 65 65 70 80 80 ns
Write Pulse Width HIG H Min 20 20 20 20 20 ns
Embedded Programming Operation

(Note 2)
Embedded Erase Operation (Note 3) Typ 5 5 5 5 5 sec
VPP Setup Time to Chip Enable LOW

(Note 4)

Am28F256A Speed Options

UnitJEDEC Standard -70 -90 -120 -150 -200

Min1010101010ns

Min1414141414µs

Min 100 100 100 100 100 ns

t

VCS

t

VPPR

t

VPPF

t

LKO

VCC Setup Time to Chip Enable LOW
(Note 4)

VPP Rise Time 90% V
VPP Fall Time 90% V
VCC < V

to Reset (Note 4) Min 100 100 100 100 100 ns

LKO

(Note 4) Min 500 500 500 500 500 ns

PPH

(Note 4) Min 500 500 500 500 500 ns

PPL

Min5050505050µs

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.

2. Embedded program operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the

minimum time for one pass through the programming algorithm.

3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a
typical time for one embedded erase operation.

4. Not 100% tested.

Am28F256A 29

SWITCHING WAVEFORMS

Addresses

WE#

OE#

CE#

Data

V

CC

t

WS

t

GHEL

Embedded

Program Setup

t

WC

t

CP

50h

t

DS

Embedded

t

CPH

Program

PA

t

AS

t

AH

t

DH

Data# Polling

PA

t

EHEH3 OR 4

IN

DQ7#D

DQ7#

D

OUT

V

PP

t

VPEL

Notes:

1. D

is data input to the device.

IN

2. DQ7# is complement of the data written to the device.

3. D

is the data written to the device.

OUT

Figure 12. AC Waveforms for Embedded Programming Operation Using CE# Controlled Writes

18879C-21

30 Am28F256A

ERASE AND PROGRAMMING PERFORMANCE

Limits

Typ

Parameter

Chip Erase Time 1 10 sec Excludes 00h programming prior to erasure
Chip Programming Time 0.5 12.5 sec Excludes system-level overhead
Write/Erase Cycles 100,000 Cycles
Byte Programming Time 14 µs

(Note 1)

Max

(Note 2) Unit

96

(Note 3)

ms

CommentsMin

Notes:

1. 25°C, 12 V V

PP

.

2. Maximum time specified is lower than worst case. Worst case is derived from the Embedded Algorithm internal counter which
allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is
significantly less than the actual device limit.

3. Typical worst case = 84 µs. DQ5 = “1” only after a byte takes longer than 96 ms to program.

LATCHUP CHARACTERISTICS

Parameter Min Max

Input Voltage with respect to V
Input Voltage with respect to V
Current –100 mA +100 mA

on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V

SS

on all pins I/O pins –1.0 V VCC + 1.0 V

SS

Includes all pins except V

. Test conditions: VCC = 5.0 V, one pin at a time.

CC

PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions Typ Max Unit

Input Capacitance VIN = 0 8 10 pF
Output Capacitance V
VPP Input Capacitance VPP = 0 8 12 pF

= 0 8 12 pF

OUT

C

C

C

IN

OUT

IN2

Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Yea rs
125°C 20 Yea rs

Am28F256A 31

PHYSICAL DIMENSIONS

PD032—32-Pin Plastic DIP (measured in inches)

1.640

1.670

.120
.160

32

.140
.225

Pin 1 I.D.

.045
.065

.005 MIN

.090
.110

.016
.022

17

.530
.580

16

0°

10°

SEATING PLANE

.015
.060

PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485
.495

.009
.015

.125
.140

.080
.095

SEATING

PLANE

.013
.021

.050 REF.

SIDE VIEW

.585
.595

.447
.453

Pin 1 I.D.

.547
.553

.026
.032

TOP VIEW

.600
.625

.009
.015

.630
.700

16-038-S_AG
PD 032
EC75
5-28-97 lv

.042
.056

.400

REF.

.490
.530

16-038FPO-5
PL 032
DA79
6-28-94 ae

32 Am28F256A

PHYSICAL DIMENSIONS

TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50 BSC

1.20

MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TS 032
DA95
3-25-97 lv

Am28F256A 33

PHYSICAL DIMENSIONS

TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50 BSC

1.20

MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TSR032
DA95
3-25-97 lv

34 Am28F256A

DATA SHEET REVISION SUMMARY FOR AM28F256A

Deleted -75, -95, and -250 speed options. Matched f or­matting to other current data sheets.

Revision C+1

Programming In A PROM Programmer:

Deleted the paragraph “(R efer to the AUTO SELEC T
paragraph in the ERASE, PROGRAM, and READ
MODE section for programming the Flash memory de­vice in-system).”

Revision C+2

Product Selector Guide

Corrected maximum access time for -200 to 200 ns.

Erase and Programming Performance

Chip Programming Time—Typical:

Changed value

from 2 to 0.5 sec.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am28F256A 35