Datasheet AM27X256-200PC, AM27X256-200JI, AM27X256-200JC, AM27X256-150PI, AM27X256-150PC Datasheet (AMD Advanced Micro Devices)

FINAL

Am27X256

256 Kilobit (32 K x 8-Bit) CMOS ExpressROM Device

DISTINCTIVE CHARACTERISTICS

■ As an OTP EPROM alternative:

— Factory optimized programming
— Fully tested and guaranteed

■ As a Mask ROM alternative:

— Shorter leadtime
— Lower volume per code

■ Fast access time

— 55 ns

■ Single +5 V power supply

■ Compatible wit h JEDEC-approved EPROM

pinout

■ ±10% power supply tolerance

■ High noise immunity

■ Low power dissipation

— 20 µA maximum CMOS standby current

■ Av ailable in Plastic Dual-In-line Pac kage (PDIP)

and Plastic Leaded Chip Carrier (PLCC)

■ Latch-up protected to 100 mA from –1 V to

+ 1 V

V

CC

■ Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility
— Two line control functions

GENERAL DESCRIPTION

The Am27X256 is a factory programmed and tested
OTP EPROM. It is progra mmed after pac kaging prior to
final test. Every device is rigorously tested under AC
and DC operating conditions to your stable code. It is
organized as 32 Kwords by 8 bits per word and is av ail­able in plastic dual in-line packages (PDIP), as well as
plastic leaded chip carrier (PLCC) packages. Express­ROM devices provide a board-ready memory solution
for medium to high volume codes with short leadtimes.
This offers manufacturers a cost-effective and flexible
alternative to OTP EPROMs and mask programmed
ROMs.

BLOCK DIAGRAM

V

CC

V

SS

OE#
CE#

A0–A14
Address

Inputs

Output Enable

Chip Enable

and

Prog Logic

Y

Decoder

X

Decoder

Data can be accessed as fast as 55 ns, allowing
high-performance microprocessors to operate with re­duced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus contention in a multiple bus micropro­cessor system.

AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.

Data Outputs DQ0–DQ7

Output
Buffers

Y

Gating

262,144

Bit Cell

Matrix

12082F-1

Publication# 12082 Rev: F Amendment/0
Issue Date: May 1998

PRODUCT SELECTOR GUIDE

Family Part Number Am27X256

= 5.0 V ± 5% -255

V

Speed Options

Max Access Time (ns) 55 70 90 120 150 200 250
CE# (E#) Access (ns) 55 70 90 120 150 200 250
OE# (G#) Access (ns) 35 40 40 50 50 50 50

CC

= 5.0 V ± 10% -55 -70 -90 -120 -150 -200

V

CC

CONNECTION DIAGRAMS
Top View

DIP PLCC

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

A14
A13
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
DQ6

DQ5
DQ4
DQ3

A6
A5
A4

A3
A2
A1
A0

NC

DQ0

5
6

7

8
9
10

11
12
13

14

A7

15

DQ1

A12

DQ2

PP

CC

DU

V

13130234

17

SS

DU

V

18

32

DQ3

A14

A13

V

A8

29

A9

28

A11

27

NC

26

OE# (G#)

25

A10

24

CE# (E#)

23

DQ7

22

DQ6

21

19 2016

DQ5

DQ4

V

PP

A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1

DQ2

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

12082F-2

Notes:

1. JEDEC nomenclature is in parenthesis.

2. Don’t use (DU) for PLCC.

PIN DESIGNATIONS

LOGIC SYMBOL

A0–A14 = Address Inputs
CE# (E#) = Chip Enable Input
DQ0–DQ7 = Data Input/Outputs
OE# (G#) = Output Enable Input
PGM# (P#) = Program Enable Input
V

CC

V

PP

V

SS

=VCC Supply Voltage
= Program Voltage Input
= Ground

NC = No Internal Connection

2 Am27X256

15

A0–A14

CE# (E#)

OE# (G#)

12082F-3

8

DQ0–DQ7

12082F-4

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

AM27X256

-55 J C

DEVICE NUMBER/DESCRIPTION

Am27X256
256 Kilobit (32 K x 8-Bit) CMOS ExpressROM Device

XXXXX

CODE DESIGNATION

Assigned by AMD

TEMPERATURE RANGE

C = Commercial (0°C to +70
I=Industrial (–40

PACKAGE TYPE

P = 28-Pin Plastic Dual In-Line Package (PD 028)
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

°C)

Valid Combinations

AM27X256-55 PC, JC
AM27X256-70

AM27X256-90
AM27X256-120
AM27X256-150
AM27X256-200
AM27X256-255

= 5.0 V ± 5%

V

CC

PC, JC, PI, JI

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Am27X256 3

FUNCTIONAL DESCRIPTION
Read Mode

T o obtain dat a at the device outputs, Chip Enable ( CE#)
and Output Enable (OE#) must be driv en low . CE# con­trols the power to the de vice and is typically used t o se­lect the device . OE# en ables th e de v ice to out put dat a,
independent of device selection. Addresses must be
stable for at least t

ACC–tOE.

Refer to the Switching

Waveforms section for the timing diagram.

Standby Mode

The device enters the CMOS standby mode when CE#
is at V

± 0.3 V. Maximum V

CC

current is reduced to

CC

100 µA. The device enters the TTL-standby mode
when CE# is at V

. Maximum V

IH

current is reduced

CC

to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen­dent of the OE# input.

Output OR-Tieing

To accommodate multiple memory connections, a
two-line control function provides:

■ Low memory power dissipation, and

■ Assurance that output bus contention will not occur.

CE# should be decoded and used as the primary de­vice-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This as­sures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular mem­ory device.

System Applications

During the switch between active and standby condi­tions, transient current peaks are produced on the ris­ing and falling edges of Chip Enab le . The magnitude of
these transient current peaks is dependent on the out­put capacitance loading of the de vi ce. At a minim um, a

0.1 µF ceramic capacitor (high frequency, low inherent
inductance) sho uld be used on each device between

and VSS to minimize transient effects. In addition,

V

CC

to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on Express­ROM device arrays, a 4.7 µF bulk electrolytic capacitor
should be used between V
devices. The location of the capacitor should be close
to where the power supply is connected to the array.

and VSS for each eight

CC

MODE SELECT TABLE

Mode CE# OE# V

Read V
Output Disable X V
Standby (TTL) V
Standby (CMOS) V

Note:

X = Either V

or VIL.

IH

IL

IH

± 0.3 V X X High Z

CC

V

IL

IH

X X High Z

PP

XD
X High Z

Outputs

OUT

4 Am27X256

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to V

All pins except VCC . . . . . . . . . –0.6 V to VCC + 0.6 V

(Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V

V

CC

Note:

1. Minimum DC voltage on inpu t or I/O pins – 0.5 V. D uring
voltage transitions, the input may overshoot V
for periods of up to 20 ns. Max imum DC voltage o n inp ut
and I/O pins is V
and I/O pins may overshoot to V
to 20ns.

Stresses above those listed under “Abso lute Maximum Rat­ings” may cause per mane nt dam age to the device. This is a
stress rating only; fun ctio nal ope ration of t he d evice at these
or any other condition s above those indicated in the opera­tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.

CC

SS

to –2.0 V

SS

+ 5 V . During voltage transitions, input

+ 2.0 V for periods up

CC

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Supply Read Voltages

for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

V

CC

for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V

V

CC

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) . . . . . . . . . . .0°C to +70°C

A

) . . . . . . . . .–40°C to +85°C

A

Am27X256 5

DC CHARACTERISTICS over operating range (unless otherwise specified)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

V

V

V
V

I

I

CC1

I

CC2

I

CC3

I

LO

OH

OL

IH

IL

LI

Output HIGH Voltage IOH = –400 µA 2.4 V

Output LOW Voltage IOL = 2.1 mA 0.45 V
Input HIGH Voltage 2.0 VCC + 0.5 V
Input LOW Voltage –0.5 +0.8 V
Input Load Current VIN = 0 V to V
Output Leakage Current V

= 0 V to V

OUT

CC

CC

VCC Active Current (Note 2) CE# = VIL, f = 10 MHz,

I

= 0 mA

OUT

VCC TTL Standby Current CE# = V

IH

1.0 µA

1.0 µA

25 mA

1.0 mA

VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA

Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:

must be applied simultaneously or before VPP, and removed simultaneously or after VPP..

1. V

CC

is tested with OE# = V

2. I

CC1

to simulate open outputs.

IH

3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is V

30

+ 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

CC

30

25

20

in mA

Supply Current

15

10

12345678910

Frequency in MHz

12082F-5

Figure 1. Typical Supply Current vs. Frequency

= 5.5 V, T = 25°C

V

CC

25

20

in mA

15

Supply Current

10

–75 –50 –55 0 25 50 75 100 125 150

Temperature in °C

12082F-6

Figure 2. Typical Supply Current vs. Temperature

= 5.5 V, f = 10 MHz

V

CC

6 Am27X256

TEST CONDITIONS

Device

Under

Test

C

L

6.2 kΩ

Note:

Diodes are IN3064 or equivalents.

Figure 3. Test Setup

SWITCHING TEST WAVEFORM

3 V

1.5 V

0 V

Input

Test Points

5.0 V

Output

2.7 kΩ

12082F-7

1.5 V

Table 1. Test Specifications

All

Test Condition -55, -70

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)

L

30 100 pF

Input Rise and Fall Times ≤ 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement
reference levels

Output timing measurement
reference levels

2.4 V

0.45 V

2.0 V

0.8 V

Input

1.5 0.8, 2.0 V

1.5 0.8, 2.0 V

Test Points

others Unit

2.0 V

0.8 V
Output

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Note: For CL = 100 pF.Note: For CL = 30 pF.

12082F-8

Steady

Changing from H to L

Changing from L to H

KS000010-PAL

Am27X256 7

AC CHARACTERISTICS

Parameter Symbols

Am27X256

Description Test Setup

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

ACC

t

CE

t

OE

t

DF

(Note 2)

Address to Output Delay

Chip Enable to Output Delay OE# = VILMax 55 70 90 120 150 200 250 ns
Output Enable to Output

Delay
Chip Enable High or Output

Enable Highto Output High Z,
Whichever Occurs First

CE#,
OE# = V

CE# = V

Max 55 70 90 120 150 200 250 ns

IL

Max35404050505050ns

IL

Max25252530303030ns

Output Hold Time from

t

AXQX

t

OH

Addresses, CE# or OE#,

Min0000000ns

Whichever Occurs First

Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or V

Notes:

CC

1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS

2.4

Addresses

0.45

2.0

0.8

Addresses Valid

2.0

0.8

UnitJEDEC Standard -55 -70 -90 -120 -150 -200 -255

applied.

CE#

t

CE

OE#

t

ACC

(Note 1)

Output

High Z

Notes:

1. OE# may be delayed up to t

is specified from OE# or CE#, whichever occurs first.

2. t

DF

– tOE after the falling edge of the addresses without impact on t

ACC

PACKAGE CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions

C

IN

C

OUT

Notes:

1. This parameter is only sampled and not 100% tested.
= +25°C, f = 1 MHz.

2. T

A

Input Capacitance VIN = 0 6 10 8 12 pF
Output Capacitance V

OUT

t

OE

t

OH

Valid Output

ACC

.

High Z

12082F-9

PD 028 PL 032

UnitTyp Max Typ Max

= 0 8 10 8 12 pF

tDF (Note 2)

8 Am27X256

PHYSICAL DIMENSIONS

PD 028—28-Pin Plastic Dual In-Line Package (measured in inches)

1.440

1.480

28

15

.600
.625

.530
.580

14

0°

10°

SEATING PLANE

.015
.060

.120
.160

.140
.225

Pin 1 I.D.

.045
.065

.090
.110

.005 MIN

.014
.022

PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485
.495

.009
.015

.125
.140

.080
.095

SEATING

PLANE

.013
.021

.050 REF.

SIDE VIEW

.585
.595

.447
.453

Pin 1 I.D.

.547
.553

.026
.032

TOP VIEW

.008
.015

.630
.700

16-038-SB-AG
PD 028
DG75
7-13-95 ae

.042
.056

.400

REF.

.490
.530

16-038FPO-5
PL 032
DA79
6-28-94 ae

Am27X256 9

REVISION SUMMARY FOR AM27X256
Revision F
Global

Changed formatting to match current data sheets.

Trademarks

Copyright © 1998 Advanced Micro D evices, Inc. All r ights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

10 Am27X256