Datasheet AM27C512-90PI, AM27C512-90PC, AM27C512-120PC, AM27C512-120JI, AM27C512-120JC Datasheet (AMD Advanced Micro Devices)

FINAL

Publication# 08140 Rev: I Amendment/0
Issue Date: May 1998

Am27C512

512 Kilobit (64 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

■ Fast access time

— Speed options as fast as 55 ns

■ Low power consumption

— 20 µA typical CMOS standby current

■ JEDEC-approved pinout

■ Single +5 V power supply

■ ±10% power supply tolerance standard

■ 100% Flashrite™ programming

— Typical programming time of 8 seconds

■ Latch-up protected to 100 mA from –1 V to

V

CC

+ 1 V

■ High noise immunity

■ Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility
— Two line control functions

■ Standard 28-pin DIP, PDIP, and 32-pin PLCC

packages

GENERAL DESCRIPTION

The Am27C512 is a 512-Kbit, ultraviolet erasable pro­grammable read-only memory. It is organized as 64K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.

Data can be typically accessed in less than 55 ns, al­lowing high-p erformance m icroproces sors to ope rate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,

thus eliminating bus contention in a mul tiple bus micro­processor system.

AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.

All signals are TTL levels, including programming sig­nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming alg orithm (100 µs pulses), re­sulting in a typical programming time of 8 seconds.

BLOCK DIAGRAM

08140I-1

A0–A15
Address

Inputs

CE#

OE#/V

PP

V

CC

V

SS

Data Outputs

DQ0–DQ7

Output
Buffers

Y

Gating

524,288

Bit Cell

Matrix

X

Decoder

Y

Decoder

Output Enable

Chip Enable

and

Prog Logic

2 Am27C512

PRODUCT SELECTOR GUIDE

CONNECTION DIAGRAMS
Top View

DIP PLCC

Notes:

1. JEDEC nomenclature is in parenthesis.

2. Don’t use (DU) for PLCC.

PIN DESIGNATIONS

A0–A15 = Address Inputs
CE# (E#) = Chip Enable Input
DQ0–DQ7 = Data Input/Outputs
OE# (G#)/V

PP

= Output Enable Input

Program Voltage Input

V

CC

=VCC Supply Voltage

V

SS

= Ground

NC = No Internal Connection

LOGIC SYMBOL

Family Part Number Am27C512

Speed Options

V

CC

= 5.0 V ± 5% -55 -255

V

CC

= 5.0 V ± 10% -55 -70 -90 -120 -150 -200
Max Access Time (ns) 55 70 90 120 150 200 250
CE# (E#) Access (ns) 55 70 90 120 150 200 250
OE# (G#) Access (ns) 35 40 40 50 50 50 50

3
4
5

2

1

9
10
11
12
13

23
22
21
20
19

7
8

18
17

6

28
27

16

14

26
25
24

15

A6
A5
A4
A3
A2
A1
A0

DQ0

A7

DQ1
DQ2

V

SS

A8
A9
A11
OE# (G#)/V

PP

A10
CE# (E#)
DQ7

V

CC

A14

DQ6

A13

DQ5
DQ4
DQ3

A15
A12

08140I-2

DQ5

DU

DQ4

DQ3

DU

13130234
5
6

7

8
9
10

11
12
13

17

18

19 2016

15

14

29
28
27

26
25
24
23
22
21

32
A6
A5
A4

A3
A2
A1
A0

NC

DQ0

A8
A9

A11

NC
OE# (G#)/V

PP

A10

CE# (E#)
DQ7
DQ6

A7

A12

A15

V

CC

A14

A13

DQ1

DQ2

V

SS

08140I-3

16

8

DQ0–DQ7

A0–A15

CE# (E#)

OE# (G#)/

V

PP

08140I-4

Am27C512 3

ORDERING INFORMATION
UV EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am27C512
512 Kilobit (65 K x 8-Bit) CMOS UV EPROM

AM27C512 -55 D C

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-In

TEMPERATURE RANGE

C = Commercial (0°C to +70

°C)

I=Industrial (–40

°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

D = 28-Pin Ceramic DIP (CDV028)

SPEED OPTION

See Product Selector Guide and Valid Combinations

B

Valid Combinations

AM27C512-55

V

CC

= 5.0 V ± 5%

DC

AM27C512-55

V

CC

= 5.0 V ± 10%

DC, DCB

AM27C512-70

DC, DCB, DI, DIB

AM27C512-90

AM27C512-120

DC, DCB, DI, DIB, DE, DEBAM27C512-150
AM27C512-200
AM27C512-255

V

CC

= 5.0 V ± 5%

DC, DCB, DI, DIB

4 Am27C512

ORDERING INFORMATION
OTP EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DES CR IP TIO N

Am27C512
512 Kilobit (65 K x 8-Bit) CMOS OTP EPROM

AM27C512 -70 P C

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C = Commercial (0

°C to +70°C)

I=Industrial (–40

°C to +85°C)

PACKAGE TYPE

P = 28-Pin Plastic DIP (PD 028)
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM27C512-55

V

CC

= 5.0 V ± 5%

AM27C512-55

V

CC

= 5.0 V ± 5%

JC, PC

AM27C512-70

JC, PC, JI, PI

AM27C512-90
AM27C512-120
AM27C512-150
AM27C512-200
AM27C512-255

V

CC

= 5.0 V ± 5%

Am27C512 5

FUNCTIONAL DESCRIPTION
Device Erasure

In order to clear all locations of their programmed con­tents, the device m ust be exp osed to an ultra violet light
source. A dosage of 15 W seconds/cm

2

is required to

completely erase the device. This dosage can be ob-

tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm

2

for 15 to 20
minutes. The device shoul d be directly under and about
one inch from the source, and all filters should be re­moved from the UV light source prior to erasure.

Note that all UV erasable devices will erase with light
sources having wav elengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex­posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.

Device Programming

Upon delivery, or after each erasure, the device has
all of its bits in t he “ONE”, or HIGH s tate . “ZER Os” are
loaded into the device through the programming pro­cedure.

The device enters the programming mode when 12.75
V ± 0.25 V is applied to the OE#/V

PP

pin, and CE# is at

V

IL

.

For programming, the data to be programmed is ap­plied 8 bits in parallel to the data pins.

The flowchart in the Programming section of the
EPROM Products Data Book (Section 5, Figure 5-1)
shows AMD’s Flashrite algorithm. The F lashrite algo­rithm reduces programming time by using a 100 µs pro­gramming pulse and by giving each address only as
many pulses to reliably program the data. After each
pulse is applied to a given address, the data in that ad­dress is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process i s repeated while se­quencing through each address of the device. This part
of the algorithm is done at V

CC

= 6.25 V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at V

CC

= VPP =

5.25 V.
Please refer to Section 5 of the EPR OM Products Data

Book for additional programming inf ormation and spec­ifications.

Program Inhibit

Programming different data to multiple devices in par­allel is easily accomplished. Except for CE#, all like in­puts of the devices may be common. A TTL low-level
program pulse applied to one dev ice’s CE# input with

OE#/V

PP

= 12.75 V ± 0.25 V, will program that particu­lar device. A high-level CE# input inhibits the other de­vices from being programmed.

Program Verify

A verification should be performed on the programmed
bits to determine that they were correctly progr ammed.
The verify should be perf ormed with OE#/V

PP

and CE#

at V

IL

, and VPP between 12.5 V and 13.0 V.

Autoselect Mode

The autosel ect mode provides ma nufacturer and de­vice identification through iden tifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro­grammed with its correspo nding programming algo­rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro­gramming the device.

To activate this mode, the programming equipment
must force V

H

on address line A9. Two identifier bytes
may then be sequenced from the de vice outputs b y tog­gling address line A0 from V

IL

to V

IH

(that is, changing
the address from 00h to 01h). All other address lines
must be held at V

IL

during the autoselect mode.

Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = V

IH

), the device identifier code. Both

codes have odd parity, with DQ7 as the parity bit.

Read Mode

T o obtain dat a at the device o utputs, Chip Enable ( CE#)
and Output Enable (OE#/V

PP

) must be driven low . CE#
controls the power to the de vice and is typically used to
select the device. OE#/V

PP

enables the device to out­put data, independent of device selection. Addresses
must be stable for at least t

ACC–tOE.

Refer to the

Switching Waveforms section for the timing diagram.

Standby Mode

The device enters the CMOS standby mode when CE#
is at V

CC

± 0.3 V. Maximum V

CC

current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at V

IH

. Maximum V

CC

current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen­dent of the OE# input.

Output OR-Tieing

To accommodate multiple memor y connections, a
two-line control function provides:

■ Low memory power dissipation, and

■ Assurance that output bus content ion will not occ ur .

CE# should be decoded and used as the primary de­vice-selecting function, while OE#/V

PP

be made a com-

6 Am27C512

mon connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low-power standby mode and that the out­put pins are only active when data is desired from a
particular memory device.

System Applications

During the switch between a ctive and standby condi­tions, transient current peaks are produced on the ris­ing and falling edges of Chip Enab le. The magnitude of

these transient current peaks is dependent on the out­put capacitance loading of the de vi ce. At a minim um, a

0.1 µF ceramic capacitor (high frequency, low inherent
inductance) sho uld be used on each device between
V

CC

and VSS to minimize transient effe cts. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit boar d traces on EPROM ar­rays, a 4.7 µF bul k electrolytic capacitor should be used
between V

CC

and VSS for each eight de vices. The loca­tion of the capacitor should be close to where the
power supply is connected to the array.

MODE SELECT TABLE

Notes:

1. V

H

= 12.0 V ± 0.5 V.

2. X = Either V

IH

or VIL.

3. A1–A8 and A10–15 = V

IL

4. See DC Programming Characteristics for VPP voltage during programming.

Mode CE# OE#/V

PP

A0 A9 Outputs

Read V

IL

V

IL

XXD

OUT

Output Disable X V

IH

X X High Z

Standby (TTL) V

IH

X X X High Z

Standby (CMOS) V

CC

± 0.3 V X X X High Z

Program V

IL

V

PP

XXD

IN

Program Verify V

IL

V

IL

XXD

OUT

Program Inhibit V

IH

V

PP

X X High Z

Autoselect
(Note 3)

Manufacturer Code V

IL

V

IL

V

IL

V

H

01h

Device Code V

IL

V

IL

V

IH

V

H

91h

Am27C512 7

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C

All Other Products . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to V

SS

All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V

A9 and VPP (Note 2) . . . . . . . . . . . . .–0.6 V to 13.5 V

V

CC

(Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V

Notes:

1. Minimum DC voltage o n input or I/O pins –0.5 V. During
voltage transitions, the input may overshoot V

SS

to –2.0 V
for periods of up to 20 ns. Max imum DC voltage o n inp ut
and I/O pins is V

CC

+ 5 V . During voltage transitions, input

and I/O pins may overshoot to V

CC

+ 2.0 V for periods up

to 20 ns.

2. Minimum DC input voltage on A9 is –0.5 V . During voltage
transitions, A9 and V

PP

may overshoot V

SS

to –2.0 V for

periods of up to 20 ns. A9 and V

PP

must not exceed +13.5

V at any time.

Stresses above those listed under “Abso lute Maximum Rat­ings” may cause per mane nt dam age to the device. This is a
stress rating only; fun ctio nal ope ration of t he d evice at these
or any other condition s above those indicated in the opera­tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

A

) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T

A

) . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Ambient Temperature (T

A

) . . . . . . . .–55°C to +125°C

Supply Read Voltages

V

CC

for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

V

CC

for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

8 Am27C512

DC CHARACTERISTICS over operating range (unless otherwise specified)

Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:

1. V

CC

must be applied simultaneously or before VPP, and removed simultaneously or after VPP..

2. I

CC1

is tested with OE# = V

IH

to simulate open outputs.

3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is V

CC

+ 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

Figure 1. Typical Supply Current vs. Frequency

V

CC

= 5.5 V, T = 25°C

Figure 2. Typical Supply Current vs. Temperature

VCC = 5.5 V, f = 10 MHz

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

V

OH

Output HIGH Voltage IOH = –400 µA 2.4 V

V

OL

Output LOW Voltage IOL = 2.1 mA 0.45 V

V

IH

Input HIGH Voltage 2.0 VCC + 0.5 V

V

IL

Input LOW Voltage –0.5 +0.8 V

I

LI

Input Load Current VIN = 0 V to V

CC

1.0 µA

I

LO

Output Leakage Current V

OUT

= 0 V to V

CC

C/I Devices 1.0

µA

E Devices 5.0

I

CC1

VCC Active Current (Note 2) CE# = VIL, f = 10 MHz,

I

OUT

= 0 mA

25 mA

I

CC2

VCC TTL Standby Current CE# = V

IH

1.0 mA

I

CC3

VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA

08140I-5

12345678910

30

25

20

15

10

Frequency in MHz

Supply Current

in mA

08140I-6

–75 –50 –55 0 25 50 75 100 125 150

30

25

20

15

10

Tem peratu re in °C

Supply Current

in mA

Am27C512 9

TEST CONDITIONS

Table 1. Test Specifications

SWITCHING TEST WAVEFORM

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

C

L

6.2 kΩ

5.0 V

Device

Under

Test

08140I-7

Figure 3. Test Setup

Note:

Diodes are IN3064 or equivalents.

Test Condition -55

All

others Unit

Output Load 1 TTL gate
Output Load Capacitance, C

L

(including jig capacitance)

30 100 pF

Input Rise and Fall Times ≤ 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement
reference levels

1.5 0.8, 2.0 V

Output timing measurement
reference levels

1.5 0.8, 2.0 V

2.4 V

0.45 V
Input

Output

Te st Points

2.0 V

2.0 V

0.8 V

0.8 V

08140I-8

3 V

0 V

Input

Output

1.5 V

1.5 V

Te st Points

Note: For CL = 100 pF.Note: For CL = 30 pF.

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

10 Am27C512

AC CHARACTERISTICS

Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or V

CC

applied.

Notes:

1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS

Notes:

1. OE# may be delayed up to t

ACC

– tOE after the falling edge of the addresses without impact on t

ACC

.

2. t

DF

is specified from OE# or CE#, whichever occurs first.

PACKAGE CAPACITANCE

Notes:

1. This parameter is only sampled and not 100% tested.

2. T

A

= +25°C, f = 1 MHz.

Parameter Symbols

Description Test Setup

Am27C512

UnitJEDEC Standard -55 -70 -90 -120 -150 -200 -255

t

AVQV

t

ACC

Address to Output Delay

CE#,
OE# = V

IL

Max 55 70 90 120 150 200 250 ns

t

ELQV

t

CE

Chip Enable to Output Delay OE# = VILMax 55 70 90 120 150 200 250 ns

t

GLQV

t

OE

Output Enable to Output Delay CE# = VILMax 35 40 40 50 50 75 75 ns

t

EHQZ

t

GHQZ

t

DF

(Note 2)

Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First

Max 25 25 25 30 30 30 30 ns

t

AXQX

t

OH

Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First

Min0000000ns

Addresses

CE#

OE#

Output

08140I-9

Addresses Valid

High Z

High Z

t

CE

Valid Output

2.4

0.45

2.0

0.8

2.0

0.8

t

ACC

(Note 1)

t

OE

tDF (Note 2)

t

OH

Parameter Symbol

Parameter

Description Test Conditions

CDV028 PL 032 PD 028

UnitTyp Max Typ Max Typ Max

C

IN

Input Capacitance VIN = 0 10 12 9 12 6 10 pF

C

OUT

Output Capacitance V

OUT

= 0 1013912610pF

Am27C512 11

PHYSICAL DIMENSIONS*

CDV028—28-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

PD 028—28-Pin Plastic Dual In-Line Package (measured in inches)

TOP VIEW

SIDE VIEW

END VIEW

INDEX AND

TERMINAL NO. 1

I.D. AREA

.565
.605

1.435

1.490

.005 MIN

.045
.065

.014
.026

.100 BSC

.015
.060

.160
.220

.125
.200

BASE PLANE

SEATING PLANE

.300 BSC

.600
BSC

.008
.018

94°

105°

.700

MAX

16-000038H-3
CDV028
DF10
3-30-95 ae

DATUM D

CENTER PLANE

DATUM D

CENTER PLANE

1

UV Lens

Pin 1 I.D.

1.440

1.480

.530
.580

.005 MIN

.045
.065

.090
.110

.140
.225

.120
.160

.014
.022

SEATING PLANE

.015
.060

.630
.700

0°

10°

.600
.625

16-038-SB-AG
PD 028
DG75
7-13-95 ae

28

15

14

.008
.015

12 Am27C512

PHYSICAL DIMENSIONS

PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

l

REVISION SUMMARY FOR AM27C512
Revision I

Global

Changed formatting to match current data sheets.

Product Selector Guide

Added the -55 speed option for V

CC

= 5.0 V ± 10%.

Ordering Information—UV EPROM Products

Valid Combinations:

-55 speed option adde d. Combi­nations DI and DIB added for -70 and -90 speed op­tions.

Ordering Information—OTP EPROM Products

Valid Combinations:

Added speed options for -55 with

V

CC

= 5.0 V ± 5% and -55 with VCC = 5.0 V ± 10%.

Trademarks

Copyright © 1998 Advanced Micro D evices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

.050 REF.

.026
.032

TOP VIEW

Pin 1 I.D.

.485
.495

.447
.453

.585
.595

.547
.553

16-038FPO-5
PL 032
DA79
6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125
.140

.009
.015

.080
.095

.042
.056

.013
.021

.400

REF.

.490
.530