Datasheet ALD1721SA, ALD1721PA, ALD1721ESA, ALD1721EPA, ALD1721EDA Datasheet (Advanced Linear Devices Inc)

ADVANCED
LINEAR
DEVICES, INC.

ALD1721E/ALD1721

EPAD™ MICROPOWER OPERATIONAL AMPLIFIER

KEY FEATURES

• EPAD ( Electrically Programmable Analog Device)

• User programmable V

trimmer

OS

• Computer-assisted trimming

• Rail-to-rail input/output

• Compatible with standard EPAD Programmer

• High precision through in-system circuit precision trimming

• Reduces or eliminates V

, PSRR, CMRR and TCVOS errors

OS

• System level “calibration” capability

• Application Specific Programming mode

• In-System Programming mode

• Electrically programmable to compensate for
external component tolerances

• Achieves 0.01pA input bias current and 35

µV

input offset voltage simultaneously

• Compatible with industry standard pinout

GENERAL DESCRIPTION

The ALD1721E/ALD1721 is a monolithic rail-to-rail precision CMOS
operational amplifier with integrated user programmable EPAD (Electri­cally Programmable Analog Device) based offset voltage adjustment. The
ALD1721E/ALD1721 operational amplifier is a direct replacement of the
ALD1701 operational amplifier, with the added feature of user-program­mable offset voltage trimming resulting in significantly enhanced total
system performance and user flexibility. EPAD technology is an exclusive
ALD design which has been refined for analog applications where preci­sion voltage trimming is necessary to achieve a desired performance. It
utilizes CMOS FETs as in-circuit elements for trimming of offset voltage
bias characteristics with the aid of a personal computer under software
control. Once programmed, the set parameters are stored indefinitely
within the device even after power-down. EPAD offers the circuit designer
a convenient and cost-effective trimming solution for achieving the very
highest amplifier/system performance.

The ALD1721E/ALD1721 operational amplifier features rail-to-rail input
and output voltage ranges, tolerance to over-voltage input spikes of
300mV beyond supply rails, capacitive loading up to 50pF, extremely low
input currents of 0.01pA typical, high open loop voltage gain, useful
bandwidth of 700KHz, slew rate of 0.7 V/µs, and low typical supply current
of 120 uA.

BENEFITS

• Eliminates manual and elaborate
system trimming procedures

• Remote controlled automated trimming

• In-System Programming capability

• No external components

• No internal chopper clocking noise

• No chopper dynamic power dissipation

• Simple and cost effective

• Small package size

• Extremely small total functional
volume size

• Low system implementation cost

• Micropower and Low Voltage

APPLICATIONS

• Sensor interface circuits

• Transducer biasing circuits

• Capacitive and charge integration circuits

• Biochemical probe interface

• Signal conditioning

• Portable instruments

• High source impedance electrode
amplifiers

• Precision Sample and Hold amplifiers

• Precision current to voltage converter

• Error correction circuits

• Sensor compensation circuits

• Precision gain amplifiers

• Periodic In-system calibration

• System output level shifter

PIN CONFIGURATION

VE2

VE1

1

8

ORDERING INFORMATION

-IN

+IN

V

2

3

-

4

Operating Temperature Range

-55°C to +125°C0°C to +70°C0°C to +70°C
8-Pin 8-Pin 8-Pin

CERDIP Small Outline Plastic Dip
Package Package (SOIC) Package

ALD1721E DA ALD1721E SA ALD1721E PA
ALD1721 DA ALD1721 SA ALD1721 PA

* Contact factory for industrial temperature range

© 1998 Advanced Linear Devices, Inc. 415 T asman Drive, Sunnyvale, California 94089 -1706 Tel: [phone] Fax: [phone] http://www .aldinc.com

2

TOP VIEW

DA, PA, SA PACKAGE

+

7

V

OUT

6

5

N/C

FUNCTIONAL DESCRIPTION

The ALD1721E/ALD1721 uses EPADs as in-circuit elements
for trimming of offset voltage bias characteristics. Each
ALD1721E/ALD1721 has a pair of EPAD-based circuits
connected such that one circuit is used to adjust V
direction and the other circuit is used to adjust V

OS
OS

in one
in the

other direction.

Functional Description of ALD1721E

While each of the EPAD devices is a monotonically adjust­able programmable device, the V

of the ALD1721E can be

OS

adjusted many times in both directions. Once programmed,
the set V

levels are stored permanently, even when the

OS

device power is removed.
The ALD1721E provides the user with an operational ampli-

fier that can be trimmed with user application-specific pro­gramming or in-system programming conditions. User appli­cation-specific circuit programming refers to the situation
where the Total Input Offset Voltage of the ALD1721E can be
trimmed with the actual intended operating conditions.

The ALD1721E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage
program range, which is ideal for applications that require
electrical offset voltage programming.

For example, an application circuit may have +6V and -2.5V
power supplies, and the operational amplifier input is biased
at +0.7V, and the average operating temperature is at 55

°C.

The circuit can be wired up to these conditions within an
environmental chamber, and the ALD1721E can be inserted
into a test socket connected to this circuit while it is being
electrically trimmed. Any error in V
conditions can be automatically zeroed out. The Total V

due to these bias

OS

OS

error is now limited only by the adjustable range and the
stability of V
amplifier. Therefore, this Total V

, and the input noise voltage of the operational

OS

error now includes V

OS

OS

as VOS is traditionally specified; plus the VOS error contribu­tions from PSRR, CMRR, TCV
total V

error term (V

OS

OST

, and noise. Typically this

OS

) is approximately ±35µV for the

ALD1721E.
The V

contribution due to PSRR, CMRR, TCVOS and

OS

external components can be large for operational amplifiers
without trimming. Therefore the ALD1721E with EPAD trim­ming is able to provide much improved system performance
by reducing these other sources of error to provide signifi­cantly reduced V

OST.

In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD1721E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD1721E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD1721E offset voltage
from operating bias conditions accounted for, any residual

errors introduced by other circuit components, such as resis­tor or sensor induced voltage errors, can also be corrected.
In this way, the “in-system” circuit output can be adjusted to
a desired level eliminating other trimming components.

Functional Description of ALD1721

The ALD1721 is pre-programmed at the factory under stan­dard operating conditions for minimum equivalent input offset
voltage. The ALD1721 offers similar programmable features
as the ALD1721E, but with more limited offset voltage pro­gram range. It is intended for standard operational amplifier
applications where little or no electrical programming by the
user is necessary.

USER PROGRAMMABLE Vos FEATURE

Each ALD1721E/ALD1721 has two pins named VE1 and
VE2 which are internally connected to an internal offset bias
circuit. VE1/VE2 have initial typical values of 1.2 /1.7 Volt.
The voltage on these pins can be programmed using the ALD
E100 EPAD Programmer and the appropriate Adapter Mod­ule. The useful programming range of VE1 and VE2 is 1.2
Volt to 3.0 Volts. VE1 and VE2 pins are programming pins,
used during programming mode. The Programming pin is
used during electrical programming to inject charge into the
internal EPADs. Increases of VE1 decrease the offset volt­age while increases of VE2 increase the offset voltage of the
operational amplifier. The injected charge is permanently
stored and determines the offset voltage of the operational
amplifier. After programming, VE1 and VE2 terminals must
be left open to settle on a voltage determined by internal bias
currents.

During programming, the voltages on VE1 or VE2 are in­creased incrementally to set the offset voltage of the opera­tional amplifier to the desired V

. Note that desired VOS can

OS

be any value within the offset voltage programmable ranges,
and can be either zero, a positive value or a negative value.
This V

value can also be reprogrammed to a different

OS

value at a later time, provided that the useful VE1 or VE2
programming voltage range has not been exceeded. VE1 or
VE2 pins can also serve as capacitively coupled input pins.

Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.

While programming, V+, VE1 and VE2 pins may be alter­nately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires the
ALD1721E/ALD1721 application circuit to accommodate
these programming pulses. This can be accomplished by
adding resistors at certain appropriate circuit nodes. For
more information, see Application Note AN1700.

2 Advanced Linear Devices ALD1721E/ALD1721

ABSOLUTE MAXIMUM RATINGS

Supply voltage, V

+

Differential input voltage range -0.3V to V
Power dissipation 600 mW
Operating temperature range PA,SA package 0°C to +70°C

DA package -55°C to +125°C
Storage temperature range -65°C to +150°C
Lead temperature, 10 seconds +260°C

13.2V
+

+0.3V

OPERATING ELECTRICAL CHARACTERISTICS
T

A

= 25

oC

V

= ±2.5V unless otherwise specified

S

1721E 1721

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Supply Voltage V

Initial Input Offset Voltage

Offset Voltage Program Range

1

2

Programmed Input Offset V
Voltage Error

Total Input Offset Voltage

Input Offset Current

Input Bias Current

Input Voltage Range

3

4

5

5

6

V

V

∆V

V

I

I

V

OS

B

S
+

OS i

OS

OS

OST

IR

±1.0 ±5.0 ±1.0 ±5.0 V

2.0 10.0 2.0 10.0 V Single Supply

35 75 50 150 µVR

≤ 100KΩ

S

±10 ±15 ±1 ±5mV

50 90 50 150 µV At user specified

target offset voltage

50 90 50 150 µV At user specified

target offset voltage

0.01 10 0.01 10 pA TA = 25°C
240 240 pA 0°C ≤ TA ≤ +70°C

0.01 10 0.01 10 pA TA = 25°C
240 240 pA 0°C ≤ TA ≤ +70°C

-0.3 5.3 -0.3 5.3 V V+ = +5V

-2.8 +2.8 -2.8 +2.8 V VS = ±2.5V

Input Resistance R

Input Offset Voltage Drift

7

IN

TCV

OS

Initial Power Supply PSRR
Rejection Ratio

8

Initial Common Mode CMRR
Rejection Ratio

Large Signal Voltage Gain A

8

V

14

10

57µV/°CRS ≤ 100KΩ

i

i

80 80 dB RS ≤ 100KΩ

83 83 dB RS ≤ 100KΩ

32 100 32 100 V/mV RL =100KΩ

10

14

Ω

20 20 V/mV 0°C ≤ TA ≤ +70°C

VO low 0.001 0.01 0.001 0.01 V RL =1MΩ V+ = 5V

Output Voltage Range VO high 4.99 4.999 4.99 4.999 V 0°C ≤ TA ≤ +70°C

VO low -2.48 -2.40 -2.48 -2.40 V RL =100KΩ
VO high 2.40 2.48 2.40 2.48 V 0°C ≤ TA ≤ +70°C

Output Short Circuit Current I

\* NOTES 1 through 9, see section titled "Definitions and Design Notes".

SC

11mA

ALD1721E/ALD1721 Advanced Linear Devices 3

OPERATING ELECTRICAL CHARACTERISTICS (cont'd)

oC

= 25

T

A

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

V

= ±2.5V unless otherwise specified

S

1721E 1721

Supply Current I

Power Dissipation P

Input Capacitance C

Maximum Load Capacitance C

Equivalent Input Noise Voltage e

Equivalent Input Current Noise i

Bandwidth B

Slew Rate S

Rise time t

Overshoot Factor 20 20 % RL = 100KΩ,

Settling Time t

S

D

IN

L

n

n

W

R

r

s

400 700 400 700 KHz

0.3 0.7 0.3 0.7 V/µsA

120 200 120 200 µAV

0.6 1.00 0.6 1.00 mW VS = ±2.5V

11

50 50 pF

55 55 nV/√Hz f = 1KHz

0.6 0.6 fA/√Hz f =10Hz

0.2 0.2 µsR

10 10 µs 0.1%

pF

= 0V

IN

No Load

= +1

V

RL = 10KΩ

= 10KΩ

L

CL = 50pF

AV = 1,RL=100KΩ
CL = 50pF

A

= 25

oC

VS = ±2.5V unless otherwise specified

T

1721E 1721

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Average Long Term Input Offset ∆ V
Voltage Stability

Initial VE Voltage VE1 i, VE2

Programmable VE Range ∆VE1, ∆VE2 1.5 2.5 1.0 V

Programmed VE Voltage Error e(VE1-VE2) 0.1 0.1 %

VE Pin Leakage Current i

9

OS

∆ time 1000 hrs

i

eb

0.02 0.02 µV/

1.2 1.7 V

-5 -5 µA

4 Advanced Linear Devices ALD1721E/ALD1721

V

= ±2.5V -55°C ≤ T

S

≤ +125°C unless otherwise specified

A

1721E 1721

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Initial Input offset Voltage V

Input Offset Current I

Input Bias Current I

OS i

OS

B

Initial Power Supply PSRR
Rejection Ratio

8

Initial Common Mode CMRR
Rejection Ratio

Large Signal Voltage Gain A

8

V

i

i

15 50 15 50 V/mV RL = 100KΩ

0.5 0.8 mV RS ≤ 100KΩ

2.0 2.0 nA

2.0 2.0 nA

75 75 dB RS ≤ 100KΩ

83 83 dB RS ≤ 100KΩ

Output Voltage Range VO low -2.47 -2.40 -2.47 -2.40 V

VO high 2.35 2.45 2.35 2.45 V RL = 100KΩ

= 25

A

oC

VS = ±5.0V unless otherwise specified

T

1721E 1721

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Initial Power Supply PSRR
Rejection Ratio

8

i

83 83 dB RS ≤ 100KΩ

Initial Common Mode CMRR
Rejection Ratio

Large Signal Voltage Gain A

8

V

i

83 83 dB RS ≤ 100KΩ

250 250 V/mV RL = 100KΩ

Output Voltage Range VO low -4.98 -4.90 -4.98 -4.90 V RL = 100KΩ

VO high 4.90 4.98 4.90 4.98

Bandwidth B

Slew Rate S

W

R

1.0 1.0 MHz

1.0 1.0 V/µsAV = +1, CL = 50pF

ALD1721E/ALD1721 Advanced Linear Devices 5

TYPICAL PERFORMANCE CHARACTERISTICS

OUTPUT VOLTAGE SWING AS A FUNCTION

OF SUPPLY VOLTAGE

±6

±25°C ≤ TA ≤ +125°C

±5

R

= 100KΩ

L

±4

±3

±2

OUTPUT VOLTAGE SWING (V)

±1

0

±1 ±2 ±3 ±4 ±7±6±5

SUPPLY VOLTAGE (V)

INPUT BIAS CURRENT AS A FUNCTION

OF AMBIENT TEMPERATURE

1000

= ±2.5V

100

10

V

S

OPEN LOOP VOLTAGE GAIN AS A FUNCTION

OF SUPPLY VOLTAGE AND TEMPERATURE

1000

100

10

GAIN (V/mV)

OPEN LOOP VOLTAGE

1

0 ±2 ±4 ±6 ±8

SUPPLY VOLTAGE (V)

±55°C ≤ T
RL = 100KΩ

SUPPLY CURRENT AS A FUNCTION

OF SUPPLY VOLTAGE

500

400

300

INPUTS GROUNDED
OUTPUT UNLOADED

TA = -55°C

-25°C

≤ +125°C

A

+25°C

1.0

0.1

INPUT BIAS CURRENT (pA)

0.01

AMBIENT TEMPERATURE (°C)

ADJUSTMENT IN INPUT OFFSET VOLTAGE

AS A FUNCTION OF CHANGE IN VE1 AND VE2

10

8
6
4

(mV)

OS

2
0

-2

-4

VOLTAGE ∆V

-6

-8

CHANGE IN INPUT OFFSET

-10

0.0 0.25 0.5 0.75 1.0 1.25 1.50
CHANGE IN VE1 AND VE2 (V)

VE2

100-25 0 75 1255025-50

VE1

200

100

SUPPLY CURRENT (µA)

0

0 ±1 ±2 ±3 ±4 ±5 ±6

OPEN LOOP VOLTAGE GAIN

AS A FUNCTION OF FREQUENCY

120
100

80

60
40

GAIN (dB)

20

OPEN LOOP VOLTAGE

0

-20
1 10 100 1K 10K 1M 10M100K

SUPPLY VOLTAGE (V)

FREQUENCY (Hz)

+70°C

+125°C

VS = ±2.5V
T

= 25°C

A

6 Advanced Linear Devices ALD1721E/ALD1721

PHASE SHIFT IN DEGREES

0

45

90
135
180

TYPICAL PERFORMANCE CHARACTERISTICS

COMMON MODE INPUT VOLTAGE RANGE

AS A FUNCTION OF SUPPLY VOLTAGE

±7
±6

±5

TA = 25°C

±4

±3
±2

VOLTAGE RANGE (V)

COMMON MODE INPUT

±1

0

0 ±1 ±2 ±3 ±4 ±5 ±6 ±7

SUPPLY VOLTAGE (V)

OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE

1000

100

LARGE - SIGNAL TRANSIENT

RESPONSE

2V/div

500mV/div 5µs/div

VS = ±1.0V
TA = 25°C
RL = 100KΩ
CL = 50pF

SMALL - SIGNAL TRANSIENT

RESPONSE

100mV/div

= ±2.5V

V

S

T

= 25°C

A

R

= 100KΩ

L

C

= 50pF

L

10

GAIN (V/mV)

OPEN LOOP VOLTAGE

1

10K

100K 1M

LOAD RESISTANCE (Ω)

LARGE - SIGNAL TRANSIENT

RESPONSE

5V/div

2V/div 5µs/div

VS = ±2.5V

= 25°C

T

A

VS = ±2.5V
T

= 25°C

A

R

= 100KΩ

L

C

= 50pF

L

10M

100

EXAMPLE B:
V

AFTER EPAD

OST

80

PROGRAMMING

TARGET = -750µV

V

OST

60

40

PERCENTAGE OF UNITS (%)

20

0

-2000

-2500

20mV/div 2µs/div

DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE

BEFORE AND AFTER EPAD PROGRAMMING

EXAMPLE A:
V

AFTER EPAD

OST

PROGRAMMING

TARGET = 0.0µV

V

OST

V

BEFORE EPAD

OST

PROGRAMMING

-1500

-500

-1000
TOTAL INPUT OFFSET VOLTAGE (µV)

500

0

1000 1500 2000 2500

ALD1721E/ALD1721 Advanced Linear Devices 7

TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO

CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE

500

PSRR = 80 dB

400

300

200

100

CHANGE IN SUPPLY VOLTAGE (µV)

EQUIVALENT INPUT OFFSET VOLTAGE DUE TO

0

0

1

EXAMPLE A:
V

EPAD PROGRAMMED

OS

AT V

2

SUPPLY

3

= +5V

4

SUPPLY VOLTAGE (V)

6

5

EXAMPLE B:

EPAD

V

OS

PROGRAMMED
AT V

789 10

SUPPLY

= +8V

THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO

CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE

500

400

V

= ±5V

SUPPLY

CMRR = 80dB

300

EXAMPLE B:

EPAD

V

OS

PROGRAMMED

200

100

CHANGE IN COMMON MODE VOLTAGE (µV)

0

EQUIVALENT INPUT OFFSET VOLTAGE DUE TO

-5

AT V

= -4.3V

IN

-4

-3

EXAMPLE A:

EPAD PROGRAMMED

V

OS

= 0V

AT V

IN

-1

-2
COMMON MODE VOLTAGE (V)

0

EXAMPLE C:

EPAD PROGRAMMED

V

OS

= +5V

AT V

IN

1

2345

EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE

FOR A COMMON MODE VOLTAGE RANGE OF 0.5V

50

40

30

20

CMRR = 80dB

10

COMMON MODE VOLTAGE RANGE OF 0.5V

VOS EPAD
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V

CHANGE IN COMMON MODE VOLTAGE (µV)

0

EQUIVALENT INPUT OFFSET VOLTAGE DUE TO

-0.5

-0.4

-0.3

-0.2 -0.1
COMMON MODE VOLTAGE (V)

0.0

0.1

0.2 0.3 0.4 0.5

8 Advanced Linear Devices ALD1721E/ALD1721

APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING

Examples of applications where accumulated total input offset voltage from various

contributing sources is minimized under different sets of user-specified operating conditions

TOTAL INPUT OFFSET VOLTAGE (µV)

2500
2000

1500
1000

500

-500

-1000

-1500

-2000

-2500

2500
2000

1500
1000

500

BUDGET AFTER

V

OS

EPAD PROGRAMMING

0

VOS BUDGET BEFORE
EPAD PROGRAMMING

EXAMPLE A

VOS BUDGET BEFORE
EPAD PROGRAMMING

2500
2000

1500
1000

500

TOTAL INPUT OFFSET VOLTAGE (µV)

-500

-1000

-1500

-2000

-2500

2500
2000

1500
1000

500

+

X

VOS BUDGET AFTER
EPAD PROGRAMMING

0

VOS BUDGET BEFORE
EPAD PROGRAMMING

EXAMPLE B

VOS BUDGET AFTER
EPAD PROGRAMMING

+

X

TOTAL INPUT OFFSET VOLTAGE (µV)

-500

-1000

-1500

-2000

-2500

0

VOS BUDGET AFTER
EPAD PROGRAMMING

EXAMPLE C

+

X

Device input V
PSRR equivalent V

+

CMRR equivalent V
TA equivalent V
Noise equivalent V

X

External Error equivalent V

OS

OS

OS

OS

OS

OS

0

-500

-1000

-1500

TOTAL INPUT OFFSET VOLTAGE (µV)

-2000

-2500

Total Input VOS
after EPAD
Programming

+

X

VOS BUDGET BEFORE
EPAD PROGRAMMING

EXAMPLE D

ALD1721E/ALD1721 Advanced Linear Devices 9

DEFINITIONS AND DESIGN NOTES:

1. Initial Input Offset Voltage is the initial offset voltage of the
ALD1721E/ALD1721 operational amplifier when shipped from
the factory. The device has been pre-programmed and tested
for programmability.

2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjust­ment in either the positive or the negative direction of the input
offset voltage from an initial input offset voltage. The input
offset programming pins, VE1 or VE2, change the input offset
voltage in the negative or positive direction, respectively. User
specified target offset voltage can be any offset voltage within
this programming range.

3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.

4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usu­ally this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCV

and noise. It can also include errors

OS

introduced by external components, at a system level. Pro­grammed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.

5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.

6. Input Voltage Range is determined by two parallel comple­mentary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD1721E/
ALD1721, the switching point between the two stages occur at
approximately 1.5V below positive supply voltage.

7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.

8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
the offset voltage from PSRR and CMRR is set to zero under the
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.

9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125°C
extrapolated to T

A = 25 °C, assuming activation energy of

1.0eV. This parameter is sample tested.

ADDITIONAL DESIGN NOTES:

A. The ALD1721E/ALD1721 is internally compensated for unity
gain stability using a novel scheme which produces a single pole
role off in the gain characteristics while providing more than 70
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1721E/ALD1721 will typically drive 50pF of
external load capacitance.

B. The ALD1721E/ALD1721 has complementary p-channel
and n-channel input differential stages connected in parallel to
accomplish rail-to-rail input common mode voltage range. The
switching point between the two differential stages is 1.5V below
positive supply voltage. For applications such as inverting
amplifier or non-inverting amplifier with a gain larger than 2.5
(5V operation), the common mode voltage does not make
excursions below this switching point. However, this switching
does take place if the operational amplifier is connected as a rail­to-rail unity gain buffer and the design must allow for input offset
voltage variations.

C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the rail­to-rail input and output feature, makes the ALD1721E/ALD1721
an effective analog signal buffer for high source impedance
sensors, transducers, and other circuit networks.

D. The ALD1721E/ALD1721 has static discharge protection.
Care must be exercised when handling the device to avoid
strong static fields that may degrade a diode junction, causing
increased input leakage currents. The user is advised to power
up the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages not to exceed 0.3V of the
power supply voltage levels.

E. VE1 and VE2 are high impedance terminals, as the internal
bias currents are set very low to a few microamperes to
conserve power. For some applications, these terminals may
need to be shielded from external coupling sources. For ex­ample, digital signals running nearby may cause unwanted
offset voltage fluctuations. Care during the printed circuit board
layout to place ground traces around these pins and to isolate
them from digital lines will generally eliminate such coupling
effects. In addition, optional decoupling capacitors of 1000pF or
greater value can be added to VE1 and VE2 terminals.

F. The ALD1721E/ALD1721 is designed for use in low voltage,
micropower circuits. The maximum operating voltage during
normal operation should remain below 10 Volts at all times. Care
should be taken to insure that the application in which the device
is used do not experience any positive or negative transient
voltages that will cause any of the terminal voltages to exceed
this limit.

G. All inputs or unused pins except VE1 and VE2 pins should be
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins
is very high. If any of these pins are left undefined, they may
cause unwanted oscillation or intermittent excessive current
drain. As these devices are built with CMOS technology, normal
operating and storage temperature limits, ESD and latchup
handling precautions pertaining to CMOS device handling
should be observed.

10 Advanced Linear Devices ALD1721E/ALD1721