Datasheet AL1402 Datasheet (ALESS)

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General Description

The AL1402 OptoRec interface is designed
to decode the ADAT
and produce four stereo pairs of audio
data. Alesis ADAT
5,297,181.

Use of this product requires a license
agreement between manufacturer and
Alesis Studio Electronics. Details and
agreement information are available upon
request from Alesis Semiconductor or
Alesis Studio Electronics.

â

optical data stream

â

U.S. patent number

GND

Features

G

Compatible with ADATâType I and II
formats

G

4stereopairsasoutputsusing
standard ADC formats

G

4 user bit outputs to receive time-code,
MIDI data, etc.

G

Internal PLL generates required clocks
from optical data.

G

Word Clock input to synchronize
outputstouser’ssystem.

Applications

G

Receive information from ADAT
compatible devices.

VDD

â

MODE0

FMT0

FMT1

MODE1

OPDIGIN

SVCO

WDCLK

BCLK

OUT 1/2
OUT 3/4
OUT 5/6 OUT 7/8

Figure A. 24 pin SOIC

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DS1402-0702 12555 Jefferson Blvd., Suite 285

Los Angeles, CA 90066

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LINMODE
MUTE
ERROR
HOLDERR
OPDIGTHRU
DVCO
USER3
USER2
USER1
USER0

Table 1 Electrical Characteristics and Operating Conditions

Symbol Description Min Typ Max Units

Recommended Operating Conditions

V

DD

IDDMaster Supply Current, Master - 7.7 - mA
IDDSlave Supply Current, Slave - 5.4 - mA
GND Ground - 0.0 - V
Fs Sample rate 30 48 55 kHz
Temp

Supply Voltage 4.5 5.0 5.5 V

Temperature 0 25 70

°C

Inputs (WDCLK, FMT, OPDIGIN, MODE, LINMODE, MUTE, HOLDERR)

V

IH

V

IL

I

IH

I

IL

C

IN

Logical “1” input voltage 0.75 V

DD

Logical “0” input voltage - - 0.25 V

--V

DD

V
Logical “1” input current - - 1 uA
Logical “0” input current - - 1 uA
Logic Input Capacitance - 5 - pF

DD
DD

Outputs (WDCLK, DVCO, OPDIGTHRU, SVCO, BCLK, ERROR)

V

OH

V

OL

I

OH

I

OL

Logical “1” output voltage 0.9 V

DD

Logical “0” output voltage - - 0.1 V

--V

DD

V
Logical “1” output current - - -8 mA
Logical “0” output current - - 8 mA

DD
DD

Outputs (OUT, USER)

V

OH

V

OL

I

OH

I

OL

Logical “1” output voltage 0.9 V

DD

Logical “0” output voltage - - 0.1 V

--V

DD

V
Logical “1” output current - - -2 mA
Logical “0” output current - - 2 mA

DD

DD

Table 2 Pin Descriptions

Pin # Name Pin

Type

1GND PowerGroundpin
2 MODE0 Input Mode select
3 FMT0 Input Format select
4 FMT1 Input Format select
5 MODE1 Input Mode select
6 OPDIGIN Input Input from optical receiver

7SVCO Output
8 WDCLK I/O Input or output word clock, see Table 4, Modes (nominal 48KHz, Fs)

9 BCLK Output Bit clock (nominal 3.072MHz, 64 x Fs)
10 OUT 1/2 Output Channels 1 and 2 data output
11 OUT 3/4 Output Channels 3 and 4 data output
12 OUT 5/6 Output Channels 5 and 6 data output
13 OUT 7/8 Output Channels 7 and 8 data output
14 USER0 Output USER0 data bit output. Used to receive timecode
15 USER1 Output USER1 data bit output. Used to receive MIDI data.
16 USER2 Output USER2 data bit output. Reserved.
17 USER3 Output USER3 data bit output. Reserved.
18 DVCO Output Recovered clock from data stream(nominal 12.288MHz, 256 x Fs)
19 OPDIGTHRU Output OPDIGIN is regenerated and clocked out on this pin to allow daisy-chaining

20 HOLDERR Input
21 ERROR Output

22 MUTE Input If high, mutes outputs
23 LINMODE Input Tie high
24 V

DD

Power +5V power pin

Derived clock from WDCLK in slave mode; derived from DVCO in Master mode
(nominal 12.288MHz, 256x Fs)

If high, the ERROR pin stays high until th e cause of the error is removed AND
the HOLDERR pin goes low.
Indicates lack of input or failure to synchronize to data stream, mutes data
outputs but not clock outputs

Description

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Los Angeles, CA 90066

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Master and Slave Modes

Use

Master Mode:

All outputs are derived from the input
optical format data stream on the OPDIGIN
(pin 6). WDCLK is an output.

Slave Mode:

DAC outputs, USER outputs, BCLK and
SVCO outputs are synchronized to WDCLK,
which is an input.

In Slave mode, WDCLK may be at an
arbitrary phase with respect to the incoming
samplesofOPDIGIN,butifthefrequencies
aren’t identical samples will be dropped,
repeated, or garbled. Generally, identical
frequencies are achieved by either: using
DVCO (pin 18) as the source from which
WDCLK is generated, or creating OPDIGIN
from a source synchronized to WDCLK.

The AL1402 OptoRec interface has been
designed for ease of use and flexibility in
systems designed to interface to the ADAT

â

protocol. It supports both left and right
justified data formats for ease of integration
into existing devices as well as new devices.
These formats allow it to operate in parallel
with many standard ADC’s.

The designer uses the FMT0, FMT1, MODE0
and MODE1 pins to select the desired
format and mode.

The format pins are summarized in Table 3,
Formats. The A L1402 provides support for

â

both the ADAT
the ADAT

â

Type I format (16-bit) and

Type II format (20-bit). Data
output is 24 bit. Data input lengths up to
24 bits is supported.

â

USER0isusedtoreceivetheADAT

format
32-bit timcode; USER1 is used to receive
MIDI data (if the source device supports
these features). USER2 and USER3 are
reservedandshouldnotbeused.

Table 3 Formats

FMT1 FMT0 Format

0 0 OUT data is right justified, B CLK falls on changing WDCLK
0 1 OUT data is left justified, BCLK rises on changing WDCLK
1 0 Chip Reset
1 1 Gated BLCK, BCLK rises on changing WDCLK

Table 4 Modes

MODE1 MODE0 Mode

0 0 Master mode, WDCLK is an output
01
1 0 Reserved

1 1 Reserved

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Slave mode, WDCLK is an input. WDCLK MUST be derived from the same clock
supplying the source

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Los Angeles, CA 90066

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TIMING

WDCLK

Justified Mode is recommended for ADAT formats.

Figure C.

LEFT CHANNEL

OUT

USER

DS

DU

t

VALID

t

Figure B/Table 5 Output Delay

Symbol Min Typ Max Units

t

DU

t

DU

t

DS

t

DS

(Master)

(Slave)
(Master)
(Slave)

-10 2

-7 5

-10 0

-8 2

(Above specifications hold after 3900 WDCLK cycles of valid input at OPDIGIN)

27
30
25
27

nsec
nsec
nsec
nsec

one period WordClock

Output
Timing
Diagram

WDCLK

Left Just 24

ADAT Type II

ADAT Type I

BCLK (rising)

RightJust24

ADAT Type II

ADAT Type I

BCLK (falling)

Left Just 24

Gated BCLK

WDCLK

SVCO

DVCO

23

MSB

†

19

â

MSB

†

15

â

MSB

∗

†

â

†

â

23

MSB

0

23

MSB

19 0

MSB

15

MSB

0

0

0

00

23

MSB

19

MSB

15

MSB

0

23

MSB

0

0

23

MSB

19

MSB

15

MSB

Master Mode

2

1

34

5

2

1

34

5

124

126125 127 128

127125124 126 128

129

129

130

130

131

131

132

133

133

Slave Mode

InSlavemodeDVCOisnotphasealignedwithWDCLKandSVCO.

∗

MSB bit is sign extended to left of frame.

†

These diagrams represent how data would be framed from an ADAT type I

or type II device. They are not actual modes of the AL1402. The Left

0

0

0

0

255253252 254 256

256252132

254253 255

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Alesis Semiconductor

Los Angeles, CA 90066

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Table 6 Package Dimensions

Dimensions (Typical)

Mechanical Specification

Figure D. Mechanical Drawing

Inches Millimeters

A

1324

BC

1

7° nom

12

K

A .606” 15.40
B .295” 7.50
C .406” 10.30

D .100” 2.50

E .008” 0.20

F .025” 0.64
G .050” 1.27
H .017” 0.42

J .011” 0.27

K .352” 8.94

L .033” 0.83

Notes:

1) Dimension “A” does not include mold
flash, protrusions or gate burrs.

D

E

G

F

H

4° nom

J

L

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Los Angeles, CA 90066

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Sample Application Schematic

+5V

TORX173*

OPTICAL IN

5

OUTPUT

VCC

GND1
GND2

6

TOTX173*

1

3

2
4

C_LIMIT

OPTICAL OUT

+5V

47uH

0.1uF

0.1uF
5

NC
INPUT

VCC

GND

NC

6

+5V

+5V

4
3

8.2k

2
1

WDCLK

RESET

OPTOGEN

19

4
5

6

NC 3

OPDGOUT

WDCLK
RESET

WDCLKNEG

NCNC 2
NC

VDD

GND

+5V

IN 1/2
IN 3/4
IN 5/6
IN 7/8

USER0
USER1
USER2
USER3

FMT0
FMT1
FMT2
FMT3

11
12
13
14

15
16
17
18
7
8
9
10

0.1uF

0.1uF

IN 1/2
IN 3/4
IN 5/6
IN 7/8

TIME CODE

MIDI DATA

+5V

20

1

OPTOREC

24

ERROR

6
3
4

21
20

23

2
5

22

OPDIGIN
FMT0
FMT1

ERROR
HOLDERR

LINMODE
MODE0

MODE1
MUTE

VDD

OPDIGTHRU

GND

1

OUT 1/2
OUT 3/4
OUT 5/6
OUT 7/8

USER0
USER1
USER2
USER3

DVCO

SVCO

WDCLK

BCLK

19
10
11
12
13

14
15
16
17
18
7
8
9

OPDIGTHRU
OUT 1/2
OUT 3/4
OUT 5/6
OUT 7/8

TIME CODE

NC
NC

SVCO (Master Mode, can be MCLK)

MIDI DATA

DVCO

WDCLK (Slave Mode)
WDCLK (Master Mode)

BCLK (Master Mode)

* Optical I/O parts shown are Toshiba parts. The Sharp GP1F33RT or equivalent is also compatible.

LEFTOUT

RIGHTOUT

INL/R

WDCLK

BCLK

MCLK

LEFTIN

RIGHTIN

OUTL/R

WDCLK

BCLK

MCLK

DACADC

Figure E. OptoGen/OptoRec setup

The OptoGen accepts input from an ADC, then outputs the Alesis optical format. The
OptoRec accepts input in Alesis optical format, then outputs to a DAC.

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DS1402-0702 12555 Jefferson Blvd., Suite 285

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Application Notes

The clock and data outputs of the AL1402
are undefined after power-up until a proper
data stream is well established at OPDIGIN
(pin 6). The clock outputs may be running
at an uncontrolled frequency. In this case,
the ERROR pin will be high, indicating that
theoutputsareinvalid. Thismaybe
prevented by applying logic one to FORMAT1
(pin 4) and logic zero to FORMAT0 (pin 3) on
power-up. This resets the AL1402, stopping
the VCO clocks and muting the data output.
The FORMAT pins may then be set to the
value required in your system. Nevertheless
the AL1402 will synchronize and produce
proper outputs when proper and valid
inputs are provided, whether this reset
procedure is used or not.

The AL1402 in Master Mode can also
produce clock outputs running at
uncontrolled frequencies if the digital input
becomes unstable after stable use, due
mostly to poor connection of the optical
cable to the optical connector. If this is

unwanted in the system an external AND
implementation can be used to correct this.
The inverted error pin and the desired
AL1402 output clock are inputs to the AND
andthedesiredmutableclockisoutput.
This AND function will mute the selected
AL1402 clock when the error pin is high (i.e.
when unstable input is present at OpDigIn).
Care should be taken when running the
AL1402 with the AL1201 DAC as the
AL1201 DAC will output noise if the AL1402
WDCLK is at an uncontrolled VCO frequency
that is beyond the AL1201 maximum
frequency. The aforem entioned AND
function can be used to select the AL1402
WDCLK to be muted when invalid
OpDigInput is present before proceeding as
the AL1201 WDCLK. See Figure F. with the
AND function implemented with NAND
gates. In place of this circuit the ERROR pin
can be used as a mute select for any audio
output stage muting circuitry that may be

present in the system

.

Figure F. AL1402 –AL1201 CLK MUTE CIRCUIT.

Alesis Semiconductor

DS1402-0702 12555 Jefferson Blvd., Suite 285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

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NOTICE

Alesis Semiconductor reserves the right to make changes to their products or to discontinue any
product or service without notice. All products are sold subject to terms and conditions of sale
supplied at the time of order acknowledgement. Alesis Semiconductor assumes no responsibility
for the use of any circuits described herein, conveys no license under any patent or other right,
and makes no representation that the circuits are free of patent infringement. Information
contained here in are only for illustration purposes and may vary depending upon a user’s
specific application. While the information in this publication has been carefully checked, no
responsibility is assumed for inaccuracies.

Alesis Semiconductor products are not designed for use in any applications which involve
potential risks of death, personal injury, or severe property or environmental damage or life
support applications where the failure or malfunction of the product can reasonably be expected
to cause failure of the life support system or to significantly affect its safety or effectiveness.

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Contact Information:
Alesis Semiconductor

12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone: [phone]
Fax: [phone]

Email: [e-mail]

Copyright 2002 Alesis Semiconductor
Datasheet July 2002
Reproduction, in part or in whole, without the prior written consent of Alesis Semiconductor is
prohibited.

Alesis Semiconductor

DS1402-0702 12555 Jefferson Blvd., Suite 285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

-8-