Datasheet AL1401A Datasheet (ALESS)

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General Description

The AL1401A OptoGen interface is
designed to accept four stereo pairs of
audio data and produce the data stream

â

appropriatefortheAlesisADAT
format, U.S. patent number 5,297,181.

Use of this product requires a license
agreement between manufacturer and
Alesis Studio Electronics. Details and
agreement information are available upon
request from Alesis Semiconductor or
Alesis Studio Electronics.

optical

GND

Features

G

Compatible with ADATâType I and II
formats

G

4 stereo pairs as inputs using standard
DAC formats

G

4 user bit inputs to transmit time­code, MIDI data, etc.

G

Internal PLL generates required clocks
from Word Clock.

Applications

G

Transmit information to ADAT
compatible devices

VDD

â

N/C
N/C

WDCLK

RESET

WDCLKNEG

FMT0

FMT1
FMT2
FMT3

OPDIGOUT
USER3

USER2
USER1
USER0
IN 7/8
IN 5/6
IN 3/4
IN 1/2

Figure A. 24 pin SOIC

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

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Table 1. Electrical Characteristics and Operating Conditions

Symbol Description Min Typ Max Units

Electrical Characteristics and Operating Conditions

V

DD

I

DD

GND Ground - 0.0 - V
Fs Sample rate 30 48 55 kHz
Temp Temperature

Outputs (OPDIGOUT)

V

OH

V

OL

I

OH

I

OL

Inputs (WDCLK, WDCLKNEG, FMT, IN, USER, RESET)

V

IH

V

IL

I

IH

I

IL

C

IN

Supply Voltage 4.5 5.0 5.5 V
Supply Current - 1.5 - mA

Logical “1” output
voltage
Logical “0” output
voltage
Logical “1” output
current
Logical “0” output
current

Logical “1” input
voltage
Logical “0” input
voltage
Logical “1” input
current
Logical “0” input
current
Logic Input
Capacitance

02570

0.9 V

DD

--V

--0.1V

---8mA

--8mA

0.75 V

DD

--V

--0.25V

--1uA

--1uA

-5-pF

°C

DDVDD

DDVDD

DD

DD

Table 2. Pin Descriptions

Pin # Name Pin Type Description

1GND Power
2N/C ­3N/C ­4WDCLK Input
5RESET Input
6WDCLKNEG Input
7FMT0 Input
8FMT1 Input

9FMT2 Input
10 FMT3 Input
11 IN 1/2 Input
12 IN 3/4 Input
13 IN 5/6 Input
14 IN 7/8 Input
15 USER0 Input
16 USER1 Input
17 USER2 Input
18 USER3 Input
19 OPDIGOUT Output
20 V

DD

Power

Ground pin
No connection
No connection
Word clock. Equal to sample frequency (Fs)
Active low reset
Sets phase of word clock
Format0, Sets data format
Format1. Sets data format
Format2. Sets data format
Format3. Sets data format
Channels1and2datainput
Channels3and4datainput
Channels5and6datainput
Channels7and8datainput
User 0 data bit input. Used to transmit timecode.
User 1 data bit input. Used to transmit MIDI data.
User 2 data bit input. Reserved, tie low.
User 3 data bit input. Reserved, tie low.
Output to optical driver
+5V power pin

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

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Table 3. Formats

Format0 Format1 Format2 Format3 Mode

000016-bitrightjustified
100018-bitrightjustified
010020-bitrightjustified
110022-bitrightjustified
0 0 1 0 16-bit left justified
1 0 1 0 18-bit left justified
0 1 1 0 20-bit left justified
1 1 1 0 22-bit left justified
0 0 0 1 Reserved
1 0 0 1 Reserved
0 1 0 1 Reserved
1 1 0 1 Reserved
001124-bitrightjustified
1 0 1 1 24-bit left justified
0 1 1 1 Reserved
1111Mute

one period WordClock, WordNeg Low

WordClock
Right Just 16
Right Just 18
Right Just 20
Right Just 22

Left Just 16
Left Just 18
Left Just 20
Left Just 22

Right Just 24

Left Just 24

15

MSB

17

MSB

19

MSB

21

MSB

23

MSB

15

MSB

17

MSB

19

MSB

21

0

0

MSB

0

MSB

0

0

0

0

0

023

15

MSB

17

MSB

MSB

21

MSB

23

MSB

0

0

0190

23

MSB

21

MSB

0

19

MSB

0

17

MSB

15

MSB

0

0

0

0

0

Figure B. Format Timing

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

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Figure C/Table 4. Input Timing

Symbol Description Min Typ Max Units

t

SI

t

HI

t

SU

t

HU

Setup of IN relative to center of bit period - 10
Hold of IN relative to center of bit period - 10
Setup of USER relative to end of right channel WDCLK time - ­Hold of USER relative to end of right channel WDCLK time - -

(Above specifications hold after 2000 WDCLK cycles)

30

30
100
100

nsec
nsec
nsec
nsec

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

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Use

The AL1401A OptoGen interface has
been designed for ease of use and
flexibility in systems designed to
interface to the ADATâprotocol. It
supports both left and right justified
16, 18, 20, 22 and 24-bit data
formats for ease of integration into
existing devices as well as new
devices. These formats allow it to
operate in parallel with many
standard DACs.

The designer uses the WDCLKNEG,
Format0, Format1, Format2 and
Format3 pins to select the desired
format.

If WDCLKNEG is high, the falling
edge of WDCLK signals the start of a
new sample period. If low, the rising

edge of WDCLK signals the start of a
new sample period. In both cases,
the first sample data sent is the odd
numbered (left) channel. The second
is the even numbered (right) channel.
The format pins are summarized in
Table 3. The AL1401A provides
support for both the ADATâType I
format (16-bit) and the ADATâType
II format (20-bit).

USER0 is used to transmit the ADAT
format 32-bit timecode. USER1 is
used to transmit MIDI data. USER2
and USER3 are reserved and should
be tied low. User bits are sampled at
the WDCLK edge that indicates the
end of right channel data.

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

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Mechanical Specification

Table 5. Package Dimensions

Dimensions (Typical)

Figure D. Mec hanical Drawing

Inches Millimeters

A

1120

BC

1

10

A .504” 12.80
B .295” 7.50
C .406” 10.30

D .100” 2.50

E .008” 0.20

F .025” 0.64
G .050” 1.27
H .017” 0.42

J .011” 0.27

K .352” 8.94

L .033” 0.83

Notes:

1) Dimension “A” does not include
mold flash, protrusions or gate
burrs.

7° nom

D

E

G

F

H

4° nom

J

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

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K

L

Sample Application Schematic

+5V

TORX173*

OPTICAL IN

5

OUTPUT

VCC

GND1
GND2

6

TOTX173*

1

3

2
4

C_LIMIT

OPTICAL OUT

+5V

47uH

0.1uF

0.1uF
5

NC
INPUT

VCC

GND

NC

6

+5V

+5V

4
3

8.2k

2
1

WDCLK

RESET

OPTOGEN

19

4
5

6

NC 3

OPDGOUT

WDCLK
RESET

WDCLKNEG

NCNC 2
NC

VDD

GND

+5V

IN 1/2
IN 3/4
IN 5/6
IN 7/8

USER0
USER1
USER2
USER3

FMT0
FMT1
FMT2
FMT3

11
12
13
14

15
16
17
18
7
8
9
10

0.1uF

0.1uF

IN 1/2
IN 3/4
IN 5/6
IN 7/8

TIME CODE

MIDI DATA

+5V

20

1

OPTOREC

24

ERROR

6
3
4

21
20

23

2
5

22

OPDIGIN
FMT0
FMT1

ERROR
HOLDERR

LINMODE
MODE0

MODE1
MUTE

VDD

OPDIGTHRU

GND

1

OUT 1/2
OUT 3/4
OUT 5/6
OUT 7/8

USER0
USER1
USER2
USER3

DVCO

SVCO

WDCLK

BCLK

19
10
11
12
13

14
15
16
17
18
7
8
9

OPDIGTHRU
OUT 1/2
OUT 3/4
OUT 5/6
OUT 7/8

TIME CODE

NC
NC

SVCO (Master Mode, can be MCLK)

MIDI DATA

DVCO

WDCLK (Slave Mode)
WDCLK (Master Mode)

BCLK (Master Mode)

* Optical I/O parts shown are Toshiba parts. The Sharp GP1F33RT or equivalentis also compatible.

LEFTOUT

RIGHTOUT

INL/R

WDCLK

BCLK

MCLK

LEFTIN

RIGHTIN

OUTL/R

WDCLK

BCLK

MCLK

DACADC

Figure E. OptoGen/OptoRec setup

The OptoGen accepts input from an ADC, then outputs the Alesis optical format. The
OptoRec accepts input in Alesis optical format, then outputs to a DAC.

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

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NOTICE

Alesis Semiconductor reserves the right to mak e changes to their products or to discontinue any
product or service without notice. All products are sold subject to terms and conditions of sale
supplied at the time of order acknowledgement. Alesis Semiconductor assumes no responsibility
for the use of any circuits described herein, conveys no license under any patent or other right,
and makes no representati on that the circuits are free of patent infringement. Information
contained herein are only for illustration purposes and may vary depending upon a user’s
specific application. While the information in this publication has been carefully checked, no
responsibility is assumed for inaccuracies.

Alesis Semiconductor products are not designed for use in applications which involve potential
risks of death, personal injury, or severe property or environmental damage or life support
applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness.

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Contact Information:
Alesis Semiconductor

12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone: [phone]
Fax: [phone]

Email: [e-mail]

Copyright 2002 Alesis Semiconductor
Datasheet July 2002

Reproduction, in part or in whole, without the prior written consent of Alesis
Semiconductor is prohibited.

Alesis Semiconductor

DS1401A-0702 12555 Jefferson Blvd., Suite285

Los Angeles, CA 90066

Phone [phone] Fax [phone] www.alesis-semi.com

-8-