Page 1
ASAHI KASEI [AKD4562]
AKD4562
Evaluation board Rev.A for AK4562
GENERAL DESCRIPTION
AKD4562 is an evaluation board for the portable digital audio 20bit A/D and D/A converter, AK4562. The
AKD4562 can evaluate A/D converter D/A converter separately in addition to loopback mode (A/D →
D/A). The A/D section can be evaluated by interfacing with AKM’s DAC evaluation boards directly. The
AKD4562 has the interface with AKM’s wave generator using ROM data and AKM’s ADC evaluation
boards. Therefore, it’s easy to evaluate the D/A section. The AKD4562 also has the digital audio interface
and can achieve the interface with digital audio systems via opt-connector.
n Ordering guide
AKD4562 --- Evaluation board for AK4562
(Cable for connecting with printer port of IBM-AT,
compatible PC and control software are packed with this.)
FUNCTION
• Compatible with 2 types of interface
- Direct interface with AKM’s A/D & D/A converter evaluation boards
- DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
GND
LIN1/2
RIN1/2
VTVA
CS8412
(DIR)
Opt In
AK4562
LOUT1/2
ROUT1/2
AK4353
(DIT)
Opt Out
A/D, D/A Data
Control
Data
10pin Header
Figure 1. AKD4562 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
Clock
Generator
ROM Data
10pin Header
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ASAHI KASEI [AKD4562]
1. Evaluation Board Manual
n Input / Output circuits & Set-up jumper pin for Input / Output circuits
(1) LINE Block
(a) LIN1,2/RIN1,2 Input circuits
J2
LIN
R36
560
C38
10u
+
JP15
LIN
LIN1
LIN1
LIN2
LIN2
J4
RIN
R38
560
C41
10u
+
JP18
RIN
RIN1
RIN1
RIN2
RIN2
Figure 2. LIN1,2/RIN1,2 Input circuits
1. Analog signal is input to LIN1 and RIN1 pins via J2 and J4 connectors.
JP15
LIN
LIN1
LIN2
JP18
RIN
RIN1
RIN2
2. Analog signal is input to LIN2 and RIN2 pins via J2 and J4 connectors.
JP15
LIN
LIN1
LIN2
JP18
RIN
RIN1
RIN2
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ASAHI KASEI [AKD4562]
(b) LOUT1/ROUT1 and OPGAL/OPGAR Selection circuits
R34
LOUT1
OPGAL
ROUT1
OPGAR
LOUT1
OPGL
ROUT1
OPGR
+
+
C39
1u
JP17
OPGL
C43
1u
JP20
OPGR
+
C37
22u
+
C42
22u
+
C40
1u
+
C44
1u
R35
10k
R40
10k
220
R39
220
JP16
LIO
JP19
RIO
OPGL LOUT1OPGR
R37
560
ROUT1
R41
560
J3
LOUT1
J5
ROUT1
Figure 3. LOUT1/ROUT1 and OPGAL/OPGAR Selection circuits
1. Analog signal is input to OPGAL and OPGAR pins via J3 and J5 connectors.
JP16
LIO
JP17
OPGL
OPGLLOUT1
OPGLLOUT1
JP19
RIO
OPGRROUT1
JP20
OPGR
OPGRROUT1
2. Analog signal is output to LOUT1 and ROUT1 pins via J3 and J5 connectors.
JP16
LIO
JP17
OPGL
OPGLLOUT1
OPGLLOUT1
JP19
RIO
OPGRROUT1
JP20
OPGR
OPGRROUT1
3. Analog signal is input to OPGAL and OPGAR pins via LOUT1 and ROUT1 pins.
JP16
LIO
JP17
OPGL
JP19
RIO
JP20
OPGR
OPGLLOUT1
OPGLLOUT1
OPGRROUT1
OPGRROUT1
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ASAHI KASEI [AKD4562]
(2) Other Jumper pins
1. JP1 (CSN) : Selection of CSN pin
SSB : SSB mode.
AKM : AKM mode.
2. JP2 (SSB) : Selection of SSB mode or AKM mode
OPEN : AKM mode.
SHORT : SSB mode.
3. JP3 (TST) : Selection of TEST pin
OPEN : Normal mode.
SHORT : Test mode.
* Always open.
4. JP4 (GND) : Analog ground and Digital ground
OPEN : Separated.
SHORT : Common. (The connector “DGND” can be open.) <default>
5. JP5 (VT) : D2V and VT
OPEN : Separated. <default>
SHORT : Common. (The connector “VT” can be open.)
6. JP9 (SDTO) : SDTO of AK4562
Always open. It can be short for only evaluation mode “7) ”.
7. JP10 (MODE) : Setting mode of CS8412
OPEN : I
2
S compatible mode.
SHORT : 16 bit LSB justified.
* AKM assumes no responsibility for the trouble when using the above circuit examples.
n Operation sequence
1) Set up the power supply lines.
[VA] (orange) = 2.2 ∼ 3.0V : for VA of AK4562 (typ. 2.5V)
[VT] (orange) = 1.8 ∼ 3.0V : for VT of AK4562 (typ. 2.5V)
[D2V] (orange) = 1.8 ∼ 3.0V : for 74LVC541 (typ. 2.5V)
[D5V] (red) = 3.6 ∼ 5.0V : for logic (typ. 5.0V)
[AGND] (black) = 0V : for analog ground
[DGND] (black) = 0V : for logic ground
Each supply line should be distributed from the power supply unit.
VT and D2V must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
Note : This evaluation board corresponds to I
2
S compatible mode for evaluation of A/D.
3) Power on.
The AK4562 and AK4353 should be reset once bringing SW1, 2 “L” upon power-up.
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ASAHI KASEI [AKD4562]
JP13
R
R
n Evaluation mode
Applicable Evaluation Mode
1) Evaluation of loopback mode (default)
2) Evaluation of D/A using ideal sine wave generated by ROM data
3) Evaluation of D/A using A/D converted data
4) Evaluation of D/A using DIR (Optical Link)
5) Evaluation of A/D using D/A converted data
6) Evaluation of A/D using DIT (Optical Link)
7) All interface signals including master clock are fed externally.
6)
5)
AKD43XX
D/A Board
AKD4562
PORT2
10pin-Header
1)
1) Evaluation of loopback mode. <default>
Nothing should be connected to PORT3 and PORT4. In case of using external clock through a BNC
connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE). This mode corresponds to only I
compatible mode.
ADC
JP7
LRCK
DI
JP6
X_BCLK
64fs32fs
JP8
BCLK
PORT4
DIR
DIRADC
PORT3
10pin-Header
3)
2)
JP1 1
SDTI
ADC
PORT1
DI
DIT
CD Player
4)
AKD53XX
A/D Board
ROM Board
2
S
JP12
DIR
CLK
JP14
XTE
GNDVD
DIR
EXT
XTL
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ASAHI KASEI [AKD4562]
JP13
R
R
JP13
R
R
JP13
R
R
2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data.
Digital signals generated by AKD43XX are used. PORT3 is used for the interface with AKD43XX. Master
clock is sent from AKD4562 to AKD43XX and BCLK, LRCK, SDTI are sent from AKD43XX to
AKD4562. Nothing should be connected to PORT4. In case of using external clock through a BNC
connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
JP1 1
SDTI
JP12
DIR
CLK
JP14
XTE
64fs32fs
ADC
DI
3) Evaluation of D/A using A/D converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3. Nothing should be connected to PORT4. In case of using
external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP6
X_BCLK
64fs32fs
ADC
JP7
LRCK
DI
JP8
BCLK
4) Evaluation of D/A using DIR. (Optical link)
PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3. DIR (CS8412) corresponds to only I
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
DIRADC
ADC
DI
JP1 1
SDTI
DIRADC
ADC
DI
2
S compatible mode or 16 bit LSB justified.
JP1 1
SDTI
JP12
DIR
JP12
DIR
GNDVD
DIR
EXT
XTL
JP14
CLK
XTE
GNDVD
DIR
EXT
XTL
JP14
CLK
XTE
64fs32fs
ADC
DI
DIRADC
ADC
DI
GNDVD
DIR
EXT
XTL
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ASAHI KASEI [AKD4562]
JP13
R
R
JP13
R
R
JP13
R
R
5) Evaluation of A/D using D/A converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3. Nothing should be connected to PORT4.
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
JP1 1
SDTI
JP12
DIR
CLK
JP14
XTE
64fs32fs
6) Evaluation of A/D using DIT. (Optical link)
PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through
optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards on the
digital-amplifier which equips DIR input. Nothing should be connected PORT3 and PORT4. In case of
using external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE). DIT
(AK4353) corresponds to only I
JP6
X_BCLK
64fs32fs
7) All interfacing signals (MCLK, BCLK, LRCK) are fed from the external circuit through PORT3.
PORT3 is used. JP7, 8, 11 and 13 should be open.
JP6
X_BCLK
ADC
ADC
DI
JP7
LRCK
DI
JP7
LRCK
DIRADC
2
S compatible mode.
JP8
BCLK
DIRADC
JP8
BCLK
ADC
ADC
JP1 1
SDTI
JP1 1
SDTI
DI
DI
JP12
DIR
JP12
DIR
GNDVD
DIR
EXT
CLK
GNDVD
DIR
EXT
CLK
XTL
XTL
JP14
XTE
JP14
XTE
64fs32fs
ADC
DI
DIRADC
ADC
DI
GNDVD
DIR
EXT
XTL
n The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Power down of AK4562. Keep “H” during normal operation.
[SW2] (DIT): Power down of AK4353. Keep “H” during normal operation.
n Indication for LED
[LED1] (VERF): Monitor VERF pin of the CS8412. LED turns on when some error has occurred to CS8412.
[LED2] (PREM): Indicate whether the input data of CS8412 is pre-emphasized or not.
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ASAHI KASEI [AKD4562]
n Serial Control
The AK4562 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2
(CTRL) with PC by 10 wire flat cable packed with the AKD4562.
Connect
PC
10 wire
flat cable
10pin
10pin Header
Connector
Figure 4. Connect of 10 wire flat cable
CCLK
CDTI
AKD4562
CSN
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ASAHI KASEI [AKD4562]
2. Control Software Manual
n Set-up of evaluation board and control software
1. Set up the AKD4562 according to previous term.
2. Connect IBM-AT compatible PC with AKD4562 by 10-line type flat cable (packed with AKD4562). Take care of the
direction of 10pin header. (This control software does not operate on Windows NT, therefore please operate it on
Windows95/98.)
3. Insert the floppy-disk labeled “AKD4562 Control Program ver 1.0” into the floppy-disk drive.
4. Access the floppy-disk drive and double-click the icon of “AKD4562.exe” to set up the control program. This
software corresponds to only AKM mode.
5. Then please evaluate according to the follows.
n Explanation of each buttons
1. [Port Setup] : Set up the printer port.
2. [Reset] : Initialize the register of AK4562.
3. [Function1] : Dialog to write data by keyboard operation.
4. [Function2] : Dialog to evaluate IPGA and OPGA.
5. [Write] : Dialog to write data by mouse operation.
Note : AK4353(DIT) is fixed to MCLK=256fs and I
AK4562’s ADC, it is necessary for AK4562 to set up MCLK=256fs and I
2
S compatible mode. Therefore, in the case of evaluation for
2
S compatible mode.
n Explanation of each dialog
1. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input register address in 2 figures of hexadecimal.
Data Box: Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4562, click “OK” button. If not, click “Cancel” button.
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ASAHI KASEI [AKD4562]
2. [Function2 Dialog] : Dialog to evaluate IPGA and OPGA
This dialog corresponds to only addr=03H and 04H.
Address Box: Input register address in 2 figures of hexadecimal.
Start Data Box: Input start data in 2 figures of hexadecimal.
End Data Box: Input end data in 2 figures of hexadecimal.
Interval Box: Data is written to AK4562 by this interval.
Step Box: Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 0 7 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4562, click “OK” button. If not, click “Cancel” button.
3. [Write Dialog] : Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data becomes
“H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4562, click “OK” button. If not, click “Cancel” button.
n Operation flow
Keep the following flow surely
1. Set up the control program according to explanation above.
2. Click “Port Setup” button.
3. Click “Write default” button.
4. Then set up the dialog and input data.
.
n Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
n Attention on the operation
If you set up Function1 or Function2 dialog, input data to all boxes. Attention dialog is indicated if you input data or
address that is not specified in the datasheet or you click “OK” button before you input data. In that case set up the dialog
and input data once more again. These operations does not need if you click “Cancel” button or check the check box.
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ASAHI KASEI [AKD4562]
MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit : Audio Precision, System Two
• MCLK : 256fs
• BCLK : 64fs
• fs : 44.1kHz
• Bit : 20bit
• Power Supply : VA=VD=VT=2.5V
• Interface : DIR/DIT
• Temperature : Room
[Measurement Results]
Parameter Input pin Results (Lch / Rch) Unit
ADC Analog Input Characteristics
S/(N+D) (-0.5dB Input)
D-Range (A-weighted)
S/N (A-weighted)
Interchannel Isolation
DAC Analog Output Characteristics
S/(N+D) - 89.5 / 89.5 dB
D-Range (A-weighted) - 93.0 / 93.0 dB
S/N (A-weighted) - 93.2 / 93.2 dB
Interchannel Isolation - 109.5 / 108.7 dB
Output PGA Characteristics (OPGA)
S/(N+D) OPGAL / OPGAR 91.7 / 91.7 dB
S/N (A-weighted) OPGAL / OPGAR 94.2 / 94.2 dB
Noise level at Mute (A-weighted) OPGAL / OPGAR 108.5 / 108.6 dB
LIN1 / RIN1
LIN2 / RIN2
LIN1 / RIN1
LIN2 / RIN2
LIN1 / RIN1
LIN2 / RIN2
LIN1 / RIN1
LIN2 / RIN2
85.3 / 84.8
85.4 / 84.7
88.6 / 88.6
88.6 / 88.6
88.6 / 88.6
88.6 / 88.6
109.6 / 108.7
109.7 / 109.8
dB
dB
dB
dB
dB
dB
dB
dB
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ASAHI KASEI [AKD4562]
[ADC Plot]
AKM AK4562 THD+N vs. Input Level
VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz
-70
-73
-76
-79
-82
d
B
-85
F
S
-88
-91
-94
-97
-100
-120 -10-110 -100 -90 -80 -70 -60 -50 -40 -30 -20
dBr
Figure 1. THD+N vs. Input Level
AKM AK4562 THD+N vs. Input Frequency
VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr
-70
-73
-76
-79
-82
d
B
-85
F
S
-88
-91
-94
-97
-100
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 2. THD+N vs. Input Frequency
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ASAHI KASEI [AKD4562]
AKM AK4562 Linearity
VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz
+0
-20
-40
d
B
-60
F
S
-80
-100
-120
-120 +0-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBr
Figure 3. Linearity
AKM AK4562 Frequency Response
VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr
+0
-0.2
-0.4
-0.6
-0.8
d
B
F
S
-1
-1.2
-1.4
-1.6
-1.8
-2
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 4. Frequency Response
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ASAHI KASEI [AKD4562]
AKM AK4562 Crosstalk
VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr
-90
-95
-100
-105
d
-110
B
-115
-120
-125
-130
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 5. Crosstalk
AKM AK4562 FFT Plot
VA=VD=VT=2.5V, fs=44.1kHz, Input=-0.5dBr, fin=1kHz
+0
-20
-40
-60
d
B
-80
F
S
-100
-120
-140
-160
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 6. FFT Plot
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ASAHI KASEI [AKD4562]
AKM AK4562 FFT Plot
VA=VD=VT=2.5V, fs=44.1kHz, Input=-60dBr, fin=1kHz
+0
-20
-40
-60
d
B
-80
F
S
-100
-120
-140
-160
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 7. FFT Plot
AKM AK4562 FFT Plot
VA=VD=VT=2.5V, fs=44.1kHz, fin=None
+0
-20
-40
-60
d
B
-80
F
S
-100
-120
-140
-160
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 8. FFT Plot
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ASAHI KASEI [AKD4562]
[DAC Plot]
AKM AK4562 THD+N vs. Input Level
VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz
-70
-73
-76
-79
d
-82
B
-85
r
-88
A
-91
-94
-97
-100
-120 +0-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 1. THD+N vs. Input Level
AKM AK4562 THD+N vs. Input Frequency
VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS
-80
-82
-84
-86
d
-88
B
-90
r
-92
A
-94
-96
-98
-100
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 2. THD+N vs. Input Frequency
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ASAHI KASEI [AKD4562]
AKM AK4562 Linearity
VA=VD=VT=2.5V, fs=44.1kHz, fin=1kHz
+0
-20
-40
d
B
-60
r
A
-80
-100
-120
-120 +0-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 3. Linearity
AKM AK4562 Frequency Response
VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS
+0.5
+0.4
+0.3
+0.2
d
+0.1
B
+0
r
-0.1
A
-0.2
-0.3
-0.4
-0.5
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
Figure 4. Frequency Response
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ASAHI KASEI [AKD4562]
AKM AK4562 Crosstalk
VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS
-80
-85
-90
-95
-100
d
-105
B
-110
-115
-120
-125
-130
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 5. Crosstalk
AKM AK4562 FFT Plot
VA=VD=VT=2.5V, fs=44.1kHz, Input=0dBFS, fin=1kHz
+0
-20
-40
-60
d
B
-80
r
A
-100
-120
-140
-160
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 6. FFT Plot
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ASAHI KASEI [AKD4562]
AKM AK4562 FFT Plot
VA=VD=VT=2.5V, fs=44.1kHz, Input=-60dBFS, fin=1kHz
+0
-20
-40
-60
d
B
-80
r
A
-100
-120
-140
-160
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 7. FFT Plot
AKM AK4562 FFT Plot
VA=VD=VT=2.5V, fs=44.1kHz, fin=None
+0
-20
-40
-60
d
B
-80
r
A
-100
-120
-140
-160
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 8. FFT Plot
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A
B
C
D
E
CN1
40
41
42
43
44
45
46
47
48
49
50
51
E E
52
R1
51
CN2
D D
C C
B B
1
2
3
4
5
6
7
8
9
10
11
12
13
C4
2.2u
U1
28
ROUT1
1
OPGAR
2
LOUT2
3
ROUT2
4
LIN1
5
RIN1
6
LIN2
7
RIN2
VCOM
8
+
C5
0.1u
26
27
LOUT1
OPGAL
AK4562
AGND
VA
9
10
C1
0.1u
C6
10u
+
25
11
R9
10
SSB
VREF
24
PDN
VD
12
23
13
CSN
DGND
C2
0.1u
C7
10u
22
CCLK
21
CDTI
20
LRCK
19
MCLK
18
TST
17
BCLK
16
SDTI
15
SDTO
VT
14
C3
0.1u
C8
10u
+
+
R2
51
R3
51
R4
51
R5
51
R6
51
R7
51
R8
51
CN3
39
38
37
36
35
34
33
32
31
30
29
28
27
A A
A
CN4
14
15
16
17
18
19
20
21
22
23
24
25
26
Title
Size Document Number Rev
A3
B
C
D
Date: Sheet
AKD4562
AK4562 Sub
E
A
of
11Wednesday, February 02, 2000
Page 21
A
B
C
D
E
D2V
ROUT1
OPGAR
JP4
LIN1
RIN1
LIN2
RIN2
GND
AGNDDGND
49
50
51
52
U1
NC
NC
1
NC
2
NC
3
LOUT2
4
ROUT2
5
NC
6
NC
7
LIN1
8
RIN1
9
NC
10
LIN2
11
RIN2
12
NC
13
NC
NC
NC
14
15
C6
2.2u
ROUT1
OPGAR
VCOM
NC
16
17
+
C7
0.1u
E E
D D
LOUT2
ROUT2
C C
B B
VA
L3
1 2
A A
A
C13
47u
(short)
+
OPGAL
LOUT1
45
46
47
48
NC
OPGAL
LOUT1
NC
AK4562
AGND
VA
VREF
18
19
C3
0.1u
+
C8
10u
B
NC
20
21
R12
10
SSB
R1
51
40
41
42
43
44
NC
SSB
PDN
VD
DGND
22
23
C4
C5
0.1u
0.1u
+
C9
10u
NC
CSN
39
NC
38
NC
R4 51
37
CCLK
R5 51
36
CDTI
35
NC
R6 51
34
LRCK
R7 51
33
MCLK
32
TST
31
BCLK
30
SDTI
29
SDTO
28
NC
27
NC
VT
NC
24
NC
25
26
VT
L2
1 2
+
C10
10u
10u
+
C11
47u
C
R8 51
R9 51
R10 51
JP5
VT
TST
SDTO
D2V
CSN1
SSB
AKM
D
JP1
CSN
C1
+
47u
1 2
L1
10u
C2
0.1u
D2V
D5V
21
3
VT
CSN
JP2
SSB
open = "L"
short = "H"
R2
47k
SSB
JP3
TST
open = "L"
short = "H"
R3
47k
TST
U2
11
Y8
12
Y7
13
Y6
14
Y5
15
Y4
16
Y3
17
Y2
18
Y1
10
GND
20
VCC
9
A8
8
A7
7
A6
6
A5
5
A4
4
A3
3
A2
2
A1
19
G2
1
G1
PDN
CSN
CCLK
CDTI
LRCK
MCLK
BCLK
SDTI
74LVC541
D1
1S1588
1
2
R11
10k
U3A
1 2
C12
0.1u
74HC14
HL
SW1
PDN
Title
Size Document Number Rev
A3
Date: Sheet
U3B
3 4
74HC14
AKD4562
AK4562
E
13Tuesday, June 13, 2000
PDN
A
of
Page 22
A
B
C
D
E
D5V
PORT1
45
IN5
3
VCC
2
IF
6
SDTO
D5V
LED2
PREM
GND
DIT
LED1
VERF
1
21
R31
1k
DIR_LRCK
DIR_BCLK
R13
C14
1k
0.1u
C16
0.1u
C15
+
10u
SDTO1
JP9
SDTO
R29
1k
L5
1 2
10u
U7
1
C
2
Cd/F1
3
Cc/F0
4
Cb/E2
5
Ca/E1
6
C0/E0
7
VD+
8
DGND
9
RXP
10
RXN
11
FSYNC
12
SCK
13
CS12/FCK
14 15
U CBL
B
U3F
74HC14
CS8412
1
2
3
4
5
6
7
8
9
10
11
12 13
R22
51
R23 51
R24 51
1312
28
VERF
27
Ce/F2
26
SDATA
25
ERF
24
M1
23
M0
22
VA+
21
AGND
20
FILT
19
MCK
18
M2
17
M3
16
SEL
R19
5.1
U4
MCKO
TX
DVDD
DVSS
MCKI
BICK
SDTI
LRCK
PDN
CSN
SCL/CCLK
SDA/CDTI TST
AVDD
VCOM
AOUTL
AOUTR
AK4353
CDTI
CCLK
CSN1
SDTO1
JP11
ADC
SDTI
DIR
M1
M0/2
AVSS
CAD0
CAD1
R18
51
D5V
C18
0.1u
24
DZF
23
NC
22
21
20
19
18
17
16
15
I2C
14
TTL
D5V
R25
1k
C20
0.1u
C19
+
10u
+
C21
10u
U5
10
CLK
Q1
Q2
11
RST
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
74HC4040
PORT2
1
10
CSN
2
9
CCLK / SCK
CDTI / SSI
3
8
4567
CTRL
9
7
6
5
3
2
4
fs
13
12
14
15
1
JP6
64fs
X_BCLK
32fs
X_BCLK
X_LRCK
D2V
C26
0.1u
M0/2
for SN74LVC07A
U6A
SN74LVC07A
SDTI
12
MCLK
JP13
CLK
DIR
XTL
EXT
C27
10u
+
C28
0.1u
C34
R32
47n
1k
C
U8C
74HCU04
56
U8B
74HCU04
34
R33
51
J1
EXT
SDTO
X1
11.2896MHz
R30
1M
U8A
74HCU04
C29
(open)
D
12
12
M1
JP14
XTE
C30
(open)
Title
Size Document Number Rev
Date: Sheet
6
E E
D D
C C
D5V
21
LH
3
X_LRCK
DIR_LRCK
X_BCLK
DIR_BCLK
D2
1S1588
1
2
BCLK
LRCK
SW2
DIT
ADC
DIR
ADC
DIR
R17
10k
C17
0.1u
JP7
LRCK
JP8
BCLK
U3C
74HC14
5 6
MCLK
BCLK
LRCK
SDTI
ROM
U3D
74HC14
9 8
PORT3
1
2
3
4
5 6
10
9
8
7
ROM
R26
10k
D5V
JP12
B B
R28
1k
DIR
VDGND
D5V
12
L6
PORT4
6
GND
6
VCC
GND
5
OUT
5
A A
DIR
47u
C35
0.1u
2 1
4
3
2
1
C31
0.1u
C32
+
10u
C33
0.01u
C36
0.01u
A
D5V
R14
10k
R20
51
R21
51
for 74HCU04, 74HC14, 74HC4040
C23
0.1u
U3E
74HC14
AKD4562
A3
R15
10k
C24
0.1u
1110
Interface
R16
10k
1 2
C25
0.1u
D5V
E
L4
10u
JP10
MODE
R27
47k
D5V
23Monday, January 24, 2000
CSN1
CCLK
CDTI
+
C22
47u
short = "H"
open = "L"
of
A
Page 23
A
E E
D D
C C
J2
LIN
J4
RIN
C38
10u
+
R36
560
C41
10u
+
R38
560
JP15
LIN
JP18
RIN
B
LIN1
LIN2
RIN1
RIN2
LIN1
LIN2
RIN1
RIN2
C
LOUT1
+
C37
C39
22u
+
1u
R35
10k
LOUT1
OPGL
JP17
OPGL
+
C40
1u
+
C42
22u
C43
+
1u
R40
10k
OPGAL
ROUT1
ROUT1
OPGR
JP20
OPGR
+
C44
1u
OPGAR
D
R34
220
J3
JP16
LIO
R37
560
R39
220
ROUT1OPGR LOUT1OPGL
JP19
RIO
R41
560
LOUT1
J5
ROUT1
E
R42
LOUT2
B B
ROUT2
A A
A
+
C45
22u
+
C46
22u
220
R43
10k
R44
220
R45
10k
B
J6
LOUT2
J7
ROUT2
U8D
74HCU04
98
U8E
74HCU04
1110
U8F
74HCU04
1312
C
U6B
SN74LVC07A
34
U6D
SN74LVC07A
98
U6F
SN74LVC07A
1312
D
U6C
SN74LVC07A
5 6
U6E
SN74LVC07A
11 10
Title
Size Document Number Rev
A3
Date: Sheet
AKD4562
Input/Output
E
of
33Tuesday, December 21, 1999
A
Page 24
Page 25
Page 26
Page 27
Page 28
Page 29
Page 30
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use
or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use,
except with the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
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