Datasheet AK9813AF Datasheet (AKM)

ASAHI KASEI [AK9813A]

AK9813A

12ch 8bit D/A Converter with EEPROM

General Description

The AK9813A includes 12 channel, 8bit D/A converters with on-chip output buffer amps and it is capable to
store the input digital data of each DAC by on-chip non-volatile CMOS EEPROM. The AK9813A is optim al ly
designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for
replacing mechanical trimmers.

Features

EEPROM SECTION



•

12 words Õ 8bit Õ 4 organization for DAC

D/A converter section



•

12 channels

•

Resolution : 8bit

•

DNL : -1a+2 LSB

•

INL : 1.5 LSB

•

Analog Output Voltage Range : GND a VCC

Operating Voltage Range



•

Digital section : 2.7Va5.5V

•

Analog section : 5.0V0.5V,3.3V0.3V

24pin VSOP



Block Diagram

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ASAHI KASEI [AK9813A]

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Ordering Guide

AK9813AF -10 to +85°C 24-pinVSOP

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ýPin Layout

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ASAHI KASEI [AK9813A]

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ýPin Description(1)

No. Pin Name I/O Function

20 DI I Serial Data Input Pin

SEL=High : 16bit data input format
SEL=Low : 14bit data input format

17 DO O

(SEL=High:CS I/F)
AK9813A reads out the data with LSB first in the 16bit
shift register to DO pin synchronously with falling
edge of CLK.
When the CS pin is high level, the DO pin becomes high
impedance. In STATUS mode, the DO pin outputs Ready/Busy
status.
(SEL=Low:LD I/F)
AK9813A reads out the data with MSB first in the 14bit
shift register to DO pin synchronously with falling
edge of CLK.
In WRITE mode, the DO pin outputs Ready/Busy status.

19 CLK I Shift Clock Input Pin(Schmitt-trigger input)

AK9813A takes in the data from DI pin synchronously with
rising edge of the CLK pin. The data are transferred to
the internal shift register.

18 CS/LD I

Chip Select Input Pin(Schmitt-trigger input)
The CS/LD is internally pulled up to VCC.

(SEL=High:CS I/F)
After the CS pin changes from high level to low level
while the CLK pin is high level, the AK9813A can input
the data to the internal shift register and takes in
the data from the DI pin synchronously with the rising
edge of the CLK pin.
After the CS pin changes from high level to low level
while the CLK pin is low level, the AK9813A becomes the
status mode and reads out the Ready/Busy status to the
DO pin.
When the CS pin changes from low level to high level
regardless of Low/High level of the CLK pin, the AK9813A
removes from the status mode to the normal mode. The CS
pin usually should be kept at high level.
(SEL=Low:LD I/F)
When the LD pin receives high pulse, the data of the
internal shift register is transferred to the internal
decoder or the register for D/A. The LD pin usually
should be kept at low level.

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ASAHI KASEI [AK9813A]

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Pin Description(2)

No. Pin Name I/O Function

1

AO1

|

12

|
AO12

O 8bit D/A outputs with OP-AMP

14 Vcc - Digital section Power Supply Pin
23 GND - Digital section Ground Pin
13 Vdd - OP-AMP and D/A section Power Supply
24 Vss - OP-AMP and D/A section Ground
2122 EA0

EA1

(SEL=High:CS I/F)

I

In AUTO READ operation and ECL operation, the address
of EEPROM is selected by the EA0 and the EA1 pins.
(SEL=Low:LD I/F)
The address of EEPROM is selected by the EA0 and the
EA1 pins.

16 ECL I When the ECL pin receives high pulse, the data in

EEPROM is automatically loaded to each corresponding
D/A, starting from AO1 to AO12 in order. Then each D/A
output is settled to pre-determined value.

15 SEL I Input Data Format Select Pin

SEL=High : CS I/F
SEL=Low : LD I/F
After power-up, this pin should be kept either at "high"
or "Low."

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ASAHI KASEI [AK9813A]

Data Configuration

AK9813A have a shift register in order to control the chip.
When the SEL pin is "H"(CS I/F), the shift register becomes 16bit configuration and the data on the DI pin
should be loaded with LSB first. When the SEL pin is "L"(LD I/F), the shift register becomes 14bit
configuration and the data on the DI pin is loaded with MSB first.
The following description shows the configuration of the shift register.
The data set consist of 2-bits for the control of the internal EEPROM, 2-bits for the address of the EEPROM
(CS I/F only), 4-bits for select of D/A converter and 8-bits for the digital input data of the 8bit D/A converter and
total data set is 16bits or 14bits.

1

Shift register configuration : SEL=High(CS I/F)

{

OUTPUT VOLTAGE FOR D/A CONVERTER

D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE FOR D/A A1 A0 EEPROM ADDRESS

00000000 •=• GND=VSS 0 1 ADDRESS : 0
00000001
00000010

11111110

•

=• VDD/255 Õ 1

•

=• VDD/255 Õ 2

•

=• VDD/255 Õ 254

0 1 ADDRESS : 1
1 0 ADDRESS : 2
1 1 ADDRESS : 3

11111111 •=• VDD

D/A CONVERTER CHANNEL SELECTION

D11 D10 D9 D8 D/A CHANNEL D11 D10 D9 D8 D/A CHANNEL

0000 Don't Care 1000 AO8
0001 AO1 1001 AO9
0010 AO2 1010 AO10
0011 AO3 1011 AO11
0100 AO4 1100 AO12
0101 AO5 1101 Can't use
0110 AO6 1110 Can't use
0111 AO7 1111 Don't Care

(NOTE) Above "Don't care" state is valid only when AK9813A is in DAC mode or WRITE mode.
Refer to the following section "Instruction Set" about mode.

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ASAHI KASEI [AK9813A]

2

Shift register configuration:SEL=Low(LD I/F)

{

OUTPUT VOLTAGE FOR D/A CONVERTER

D0 D1 D2 D3 D4 D5 D6 D7 OUTPUT VOLTAGE FOR D/A EA1 EA0 EEPROM ADDRESS

00000000
10000000
01000000

01111111
11111111

•

=• GND=VSS

•

=• VDD/255 Õ 1

•

=• VDD/255 Õ 2

•

=• VDD/255 Õ 254

•

=• VDD

0 0 ADDRESS : 0
0 1 ADDRESS : 1
1 0 ADDRESS : 2
1 1 ADDRESS : 3

NOTE)
EEPROM ADDRESS is selected

by the EA0 and EA1 pins.

D/A CONVERTER CHANNEL SELECTION

D8 D9 D10 D11 D/A CHANNEL D8 D9 D10 D11 D/A CHANNEL

0000 Don't Care 1000 AO8
0001 AO1 1001 AO9
0010 AO2 1010 AO10
0011 AO3 1011 AO11
0100 AO4 1100 AO12
0101 AO5 1101 CAN'T USE
0110 AO6 1110 CAN'T USE
0111 AO7 1111 Don't Care

(NOTE) Above "Don't care" state is valid only when AK9813A is in DAC mode or WRITE mode.
Refer to the following section "Instruction Set" about mode.

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ASAHI KASEI [AK9813A]

Instruction Set

The AK9813A can be controlled for the following mode. The following mode is common to the LD I/F and the
CS IF. When LD I/F is selected, "A1" and "A0" are set by the external pins (EA0 pin and EA1 pin).

1

DAC mode(External DI pin -> D/A converter) [Õ:Don't Care]

{

A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function

ÕÕ

2

CALL mode(Internal EEPROM -> D/A converter) [Õ:Don't Care]

{

0 0 D/A Channel Digital data for D/A D/A output

A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function

ADDRESS

1 0 D/A Channel

ХХХХХХХХ

READ

• The output of D/A converter is set by the data in the internal EEPROM.

3

ALL CALL mode(Internal EEPROM -> D/A converter) [Õ:Don't Care]

{

A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function

ADDRESS

100000

ХХХХХХХХ

ALL CHANNEL READ

• The outputs of all D/A converters are set by the data in the internal EEPROM.

• • •

Internal ECL funct ion

4

WRITE ENABLE mode(Internal EEPROM WRITE ENABLE) [Õ:Don't Care]

{

A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function

ÕÕ

110000

ХХХХХХХХ

WRITE ENABLE

• After WRITE ENABLE mode is executed, the programming to the internal EEPROM is enabled. Upon
power-up and after the execution of the ECL function, the AK9813A is in the programming disable state.

5

WRITE DISABLE mode(Internal EEPROM WRITE DISABLE) [Õ:Don't Care]

{

A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function

ÕÕ

111111

ХХХХХХХХ

WRITE DISABLE

• After WRITE DISABLE mode is executed, the programming to the internal EEPROM is disabled.

6

WRITE mode(External DI pin -> Internal EEPROM) [Õ:Don't Care]

{

A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function

ADDRESS

0 1 D/A Channel Digital data for D/A WRITE

• The digital data for D/A (D0aD7) is written into the specified address in the internal EEPROM. The state
of the internal EEPROM must be the programming enable state.

7

READ mode(Internal EEPROM -> External DO pin) [Õ:Don't Care]

{

A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function

ADDRESS

1 1 D/A Channel

ХХХХХХХХ

EEPROM DATA output

•The DO pin outputs the data in the internal EEPROM synchronously with the falling edge of of the input
pulse of the CLK pin.

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ASAHI KASEI [AK9813A]

Functional Description

1

Timing Diagram for CS I/F (SEL="H")

{

1.DAC mode:The internal EEPROM is not used.

2.WRITE ENABLE/DISABLE mode:The programming state of the internal EEPROM is set.

3.CALL mode: The output of the D/A is set by the data in the internal EEPROM.

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4.ALL CALL mode : The outputs of the all D/As are set by the data in the internal EEPROM.

•

The D/A outputs are set from AO1 to AO12 in order.

5.WRITE mode:The digital input data for D/A converter is written into the internal EEPROM.

6.READ mode:The data in the internal EEPROM is read from the DO pin.

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7.STATUS mode: The DO pin outputs the Ready/Busy status from the DO pin.

8.ECL function : For "H" pulse to the ECL pin, the data in the selected address in the internal EEPROM is

automatically loaded. Then each D/A converter output is settled to pre-determined value.

9. Transfer mode for the cascade connection

In case that AK9813A devices are connected in cascade, the AK9813A under programming cycle can transfer
the data to the other AK9813A. The some AK9813A devices can be operated by the common CS signal at the
same time.
Please note that the input data into to the AK9813A under programming cycle should be all"0" when the CS
pin is changed from "L" to "H". If data except all"0" is input into the AK9813A under programming cycle,
accidental data disturbance may occur.

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ASAHI KASEI [AK9813A]

2

Timing Diagram for LD I/F (SEL ="L")

{

1.DAC mode:The internal EEPROM is not used.

2.WRITE ENABLE/DISABLE mode:The programming state of internal EEPROM is set.

3.CALL mode: The output of the D/A is set by the data in the internal EEPROM.

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ASAHI KASEI [AK9813A]

4.ALL CALL mode : The outputs of the all D/As are set by the data in the internal EEPROM.

•

The D/A outputs are set from AO1 to AO12 in order.

5.WRITE mode:The digital input data for D/A converter is written into the internal EEPROM.

(NOTE)

In case that AK9813A devices are connected in cascade, when a AK9813A device is under programming

∗

cycle, the AK9813A device under programming cycle can not transfer the data to the other AK9813A device
and some AK9813A devices can not be operated by the common CS signal at the same time.

While programming cycle, the CS/LD pin should be "L".

∗

When the Ready/Busy signal from the DO pin is verified, the CS pin should be changed from "H" to "L" and

∗

kept at "L". If the CS pin is kept at "H", the Ready/Busy signal does not output correctly.

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ASAHI KASEI [AK9813A]

6.READ mode:The data in the internal EEPROM is read from the DO pin.

7.ECL function:

When the ECL pin received high pulse, the data in EEPROM is automatically loaded to each corresponding
D/A, and starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value.

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ASAHI KASEI [AK9813A]

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Spec. Units

Power Supply
Input Voltage
Ambient Temperature
Storage Temperature

VCC
VIO
Ta
TST

relative to GND
relative to GND

-0.3∼+6.5

-0.3∼VCC+0.3

-10∼+85

-65∼+150

V
V

C

°

C

°

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Conditions min typ max Units

Power Supply 1

VCC 2.7 5.5 V

(Digital section)

(DAC,AMP sections)
Analog Outpu t
Source Current 1
Analog Outpu t

VDD1 4.5 5.0 5.5 Power Supply 2
VDD2
IAL 1 mA

IAH

VDD≥VCC

VDD=5.0V0.5V

3.0 3.3 3.6

1mA

V

Sink Current 1
Analog Outpu t
Source Current 2
Analog Outpu t

IAL 500 uA

IAH

VDD=3.3V0.3V

500 uA
Sink Current 2
Analog Outpu t
Load Capacitance

AOC

0.8 1.0 uF

0.001 uFLoad Crcuit-A

Load Circuit-B 1.0 uF

•

Load Circuit-A

•

Load Circuit-B

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ASAHI KASEI [AK9813A]

ELECTRICAL CHARACTERISTICS

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DC Characteristics

(1)Digital Section

(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V0.3V(VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)

Parameter Symbol Pin Conditions min max Units

Power Suppl y

VCC 2.7 5.5 V
(Digital Section)
Operating Current

ICC VCC CLK=1MHz 1.5 mA
(READ) (1)(2)
Leakage Current ILI CLK,DI

VIN=VCC -10.0 10.0 uA
CS/LD
EA0,EA1
ECL,SEL

High Level
Input V oltage1
Low Level
Input V oltage1
High Level
Input V oltage2
Low Level Input

VIH 0.5ÕVCC V

DI

VIL

EA0,EA1

0.2ÕVCC V

ECL,SEL

VIH 0.6ÕVCC V

CS/LD
CLK

VIL

0.15ÕVCC V

Voltage2

4.5V≤VCC≤5.5V

IOH=-400uA

2.7V≤VCC<4.5V

VCC-0.4 VHigh Level

0.7ÕVCC V

Output V oltage

VOH1

VOH2

DO

IOH=-200uA

VOL1

Output V oltage

VOL2

4.5V≤VCC≤5.5V

IOL=1.0mA

2.7V≤VCC<4.5V

0.4 VLow Level

0.4 V

IOL=1.0mA

(1) All input pins are connected to either VCC or GND.
(2) DO=OPEN

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ASAHI KASEI [AK9813A]
(2)Analog Section

(2-1)VDD=5.0V0.5V

(VCC=2.7V∼5.5V,VDD=5.0V0.5V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)

Parameter Symbol Pin Conditions min typ max Units

Power Suppl y1

VDD1

VDD≥VCC

4.5 5.0 5.5 V
(Analog Section)
Power Dissipation1

IDD1

VDD

AO1∼AO12=OPEN

10.0 mA
(Analog Section)
Resolution Res 8 bits

Integral (3)

LE -1.5 1.5 LSB
Non-Linearity :INL
Differential

LE

D

AO1

|

AO12

AO1∼AO12=OPEN

0.05V≤AO
VDD-0.1V

≤

-1.0 2.0 LSB

Non-Linearity :DNL
Buff er-AMP Minimum
Output V oltage 1
Buff er-AMP Minimum
Output V oltage 2
Buff er-AMP Minimum

Output V oltage 3
Buff er-AMP Minimum
Output V oltage 4
Buff er-AMP Minimum
Output V oltage 5
Buffer-AMP Maximum

Output V oltage 1
Buffer-AMP Maximum
Output V oltage 2
Buffer-AMP Maximum
Output V oltage 3
Buffer-AMP Maximum

Output V oltage 4
Buffer-AMP Maximum
Output V oltage 5

VAOL1 IAL = 0uA

Data= 00(Hex)

VAOL2 IAL = 500uA

Data= 00(Hex)

VAOL3 IAH = 500uA

Data= 00(Hex)

VAOL4 IAL = 1mA

Data= 00(Hex)

VAOL5 IAH = 1mA

Data= 00(Hex)

VAOH1 IAH = 0uA

VAOH2 IAL = 500uA

AO1

|

AO12

Data= FF(Hex)

Data= FF(Hex)

VAOH3 IAH = 500uA

Data= FF(Hex)

VAOH4 IAL = 1mA

Data= FF(Hex)

VAOH5

IAH = 1mA
Data= FF(Hex)

GND 0.05 V

-0.1 0.1 V

GND 0.1 V

-0.2 0.2 V

GND 0.2 V

VDD-0.1 VDD V

VDD-0.2 VDD V

VDD-0.2 VDD+0.2 V

VDD-0.3 VDD V

VDD-0.3 VDD+0.3 V

(3) Integral Non-Linearity is the error between the actual line and the ideal line.

The ideal line exhibits a perfect linear D/A converter output characteristic between the input
digital data"00" and the input digital data"FF".

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ASAHI KASEI [AK9813A]
(2-2) VDD=3.3V0.3V

(VCC=2.7V∼3.6V,VDD=3.3V0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)

Parameter Symbol Pin Conditions min typ max Units
Power Supply 2
(Analog Section)
Power Dissipation2

VDD2

IDD2

VDD

VDD ≥ VCC

AO1∼AO12=OPEN

3.0 3.3 3.6 V

7.0 mA
(Analog Section)
Resolution Res 8 bits
Integral (3)

LE -1.5 1.5 LSB
Non-Linearity :INL
Differential

LE

D

AO1

|

AO12

AO1∼AO12=OPEN

0.15V≤AO
≤VDD-0.15V

-1.0 2.0 LSB
Non-Linearity :DNL
Output V oltage for
Input data "05"
Output V oltage for

AO1∼AO12=OPEN
VDD=3.3V

0.1 0.15 V

3.15 3.25 V
Input data "FA"
Buff er-AMP Minimum
Output V oltage 6
Buff er-AMP Minimum
Output V oltage 7
Buff er-AMP Minimum
Output V oltage 8
Buff er-AMP Minimum
Output V oltage 9
Buff er-AMP Minimum
Output V oltage 10
Buffer-AMP Maximum
Output V oltage 6
Buffer-AMP Maximum
Output V oltage 7
Buffer-AMP Maximum
Output V oltage 8
Buffer-AMP Maximum
Output V oltage 9
Buffer-AMP Maximum
Output V oltage 10

VAOL6 IAL = 0uA

Data= 00(Hex)

VAOL7 IAL = 250uA

Data= 00(Hex)

VAOL8 IAH = 250uA

Data= 00(Hex)

VAOL9 IAL = 500uA

Data= 00(Hex)

VAOL10 IAH = 500uA

Data= 00(Hex)

VAOH6 IAH = 0uA

VAOH7 IAL = 250uA

AO1

|

AO12

Data= FF(Hex)

Data= FF(Hex)

VAOH8 IAH = 250uA

Data= FF(Hex)

VAOH9 IAL = 500uA

Data= FF(Hex)

VAOH10

IAH = 500uA
Data= FF(Hex)

GND 0.05 V

-0.1 0.1 V

GND 0.1 V

-0.2 0.2 V

GND 0.2 V

VDD-0.1 VDD V

VDD-0.2 VDD V

VDD-0.2 VDD+0.2 V

VDD-0.3 VDD V

VDD-0.3 VDD+0.3 V

(3) Integral Non-Linearity is the error between the actual line and the ideal line.

The ideal line exhibits a perfect linear D/A converter output characteristics between the input digital
data"05" and the input digital data "FA".

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ASAHI KASEI [AK9813A]

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AC Characteristics

(1) CS I/F, LD I/F : Common Timing

(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)

Parameter Symbol Conditions min max Units
Vcc Rise Time tVCR 50 ms
Auto Address Hold Time tVAH 3.5 ms
Auto Read Time tPOR Test Load2 3.5 ms
ECL "H" Pulse Width tECW1

tECW2

*1
*2

100
250

ns

ns
External Call Time tECL Test Load2 3.5 ms
Address Set Up Time tESU1

tESU2

*1
*2

50

100

ns

ns
ECL Address Hold Time tEAH 3.5 ms
Repeat Call Prohibition Time tECC1

tECC2

*1
*2

20

100

ns

ns

*1:4.5V≤Vcc≤5.5V
*2:2.7V≤Vcc<4.5V

<AUTO READ>

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ASAHI KASEI [AK9813A]

(2)CS I/F Timing

(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V  0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)

Parameter Symbol Conditions min max Units

Clock "L" Pulse Width tCKL1

tCKL2

Clock "H" Pulse Width tCKH1

tCKH2
Clock Rising Time
Clock Falling Time

tCr

tCf 200 ns
Data Set Up Time tDSU1

tDSU2
Data Hold Time tDHD1

tDHD2
CS Set Up Time tCSU1

tCSU2

*5
*6
*5
*6

*5
*6
*5
*6
*5
*6

200
500
200
500

30

150

60
150
100
250

ns
ns
ns
ns

ns
ns
ns
ns
ns
ns

CS Hold Time tCCH 200 ns

CS "H" Hold Time tCSH

DAC etc *3,*4,*5
*3,*4,*6
WRITE *4,*5
*4,*6

100
250

10

15

ns

ns
ms
ms

CALL•READ 15 us
ALL CALL 3.5 ms

Data Output Enable Time tDOD1

tDOD2

Data Output Float Delay tDOZ1

tDOZ2

Data Output Delay tDOC1

tDOC2

D/A Output Setting Time

tCSD

*5
*6
*5
*6
Test Load1 *5
*6

200
500
200
500
170
300

ns

ns

ns

ns

ns

ns

DAC Test Load2 200 us
CALL Test Load2 250 us

ALL CALL Test Load2 3.5 ms
Status Set Up Time tSSU 100 ns
Status Hold Time tSHD1

tSHD2

*5

*6

100
250

ns

ns
*3: Please refer to "DAC etc" regarding CS "H" Hold Time before status mode execute.
*4: If READY/BUSY="H" is confirmed in status mode in the WRITE mode, the CS pin can be changed to

"L" shorter than the values specified on above.

Please refer to "DAC etc" regarding CS "H" Hold Time in case that AK9813 to be connected in cascade

is under programming cycle(READY/BUSY="L").
*5: 4.5V≤Vcc≤5.5V
*6: 2.7V≤Vcc<4.5V

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ASAHI KASEI [AK9813A]
<Input/Output Waveform>

<STATUS Output>

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ASAHI KASEI [AK9813A]
(3)LD I/F Timing

(VCC=2.7V∼5.5V,VDD=5.0V0.5V or 3.3V  0.3V (VDD≥VCC),GND,VSS=0V,Ta=-10∼85°C)

Parameter Symbol Conditions min max Units

Clock "L" Pulse Width tCKL1

tCKL2

Clock "H" Pulse Width tCKH1

tCKH2
Clock Rising Time
Clock Falling Time

tCr

tCf 200 ns
Data Set Up Time tDCH1

tDCH2
Data Hold Time tCHD1

tCHD2

*5
*6
*5
*6

200
500
200
500

*5
*630150
*5
*660150

ns
ns
ns
ns

ns
ns
ns

ns
Load Set Up Time tCHL 200 ns
Load Hold Time tLDC1

tLDC2

Load "H" Pulse Width

tLDH1
tLDH2

*5
*6
modes except *5
READ mode *6

100
250
100
250

ns

ns

ns

ns

tLDH3 READ mode 5 us

Data Output Delay tDO1

tDO2

D/A Output Setting Time

tLDDD

Test Load1 *5
Test Load1 *6

170
300

ns

ns

DAC Test Load2 200 us
CALL Test Load2 250 us
ALL CALL Test Load2 3.5 ms

Address Set Up Time tASU1

tASU2

Write Address Hold Time tWAHD1

tWAHD2

*5
*6

100

200
*5
*620100

ns
ns
ns

ns
Programming Cycle tWRT *7 15 ms
Ready Signal Delay tRYD Test Load1 0.4 us
Repeat Write Prohibition Time tRYH1

tRYH2

Test Load1 *5
Test Load2 *620100

ns

ns

CALL,READ mode 15 us Read Hold Time tRHD
ALL CALL mode 3.5 ms
CALL,READ mode 15 us Read Address Hold Time tRAHD
ALL CALL mode 3.5 ms

*7: If READY/BUSY="L" is confirmed in status mode in the WRITE mode, the next operation can be

started.

DAD03E-00 1999/05

- 21 -

ASAHI KASEI [AK9813A]
<Input/Output Waveform>

<Data Timing>

<Write mode>

* Please refer to the data timing regarding the input timing for the DI pin

DAD03E-00 1999/05

- 22 -

ASAHI KASEI [AK9813A]
<Call mode>

<All Call mode>
<Read mode>

* Please refer to the data timing regarding the input timing for the DI pin

* AC measurement circuit

Test Load1 • Test Load2

•

AC test point

•

•

Digital Input/Output Level : 50%
Analog Output Level : 90%

20% of Vcc

•

10% of Vcc

DAD03E-00 1999/05

- 23 -

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice. Before

considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.

z AKM assumes no liability for infringement of any patent, intellectual property, or other

right in the application or use of any information contained herein.

z Any export of these products, or devices or systems containing them, may require an

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Representative Director of AKM. As used here:

(a) A hazard related device or system is one designed or intended for life support or

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other fields, in which its failure to function or perf orm may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.

(b) A critical component is one whose fa ilure to function or per form may reasonably be

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