Page 1
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 1 -
GENERAL DESCRIPTION
The AK5383 is a 24bit, 128x oversampling 2ch A/D Converter for professional digital audio systems. The
modulator in the AK5383 uses the new developed Enhanced Dual Bit architecture. This new architecture
achieves the wide dynamic range, while keeping much the same superior distortion characteristics as
conventional Single Bit way. The AK5383 performs 110dB dynamic range, so the device is suitable for
professional studio equipment such as digital mixer, digital VTR etc.
FEATURES
p Enhanced Dual Bit ADC
p Sampling Rate: 1kHz~108kHz
p Full Differential Inputs
p S/(N+D): 103dB
p DR: 110dB
p S/N: 110dB
p High Performance Linear Phase Digital Anti-Alias filter
• Passband: 0~21.768kHz(@fs=48kHz)
• Ripple: 0.001dB
• Stopband: 110dB
p Digital HPF & Offset Calibration for Offset Cancel
p Power Supply: 5V±5%(Analog), 3~5.25V(Digital)
p Power Dissipation: 210mW
p Package: 28pin SOP, VSOP
p AK5393 Pin compatible
LRCK
VREFL
GNDL
SCLKSMODE1
FSYNC
Serial Output
Interface
SMODE2
DGNDVA
AGND
BGND
CAL
RST
VD
Controller
SDATA
MCLK
DFS
HPFE
ZCAL
AINR-
GNDR
Delta-Sigma
Modulator
Delta-Sigma
Modulator
Voltage
Reference
Voltage
Reference
Decimation
Filter
Decimation
Filter
HPF
HPF
Calibration
SRAM
VCOML
AINL+
AINL-
AINR+
VCOMR
VREFR
12 11 14 13
16
15
19
17
18
8
7
109
212223
27
28
26
24
25
6
5
4
3
2
1
Enhanced Dual Bit ∆Σ 96kHz 24-Bit ADC
AK5383
Page 2
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 2 -
n
Ordering Guide
AK5383VS –10 ~ +70°C 28pin SOP
AK5383VF –40 ~ +85°C 28pin VSOP
AKD5383 AK5383 Evaluation Board
n
Pin Layout
6
5
4
3
2
1
VREFL
GNDL
AINL+
VCOML
AINL-
ZCAL
VD 7
DGND
8
Top
View
10
9
CAL
RST
SMODE2 11
SMODE1 12
13
14
LRCK
SCLK
VREFR
GNDR
VCOMR
AINR+
AINR-
VA
AGND
BGND
TEST
HPFE
DFS
MCLK
23
24
25
26
27
28
22
21
19
20
18
17
16
15
FSYNC
SDATA
n Compatibility with AK5393
AK5393 AK5383
S/(N+D) 105dB 103dB
DR, S/N 117dB 110dB
Page 3
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 3 -
PIN/FUNCTION
No. Pin Name I/O Function
1 VREFL O Lch Reference Voltage Pin, 3.75V
Normally connected to GNDL with a 10µ F electrolytic capacitor and
a 0.1µF ceramic capacitor .
2 GNDL - Lch Reference Ground Pin, 0V
3 VCOML O Lch Common Voltage Pin, 2.75V
4 AINL+ I Lch Analog positive input Pin
5 AINL- I Lch Analog negative input Pin
6 ZCAL I Zero Calibration Control Pin
This pin controls the calibration reference signal.
"L": VCOML and VCOMR
"H": Analog Input Pins (AINL±, AINR±)
7 VD - Digital Power Supply Pin, 3.3V
8 DGND - Digital Ground Pin, 0V
9 CAL O Calibration Active Signal Pin
"H" means the offset calibration cycle is in progress. Offset calibration starts
when RST
goes "H". CAL goes "L" after 8704 LRCK cycles for DFS="L",
17408 LRCK cycles for DFS ="H".
10
RST
I Reset Pin
When "L", Digital section is powered-down. Upon returning "H", an
offset calibration cycle is started. An offset calibration cycle should always
be initiated after power-up.
1112SMODE2
SMODE1
IISerial Interface Mode Select Pin
MSB first, 2's compliment.
SMODE2 SMODE1 MODE LRCK
L L Slave mode : MSB justified : H/L
L H Master mode : Similar to I
2
S : H/L
H L Slave mode : I
2
S : L/H
H H Master mode : I
2
S : L/H
13 LRCK I/O Left/Right Channel Select Clock Pin
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset
when SMODE1 "H".
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ASAHI KASEI [AK5383]
M0049-E-03 2000/4
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14 SCLK I /O Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
15 SDATA O Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
16 FSYNC I/O Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I
2
S mode, FSYNC is
Don’t care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
17 MCLK I Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
18 DFS I Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
19 HPFE I High Pass Filter Enable Pin
"L": Disable
"H": Enable
20 TEST I Test Pin ( pull-down pin)
Should be connected to GND.
21 BGND - Substrate Ground Pin, 0V
22 AGND - Analog Ground Pin, 0V
23 VA - Analog Supply Pin, 5V
24 AINR- I Rch Analog negative input Pin
25 AINR+ I Rch Analog positive input Pin
26 VCOMR O Rch Common Voltage Pin, 2.75V
27 GNDR - Rch Reference Ground Pin, 0V
28 VREFR O Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10µ F electrolytic capacitor and a 0.1µF
ceramic capacitor
Note: All digital inputs should not be left floating.
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ASAHI KASEI [AK5383]
M0049-E-03 2000/4
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ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1)
Parameter Symbol min max Units
Power Supplies: Analog
Digital
|BGND-DGND| (Note 2)
VA
VD
∆GND
-0.3
-0.3
-
6.0
6.0
0.3
V
V
V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Analog Input Voltage VINA -0.3 VA+0.3 V
Digital Input Voltage VIND -0.3 VD+0.3 V
Ambient Temperature (power applied)
AK5383VS
AK5383VF
Ta
Ta
-10
-40
70
85
°C
°C
Storage Temperature Tstg -65 150 °C
Notes: 1. All voltages with respect to ground.
2. AGND, BGND and DGND must be connected to t h e same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies: Analog
(Note 3) Digital
VA
VD
4.75
3.0
5.0
3.3
5.25
5.25
V
V
Notes:1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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ASAHI KASEI [AK5383]
M0049-E-03 2000/4
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ANALOG CHARACTERISTICS
(Ta=25°C; VA=5.0V; VD=3.3V; AGND,BGND,DGND=0V; fs=48kHz; Signal Frequency=1kHz;
24bit Output; Measurement frequency=10Hz~20kHz; unless otherwise specified)
Parameter min typ max Units
Resolution 24 Bits
Analog Input Characteristics:
fs=48kHz -1dBFS
-20dBFS
-60dBFS
96
-
-
103
87
47
dB
dB
dB
S/(N+D)
fs=96kHz
BW=40kHz
-1dBFS
-20dBFS
-60dBFS
93
-
-
100
81
41
dB
dB
dB
Dynamic Range (-60dBFS with A-Weighted ) 105 110 dB
S/N ( A-Weighted ) 105 110 dB
Interchannel Isolation 110 120 dB
Interchannel Gain Mismatch 0.1 0.5 dB
Gain Drift 150 ppm/°C
Offset Error after calibration, HPF=OFF
after calibration, HPF=ON
±200
±1
±1000 LSB
24
LSB
24
Offset Drift (HPF=OFF) - ±10 - LSB24/°C
Offset Calibration Range (HPF=OFF) ±50 mV
Input Voltage (AIN+)-(AIN-) ±2.3 ±2.45 ±2.6 V
Input Impedance 8 14 kΩ
Power Supplies
Power Supply Current
VA
VD (fs=48kHz; DFS=L)
(fs=96kHz; DFS=H)
38
6
9
54
9
14
mA
mA
mA
Power Dissipation 210 300 mW
Power Supply Rejection (Note 4) 70 dB
Note: 4. PSRR is applied to VA, VD with 1kHz, 20mVpp.
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ASAHI KASEI [AK5383]
M0049-E-03 2000/4
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FILTER CHARACTERISTICS(fs=48kHz)
(Ta=25°C; VA=5.0V±5%; VD=3.0~5.25V; fs=48kHz, DFS=L)
Parameter Symbol min typ max Units
ADC Digital Filter(Decimation LPF):
Passband (Note 5) PB 0 21.768 kHz
Stopband (Note 5) SB 26.232 kHz
Passband Ripple PR ±0.001 dB
Stopband Attenuation (Note 6) SA 110 dB
Group Delay Distortion ∆GD 0 us
Group Delay (Note 7) GD 38.7 1/fs
ADC Digital Filter(HPF):
Frequency response (Note 5) -3dB
-0.1dB
FR 1.0
6.5
Hz
Hz
FILTER CHARACTERISTICS(fs=96kHz)
(Ta=25°C; VA=5.0V±5%; VD=3.0~5.25V; fs=96kHz, DFS=H)
Parameter Symbol min typ max Units
ADC Digital Filter(Decimation LPF):
Passband (Note 5) PB 0 43.536 kHz
Stopband (Note 5) SB 52.464 kHz
Passband Ripple PR ±0.003 dB
Stopband Attenuation (Note 8) SA 110 dB
Group Delay Distortion ∆GD 0 us
Group Delay (Note 7) GD 38.8 1/fs
ADC Digital Filter(HPF):
Frequency response (Note 5) -3dB
-0.1dB
FR 2.0
13.0
Hz
Hz
Notes: 5. The passband and stopband frequencies scale with fs.
6. The analog modulator samples the input at 6.144MHz for an output word rate of 48kHz.
There is no rejection of input signals which are multiples of the sampling frequency
(that is: there is no rejection for n x 6.144MHz ± 21.768kHz, where n=1,2,3···).
7. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal
to setting the 24bit data of both channels to the output register.
40.7/fs(DFS = "L"),40.8/fs(DFS = "H")typ. at HPF:ON.
8. The analog modulator samples the input at 6.144MHz for an output word rate of 96kHz.
There is no rejection of input signals which are multiples of the sampling frequency
(that is: there is no rejection for n x 6.144MHz ± 43.536kHz, where n=1,2,3···).
Page 8
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 8 -
DIGITAL CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%VD
-
-
-
-
30%VD
V
V
High-Level Output Voltage Iout=-20µ A
Low-Level Output Voltage Iout=20µ A
VOH
VOL
VD-0.1
-
--
0.1
V
V
Input Leakage Current Iin - - ±10 µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V; CL=20pF)
Parameter Symbol min typ max Units
Control Clock Frequency
Master Clock 256fs:
Pulse width Low
Pulse width High
Serial Data Output Clock (SCLK)
Channel Select Clock (LRCK)
duty cycle
fCLK
tCLKL
tCLKH
fSLK
fs
0.256
29
29
1
25
12.288
6.144
48
13.824
6.912
108
75
MHz
ns
ns
MHz
kHz
%
Serial Interface Timing (Note 9)
Slave Mode(SMODE1="L")
SCLK Period
SCLK Pulse width Low
Pulse width High
SCLK falling to LRCK Edge (Note 10)
LRCK Edge to SDATA MSB Valid
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Master Mode(SMODE1="H")
SCLK Frequency (DFS="L")
SCLK Frequency (DFS="H")
duty cycle
FSYNC Frequency
duty cycle
SCLK falling to LRCK Edge
LRCK Edge to FSYNC rising
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
tSLK
tSLKL
tSLKH
tSLR
tDLR
tDSS
tSF
fSLK
fSLK
fFSYNC
tSLR
tLRF
tDSS
tSF
144.7
65
65
-45
-45
-20
-20
128fs
64fs
50
2fs
50
1
45
45
45
45
20
45
20
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
Hz
%
ns
tslk
ns
ns
Reset/Calibration timing
RST
Pulse width
RST
falling to CAL rising
RST
rising to CAL falling (Note 11)
RST
rising to SDATA Valid (Note 11)
tRTW
tRCR
tRCF
tRTV
150
8704
8960
50
ns
ns
1/fs
1/fs
Notes: 9. Refer to Serial Data interface.
10. Specified LRCK edges not to coincide with the rising edges of SCLK.
11. The number of the LRCK rising edges after RST
brought high at DFS="L". The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer. When DFS="H", tRCF=17408 and tRTV=17920.
Page 9
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
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n Timing Diagram
LRCK
SCLK
SDATA
tDSS
tSLR
tSLKL
tSLKH
tSLK
tDLR
MSB MSB-1
MSB-2
Serial Data Timing (Slave Mode, FSYNC="H")
LRCK
SCLK
tSLR
tSF
SDATA
tDLR
MSB D1 D0
tSF
tDSS
FSYNC
Serial Data Timing (Slave Mode)
LRCK
SCLK
SDATA
tDSS
tSLR
tSLKL
tSLKH
tSLK
MSB
MSB-1
tDSS
Serial Data Timing (I2S Slave Mode, FSYNC = Don't Care)
Page 10
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 10 -
LRCK
SCLK
tSLR
tSF
SDATA
MSB-1
tSF
tDSS
MSB
FSYNC
tLRF
Serial Data Timing (Master Mode & I2S Master Mode, DFS ="L")
RST
SDATA
tRTV
tRCR
CAL
tRTW
tRCF
Reset & Calibration Timing
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ASAHI KASEI [AK5383]
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OPERATION OVERVIEW
n
System Clock Input
The external clocks which are required to operate the AK5383 are MCLK, LRCK(fs), SCLK. MCLK should be
synchronized with LRCK but t he phase is free of care. MCLK should be 256fs in normal sampling mode(DFS="L") and
double sampling mode needs 128fs as MCLK. Table 2 illustrates standard audio word rates and corresponding frequencies
used in the AK5383.
As the AK5383 includes the phase detect circuit for LRCK, the AK5383 is reset automatically when the synchronization
is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
All external clocks must be present unless RST
="L", otherwise excessive current may result from abnormal operation of
internal dynamic logic.
Speed Normal(DFS ="L") Double(DFS ="H")
LRCK (max) 54kHz 108kHz
SCLK ~128fs ~64fs
MCLK 256fs 128fs
Table 1. System Clocks
fs MCLK SCLK
32.0kHz 8.1920MHz 4.0960MHz
44.1kHz 11.2896MHz 5.6448MHz
48.0kHz 12.2880MHz 6.1440MHz
96.0kHz 12.2880MHz 6.1440MHz
Table 2. Examples of System Clock Frequency
n
Serial Data Interface
The AK5383 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 3). The data
format is MSB-first, 2's complement.
Figure SMODE2 SMODE1 Mode LRCK
Figure 1 L L Slave Mode Lch = H, Rch =L
Figure 2 L H Master Mode Lch =H, Rch =L
Figure 3 H L I2S Slave Mode Lch =L, Rch =H
Figure 4 H H I2S Master Mode Lch =L, Rch = H
Table 3. Serial I/F Format
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ASAHI KASEI [AK5383]
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LRCK(i)
SCLK
(i)
012 2021232415 01 20222325 012522 21 24
Lch Data Rch Data
SDATA(o
)
23 22 23 21 7 4 243 20
1
21
22
310
3 23
FSYNC(i)
FSYNC(i
)
23
23
22 5 354 310222 4210
2223
23
SDATA(o
)
23:MSB,0:LSB
Figure 1. Serial Data Timing (Slave Mode)
LRCK(o)
SCLK(o
)
0 1 2 20 21 23 24 15 34 3 20 21 23 0 12522 2 223 01
FSYNC(o)
23 23 5 354 310
2
22 4210 23
SDATA(o
)
Lch Data
33 2524 33 34
22
23:MSB,0:LSB
Rch Data
Figure 2. Serial Data Timing (Master mode, DFS="L")
LRCK(i
)
SCLK(i)
0 1 2 1920 2223 0 1 19 2122 24 0 12421 20 233 23
23 23 22 6 465 421
3
22 5321 23
SDATA(o)
Lch Data
Rch Data
23:MSB,0:LSB
0 0
Figure 3. Serial Data Timing (I2S Slave mode, FSYNC: Don’t care.)
LRCK(o
)
SCLK(o
)
0 1 2 20 21 23 24 15 34 3 20 21 23 0 12522 2 223 01
FSYNC(o
)
23 23 23 5 354 310
2
22 4210 23
SDATA(o)
Lch Data Rch Data
33 2524 33 34
22
23:MSB,0:LSB
Figure 4. Serial Data Timing (I2S Master mode, DFS="L")
Page 13
ASAHI KASEI [AK5383]
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n
Offset Calibration
When RST pin goes to "L", the digital section is powered-down. Upon returning "H", an offset calibration cycle is
started. An offset calibration cycle should always be initiated after power-up.
During the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of each
channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be
obtained from either the analog input pins (AIN+/-) or the VCOM pins depending on the state of the ZCAL pin. With
ZCAL "H", the analog input pin voltages are measured, and with ZCAL "L", the VCOM pin voltages are measured. The
CAL output is "H" during calibration.
n Digital High Pass Filter
The AK5383 also has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1Hz at fs=48kHz
and also scales with sampling rate(fs).
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ASAHI KASEI [AK5383]
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SYSTEM DESIGN
Figure 5 and 6 show the system connection diagram. An evaluation board[AKD5383] is available which demonstrates
the optimum layout, power supply arrangements and measurement results.
VREFL
1
GNDL
2
VCOML
3
AINL+
4
AINL-
5
ZCAL
6
VD
7
DGND
8
CAL
9
RST
10
SMODE2
11
SMODE1
12
VREFR
28
GNDR
27
VCOMR 26
AINR+
25
AINR- 24
VA 23
AGND
22
BGND
21
TEST 20
HPFE 19
DFS 18
MCLK
17
0.1µ10µ
+
AK5383
13
14
16
15
LRCK
SCLK
FSYNC
SDATA
0.22µ
Lch+
+3.3~5V
Digital
Rch+
Rch-
0.22µ
Reset &
Cal Control
10µ
+
0.1µ
System
Controller
Mode
Select
+5V
Analog
+
0.1µ
10µ
0.1µ
10µ
+
Lch-
fs
256fs
Analog GroundSystem Ground
@fs=48k
Figure 5. Typical Connection Diagram
Notes:
- LRCK = fs, SCLK=64fs.
- Power lines of VA and VD should be distributed separately from the point
with low impedance of regulator etc.
- AGND, BGND and DGND must be connected to the same analog ground plane.
- All input pins except pull-down/pull-up pins should not be left floating.
Analog GroundDigital Ground
System
Controller
VREFL
1
GNDL2
VCOML3
AINL+
4
AINL-5
ZCAL
6
VD
7
DGND
8
CAL
9
RST
10
SMODE211
SMODE112
VREFR 28
GNDR 27
VCOMR
26
AINR+
25
AINR-
24
VA
23
AGND
22
BGND
21
TEST 20
HPFE
19
DFS
18
MCLK
AK5383
17
13
14
16
15
LRCK
SCLK
FSYNC
SDATA
Figure 6 Ground layout
Page 15
ASAHI KASEI [AK5383]
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1. Grounding and Power Supply Decoupling
The AK5383 requires careful attention to power supply and grounding arrangements. Analog ground and digital ground
should be separate and connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK5383 as possible, with the small value ceramic capacitor being the
nearest.
2. On-chip voltage reference and VCOM
The reference voltage for A/D converter is a differential voltage between the VREFL/R output voltage and the GNDL/R
input voltage. The GNDL/R are connected to AGND and a 10uF electrolytic capacitor parallel with a 0.1uF ceramic
capacitor between the VREFL/R and the GNDL/R eliminate the effects of high frequency noise. Especially a ceramic
capacitor should be as near to the pins as possible. And all digital signals, especially clocks, should be kept away from the
VREFL/R pins in order to avoid unwanted coupling into the AK5383. No load current may be taken from the VREFL/R
pins.
VCOM is a common voltage of the analog signal. In order to eliminate the effects of high frequency noise, a 0.22uF
ceramic capacitor should be connected as near to the VCOM pin as possible. And all signals, especially clocks, should be
kept away from the VCOM pin in order to avoid unwanted coupling into the AK5383. No load current may b e drawn from
the VCOM pin.
3. Analog Inputs
Analog signal is differentially input into the modulator via the AIN+ and the AIN- pins. The input voltage is the difference
between AIN+ and AIN- pins. The full-scale of each pin is nominally ± 2.45Vpp(typ). The AK5383 can accept input
voltages from AGND to VA. The ADC output data format is 2's complement. The output code is 7FFFFFH(@24bit) for
input above a positive full scale and 800000H(@24bit) for input below a negative full scale. The ideal code is 000000H
(@24bit) with no input signal. The DC offset is removed by the offset calibration.
The AK5383 samples the analog inputs at 128fs(6.144MHz @fs=48kHz,DFS="L"). The digital filter rejects noise above
the stop band except for multiples of 128fs. A simple RC filter may be used to attenuate any noise around 128fs and most
audio signals do not have significant energy at 128fs.
The AK5383 accepts +5V supply voltage. Any voltage which exceeds the upper limit of VA+0.3V and lower limit of
AGND-0.3V and any current beyond 10mA for the analog input pins(AIN+ /-) should be avoided. Excessive currents to the
input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution
specially in case of using ±15V in other analog circuits.
Page 16
ASAHI KASEI [AK5383]
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Figure 7shows an input buffer circuit example 1. This is a full-differential input buffer circuit with an inverted-amp
(gain :-10dB). The capacitor of 10nF between AIN+ /- decreases the clock feed through noise of modulator, and composes
a 1st order LPF(fc=360kHz) with 22ohm resistor before the capacitor. This circuit also has a 1st order LPF(fc=370kHz)
composed of op-amp. In this example, the internal offset is removed by self calibration. The evaluation board should be
referred about the detail.
4.7k
+
+
22
3k
910
+
22
910
AK5383
AIN+
AIN-
CAL
ZCAL
Analog In
8.1Vpp
"L" at self calibration
47
µ
47
µ
NJM5532
VA=±5V
VP=±15V
4.7k
10
µ
+
10k
10k
0.1
µ
Bias
VA+
2.45Vpp
2.45Vpp
VP+
VP-
Bias
470p
3k
470p
Bias
10n
Figure 7 Differential Input Buffer Example 1
Figure 8 shows an input buffer circuit example 2. (1
st
order HPF; fc=0.66Hz, Table 4, 1st order LPF; fc=590kHz, gain=-
14dB, Table 5). The analog signal is able to input through XLR or BNC connectors.
(short JP1 and JP2 for BNC input, open
JP1 and JP2 for XLR input)
. The input level of this circuit is +/-12.4Vpp (AK5383: +/-2.45Vpp Typ.).
180
100
Bias
Vin+
AK5383 AIN+
+
VA
1.5n
1k
10k
22u
180
Vin-
AK5383 AIN-
+
1k22u
10k
0.1u
10u
4.7k
4.7k
XLR
BNC
+
4.7k
4.7k
JP2
JP1
NJM5534
NJM5534
NJM5534
2.45Vpp
2.45Vpp
12.4Vpp
12.4Vpp
Figure 8 Differential Input Buffer Example 2
fin 1Hz 10Hz
Frequency Response -1.56dB -0.02dB
Table 4. Frequency Response of HPF
Fin 20kHz 40kHz 6.144MHz
Frequency Response -0.005dB -0.02dB -15.6dB
Table 5. Frequency Response of LPF
Page 17
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 17 -
PACKAGE (AK5383VS)
0-10°
0.10
0.15- 0 .05
1.095TYP
18.7±0.3
28pin SOP (Unit: mm)
7.5 ± 0.2
0.75
±
0.2
+0.1
10.4
±
0.3
2.2 ± 0.1
1.27
0.12 M
+0.1
0.1-0.05
0.4
±
0.1
n
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
Page 18
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 18 -
PACKAGE (AK5383VF)
1.0
0.1±0.1
0-10
°
Detail A
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0.10
0.15 -0 .05
0.22±0.1
0.65
*9.8±0.2 1.25±0.2
A
1
14
15
28
28pin VSOP (Unit: mm
)
*5.6
±
0.2
7.6
±
0.2
0.5
±
0.2
+0.1
0.675
n
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
Page 19
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 19 -
MARKING (AK5383VS)
AKM
AK5383VS
XXXBYYYYC
JAPAN
XXXXBYYYYC: Date code identifier
XXXB: Lot number (X : Digit number, B : Alpha character )
YYYYC: Assembly date (Y : Digit number C : Alpha character)
Page 20
ASAHI KASEI [AK5383]
M0049-E-03 2000/4
- 20 -
MARKING (AK5383VF)
AKM
AK5383VF
XXXBYYYYC
XXXXBYYYYC: Date code identifier
XXXB: Lot number (X : Digit number, B : Alpha character )
YYYYC: Assembly date (Y : Digit number C : Alpha character)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application
or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except
with the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to person
or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless
from any and all claims arising from the use of said product in the absence of such notification.
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