Datasheet AK4393VF Datasheet (AKM)

ASAHI KASEI [AK4393]

A

AK4393

Advanced Multi-Bit 96kHz 24-Bit

DS

DAC

GENERAL DESCRIPTIO N

The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a
24bit digital filter. The AK4393 introduces the advanced multi-bit system for DS modulator. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as conventional Single-Bit way. In the AK4393, the analog outputs are filtered in the
analog domain by switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog output s
are full differential output, so the device is suitable for hi-end applications. The operating voltages support
analog 5V and digital 3.3V, so it is easy to I/F w it h 3. 3V logic IC.

FEATURES

· 128x Oversampling

· Sampling Rate up to 108kHz

· 24Bit 8x Digital Filter
Ripple: ±0.005dB, Attenuation: 75dB

· High Tolerance to Clock Jitter

· Low Distortion Differenti al Output

· Digital de-emphasis for 32, 44.1, 48 & 96kHz sampling

· Soft Mute

· THD+N: -100dB

· DR, S/N: 120dB

· I/F format : MSB justified, 16/20/24bit LSB justified, I

2

S

· Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs

Double Speed: 128fs, 192fs, 256fs or 384fs

· Power Supply: 4.75 to 5.25V (Analog), 3 to 5. 25V (Digital)

· Small Package: 28pin VSOP

LRCK

BICK

SDAT

PDN

SMUTE

DFS

Audio Data

Interface

De-emphasis

Soft Mute

De-emphasis

Soft Mute

DIF2DIF1DIF0

DEM0DVDD

DEM1

De-emphasis

Control

8x

Interpolator

8x

Interpolator

DS

Modulator

DS

Modulator

AVDD

SCF

AVSSDVSS

BVSS
VCOM

AOUTL+

SCF

AOUTL-

AOUTR+
AOU TR-

Control Register Clock Divider

CSN

CCLK

CDTI

P/S

MCLK CKS0

CKS1 CKS2 VREFH VREFL

M0039-E-01 2000/5

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ASAHI KASEI [AK4393]

n Ordering Guide

AK4393VF -40 ~ +85 °C 28pin VSOP (0.65mm pitch)
AKD4393 Evaluation Board

n

n Pin Layout

nn

DVSS

DVDD

MCLK

PDN

BICK

SDATA

LRCK 7

SMUTE/CSN 8

DFS

DEM0/CCLK

DEM1/CDTI 11

DIF0 12

DIF1

10

13

1

2

3

4

5

6

Top
View

9

28

27

26

25

24

23

22

21

20

19

18

17

16

CKS2

CKS1

CKS0

P/S

VCOM

AOUTL

AOUTL-

AOUTR+

AOUTR-

AVSS

AVDD

VREFH

VREFL

+

DIF2

14

15

BVSS

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ASAHI KASEI [AK4393]

PIN/FUNCTION

No. Pin Name I/O Function

1 DVSS - Digital Ground Pin
2 DVDD - Digital Power Supply Pin, 3.3V or 5.0V
3 MCLK I Master Clock Input Pin

PDN I Power-Down Mode Pin

4

BICK I Audio Serial Data Clock Pin

5

SDATA I Audio Serial Data Input Pin

6

7 LRCK I L/R Clock Pin

SMUTE I Soft Mute Pin in parallel mode

8

CSN I Chip Select Pin in serial mode
DFS I Double Speed Sampling Mode Pin (Internal pull-down pin)

9

DEM0 I De-emphasis Enable Pin in parallel mode

10

CCLK I Control Data Clock Pin in serial mode
DEM1 I De-emphasis Enable Pin in parallel mode

11

CDTI I Control Data Input Pin in serial mode
12 DIF0 I Digital Input Format Pin
13 DIF1 I Digital Input Format Pin
14 DIF2 I Digital Input Format Pin
15 BVSS - Sub strate Ground Pin, 0V
16 VREFL I Low Level Voltage Reference Input Pin
17 VREFH I High Level Voltage Reference Input Pin
18 AVDD - Analog Power Supply Pin, 5.0V
19 AVSS - Analog Ground Pin, 0V
20 AOUTR- O Rch Negative analog output Pin
21 AOUTR+ O Rch Positive analog output Pin
22 AOUTL- O Lch Negative analog output Pin
23 AOUTL+ O Lch Positive analog output Pin
24 VCOM O Common Voltage Output Pin, 2.6V
25 P/S I Parallel/Serial Select Pin (Internal pull-up pin)

26 CKS0 I Master Clock Select Pin
27 CKS1 I Master Clock Select Pin
28 CKS2 I Master Clock Select Pin

When at “L”, the AK4393 is in power-down mode and is held in reset.
The AK4393 should always be reset upon power-up.

The clock of 64fs or more than is recommended to be input on this pin.

2’s complement MSB-first data is input on this pin.

When this pin goes "H", soft mute cycle is initiated.
When returning “L”, the output mute releases.

“L”: Normal Speed , “H”: Double Speed

“L”: Serial control mode, “H”: Parallel control mode

Note: All input pins except internal pull-up/down pins should not b e left floating.

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ASAHI KASEI [AK4393]

ABSOLUTE MAXI MUM RATINGS

(AVSS, BVSS, DVSS = 0V; Note 1)

Parameter Symbol min max Units

Power Supplies: Analog

Digital

| BVSS-DVSS | (Note 2)
Input Current , Any pin Except Supplies IIN ­Input Voltage VIND -0.3 DVDD+0.3 V
Ambient Operating Temperature Ta -40 85
Storage Temperature Tstg -65 150

Notes: 1. All voltages with respect to ground.

2. AVSS, BVSS and DVSS must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

AVDD
DVDD

GND

D

-0.3

-0.3

-

6.0

6.0

0.3

±

10

V
V
V

mA

C

°

C

°

RECOMMENDED OPERATING CONDITIONS

(AVSS, BVSS, DVSS=0V; Note 1)

Parameter Symbol min typ max Units

Power Supplies:
(Note 3)

Voltage Reference
(Note 4)

Notes: 3. The power up sequence between AVDD and DVDD is not critical.

4. Analog output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.

Analog
Digital
“H” voltage reference
“L” voltage refer ence
VREFH-VREFL

AVDD

DVDD
VREFH
VREFL

VREF

D

4.75

3.0

AVDD-0.5

AVSS

3.0

5.0

3.3

5.25

5.25

-

-

-

AVDD

-

AVDD

V
V
V
V
V

* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

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ASAHI KASEI [AK4393]

ANALOG CHARACTERISTICS

(Ta = 25°C; AVDD = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS;
fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz;

600W; External circuit: Figure 11; unless otherwise specified)

R

³

L

Parameter min typ max Units

Resolution 24 Bits
Dynamic Characteristics (Note 5)
THD+N

fs=44.1kHz
BW=20kHz
fs=96kHz

BW=40kHz
Dynamic Range
(-60dBFS with A-weighted)

S/N (A-weighted

fs=44.1kHz (Note 6)
(Note 7)

fs=96kHz
(Note 7)

fs=44.1kHz (Note 8)
(Note 7)

fs=96kHz
(Note 7)

0dBFS

-60dBFS
0dBFS

-60dBFS
112

-

111

-

112

-

111

-

-100

-53

-97

-51
117
120
116
118
117
120
116
118

-90

-86

dB

-

dB
dB

-

dB
dB
dB
dB
dB
dB
dB
dB
dB

Interchannel Isolation (1kHz) 100 120 dB

DC Accuracy

Interchannel Gain Mismatch 0.15 0.3 dB
Gain Drift (Note 9) 20 - ppm/°C
Output Voltage (Note 10)
Load Resistance (Note 11) 600

±

2.25

2.4

±

2.55 Vpp

±

W

Output Current 3.5 mA

Power Supplies

Power Supply Current

Normal Operation (PDN = “H”)

AVDD
DVDD(fs=44.1kHz)
DVDD(fs=96kHz)
AVDD + DVDD

60

­3
5

-

-

90

mA
mA
mA
mA

Power-Down Mode (PDN = “L”)

AVDD + DVDD (Note 12) 10 50 µA

Power Supply Rejection (Note 13) 50 dB

Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.

At 96kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode.
Refer to the eva board manual.

6. 101dB at 16bit data and 116dB at 20bit data.

7. By Figure12. External LPF Circuit Example 2.

8. S/N does not depend on input bit length.

9. The voltage on (VREFH-VREFL) is held +5V externally.

10. Full-scale voltage (0dB). Output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.

11. For AC-load. 1kW for DC-load.

12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK and

LRCK) are held DVSS.

13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.

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ASAHI KASEI [AK4393]

FILTER CHARA CTERISTICS (fs = 44.1kHz)

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF)

Parameter Symbol min typ max Units
Digital Filter

Passband ±0.01dB (Note 14)

-6.0dB
Stopband (Note 14) SB 24.1 kHz
Passband Ripple PR
Stopband Attenuation SA 75 dB
Group Delay (Note 15) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response 0 ~ 20.0kHz -

Note: 14. The passband and stopband frequencies scale with fs.
For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.

15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of

both channels to input register to the output of analog signal.

PB 0

- 22.05

0.2 - dB

±

20.0

-

0.005 dB

±

kHz
kHz

FILTER CHARACTERISTICS (fs = 96kHz)

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF)

Parameter Symbol min typ max Units
Digital Filter

Passband ±0.01dB (Note 14)

-6.0dB
Stopband (Note 14) SB 52.5 kHz
Passband Ripple PR
Stopband Attenuation SA 75 dB
Group Delay (Note 15) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response 0 ~ 40.0kHz -

PB 0

- 48.0

0.3 - dB

±

43.5

-

0.005 dB

±

kHz
kHz

DC CHARACTERISTICS

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V)

Parameter Symbol min typ max Units

High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current (Note 16) Iin - -

Note: 16. DFS and P/S pins have internal pull-down or pull-up devices, nominally 100kW.

M0039-E-01 2000/5

VIH
VIL

- 6 -

70%DVDD

-

-

-

-

30%DVDD

10

±

V
V

µA

ASAHI KASEI [AK4393]

SWITCHING CHARACTERISTICS

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; CL = 20pF)

Parameter Symbol min typ max Units
Master Clock Timing

Normal Speed: 256fs, Double Speed: 128fs

Pulse Width Low
Pulse Width High

Normal Speed: 384fs, Double Speed: 192fs

Pulse Width Low

Pulse Width High
Normal Speed: 512fs, Double Speed: 256fs
Normal Speed: 768fs, Double Speed: 384fs

Pulse Width Low

Pulse Width High

LRCK Frequency (Note 17)
Normal Speed Mode (DFS = “L”)
Double Speed Mode (DFS = “H”)
Duty Cycle

Serial Interface Timing

BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “” to LRCK Edge (Note 18)
LRCK Edge to BICK “” (Note 18)
SDATA Hold Time
SDATA Setup Time

Control Interface Timing

CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “¯” to CCLK “”
CCLK “” to CSN “”

Reset Timing

PDN Pulse Width (Note 19) tP W 150 ns

Notes: 17. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.

18. BICK rising edge must not occur at the same time as LRCK edge.

19. The AK4393 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.

fCLK

tCLKL

tCLKH

fCLK
tCLKL
tCLKH

fCLK

fCLK
tCLKL
tCLKH

fsn
fsd

Duty

tBCK
tBCKL
tBCKH

tBLR

tLRB

tSDH

tSDS

tCCK
tCCKL
tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

7.7
28
28

11.5
20
20

15.4

23.0

7
7

30
60
45

140

60
60
20
20
20
20

200

80
80
50
50

150

50
50

44.1

88.2

13.824 MHz
ns
ns

20.736 MHz
ns
ns

27.648

41.472

54

108

55

MHz
MHz

ns
ns

kHz
kHz

%

ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns

M0039-E-01 2000/5

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ASAHI KASEI [AK4393]

n Timing Diagram

1/fCLK

MCLK

LRCK

BICK

LRCK

tCLKH

tBCKH

50%DVDD

tCLKL

1/fns,1/fds

50%DVDD

tBCK

50%DVDD

tBCKL

Clock Timing

50%DVDD

BICK

SDATA

tBLR

tLRB

tSDS

Audio Interface Timing

tSDH

50%DVDD

50%DVDD

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ASAHI KASEI [AK4393]

CSN

CCLK

CDTI

CSN

tCSS

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

WRITE Command Input Timing

50%DVDD

50%DVDD

50%DVDD

tCSW

50%DVDD

tCSH

CCLK

CDTI

PDN

D3 D2 D1 D0

WRITE Data Input Timing

tPW

Power-down Timing

50%DVDD

50%DVDD

30%DVDD

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ASAHI KASEI [AK4393]

OPERATION OVERVI EW

n System Clock

The external clocks, which are requ ired to operate the A K4393, are MCL K, LRC K and BICK. The m aster clock (MC LK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. The sampling speed is set by DFS (Table 1). The sampling rate (LRCK), CKS0/1/2
and DFS determine the frequency of MCLK (Table 2).

All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4393 is in normal operation
mode (PDN = “H”). If these clocks are not provided, the AK4393 may draw excess current because the device utilizes
dynamic refreshe d logi c in tern ally. If the external clocks are not present, th e A K4393 sh ou ld be in th e power-down mode
(PDN = “L”) or in the reset m ode (RSTN = “0”). Af ter exiting reset at pow er-up etc., the A K4393 is in pow er-dow n mode
until MCLK and LRCK are input.

DFS Sampling Rate (fs)

0 Normal Speed Mode 30kHz~54kHz
1 Double Speed Mode 60kHz~108kHz

Table 1. Sampling Speed

Default

Mode CKS2 CKS1 CKS0 Normal

0 0 0 0 256fs 128fs
1 0 0 1 256fs
2 0 1 0 384fs 192fs
3 0 1 1 384fs
4 1 0 0 512fs 256fs
5 1 0 1 512fs
6 1 1 0 768fs 384fs
7 1 1 1 768fs N/A

Table 2. System Clocks

LRCK MCLK BICK

fs 256fs 384fs 512fs 768fs 64fs

32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz

44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz

48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz

Table 3. System clock example (Normal Speed Mode)

LRCK MCLK BICK

fs 128fs 192fs 256fs 384fs 64fs

88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz

96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz

Double

Default

256fs

384fs

N/A

Table 4. System clock example (Double Speed Mode)

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ASAHI KASEI [AK4393]

(

)

(

)

(

)

n Audio Serial Interface Format

Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the
DIF0-2 as shown in Table 5. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising
edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs.

Mode DIF2 DIF1 DIF0 Mode B ICK Figure

0 0 0 0 0: 1 6bit LSB Justified
1 0 0 1 1: 2 0bit LSB Justified
2 0 1 0 2: 24bit MSB Justified

30113: I

2

S Compatible

4 1 0 0 4: 2 4bit LSB Justified

³
³
³

³
³

32fs
40fs
48fs

48fs
48fs

Figure 1
Figure 2
Figure 3

Figure 4
Figure 2

Table 5. Audio Data Formats

LRCK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

BICK

32fs

SDATA

Mode 0

BICK

64fs

SDATA

Mode 0

LRCK

BICK

64fs

SDATA

Mode 1

SDATA

Mode 4

15 14 6 5 4

1

014

Don’t care
15:MSB, 0:LSB

3210 1514

15 16 17 31 0 1

15 14 0

15 14 6 5 4 3 2 1 0

14

15 16 17 31 0 1

Don’t care

15 14 0

Lch Data Rch Data

Figure 1. Mode 0 Timing

091 10 11 12 31 0 1 9 10 11 12 31 0 1

Don’t care Don’t care
19:MSB, 0:LSB

Don’t care
23:MSB, 0:LSB

8

19 0

23 23

22 21 22 21

20 19 0

Don’t care

8

19 0

20 19 0

Lch Data Rch Data

Figure 2. Mode 1,4 Timing

M0039-E-01 2000/5

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ASAHI KASEI [AK4393]

(

)

(

)

LRCK

BICK

64fs

SDATA

LRCK

BICK

64fs

SDATA

0221 2 24 31 0 1 31 0 1

22 1 0 Don’t care23

23:MSB, 0:LSB

23 30 2222423 30

22 1

23

0 Don ’t c are

Lch Data Rch Data

Figure 3. Mode 2 Timing

031 2 24 31 0 1 31 0 1

22

23
23:MSB, 0:LSB

23 25 322423 25

0

1

Don’t care

22 1

0

Don’t care23

Lch Data Rch Data

Figure 4. Mode 3 Timing

2223

23

n

n De-emphasis filter

nn

A digital de-emphasis filter is available for 32, 44.1, 48 or 96kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with the DEM0, DEM1 and DFS input pins.

DEM1 DEM0 DFS Mode

0 0 0 44.1kHz

Default
010OFF
1 0 0 48kHz
1 1 0 32kHz
001OFF
011OFF
1 0 1 96kHz

111OFF

Table 6. De-emphasis filter control

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ASAHI KASEI [AK4393]

n Soft mute operation

Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -

¥

during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually
changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the
operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source
without stopping the signal transmission.

SMUTE

Attenuation

AOUT

0dB

-

¥

1024/fs

(1)

GD

(2)

1024/fs

(3)

GD

Notes:

(1) The output signal is attenuated by -¥ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.

Figure 5. Soft mute operation

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ASAHI KASEI [AK4393]

n System Reset

The AK4393 should be reset once by bringing PDN = “L” upon power-up. The AK4393 is powered up and the internal
timing starts clocking by LRCK “” after exiting reset and pow er down state by MCLK. The AK4393 is in the power-dow n
mode until MCLK and LRCK are input.

n Power-Down

The AK4393 is placed in the power-dow n m ode by bringi ng PDN pin “L ” and the anlog ou tputs are floatin g (Hi-Z). Figu re
6 shows an example of the system timing at the power-down and power-up.

PDN

Internal
State

D/A In
(Digital)

D/A Out

Normal Operation

GD

(1)

Power-down Normal Operation

“0” data

(3)

(2)

(3)

GD

(Analog)

(4)

Clock In

MCLK, LRCK, BICK

External
MUTE

(5)

Don’t care

Mute ON

Notes:

(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.

The timing example is shown in this figure.

Figure 6. Power-down/up sequence example

(1)

n Click Noise from analog output

Click noise occurs from analog output in the following cases.

1) When switching de-emphasis mode by DEM0, DEM1 and DFS pins,

2) When switching serial data mode by DIF0, DIF1 and DIF2 pins,

3) When going and exiting power down mode by PDN pin,

4) When switching normal speed and double speed by DFS pin,
However in case of 1) & 2), If the input data is “0” or the soft mute is enabled (after 1024 LRCK cycles from SMUTE =
“H”), no click noise occur except for switching DFS pin.

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ASAHI KASEI [AK4393]

n Mode Control Interface

Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4393. For DIF2-0,
CKS2-0 and DFS, the setting of pin and register are “ORed” internally. So, even serial control mode, pin setting can also
control these functions.

The serial control interface is enabled by the P/S pin = “ L”. In this mode, pin setting must be all “L”. In ternal registers may
be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits,
C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first,
8bits). The AK4393 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The
writing of data becomes valid by CSN “”. The clock speed of CCLK is 5MHz(max). The CSN and CCLK must be fixed
to “H” when the register does not be accessed.

PDN = “L” resets the regis ters to their def ault values . When the state of P/S pin is ch anged, the A K4393 sh ould be reset by
PDN = “L”. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.

CSN

0 1234567

8 9 10 11 12 13 14 15

CCLK

CDTI

C1

D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3

C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data

Figure 7. Control I/F Timing

*The AK4393 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4393 is in the pow er down mode (PDN = “L”) or th e MCLK is not provided, writin g into the control register

is inhibited.

*For setting the registers, the following sequence is recommended.



Control 1 register

(1) Writing RSTN = “0” and other bits (D6-D1) to the register at the same time.
(2) Writing RSTN = “1” to the register. The other bits are no change.



Control 2 register

This writing sequence has no limitation like control 1 register.
*When RSTN = “0”, the click noise is output from AOUT pins.
*If the mode setting is done without setting RSTN = “0”, large noise may be output from AOUT pins. (Especially when

CKS0/1/2 are changed.)

M0039-E-01 2000/5

- 15 -

ASAHI KASEI [AK4393]

n Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN
01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE
02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0

Notes:

For addresses from 03H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the only
internal timing is reset and the registers are not initialized to their default values. DIF2-0, CKS2-0 and DFS bits are
ORed with pins respectively.

n

n Register Definitions

nn

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN

default 00000001

RSTN: Internal timing reset

0: Reset. All registers are not initialized.
1: Normal Operation
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.

DIF2-0: Audio data interface modes (see Table 5)

Initial: “000”, Mode 0
Register bits are ORed with DIF2-0 pins if P/S = “L”.

CKS2-0: Master Clock Frequency Select (see Table 2)

Initial: “000”, Mode 0
Register bits are ORed with CKS2-0 pins if P/S = “L”.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE

default 00000000

SMUTE: Soft Mute Enable

0: Normal operation
1: DAC outputs soft-muted

DEM1-0: De-emphasis response (see Table 6)

Initial: “00”, 44.1kHz

DFS: Sampling speed control (see Table 1)

0: Normal speed
1: Double speed
Register bit is ORed with DFS pin if P/S = “L”.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0

default 00000000

TEST7-0: Test mode. Do not write any data to 02H.

M0039-E-01 2000/5

- 16 -

ASAHI KASEI [AK4393]

SYSTEM DESIGN

Figure 8 and 9 show th e sys tem con nection diagram . A n evaluation board (AKD4393) is av ailable wh ich dem onstrates th e
optimum layout, power supply arrangements and measurement results.

Digital

Supply

Master Clock

Reset & Power down

64fs

24bit Audio Data

Micro­controller

0.1u10u

+

fs

DVSS

1

DVDD

2

MCLK

3

PDN

4

BICK

5

SDATA6
LRCK

7

CSN

8

DFS9
CCLK10
CDTI

11

DIF0

12
13

DIF1
DIF2

14

AK4393

CKS2
CKS1
CKS0

P/S 25

VCOM

AOUTL+

AOUTL-

AOUTR+

AOUTR-

AVSS
AVDD

VREFH 17

VREFL

BVSS

28
27
26

10u

+

10u
+

10u

0.1u

Rch

24
23
22
21
20
19

0.1u

18

0.1u

16
15

Lch
LPF

LPF

+

Analog
Supply 5V

Analog GroundDigital Ground

Figure 8. Typical Connection Diagram (Serial mode)

Notes:

- LRCK = fs, BICK = 64fs.

- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of
regulator etc.

- AVSS, BVSS and DVSS must be connected to the same analog ground plane.

- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.

- All input pins except pull-down/pull-up pins should not be left floating.

Lch Out

Rch Out

M0039-E-01 2000/5

- 17 -

ASAHI KASEI [AK4393]

Digital

Supply

Master C lock

Reset & Power down

64fs

24bit Audio Data

fs

Mode
setting

0.1u10u

+

DVSS

1

DVDD

2

MCLK

3

PDN

4

BICK

5

SDATA6
LRCK

7
8

SMUTE
DFS9
DEM010
DEM1

11

DIF0

12
13

DIF1
DIF2

14

AK4393

CKS2
CKS1
CKS0

P/S 25

VCOM

AOUTL+

AOUTL- 22

AOUTR+

AOUTR-

AVSS

AVDD

VREFH

VREFL

BVSS

28
27
26

24
23

21
20
19

0.1u

18
17

0.1u

16
15

Master

Clock

Select

10u

0.1u

+

Lch
LPF

Rch

LPF

10u

+

Lch Out

Rch Out

Analog

+

10u

Supply 5V

Analog GroundDigital Ground

Figure 9. Typical Connection Diagram (Parallel mode)

Notes:

- LRCK = fs, BICK = 64fs.

- Power lines of AVDD and DVDD should be distribu ted separately from th e point with low impedan ce of regulator
etc.

- AVSS, BVSS and DVSS must be connected to the same analog ground plane.

- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.

- All input pins except pull-down/pull-up pins should not be left floating.

Analog GroundDigital Ground

CKS2
CKS1
CKS0 26

VCOM

AOUTL+

AOUTL-

AOUTR+

AOUTR-

AVSS

AVDD
VREFH
VREFR

BVSS

28
27

P/S 25

24
23
22
21
20
19
18
17
16
15

System

Controller

DVSS

1

DVDD

2

MCLK

3

PDN

4

BICK

5

7
8

11
12
13
14

SDATA6
LRCK

SMUTE

DFS9
DEM010
DEM1
DIF0
DIF1
DIF2

AK4393

Figure 10. Ground Layout

M0039-E-01 2000/5

- 18 -

ASAHI KASEI [AK4393]

1. Grounding and Power Supply Decoupli ng

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If AVDD and
DVDD are supplied separately, the power up sequence is not critical.

to analog ground plane.

System analog ground and digital ground should be connected together near to where the

AVSS, BVSS and DVSS must be connected

supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as
possible.

2. Voltage Reference

The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to
AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic
capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the ef fects of hi gh frequ ency noise. No load curren t m ay be draw n f rom VCOM pin . A ll
signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted
coupling into the AK4393.

3. Analog Outputs

The analog outputs are full differential outputs and 2.4Vpp (typ@VREF=5V) centered around VCOM. The differential
outputs are summed ex ternally, V

= (AOUT+) - (AOUT-) between A OUT+ and AOUT-. If th e sum min g gain is 1, the

AOUT

output range is 4.8Vpp (typ@VREF=5V). The bias voltage o f the external summing circuit is supplied externally. The
input data format is 2's complement. The output voltage (V
negative full scale for 800000H (@24bit). The ideal V

AOUT

) is a positive full scale for 7FFFFFH (@24bit) and a

AOUT

is 0V for 000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband.

Figure 11 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 12 shows an example of differential outputs and LPF circuit example by three op-amps.

AK4393

AOUT-

AOUT+

1k 1k

1k

3.3n

1k 1k

1k 1n

1n

+Vop

Analog

Out

-Vop

Figure 11. External LPF Circuit Example 1

M0039-E-01 2000/5

- 19 -

ASAHI KASEI [AK4393]

+15

4.7n

2

3

4.7n

0.1u

4

­7

NJM5534D

-15

10u

+

100

6

Lch

AOUTL-

47u

+

300

620

300

10n

10n

3
2

7

­4

NJM5534D

6

220

300

0.1u

0.1u

10u

10u

430

100

3

2

1

620

620

430

AOUTL+

47u

620

300

300

10n

10n

3
2

7

-

4

NJM5534D

220

10u

0.1u

6

10u

0.1u

100

0.1u

+

10u

300

Figure 12. External LPF Circuit Example 2

M0039-E-01 2000/5

- 20 -

ASAHI KASEI [AK4393]

)

PACKAGE

28pin VSOP (Unit: mm

0.675
28

0.22±0.1

1

Seating Plane

*9.8±0.2 1.25±0.2

15

A

0.2

0.10

14

0.65

Deta il A

*5.6

±

+0.1

0.15-0.05

0.1±0.1

0.2

±

0.5

0.2

±

7.6

NOTE: Dimension "*" does not include mold flash.

n

n Material & Lead finish

nn

Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate

0-10

°

M0039-E-01 2000/5

- 21 -

ASAHI KASEI [AK4393]

MARKING

AKM

AK4393VF

XXXBYYYYC

XXXXBYYYYC data code identifier

XXXB: Lot number (X : Digit number, B : Alpha character )
YYYYC: Assembly date (Y : Digit number C : Alpha character)

IMPORTANT NOTICE

These products and their specifications are subject to change without notice. Before considering any

·

use or application, consult the Asahi Kasei Micros ystems Co., Ltd. (AKM) s ales off ice or authorized
distributor concerning their current s tatus.

AKM assumes no liability for infringem ent of any patent, intellectual property, or other right in the

·

application or use of any information contained herein.

Any export of these products, or devices or systems containing them, may require an export license or

·

other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or str ategic m aterials.

AKM products are neither intended nor authorized for use as c ritical com ponents in any safety, life

·

support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Direc tor of AKM. As us ed
here:
(a) A hazard related device or system is one designed or intended f or lif e suppor t or m aintenanc e of

safety or for applications in medicine, aer ospace, nuclear ener gy, or other fields, in which its
failure to function or perform m ay reasonably be expected to result in loss of lif e or in signific ant
injury or damage to person or property.

(b) A critical component is one whose failure to func tion or perfor m m ay reasonably be expected to

result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must theref ore meet ver y high standards of perform ance and
reliability.

It is the responsibility of the buyer or distributor of an AKM product who distributes, dispos es of, or

·

otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.

M0039-E-01 2000/5

- 22 -