Datasheet AHA4501A-050PQC Datasheet (Advanced Hardware Architectures)

PS4501-1100

2365 NE Hopkins Court

Pullman, WA 99163-5601

tel: [phone]

fax: [phone]

e-mail: [e-mail]

www.aha.com

advancedhardwarearchitectures

Product Specification

AHA4501 Astro

36 Mbits/sec Turbo Product Code

Encoder/Decoder, 3.3V

This product and the algorithm are covered under multiple patents pending.

Advanced Hardware Architectures, Inc.

PS4501-1100 i

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

2.0 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.1 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.2 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.3 Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.4 Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.5 Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.6 Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.6.1 Encode Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.6.2 Decode Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.6.3 Resynchronize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.7 Helical Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.8 Data Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.9 Encoding/Decoding Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.10 Summary of Channel Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.11 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.12 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.0 Internal Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.1 Configuration 0, Address 0x00 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.2 Configuration 1, Address 0x01 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.3 Configuration 2, Address 0x02 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.4 Feedback, Address 0x03 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.5 Quantization, Address 0x04 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.6 Corrections, Address 0x05 - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.7 Synchronization, Address 0x05 - Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.8 Status, Address 0x06 - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.9 Control/Interrupt, Address 0x07 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.10 Reserved, Address 0x08 - Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.0 Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.1 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.2 Microprocessor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.3 Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.4 Output Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

7.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4

7.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.2.1 DC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.2.2 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7.2.3 Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8.0 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

9.0 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

10.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

11.0 Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Advanced Hardware Architectures, Inc.

ii PS4501-1100

Figures

Figure 1: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 2: IDATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Figure 3: Input Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 4: 2D Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 5: Encoded/Interleaved Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 6: Encoding at the Maximum Input Rate (bit/clock) with Maximum Output Rate (bit/clock). . . . . . . . . . . . . . .7

Figure 7: Encoding at Less Than Maximum Input Rate with Maximum Output Rate . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 8: Decoding with Continuous Input Data Rate - STITER not Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 9: Decoding with Burst Input Data Rate - STITER not Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 10: Decoding with Burst Input Data Rate - STITER Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 11: DUMP Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 12: Turbo Product Code vs. Reed-Solomon/Viterbi Performance Comparison. . . . . . . . . . . . . . . . . . . . . . . .19

Figure 13: Comparison of TPC Code Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 14: Performance Curve of E

b/No

for BER of 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 15: Pinout – 100 MQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 16: Current vs. Data Rate (typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 17: Signal Timing vs. Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 18: Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 19: Data Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 20: Microprocessor Interface Timing (Write); PROCMODE=0, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 21: Microprocessor Interface Timing (Read); PROCMODE=0, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 22: Microprocessor Interface Timing (Write); PROCMODE=0, MUXMODE=1 . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 23: Microprocessor Interface Timing (Read); PROCMODE=0, MUXMODE=1 . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 24: Microprocessor Interface Timing (Write); PROCMODE=1, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 25: Microprocessor Interface Timing (Read); PROCMODE=1, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 26: Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 27: Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 28: Power On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 29: AHA4501 Package Specifications – 100 MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Advanced Hardware Architectures, Inc.

PS4501-1100 iii

Tables

Table 1: Recommended QSHIFT Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 2: Channel Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 3: Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 4: Supported Codes with Recommended Feedback Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 5: Pin Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 6: Data Input Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 7: Data Output Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 8: Microprocessor Interface Timing Requirements - Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 9: Microprocessor Interface Timing Requirements - Read; PROCMODE=0, MUXMODE=0 . . . . . . . . . . . .28

Table 10: Microprocessor Interface Timing Requirements - Write; PROCMODE=0, MUXMODE=1. . . . . . . . . . . . .29

Table 11: Microprocessor Interface Timing Requirements - Read; PROCMODE=0, MUXMODE=1 . . . . . . . . . . . .30

Table 12: Microprocessor Interface Timing Requirements - Write; PROCMODE=1, MUXMODE=0. . . . . . . . . . . . .31

Table 13: Microprocessor Interface Timing Requirements - Read; PROCMODE=1, MUXMODE=0 . . . . . . . . . . . .32

Table 14: Interrupt Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 15: Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 16: Power On Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 17: PQFP (Plastic Quad Flat Pack) 14 × 20 mm Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

PS4501-1100 Page 1 of 36

Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

The AHA4501 is the first single-chip Forward
Error Correction LSI device using Turbo Product
Codes (TPC). The device operates as a block code
encoder at the input or a block code decoder at the
output of a communication channel. The device
supports various programmable features, such as
block size, codes and code rates, to optimize various
communication channel needs for error
performance and data throughput. Turbo Product
Codes offer a higher performance alternative to
Reed-Solomon or Reed-Solomon concatenated
with Viterbi error correction methods.

When encoding, the device appends the Error
Correction Code (ECC) bits to the blocks, and
outputs the encoded blocks. When decoding, the
device accepts soft decision values and stores the
data as a block in its internal RAM. The block is
then decoded iteratively by running it through the
device’ s soft in/soft out (SISO) decoder . The device
iterates to the maximum programmed iteration
limit. The decoded bloc k is then o utput thr ough th e
device output data port.

This specification describes the functional
operation, programming, timing and ordering
information. Please contact AHA for additional
support material, including e valuation softwa re and
relevant technical publicat ions; o r visit ou r website
at http://www.aha.com.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

– Code block – A data stream to be encoded or

decoded is segmented into blocks for processing
by the AHA4501. Data in a code block is
configured as a 2D or 3D array.

– Axis iteration – Decodi ng one axis of an ar ray (all

x rows, all y columns, or all z columns).

– Full it eration – Decoding all axe s o f a n ar ra y ( all

rows and columns).

– Soft value – Input to the decoder from either an

Analog/Digital Converter(ADC) or digital
demodulator.

– Code r ate – Ratio of t he number of data bits to the

number of data and ECC bits.

– Data rate – The rate at which unencoded data is

input to the devic e when enco ding or outp ut from
the device when decoding.

– Channe l Rate – The rate at whi ch encoded data is

output from the d evice when en coding or in put to
the device when decoding. Note that system
channel ra te may be different due to external
synchronization marks or other overhead.

– Original Arr ay (OA) – The soft decision input data

array . Data is stored as a 6 bit soft value per locat ion
to support the maximum 6 bit inp ut qu anti zat ion.

– Inte rmed ia te S t or age Ar ra y (ISA) – The storage

array for data between iterating.

– Hard Deci sion Array (HDA) – The har d decision

output. Data is stored as one bit per location.

–(n

1,k1

)x(n2,k2) – A general representat ion of a 2D
block code for use in the desc riptions to follow in
this specification. For example, in a
(64,57)x(64,57) code; n

1,n2

=64 represents the

length of the data + ECC bits, and k

1,k2

=57
represents the length of only the data bits. 3D
codes are represented as (n

1,k1

)x(n2,k2)x(n3,k3)
– Vector – One row or column of data in a block.
– Laten cy – The time from t he first bit of a block in

to first bit of the same block out.

– Active low signals have an “N” appended to the

end of the signal name. F or e xample, MCSN an d
RESETN.

– Hex values are represented with a prefix of “0x”,

such as register “0x00”. Binary values do not
contain a prefix.

1.2 FEATURES

PERFORMANCE:

• Maximum 50 Mbits/sec channel rate encoding

• 36.5 Mbits/sec chann el rate d ecoding for a 64x5 7

square code at two iterations

• Two or more devices can be used in parallel to

increase throughput

• Optional “helical” interleaving (encoding) and

deinterleaving (decoding)

FLEXIBILITY:

• Internal buffering all ows conti nuous data

streaming

• Programmable block size from 256 to 4096 bits

• Two or three dimensional blocks

• Programmable number of iterations per block up

to 32

• Programmable quantization up to 6-bits for so ft or

hard decision input data (deco din g )

• Support for external synchronization

SYSTEM INTERF ACE:

• Serial or 8-bit parallel input and output data ports

• Selectab le microprocessor interface for Intel or

Motorola pro cessors

• Control Commands for: Decode, Encode, Soft

Reset, Resynchronize and Dump Current Block

• System Interrupts include Block Decode Complete,

Block Correction Incomplete, Sync Mark Mismatch

• Number of corrections per block accumulated in

an internal register

OTHERS:

• 3.3 Volt operation

• 100 pin quad flat package

• Output signals may be tris tated to f acilit ate board

level testing

Page 2 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

Figure 1: Functional Block Diagram

2.0 FUNCTIONAL OVERVIEW

The sections below describe the various
configurations, programming and other special
considerations for developing an error correction
system using the AHA4501.

Refer to Figure 1: Functional Block Diagram
for the data f low while reading t he remainder of this
section.

2.1 DATA INPUT

Data is input to the IDATA port via a fully
synchronous ready/accept handshake. Data is
registered internally on the rising edge of clock
when both the ready input (IRDY) and the accept
output (IACPT) are asserted. Refer t o Section 8.0
Figure 18 for data input timing details.

When encoding, data is input either serially
(one bit per handshake) on I DATA[0], or in paral lel
(one byte per handshake) on IDATA[7:0]. When
parallel loading i s used, IACP T toggles at most once
every eight clocks since the data is serialized
internally.

When decoding, data is input one quantization
value per handshake on IDATA[(q- 1):0] where q i s
the input quantization size. The quantization size is
configurable based on the setting of QSIZE[1:0]
within the Quant register. The QMODE[1:0] bits
within the Quant register determine the type of

input data. The input data may be 2’s complement,
sign/magnitude, or unsigned. When QMODE =
“00”, all unused IDATA inputs should be tied to
IDATA[q-1]. When QMODE = “01” or “10”, all
unused IDATA inputs should be tied to ground.
Figure 2 shows example connecti ons when QSIZE
= “01” (3 bits).

IDATA[7:0]

SISO

INPUT

ISA

OUTPUT

ODATA[7:0]

ORDY
OACPT

OSYNC

ENCODER/

HDA

SRAM

FEEDBACK

MULTIPLIER

OA

SRAM

CONTROL R EGISTERS

SRAM

MICROPROCESSOR

INTERFACE

MUXMODE

MDATA[7:0]

PROCMODE

MCSN

MA[2:0]

MRDN_DSN

MWRN_RWN

MALE

MINTN_INTR

IRDY

IACPT

ISYNC

CLOCK

CLOCK

RESETN

AHA4501

DECODER

MRDY_DTACKN

PS4501-1100 Page 3 of 36

Advanced Hardware Architectures, Inc.

Figure 2: IDATA Interface

The value of QSHIFT[1:0] in the Quant register
sets the number of bit positions the inpu t data is
shifted left internally before decoding begins. The
IDATA bits should be shifted to fill the internal
resolution, allowing for higher precision for internal
processing. The increased precision results in the
best possible decoding performance. Throughput
and latency are no t affect ed by the qu antization size
or shift values. The following equations should be
used to dete rmine how to set QSHIFT[1:0] in
relation to QSIZE[1:0]. In ea ch equatio n, qsize and
qshift are the values repr esented by the programmed
value, instead of the programmed value itself. For
example, if QSIZE[1:0] = “01”, qsize in the
following equations would be 3 bits.

QMODE[1:0] = “01” or “10”:

qsize + qshi ft < 6

or

qshift < 6 - qsize

QMODE[1:0] = “00”:

qsize + qshift < 7

or

qshift < 7 - qsize

For best performance, do not shift the data
beyond the internal resolution (7 bits). The above
equations guarantee that this does not occur. For
example, if a particular system has three
quantization bits using QMODE[1:0] = “00”, the
following shows the values to program for each
register.

QSIZE[1:0] = “01” (3 bit input values)

qshift < 7 - qsize

qshift < 7 - 3

qshift < 4

QSHIFT[1:0] = “11” (shift left of 3)

For best performance, do not shift the data
beyond the internal resolution (7 bits). The above
equations guarantee that this does not occur.

The following table shows recommended
QSHIFT values for each QMODE and QSIZE.

Table 1: Recommended QSHIFT Values

For QMODE = “00” connect IDATA as shown For QMODE = “01” or “10” connect IDATA as shown

IDATA7

IDATA2

IDATA6

IDATA3

IDATA4

IDATA5

IDATA2
IDATA1
IDATA0

IDATA1
IDATA0

AHA4501

IDATA7

IDATA2

IDATA6

IDATA3

IDATA4

IDATA5

IDATA2
IDATA1
IDATA0

IDATA1
IDATA0

AHA4501

QSIZE (bits) 2s COMPLEMENT SIGN/MAGNITUDE UNSIGNED

1NA3NA
2333
3322
4211
5100
6 0 NA NA

Page 4 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

2.2 ENCODING

When encoding a 2D bl ock for a (n1,k1)x(n2,k2)

code, k

1×k2

data bits constitute one block. When

encoding a 3D block for a (n

1,k1

)x(n2,k2)x(n3,k3)

code, k

1×k2×k3

data bits constitute one block. The
input data is loaded into the OA SRAM input buffer
as an array with 1 bit per SRAM locat ion. Encoding
begins once the entire block is in the OA SRAM
buffer. The device’s OA SRAM can accommodate
another block while the device encodes the first
block in the buf fer. ECC bits are generated fo r each
x-axis row of the block array and are appended to the
end of the vector. Each y-axis column and each z­axis column (if applicable) are then encoded in the
same fashion. The encoded block is loade d into the
HDA SRAM output buffer and then tra nsferred out
of the device through the ODATA port.

The following figure shows one block of a
(8,4)x(8,4) product code. ‘D’ represents dat a and ‘E’
represents ECC bits. Organizing data blocks into
arrays and interleavi ng are performed by the device
automatically without any system intervention.

DDDDEEEE
DDDDEEEE
DDDDEEEE
DDDDEEEE
EEEEEEEE
EEEEEEEE
EEEEEEEE
EEEEEEEE

The following list of r egist er set tings shows an
example program to encode data. In this example,
the outgoing data is not interleaved, the incoming
data loads in parallel on the IDATA[7:0] bus, the
block code is a 2D (64,57)x(64,57) product code,
and the output asserts OSYNC with the first bit of
every third block. OSYNC usage is discussed
further in Section 2.6.

-Program Config0 register
INTER 0

PAR_SER 1

-Program

Config1 register

XCODE[2:0] 111
Reserved bits 00011

-Program

Config2 register

YCODE[2:0] 111
ZCODE[2:0] 000

-Program

Sync register

SYNC MARK FREQUENCY[3:0] 0011

-Program

Control register

ENCODE 1

After these registers are programmed, the
AHA4501 asserts IACPT to allow IACPT-IRDY
handshakes.

2.3 DECODING

Decoding is done in an iterative fashion.
Decoding begins once a complete recei ved dat a
block is available in the OA SRAM. The device’s
OA SRAM can accommodate another block while
the device decodes the first block. Each full iteration
begins by passing an x-row from the OA SRAM
into the Soft Inpu t Soft Output ( SISO) decoder. The
SISO output is multiplied by a programmable
XFEEDBACK[2:0] value, and stored in the ISA
SRAM. The completion of all x-rows cons titutes
one axis iteration. Refer to Section 2.4 for an
explanation of the feedback multipliers.

Next, each y-axis column from the OA SRAM
is passed into t he SISO decoder. The SISO output is
multiplied b y the programmable
YFEEDBACK[2:0] value and stored in the ISA
SRAM. The c ompletion of all y-columns
constitutes one axis iteration.

If a 3D code is being decoded, each z-axis
column from the ISA SRAM is passed int o the SISO
decoder. The SISO out put is multiplied by the
programmable ZFEEDBACK[2:0] value and stored
in the ISA SRAM. The completion of all z-columns
constitutes one axis iteration.

One full iteratio n is comple ted when one X an d
one Y axis iteration is complete for a 2D code; or
one X, one Y, and one Z axis iteration is complete
for a 3D code. The iterations continue until the
iteration counter equals the number progra mmed in
ITER[4:0] within the Config0 register.

The following sequence may be used to
program the AHA4501 for decodi ng data. This
configuration decodes the same blocks of data
encoded using the configuration shown in the
encoding section.

- Program Config0 register
PAR_SER 1

When decoding, the PAR_SER bit configures the
output on ODAT A[7:0]. In this case, parallel output
is selected.

STITER 1

The STITER bit causes the AHA4501 to stop
decoding when a full iteration completes with no
corrections.

ITER[4:0] 00100

Set for 4 iterations. Refer to Section 4.0
Performance Curves.

- Program Config1 register
XCODE[2:0] 111

(64,57) code type

Reserved bits 00011

PS4501-1100 Page 5 of 36

Advanced Hardware Architectures, Inc.

-Program Config2 register
OECC 0

No ECC bits will be output with the data.

XFBCK[2] 1

Usually set for a feedback multiplier of 1/2 with
square codes.

YCODE[2:0] 111

(64,57) code type

-Program Feedback register
YFEEDBACK[2:0] 100

-Program Quant register
QMODE[1:0] 01

This depends on the type of ADC selected to
recover the transmitted data. For this example
sign/magnitude is selected.

QSIZE[1:0] 10

This also depends on the type of ADC selected.
For this example, 4 bit quantization is selected.

QSHIFT[1:0] 01

This should be set for a 1 bit left shift for the best
possible internal precision with 7 bit internal
resolution and 4 bit quantization. Refer to Section

2.1 Data Input for guidelines on setting
QSHIFT[1:0].

-Program Sync register
SYNC MARK LENGTH[3:0] 0101

The length of the sync mark is selected by the
system designer. For this e xample, the sync mark
length is 20 bits long.

SYNC MARK FREQUENCY[3:0] 0011

-Program Control register
Decode 1

After these registers are programmed, the
AHA4501 asserts IACPT and discards the input
data until ISYNC is asserted.

2.4 FEEDBACK

The TPC algorithm uses feedback, or
weighting, values for perf ormance timing. After
each axis iteratio n, the out put of the SISO De coder
is multiplied by the fee dback cons tant for th at axis.
These values are then fed back into the SISO for
future iterations.

The feedback multiplier values used for each
code axis vary from 1/4 to 11/16 depending on the
number of iterations and system parameters (soft
input bits, resolution). The feedback multipliers
must be tuned to give optimum decoder perfor mance
in a given system. The following describe s the
tuning process. The choice of feedback m ultiplier
has no effect on through put or latency.

For 2D square (XCODE[2:0] = YCODE[2:0])
codes, a typical feedback multiplier value for both
axes at 3 or 4 iterations is 8/16. For 3D cubic
(XCODE[2:0] = YCODE[2:0] = ZCODE[2:0])
codes, a typical feedback multiplier value at 6
iterations is 7/16.

When using non-square or cubic codes, the
following general rules should be applied. Parity
codes should have their feedback multiplier values
set higher than Hamming codes when mixed. For
example, in a (32,26)x(32,26)x( 4,3) code, the X and
Y feedback multipliers should be set to 6/16 while
the Z feedback should be set to 9/16 or 10/16. When
mixing Hamming codes with shorter Hamming
codes, the feedback mult iplier should be set slightly
higher for the shorter code . For example, in a
(64,57)x(32,26) code, the X feedback multiplier
could be set to 8/16, while the Y feedback multiplier
could be set to 9/16.

The feedback values must be tuned for the
number of iterations allowed in a system. For less
iterations than the above guidelines, the feedback
values should be incr eased. For more i terations, th e
values should be decreased. For example, when
using a (64,57)x(64,5 7) code with only 2 ite rations,
the feedback multiplier for both axes should be set
to 10/16. Conversely, in a system that allows 12 or
more iterations, the value for the feedback s hould be
set to 7/16.

The feedback may also need to be tuned
depending on the number of soft input bits
(QSIZE[1:0]). This parameter will only affect the
optimum feedback multiplier value slightly,
meaning that it should be adjusted by only 1/16 or 2 /
16 to allow for these differenc es.

Since systems vary widely, the system designer
should experiment with various feedback multiplier
values to obtain the best performance.
Recommended starting values for feedback are
listed in Table 4.

2.5 DATA OUTPUT

Data is output through the ODATA port via a
fully synchronous ready/accept handshake . Data is
transferred on th e rising edge of clock when both the
accept input (OACPT) and the ready output
(ORDY) are asserted. Refer to Secti on 8.0 Figure 19
for data output timing details.

When encoding, data is always out put ser ia ll y
on ODAT A[ 0]. When decoding, data can be out put
either serially on ODATA[0] or in 8-bit parallel on
ODATA[7:0].

2.6 SYNCHRONIZATION

Since the TPC is a block code, data
synchronization is req uired to correctly decode each
block. External synchronization circuitry is
required to insert an d detect synchronization mark s.
The AHA4501 provides features to remove the
synchronization marks and indicate correct
synchronization mark placement.

Page 6 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

The ISYNC and OSYNC signals are handled in
the same fashion as IDATA[7:0] and ODATA[7:0].
ISYNC is registered internall y on the r ising edge of
clock when both IRDY and IACPT are asserted.
OSYNC is only valid when the ORDY output si gnal
is asserted.

2.6.1 ENCODE SYNCHRONIZATION

When encoding, the AHA4501 provides the
output signal OSYNC to indicate when a
synchronization mark sho uld be inserted in t he data
stream. OSYNC is asserted with the firs t data bit of
each x output blocks, where x is the value of SYNC
MARK FREQUENCY[3:0] programmed within
the Sync register. The system can then use OSYNC
to insert a synchroniza tion mark in the encoded data
stream before transmitting.

2.6.2 DECODE SYNCHRONIZATION

When decoding, the synchronization circuitry
depends on the channe l a nd demodulation meth od.
For the first block a fter reset, the AHA4501 discards
the input data on IDATA[7:0] until the ISYNC
signal is asserted. The first bit of the block is
registered on the same clock as ISYNC is asserted.

After the first bl ock, synchronizat ion marks are
automatically removed from the data by
programming SYNC MARK LENGTH[3:0] and
SYNC MARK FREQ[3:0] within the Sync register .
SYNC MARK LENGTH[3:0] configures the
AHA4501 to remove x bits from the start of every
synchronization block, where x is 4 times SYNC
MARK LENGTH[3:0]. The AHA4501 expects a
synchronization mark at the block inte rval specified
by SYNC MARK FREQUENCY[3:0].

If ISYNC is not asserted with the first bit after
SYNC MARK LENG TH[3:0] han dshakes, a loss of
synchronization is indicated by assertion of the
SMMIS bit in the Interrupt register. If the system
designer chooses not to use the synchronization
support logic of the AHA4501, the ISYNC signal
must be tied high. The CORRECTIONS[9:0] cou nt
and CORINC bit can also be u sed t o indicat e a l oss
of synchronization. The control microprocessor
may use this information to send a resynchronize
command to cause the AHA4501 to synchron ize on
the start of the next data block by discarding input
data until ISYNC is asserted.

The OSYNC signal is assert ed with th e first bit
of every block when decoding.

2.6.3 RESYNCHRONIZE

Loss in synchronization may be detec ted usi ng
SMMIS, CORINC, NITER[4:0], and
CORRECTIONS[9:0]. The control micr oprocessor
may use this informat ion to determine that the
AHA4501 is not synchronized and issue a
resynchronize command. The AHA4501 does not
automatically re synchr onize t he dat a stre am unles s
instructed to do so by the m icroprocessor.

The resynchronize command causes the
AHA4501 to stop decoding blocks and discard the
input data until ISYNC is asserted. The AHA4501
continues to output any blocks that have been
decoded and are waiting to be unloaded from the
HDA SRAM.

The AHA4501 registers the input from
IDA T A[7:0] on the same c lock as ISYNC is asserted.

2.7 HELICAL INTERLEAVING

The device can optionall y interleave when
encoding and deinterleave when decodi ng.
Interleaving data spreads bursts of noise across all
axes of the block code for the best error correction
performance in burst channel use. Interleaving in
the AHA4501 is applied aft er encoding takes pl ace.
Deinterleaving in the AHA4501 t akes place before
the decoding operation.

Helical interleaving i s applied alo ng a diagonal
path through the encoded b lock. Data is output along
diagonal lines from the upper left to lower right
corner (for a 2D code). The first diagonal output
starts with the bit row 1, column 1 followed by the
diagonal starting at row 1, column 2. For 3D codes,
instead of readin g di agonal ly t hrough the 2D ar ray,
interleaving r eads diagonally th rough a cube of dat a.

The example below shows how interleaving is
applied for a 2D (64,57)x(64,57) code.

Figure 3: Input Block

Note: The number reflect s the bit order, including

generated ECC bits.

0123 63

64 65 66 67 127

128 129 191

192 193

4032 4033 4095

. . .

. . .. . .. . .

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

130

. . .

. . . . . .

PS4501-1100 Page 7 of 36

Advanced Hardware Architectures, Inc.

The encoded, interleaved data output is taken
along diagonal lines starting with bit 0 as shown
below . The order of the interleaving is note d for each
diagonal line.

Figure 4: 2D Interleaving

For the (64,57)x(64,57) block, the data output
from the AHA4501 is: 0, 65, 130, . .., 4095, 1, 66, ...,
4031, 4032, 2, 67, ..., ..., 63, 64 , ..., 4094 for a total
of 4096 bits output. The AHA4501 operating as a
decoder deinterleaves the block to restore it to its
orginal order.

Figure 5: Encoded/Interleaved Data Output

Data bits are output from the encoder in row
order from left to right. 3D interleaving/
deinterleaving is done by reading/writing cells
diagonally through t he x, y, and z dimensions. Note
that the data rate drops when interleaving and/or
deinterleaving as di scussed in Section 2.8.

2.8 DATA THROUGHPUT

The AHA4501 contains internal buffering at the
input (OA SRAM) and the output (HDA SRAM) to
allow the device to maintain a constant input data
rate with no external memory. The AHA4501 is
capable of loading a code block into 1/2 of the OA
SRAM while it is processing a second code block
from the other 1/2 of the OA SRAM. The second
code block is loaded int o the 1/2 of the HDA SRAM
while a third code block can be output from the
other 1/2 of the HDA SRAM. This ping-pong buffer
arrangement on the input and output sides of the
AHA4501 allows code blocks to be processed in a
continuous stream as lon g as the ov erall ban dwidth
of the device is not exceeded.

When encoding a data block, the data can be
transferred continuously at up to one bit per clock,
independent of the code type. A 1 clock delay
occurs between blocks.

When decoding a code block and not
deinterlea ving, the max imum input ra te is one soft
value per clock, independ ent of code type. A 1 clock
delay occurs between blocks. When decoding a
code block and deinterle aving, the maxi mum input
rate is one soft value e very 3 clocks, ind ependent of
code type. A 1 clock delay also occurs between
blocks when deinterleaving.

The following diagrams illustrate how code
blocks are processed through the AHA4501 and
when the internal status registers update the status
of the blocks.

In Figure 6,

the data is input at a bit per clock
and encoded. The data is encoded by appending
ECC bits to the data. Note that the data is always
encoded faster than da ta can be i nput to t he device.
Since the output is operating at a bit/clock and there
are more output bits than input bits, the output is t he
limiting facto r in the system . After the init ial buf fer
loading, the input must wa it for the out put to f i nish
unloading a block before accepting another block.
The ratio of the input blo ck size to t he output blo ck
size is the code rate

.

Figure 6: Encoding at the Maximum Input Rate (bit/clock) with Maximum Output Rate (bit/clock)

0123 63

64 65 66 67 127

128 129

1

191

192 193

4032 4033 4095

. . .

. . .. . .. . .

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

130

. . .

. . . . . .

2 4 126

127

3

0 65 130 . . . 4095

1 66 131 . . . 4032

2 67 4033

368

63 64 4094

4030

4029. . .129

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

132

4031

. . . 3968

1

Input Data

Encoding

Output Data

COMPL Interrupt

234 5

1 2 3

1 2 3 4

1 2 3 4

Page 8 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

In Figure 7, the data is input a t a slo wer rat e than

the output rate which allo ws a constant input data rate

.

In Figure 8,

the received data is input at a bit
every ot her clock and decoded. When deco ding, the
decode time is v ariable de pending on the n umber of
iterations used, type of code and the status of the
STITER bit. In this example, the iterat ions are set so
that the decode time is app roximately eq ual to the
data input time. For continuous data input, set the
ITER[4:0] count such that the decoder time is less
than the data block in put ti me. Refe r to Sect ion 2.9
Encoding/Decoding Time for decoding time
calculations

.

In Figure 9,

the received data is input at a bit
every other clock and decoded. When decoding, the
decode time is v ariable depending on th e number of
iterations used, type of code and the status of the
STITER bit. In this example, the iteration count in
ITER is set to 6 to illustra te a case where the decode
time is the limiting factor in the throughput. To
achieve maximum decoder performance with burst
data, set the iteration count such that the decoder
time is equal to or exceeds th e data block input time.

Figure 7: Encoding at Less Than Maximum Input Rate with Maximum Output Rate

Figure 8: Decoding with Continuous Input Data Rate - STITER not Asserted

Figure 9: Decoding with Burst Input Data Rate - STITER not Asserted

Input Data

Encoding

Output Data

COMPL Interrupt

1 2 3 4

1 2 3

1 2 3 4

1 2 3 4

Input Data

Decoding

Output Data

Status/Corrections Register

block 1 block 2

1 2 3

block 3

1 2 3

1 2 3

CORINC & COMPL Interrupt

1 2 3

Input Data

Decoding

Output Data

Status/Corrections Register

block 1 block 2 block 4

1 2 3 4

1 2 3 4

block 3

5

1 2 3

CORINC & COMPL Interrupt

1 2 3 4

PS4501-1100 Page 9 of 36

Advanced Hardware Architectures, Inc.

In Figure 10, the received data is input at a bit

per clock and decod ed. In this example , the iteration
count in ITER is set to 6 and the STITER bi t is set to
illustrate a case where the decode time is variable
depending on the number of iterations required to
correct the error s in the code block. In this e xample,
blocks 1, 2, 4, and 5 decode in 2 iterations while
block 3 requires 6 iterations to decode.

When decoding, writing a one to the DUMP bit
within the Control register causes the module to
stop iterations on the curr ent block and send it to the
output data port. Th e dump occurs upon compl etion
of the axis iteration following the current axis
iteration. The worst case dela y is two axis iterations
(which is equal to one full iterati on for 2-D codes) .

Decoding then begins on the next (already loaded)
data block, and another block can begin loading.

In Figure 11, the example from Figure 10 is
shown to illustrate the DUMP feature. In the third
decoding block, DUMP is set in the fourth it eration.
The decoder finishes the current full iteration before
it outputs the block. Decoding on block 4 starts
normally.

The DUMP feature is useful when using an
input buf fer with the STITER configu ration bit, and
the input bu ffer becomes full. Note that the DUMP
bit does not caus e loss of data. Upon completi on of
the dump, the COMPL interrupt bit is set, and the
CORINC bit is set if any corr ections were m ade in
the last axi s iteration. This bit should n ot be set
when encoding

.

Figure 10: Decoding with Burst Input Data Rate - STITER Asserted

Figure 11: DUMP Feature

Input Data

Decoding

Output Data

Status/Corrections Register

block 1 block 2 block 4

1 2 3 4

1 2 3

block 3

5

1 2

4 5

6

4

block 5

CORINC & COMPL Interrupt

1

2 3 4

3 5

5

Input Data

Decoding

Output Data

Status/Corrections Register

block 1 block 2 block 4

1 2 3 4

1

block 3

5

1 2

6

4

block 5

CORINC & COMPL Interrupt

1 2 3 4

3 5

5

123212

123412

4 5

12

Iterations

DUMP Bit Set

Page 10 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

2.9 ENCODING/DECODING TIME

The time required to encode a data block is equivalent to the time to decode 1 code block with 1 full
iteration. Since the AHA4501 can per form 1 full iteration fast er than data can be transferre d serially through
the encoded data output p ort, the output rate is the limiting factor for the overall data rate.

The time to decode a c ode block depends on the input clock frequency, the code type, and t he number
of iterations. The foll owing equations are used to compute the overall decoding time. The decoding time
can be used to compute the data rate and latency.

Note that if the STITER bit i s set in the Config0 register, the AHA4501 stops iterating when there are
no corrections. When the STITER bit is set, the number of iterations is unpredictable and the decode time
may be shortened or lengthened depending on the error content data stream. The number of iterations will
never be mor e than the number set in ITER[ 4:0] even when STITER is set.

nx = Length of entire vector (data + ECC) for X axis code
kx = Length of data vector for X axis code
ny = Length of vector (data + ECC) for Y axis code
ky = Length of data vector for Y axis code
nz = Length of vector (data + ECC) for Z axis code (nz=1 for 2D codes)
kz = Length of data vector for Z axis code (kz=1 for 2D codes)
i = Iterations
d = Number of clocks to decode one block
f = Clock frequency (Hz)
r

ch

= Channel rate (bits/sec)

r

d

= Data rate (bits/sec)

C

1,C0

= decode constants, see table 1.

CR = code rate.

Code rate for a (nx,kx)

x (ny,ky) x (nz,kz) code:

Clocks to decode an entire block:

d = c

1

x i + c

0

Maximum channel rate for a 3D block (for a 2D block, nz = 1):

Maximum data rate for a 3D block (for a 2D block, kz=1):

If interleaving is used, the maximum channel rate will be the lesser of r

ch

listed above and f / 3 and the

maximum data rate will be the lesser of r

d

listed above and (f x CR)/ 3.

CR

kx ky kz

××

nx ny nz××

----------------------------- -





=

r

ch

nx ny nz× f××

d

------------------------------------- -=

r

d

kx ky kz×

f

××

d

------------------------------------ -=

PS4501-1100 Page 11 of 36

Advanced Hardware Architectures, Inc.

2.10 SUMMARY OF CHANNEL RATES

The channel rates listed i n the following table are calculated with a 50 MHz clock frequency . The channel
rate changes in proport ion with the change in clock fre quency. Fo r example, if the clock frequenc y is 25 Mhz,
all channel rates are divided by 2. To compute data rate, multiply these values by the overall code rate.

Note: This table does not include all codes supported by the device. For decode times and code rates for codes

other than those listed here, see the AHA4501 windows evaluation software.

Table 2: Channel Rates

BLOCK CONFIGURATION

(n

1,k1

)x(n2,k2)x(n3,k3)

NUMBER OF ITERATIONS

23 6

C

1

C

0

(64,57)x(64,57) decode time (clocks) 5612 7963 15016

2351 910

Code Rate = .793 channel rate (Mbits/sec) 36.5 25.7 13.6

(32,26)x(32,26)x(4,3) decode time (clocks) 8368 11917 22564

3549 1270

Code Rate = .495 channel rate (Mbits/sec) 24.5 17.2 9.1

(16,11)x(16,11)x(16,11) decode time (clocks) 7816 11197 21340

3381 1054

Code Rate = .325 channel rate (Mbits/sec) 26.2 18.3 9.6

(32,26)x(16,11)x(8,4) decode time (clocks) 7992 11421 2 1708

3429 1134

Code Rate = .278 channel rate (Mbits/sec) 25.6 17.9 9.4

(64,57)x(32,26) decode time (clocks) 2972 4227 7992

1255 462

Code Rate = .724 channel rate (Mbits/sec) 34.5 24.2 12.8

(32,26)x(16,11)x(4,3) decode time (clocks) 4304 6141 11652

1837 630

Code Rate = .419 channel rate (Mbits/sec) 23.8 16.7 8.8

(64,57)x(8,4)x(4,3) decode time (clocks) 4448 6357 12084

1909 630

Code Rate = .334 channel rate (Mbits/sec) 23.0 16.1 8.5

(32,26)x(32,26) decode time (clocks) 1540 2211 4224

671 198

Code Rate = .660 channel rate (Mbits/sec) 33.2 23.2 12.1

(16,11)x(16,11)x(4,3) decode time (clocks) 2224 3181 6052

957 310

Code Rate = .354 channel rate (Mbits/sec) 23.0 16.1 8.5

(32,26)x(16,11) decode time (clocks) 860 1239 2376

379 102

Code Rate = .559 channel rate (Mbits/sec) 29.8 20.7 10.8

(16,11)x(16,11) decode time (clocks) 464 679 1324

215 34

Code Rate = .473 channel rate (Mbits/sec) 27.6 18.9 9.7

Page 12 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

2.11 LATENCY

Since product cod es ar e bloc k code s, the data for a n e ntire b lock mus t be inp ut to the AHA4501 before
encoding or decoding can start. If interleaving is not enabled, the latency (in clock cycles) from the first
input bit of a block to the first output bit of the same block is:

If interleaving is enabled the latency for encoding a block (in clock cycles) is:

block input time + block encode time + 17

The latency for decoding an interleaved block (in clock cycles) is:

block input time + block decode time + 19

For example, the block decode time and latency to decode a (64, 57)x(64,57) non-int erleaved co de with
2 iterations and a 50 MHz clock are shown below. The example assumes the input and output operate at
maximum speed.

The time to decode a (64,57)x(64,57) block (as shown in Section 2.10) is:

Assuming that the dat a is input at the dec ode data rate (i .e., the block in put time equals th e block decode
time) the total latency is:

2.12 MICROPROCESSOR INTERFACE

The AHA4501 is capable of interfacing directly to a microprocessor for embedded applications. All
register accesses to the AHA4501 are performed on an 8-bit bidirectional bus, using either an Intel

®

or

Motorola

®

style interface. The interface is in Motorola® mode when the PROCMODE input signal is

asserted, otherwise the interface is in Intel

®

mode.

A MUXMODE input is also provided to allow the data and address to be multiplexed on the
MDATA[7:0] bus. The data and address are multiplexed when MUXMODE is asserted, otherwise both
MDATA and MA busses are used.

Refer to Section 8.0 for microprocessor interface timing diagrams.

3.0 INTERNAL REGISTER PROGRAMMING

Table 3: Register Summary

Notes:

1) U - These bits remain unchanged after a soft reset.

2) The reserved bits in Register Address 0x01 must be written to 00011 after any hard reset.

ADDRESS R/W MNEMONIC REGISTER NAME HARD RESET SOFT RESET

0x00 R/W Config0 Configuration0 0x26 unchanged
0x01 R/W Config1 Configuration1 0xE0 unchanged
0x02 R/W Config2 Configuration2 0x38 unchanged
0x03 R/W Feedback Feedback 0x24 unchanged
0x04 R/W Quant Quantization 0x0C unchanged

0x05

R Correct Corrections/

0x00 unchanged

W Sync Synchronization

0x06 R Status Status 0x00 unchanged
0x07

R Interrupt Interrupt

0x00 UUUUU000

W Control Control

0x08 Reserved Reserved 0x0C unchanged

block input time block decode(encode) time + 9+

5612

1

50 MHz

-------------------





112.2µs=×

2112.2×µs 9

1

50MH z

------------------





×

+ 224.47µs=

PS4501-1100 Page 13 of 36

Advanced Hardware Architectures, Inc.

3.1 CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE

This register is initialized to 0x26 after hard reset, unchanged after soft reset.
INTER - Deinterleave incoming data when decoding, an d interleave outgoing data when encoding. See

Section 2.1 Data Input for details about interleaving/deinterleaving.

P AR_SER - Parallel/Serial Mode Select. When P AR_SER is se t during encoding, the d evice will input 8 bits

in parallel from the IDATA[7:0] bus. The first encoded bit output on ODATA[0] will be from
IDATA[0]. In other wo rds, IDATA[0] is the LSB and IDATA[7] is the MSB. The IRDY pin
controls the flow of data into IDATA[7:0]. Typically, the IACPT pin will be active 1 out of 8
clock cycles when in parallel mode. During encoding the output is always bit serial on
ODATA[0].

When PAR_SER is not set during encoding, the data is input from IDATA[0] one bi t per
handshake and output from ODATA[0] one bit per handshake. The unused pins IDATA[7:1]
should not be left floating, they should be tied to GND.

When PAR_SER is set during decodi ng, the device will pack the output de coded data bits into
8-bit bytes on ODATA[7:0] . The out put bi t on ODATA[0] is g enerat ed fr om the fi rst s of t input
symbol. ODAT A[0] is the LSB and ODATA[7] i s the MSB. The ORDY pin controls the f low of
data out of ODATA[7:0]. Typically, the ORDY pin is active 1 out of 8 clock cycles when in
parallel mode. The input da ta will be on IDATA[n-1 :0] where n is the number of soft input bits.
The unused IDATA pins should not be left floating, they should be tied to GND.

When PAR_SER is not set during decoding, the data is input from IDATA[n-1:0] one soft
symbol per handshake where n is the number of soft i nput bits. The decode d data is output from
ODATA[0] one bit per handshake.

STITER - Stop iterating when no corrections. Used only when decoding; the AHA4501 can determine if

future iterations can be useful. When this bit is set, the module stops iterating when the
decoding is completed. When cleared, it always executes the number of full iterations in
ITER[4:0]. Note that in either case, the number of full iterations does not exceed ITER[4:0]. At
any time after the first iteration, the microprocessor can also write a 1 to the DUMP bi t in the
Control reg ister , in which case al l future iter ations are cance lled and the current block is output.
This bit is ignored when encoding.

ITER[4:0] -Maximum Iterations. Used only when decoding; number of full iterations to perform for each

block. One full ite ration i s def ined a s deco din g the x and y axes for a 2D bloc k or a ll x, y and z
axes for a 3D block. The value of 0x0 indicates 32 full iterations. If STITER is asserted, less
iterations than the ITER[4:0] count may be performed. This value is ignored when encoding.

3.2 CONFIGURATION 1, ADDRESS 0x01 - READ/WRITE

This register is initialized to 0xE0 after hard reset, unchanged after soft reset.
XCODE[2:0] -Code for x axis of product array. See Config2 register ZCODE [2:0] description.
res - Reserved bits [4:0]. Mu st be written to 00011.

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x00 INTER PAR_SER STITER ITER[4:0]

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x01 XCODE[2:0] res

Page 14 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

3.3 CONFIGURATION 2, ADDRESS 0x02 - READ/WRITE

This register is initialized to 0x38 after hard reset, unchanged after soft reset.
OECC - Output ECC Bits. Used only when decodin g. When cl eared , only the da ta bit s are out put; tota l

output bits per b lock = k

1×k2

(2D), or k1×k2×k3 (3D). When set, both the data and ECC bits are

output; total output bits per block = n

1×n2

(2D), n1×n2×n3 (3D).
XFBCK[2] -x axis feedback bit 2. See description for Feedback register (0x03).
YCODE[2:0] -Code for y axis of product array. See ZCODE[2:0] description for code definitions.
ZCODE[2:0] -Code for z axis of product array. Set to 000 for all 2D codes.

Each code axis is defined as follows:

The following rules must be followed when selecting codes:

1) The (4,3) parity code and “n

0

code” is illegal for both the x axis code and the y axis code.

2) 2D codes require that the x dimension product code and the y dimension product code be
at least 16 bits.

3) n

1

x n2 x n3 must be less than or equal to 4096.

The AHA4501 is designed to allow any combination of x, y and z codes that follow the

above rules. The code combinations listed below have been fully verified.

In addition to the following codes, the TPC codes may be shortened with zero padding

techniques. Contact AHA Application Engineering for details.

Ta ble 4: Supported Codes with Recommended Feedback Values

Note: The feedback values listed in T able 4 ar e r ecommended starting values. Dependin g on the tar get Bit Err or Rate,
the user may wish to adjust the feedback values slightly for more optimal performance. The AHA4501 Windows
Evaluation software can be used to fine tune the feedback for any selected configuration.

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x02 OECC XFBCK[2] YCODE[2:0] ZCODE[2:0]

111
110
101
100

(64,57)
(32,26)

(16,11)

(8,4)

-- Extended Hamming Codes

*

011
010
001

(16,15)

(8,7)
(4,3)

-- Parity Only Codes - even parity

* 000 no code * valid only in ZCODE[2:0]

BLOCK CONF IGURA T I ON

(n1,k1)x(n2,k2)x(n3,k3)

BLOCK SIZE

(bits)

DATA SIZE

(bits)

CODE

RATE

FEEDBACK

(4 iterations)

FEEDBACK

(32 iterations)

(64,57)x(64,57) 4096 3249 0.793 1/2,1/2 7/16,7/16

(32,26)x(32,26)x(4,3) 4096 2028 0.495 3/8,3/8,11/16 5/16,5/16,9/16

(16,11)x(16,11)x(16,11) 4096 1331 0.325 7/16,7/16,7/16 3/8,3/8,3/8

(32,26)x(16,11)x(8,4) 4096 1144 0.278 3/8,3/8,7/16 3/8,3/8,3/8

(64,57)x(32,26) 2048 1482 0.724 1/2,9/16 7/16,1/2

(32,26)x(16,11)x(4,3) 2048 858 0.419 3/8,7/16,11/16 5/16,3/8,9/16

(64,57)x(8,4)x(4,3) 2048 684 0.334 3/8,7/16,11/16 5/16,3/8,9/16

(32,26)x(32,26) 1024 676 0.660 1/2,1/2 7/16,7/16

(16,11)x(16,11)x(4,3) 1024 363 0.354 3/8,3/8,11/16 5/16,5/16,9/16

(32,26)x(16,11) 512 286 0.559 7/16,1/2 3/8,7/16
(16,11)x(16,11) 256 121 0.473 1/2,1/2 7/16,7/16

PS4501-1100 Page 15 of 36

Advanced Hardware Architectures, Inc.

3.4 FEEDBACK, ADDRESS 0x03 - READ/WRITE

This register is initialized to 0x24 after hard reset, unchanged after soft reset.
XFEEDBACK[1:0] - Feedback multiplier for x axis iteration. Used only when decoding.
YFEEDBACK[2:0] - Feedback multiplier for y axis iteration. Used only when decoding.
ZFEEDBACK[2:0] - Feedback multiplier for z axis iteration. Used only when decoding 3D codes.

Each feedback value is defined as follows:

000 - Multiply feedback by 1/4
001 - Multiply feedback by 5/16
010 - Multiply feedback by 3/8
011 - Multiply feedback by 7/16
100 - Multiply feedback by 1/2
101 - Multiply feedback by 9/16
110 - Multiply feedback by 5/8
111 - Multiply feedback by 11/16

Refer to the Section 2.3 Decoding for a functional description of the feedback values.

3.5 QUANTIZATION, ADDRESS 0x04 - READ/WRITE

This register is initialized to 0x0C after hard reset, unchanged after soft reset.
res - Reserved bits. Must be written to 00.
QSH IF T[1 :0 ] - Quanti zation Shift. Used only when decoding; mu st be set to “00” when encodi ng. The input

data can be shifted bitwise left inside the device before decoding begins. This is useful with
smaller input quantization sizes. See Section 2.1 Data Input for details about how to set this
value. Defined as follows:

00 - No shift
01 - Shift input data left 1 (multiply by 2)
10 - Shift input data left 2 (multiply by 4)
11 - Shift input data left 3 (multiply by 8)

QSI ZE[1:0 ] - Quantization Size for soft in put dat a. Used only when decoding. Specifies the n umber of bits

of data for each soft inpu t value. Soft i nput data must a lways be driven on I DATA[QSIZE-1:0].
Defined as fo llows:

00 - 1 bit, 2 bits
01 - 3 bits
10 - 4 bits
11 - 5 bits

*See Note 1 for 6 bit

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x03 XFEEDBACK[1:0] YFEEDBACK[2:0] ZFEEDBACK[2:0]

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x04 res QSHIFT[1:0] QSIZE[1:0] QMODE[1:0]

Page 16 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

Notes:

1) 6 bit quantization is supported when QMODE[1:0] = “00”. Since the data is in 2’s complement
notation, the data on IDAT A[5:0] is transferr ed directly to the OA SRAM. The value of QSIZE[1:0]
is ignored when QMODE[1:0]= “00”.

2) 1 bit quantization (hard decision input) is supported by setting QSIZE[1:0] = “00” and
QMODE[1:0] = “01”. It is recommended that QSHIFT[1:0] be set t o “11” for hard decisio n inp ut
data. The hard decision input is connected to IDATA[1]. IDATA[0] must be tied high.

QMODE[1:0] - Quantization Mode for soft input data. Used only when decoding; must be set to “00” for

encoding. When set to “00”, input data is assumed to be in signed 2's complement notation
(mid-tread). When set to “01”, data is assumed to be mid-riser sign /magnit ude not ation . When
set to “10”, data is assumed to be mid-riser unsigned. The confidence mapping for each mode
is shown on the next page with four bit quantization.

3.6 CORRECTIONS, ADDRESS 0x05 - READ

This register is initialized to 0x00 after hard reset, unchanged after soft reset.

COR REC TI ON S[ 7:0 ] - The ei ght least signific ant bits of the number of hard decision correct ions made over

the entire number of iterations executed on one block. The upper two most sign if ic ant bits are
accessed via the Status register. This value is updated each time the COMPL interrupt bit is
set. This value contains the count of the number of bits corrected between the input data
(assuming hard decisi on decoding), and t he output data. If t he count overflows , the CFLOW bit
is set, and the value of the count is invalid. Invalid when encoding.

3.7 SYNCHRONIZATION, ADDRESS 0x05 - WRITE

This register is initialized to 0x00 after hard reset, unchanged after soft reset.

SYN C M A R K LENGTH[ 3 : 0 ] - When decoding, the module can aut omatic ally re move sync mar ks f rom the

incoming data stream. The number of bit s to be discarded is 4 time s the value of the Sync Mark
Length register. This allows sync marks to be f rom 4 to 60 bi ts in length. A value of ze ro results
in no discarded bits.

SYNC MARK FREQUENCY[3:0] - The number of blocks between synchronization marks. When

encoding, the OSYNC signal asserts with the first bit of each x output blocks, where x is the
value of SYNC MARK FREQUENCY[3:0] in the Sync regist er . When d ecoding, the ISYNC is
checked at the first bit of each x input blocks, where x is the value of SYNC MARK
FREQUENCY[3:0] in the Sync register. If the ISYNC signal is not asserted, the Sync Mark
Mismatch interrupt bit is set. A value of 1 indicates that the signals are asserted/checked at the
start of every block. A value of 0 indicates every 32 blocks.

See Section 2.6 Synchronization for more information.

QMODE[1:0] Input Data Type

Hard Decision 0

Confidence Range

No

Confidence

Hard Decision 1

Confidence Range

Max . . . Min Min . . . Max

00 2’s Complement 1000 . . . 1111 0000 0001 . . . 0111
01 Sign/Magnitude 0111 . . . 0000 N/A 1000 . . . 1111
10 Unsigned 0000 . . . 0111 N/A 1000 . . . 1111

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x05 CORRECTIONS[7:0]

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x05 SYNC MARK LENGTH [3:0] SYNC MARK FREQUENCY[3:0]

PS4501-1100 Page 17 of 36

Advanced Hardware Architectures, Inc.

3.8 STATUS, ADDRESS 0x06 - READ ONLY

This register is initialized to 0x00 after hard reset, unchanged after soft reset.
NOTE: This register must not be written.

NITER[4:0] - Number of iterations. The actual number of iterations performed in the last block decoded.

This value is updated each t ime the COMPL interrupt bit is set. Note that if t he STITER bit is
cleared, this value will always be equal to the programmed ITER[4:0] value.

The internal iteration value is incremented after a y-axis iteration is completed for 2D codes or
after a z-axis iteration is completed for 3D codes. If the STITER bit is set, the iterations may
finish after an axis iteration rather than a full iteration. In this case, the NITER[4:0] value will
be the numbe r of full iterat ions completed.

CFLOW - Correction Overflow. Set if the CORRECTIONS[9:0] count exceeded the value of 1024

corrections. When set, the CORRECTIONS[9:0] count value is invalid.

CORRECT[9:8] - The two most significant bits of the number of hard decision corrections made over the

entire set of iter ations. This value is updated each time the COM PL in te rr upt bit is set. Invalid
when encoding.

3.9 CONTROL/INTERRUPT, ADDRESS 0x07 - READ/WRITE

This register is initialized to 0x00 after hard reset. The interrupt bits [2:0] are reset, but all other register

contents are unchanged after soft reset.

Note: All interrupts and bits 0, 1, 2 are cleared when this register is read.

DECODE (R/W) - When set, the module performs decoding on the input data. The DECODE bit must not

be set with the ENCODE bit. If both bits are cleared, the module is idle and does not accept
input data. The SRESET bit should b e writte n with or after clea ring the DECODE bit to ensure
proper operation. The DECODE bit should not be set within 5 clocks of SRESET.

ENC OD E (R / W ) - When set, the module p erforms en coding on t he input da ta. The out put data i s a seri al bit

stream of both data and ECC code bits. The ENCODE bit must not be set with the DECODE
bit. If both bits are cl eared, the module is idl e, and does not accept input da ta. The SRESET bi t
should be written with or after clearing the ENCODE bit to ensure proper operation. The
ENCODE bit should not be set within 5 clocks of SRESET.

CORINCM (R/W) - Correction Incomplete Mask. When cleared, the MINTN_INTR interrupt signal is

asserted when the CORINC interrupt bit is asserted. When set, the interrupt si gnal is not
asserted with CORINC.

SMMISM (R/W) - Sync Mark Mismatch Mask. When cleare d, the MINTN_I NTR interrupt si gnal is

asserted when the SMMIS inter rupt bit is assert ed. When set, the inte rrupt signal is not ass erted
with SMMIS.

COMPLM (R/W) - Block Decode Co mplete Mask. When cleared, the MINTN_INTR interrupt signal is

asserted when the COMPL inter rupt bit is asserted. Whe n set, the interrupt si gnal is not asserted
with COMPL.

Address

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x06 NITER[4:0] CFLOW CORRECT[9:8]

RD/WR

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Read

DECODE ENCODE CORINCM SMMISM COMPLM

CORINC SMMIS COMPL

Write SRESET RESYNC DUMP

Page 18 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

CORINC (R) - Correction Incomplete. The nature of the algorithm allows the module to determine if

another iteration would be useful. When the module has reached the maximum number of
iterations progra mmed in ITER[4:0 ], a check is do ne to determine if anoth er iteration wou ld be
useful. If another it eration would be useful, then the data in the block may or may not be
correct, and the CORINC interrupt bit is set. Note that this bit is pessimistic, meaning that it
may be asserted when error less da ta is o utput from the device whe n the l ast corr ection happens
on the last iteration. This is especially true when the value of ITER[4:0] is 2 or less. Therefore,
it must not be used to discard a block of data if set. Its use is more valuable in verifying that a
correct synchronization of data has occurred, or that synchronization has been lost. This bit is
never set when encoding.

SRESE T ( W ) - Soft Reset. Writing a 1 to this bit causes a reset of the entire data path. The input and output

ports immediately st op handshaking d ata. The Control/Interrupt register bits [2:0] a re reset, but
all other register conten ts ar e unaffected by SRESET. Note that all data int ern al to the module
is lost. SRESET should not be issued at the same time as either DECODE or ENCODE.

SMMIS (R) -Sync Mark Mismatch. After the first block of data has been input to the device, each x block

is checked for asse rtion of t he ISYNC signal with the f irst bit of the block, whe re x is the value
of SYNC MARK FREQUENCY[3:0] in the Sync register. If the ISYNC signal is not asserted
when the module is at the start of a new bl ock, t he SMMIS bit i s se t. Note , however, that when
this condition occurs, the module assumes the ISYNC signal is incorrect, and does not set the
write pointers to the b eginni ng of the block. I f this is neces sary, the microprocessor must i ssue
a resynchronize command by setting the RESYNC bit of the Control register. This bit will
never be set when encoding.

RES YN C (W ) - Re synchronize. When decoding, if t he microprocesso r has determin ed that synchr onization

has been lost in the data stream, it can issue a RESYNC by writing a one to this bit. This will
cause the module to st op reading inp ut data bits, discard al l data read i n the current input block,
and wait for an ISYNC signal. Note that the block that is being decoded when a RESYNC is
issued will be output to the data port. This bit must not be set when encoding.

COMPL (R) - Block Decode Complete Set at the completion of each block encoding or decoding cycle,

indicating that the block is ready to be output. When decoding, the value of NITER[4:0], and
the CORRECTIONS[9:0] count value in the Correct and Status registers are updated each time
the COMPL bit is set. The CORINC bit will also be set with COMPL if the incomplete
condition was detected.

DUMP (W) -Dump Current Block. When decoding, writing a 1 to this bit will cause the module to stop

iterations on the current block and send it to the output data port. The dump occurs upon
completion of the axis it eration following th e current axis i teration. The worst ca se delay is two
axis iterations ( which i s equal t o one ful l itera tion for 2D codes). Decoding t hen begins on the
next (already loaded) data block, and another block can begin loading.

3.10 RESERVED, ADDRESS 0x08 - RESERVED

This register is for production test purposes only.

PS4501-1100 Page 19 of 36

Advanced Hardware Architectures, Inc.

4.0 PERF ORMANCE CURVES

The following figures show a co mparison betw een the (64,57)x(64,57 ) TPC implementatio n which has
a code rate of 0.793, and two Reed-Solomon/Viterbi implementations with code rates of 0.806 and 0.790.
The modulation is Phase Shift Keying (PSK), and the channel model is Additive White Gaussian Noise
(A WGN). Note that the TPC implementation consistently outperforms the RS/Viterbi implementations at 2
iterations. Additional iterations increase TPC performance.

Figure 12: Turbo Product Code vs. Reed-Solomon/Viterbi Performance Comparison

Figure 13 shows the performance of the three 4k block codes in the same channel with 32 iterations.

Figure 13: Comparison of TPC Code Types

Figure 14 shows the Eb/No required to achieve a Bit Erro r Rate (BER) of 10

-5

.

using the (64,57)x(64,57)
block code in an AWGN channel. This figure shows the correction performance trade-offs between input
quantization bits and iterations (data rate). Optimum performance occurs with 32 iterations and 6 input
quantization bits, however, excellent performance can be achieved with only 3 input quantization bits or
only 3 iterations.

12345678910

Eb/No (dB)

10

−8

10

−7

10

−6

10

−5

10

−4

10

−3

10

−2

10

−1

10

0

Bit Error Rate, P(e)

Turbo Product Code vs. Reed−Solomon/Viterbi

(64,57) x (64,57) Hamming Product Code, Rate = 0.793

Uncoded PSK, rate=1
RS/Viterbi, Rate=0.806
RS/Viterbi, Rate=0.790
TPC, 1 Iteration
2 Iterations
3 Iterations
4 Iterations
6 Iterations
32 Iterations
Shannon Capacity

Turbo Produc t Co d e Performance

AHA4501 EVM, 4096 bit blocks

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

012345678910

Eb/No (dB)

Bit Error Rate P(e)

Uncoded PSK Channel
(64,57) x(64,57), R= .793
(32,26) x(32,26)x( 4,3), R=.495
"(16, 11)x(16,11)x(16,11), R=.325

Page 20 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

Figure 14: Performance Curve of Eb/No for BER of 10

-5

5.0 SIGNAL DESCRIPTIONS

This section contains descriptions for all the pins. Each signal has a type code associated with it. The

type codes are described in the following table.

5.1 SYSTEM CONTROL

TYPE CODE DESCRIPTION

I Input only pin

O Output only pin

I/O Input/Output pin

S Synchronous signal

A Asynchronous signal

SIGNAL TYPE DESCRIPTION

CLK I System Clock. 50 MHz maximum frequency.
RESETN I

A

Power on Reset. Active low rese t sign al. RESETN sho uld be a minimu m of
4 clock periods. When RESETN is asserted, all registers are reset as defined
in Section 3.0 Internal Register Programming, all control signals are
deasserted , and the data p ath is cleared.

TRI_STATE I Tristate Enable. When this pin is asserted high, the I/O and output signal

drivers are tristated. Tied low for normal operation.

TESTMODE I Testmode Enable. Tied low for normal operation.

32

16

12

8

6

5

4

3

2

1

6

5

4

3

2

1

3

3.25

3.5

3.75

4

4.25

4.5

4.75

5

5.25

5.5

5.75

6

6.25

6.5

6.75

E

b

/N

0

(dB) for BER = 10

-

5

Iterations

Soft Input Bits

6-7
5-6

4.5-5
4-4.5

3.75-4

3.5-3.75

3.25-3.5
3-3.25

Eb/N

0

PS4501-1100 Page 21 of 36

Advanced Hardware Architectures, Inc.

5.2 MICROPROCESSOR INTERFACE

5.3 INPUT INTERFACE

5.4 OUTPUT INTERFACE

SIGNAL TYPE DESCRIPTION

MDATA[7:0] I/OAProcessor Data. Data for all microprocessor reads a nd writes of registers

within the AHA4501 transfers across this bus.

MA[2:0] IAProcessor Address Bus. Used to address internal regi sters within the

AHA4501.

MCSN IAProcessor Chip Select. Sel ects the AHA4501 as th e source or desti nation of

the current microprocessor bus cycle. MCSN needs to be active for a
minimum of one clock cycle to start a microprocessor access.

MWRN_RWN IAProcessor Read/Write Select. When PROCMODE is deasserted, this is the

active low write enable signal. When PROCMODE is asserted, this is the
active low read/write select signal.

MRDY_DTACKN OAProcessor Ready/Data Transfer Acknowledge. When PROCMODE is

deasserted, this is an active high ready signal. When PROCMODE is
asserted, this signal is an active low data transfer acknowledge.

MRDN_DSN IAProcessor Read Enable/ Data Strobe. When PROCMODE is deasserted, this

is the active lo w read enable sig nal. When PROC MODE is asserted, this is
the active low data strobe signal.

MINTN_INTR OAProcessor Interrupt. When PROCMODE is deasserted, this signal is active

high. When PROCMODE is asserted, this signal is active low.

MALE IAProcessor Address Latch Enable. When PROCMODE is not asserted and

MUXMODE is asserted, this signal is the active high address latch enable.
Otherwise, this pin is not used and must be tied low.

PROCMODE IAProcessor Mode. Intel

®

mode when deasserted, Motorola® mode when

asserted.

MUXMODE IAMuxed Processor Mode. Deassert for non-muxed address and data bus

mode, assert for muxed address and data bus mode.

SIGNAL TYPE DESCRIPTION

IDATA[7:0] I

S

Data input bus.

IRDY I

S

Input data ready. Data is registered into the AHA4501 on the rising edge of
clock when IRDY and IACPT are asserted.

IACPT OSInput data accept. Dat a is registered into the AHA4501 on the rising edge of

clock when IRDY and IACPT are asserted.

ISYNC I

S

Input synchronize. Asserted with IDATA for the first bit of data after the
detection of a sync mark in the data stream. ISYNC is ignored when encoding.

SIGNAL TYPE DESCRIPTION

ODATA[7:0] OSData output bus.

ORDY OSOutput data ready. Data is registered out of the AHA450 1 on th e rising edg e

of clock when ORDY and OACPT are asserted.

OACPT I

S

Output data accept. Data is registered out of the AHA4501 on the rising
edge of clock when ORDY and OACPT are asserted.

OSYNC OSOutput synchronize. Asserted with ODATA for the first bit in every x

blocks, as programmed in the SYNC MARK FREQUENCY[3:0] section o f
the Sync register.

Page 22 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

6.0 PINOUT

Table 5: Pin Designation

NC - not connected internally.

PIN SIGNAL PIN SIGNAL PIN SIGNAL

1

MALE

41 GND 81 IDATA[6]

2 MCSN 42 VDD 82 IDATA[7]
3 GND 43 ODATA[1] 83 NC
4 MA[0] 44 ODATA[2] 84 VDD
5 VDD 45 ODATA[3] 85 NC
6 GND 46 VDD 86 GND
7 MA[1] 47 GND 87 NC
8 MA[2] 48 ODATA[4] 88 NC
9 VDD 49 ODATA[5] 89 NC

10 TIED GND 50 VDD 90 VDD

11 GND 51 GND 91

GND
12 MINTN_INTR 52 NC 92 MUXMODE
13 MRDY_DTACKN 53 ODATA[6] 93 TESTMODE
14 NC 54 ODATA[7] 94 RESETN
15 MDATA [7] 55 VDD 95 MRDN_DSN
16 MDATA [6] 56 GND 96 MWRN_RWN
17 VDD 57 ORDY 97 GND
18 GND 58 OSYNC 98 TRI_STATE
19 MDATA [5] 59 IACPT 99 VDD
20 MDATA[4] 60 NC 100 PROCMODE
21 MDATA[3] 61

NC
22 MDATA [2] 62 GND
23 VDD 63 GND
24 GND 64 VDD
25 MDATA [1] 65 VDD
26 MDATA[0] 66 CLK
27 NC 67 ISYNC
28 NC 68 IRDY
29 NC 69 OACPT
30 NC 70 IDATA[0]
31

VDD

71 IDATA[1]

32 GND 72 GND
33 NC 73 IDATA[2]
34 NC 74 GND
35 NC 75 VDD
36 VDD 76 VDD
37 GND 77 IDATA[3]
38 NC 78 IDATA[4]
39 NC 79 IDATA[5]
40 ODATA[0] 8 0 GND

PS4501-1100 Page 23 of 36

Advanced Hardware Architectures, Inc.

Figure 15: Pinout – 100 MQFP

AHA4501-050 PQC

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

123456789

101112131415161718192021222324252627282930

32
31

TM

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

8079787776757473727170696867666564636261605958575655545352

51

MALE

MCSN

GND

MA[0]

VDD

GND

MA[1]

MA[2]

VDD

TIED GND

GND

MINTN_INTR

MRDY_DTACKN

NC

MDATA[7]

MDATA[6]

VDD

GND

MDATA[5]

MDATA[4]

MDATA[3]

MDATA[2]

VDD

GND

MDATA[1]

MDATA[0]

NCNCNC

NC

GND

IDATA[5]

IDATA[4]

IDATA[3]

VDD

VDD

GND

IDATA[2]

GND

IDATA[1]

IDATA[0]

OACPT

IRDY

ISYNC

CLK

VDD

VDD

GND

GNDNCNC

IACPT

OSYNC

ORDY

GND

VDD

ODATA[7]

ODATA[6]NCGND

VDD
ODATA[5]
ODATA[4]
GND
VDD
ODATA[3]
ODATA[2]
ODATA[1]
VDD
GND
ODATA[0]
NC
NC
GND
VDD
NC
NC
NC
GND
VDD

IDATA[6]
IDATA[7]

NC

VDD

NC

GND

NC
NC
NC

VDD

GND

MUXMODE

TESTMODE

RESETN

MRDN_DSN

MWRN_RWN

GND

TRI_STATE

VDD

PROCMODE

Page 24 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

7.0 ELECTRICAL SPECIFICATIONS

7.1 ABSOLUTE MAXIMUM RATINGS

Absolute maximum voltage ratings are for voltage excursions which are transitory in nature.

7.2 RECOMMENDED OPERATING CONDITIONS

7.2.1 DC SPECIFICATIONS

Figure 16: Current vs. Data Rate (typ)

SYMBOL PARAMETER MIN MAX UNITS

V

DD

Power supply voltage 4.6 Volts

V

PIN

Voltage applied to any pin -0.5 4.6 Volts

SYMBOL PARAMETER MIN MAX UNITS

V

DD

Power supply voltage 3.0 3.6 Volts

T

A

Operating temperature 0 70 °C

SYMBOL PARAMETER CONDITIONS MIN MAX UNITS

V

IL

Input low voltage −0.3 0.8 Volts

V

IH

Input high voltage 2.0 VDD−0.3 Volts

V

OL

Output low voltage 4ma output loads 0.4 Volts

V

OH

Output high voltage 4ma output loads 2.4 Volts

I

IL

Input low current VIN = 0 Volts -5 µAmps

I

IH

Input high current VIN = VDD Vol t s 5 µAmps

I

DD

Active IDD current

50 MHz clock, decoding at maximum
data rate, V

DD

=3.3V, no loads

250 mAmps

I

DD

Supply current (static) 1.0 mAmps

I

DD

Standby current

Chip idle, 50 MHz clock, V

DD

=3.3V,

no loads

20 mAmps

I

OL

Output low current 4 mAmps

I

OH

Output high current 4 mAmps

10 50

50

100

150

200

250

Clock (MHz)

Current (mA)

20 30 40

0

PS4501-1100 Page 25 of 36

Advanced Hardware Architectures, Inc.

7.2.2 TEST CONDITIONS

Note: The timing diagrams for these signals assume a capacitive load of 20pF. The specified signal timings must

be derated by the factor shown in Figure 17 when operating at loads other than 20pF.

Figure 17: Signal Timing vs. Output Load

*Production test conditions

7.2.3 PIN CAPACITANCE

Notes: Not tested in production.

PARAMETER VALUE

AC timing reference 1.4 V

10 50

0.9

1.0

1.1

1.2

1.3

Load Capacitance (pF)

Multiplication Factor

20 30 40

LOAD

CAPACITANCE

MULTIPLICATION

FACTOR

10 pF 0.92
20 pF 1.00
30 pF 1.08
40 pF 1.16

50 pF* 1.25

SYMBOL PARAMETER MAX UNITS

C

IN

Input capacitance 10 pF

C

OUT

Output self load capacitance 10 pF

C

IO

I/O self load capacitance 10 pF

Page 26 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

8.0 TIMING SPECIFICATIONS

Figure 18: Data Input Timing

Note: For the first block after reset, the input data is discarded until the ISYNC signal is asserted (decoding only).

Table 6: Data Input Timing Requirements

Figure 19: Data Output Timing

Table 7: Data Output Timing Requirements

NUMBER PARAMETER MIN MAX UNITS NOTES

1 IRDY, ISYNC, IDATA setup to CLK rising edge 5 ns
2 IACPT delay from CLK rising edge 9 ns
3 IRDY, ISYNC, IDATA hold from CLK rising edge 2 ns
4 IACPT hold from CLK rising edge 2 ns

NUMBER PARAMETER MIN MAX UNITS NOTES

1 OACPT setup to CLK rising edge 5 ns
2

ORDY, OSYNC, ODATA delay from CLK rising
edge

9ns

3 OACPT hold from CLK rising edge 2 ns
4 ORDY, OSYNC, ODA T A h old from CLK rising edge 2 ns

Data 1

CLK

IRDY

(In)

IACPT

(Out)

ISYNC

(In)

IDATA[7:0]

(In)

4

Discard

Data

See Note

Data 0

2

1

3

CLK

ORDY

(Out)

OACPT

(In)

OSYNC

(Out)

ODATA[7:0]

(Out)

4

Data 1

2

1

3

Data 0 Data 2

2

2

PS4501-1100 Page 27 of 36

Advanced Hardware Architectures, Inc.

Figure 20: Microprocessor Interface Timing (Write); PROCMODE=0, MUXMODE=0

Table 8: Microprocessor In te rf ace Timi ng Re qu ire ment s - Writ e

Notes:

1) The microprocessor interface can be asynchronous to CLK. The above timings indicate the required setup and
hold to allow for fastest microprocessor accesses.

2) Write cycle begins when both MCSN and MWRN_RWN are low and meet setup to rising edge of CLK.

3) MC SN may be held low continuously for back to back accesses.

4) Neither MRDN_DSN nor MWRN_RWN may pulse high or low for less than one clock period.

5) Tcp = clock period. (ns)

6) Asynchronous operation only

NUMBER PARAMETER MIN MAX UNITS NOTES

1 MCSN, MWRN_RWN setup to CLK rising edge 5 ns 1,2,3,4
2 MWRN_RWN low to MDATA[7:0] valid 1 Tcp−3ns ns 5
3 CLK rising edge to MRDY_DTACKN high 15 ns
4 MCSN high to MRDY_DTACKN tristate 12 ns
5 MCSN low to MRDY_DTACKN active 12 ns
6 MWRN_RWN low to MRDY_DTACKN low 15 ns
7 MCSN low setup to MWRN_RWN low 2 ns 6

CLK

MA[2:0]

(In)

MDATA[7:0]

(In)

MCSN

(In)

MWRN_RWN

(In)

1

Data

Address

MRDY_DTACKN

(Out)

1

2

1

45 6 3

7

Page 28 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

Figure 21: Microprocessor Interface Timing (Read); PROCMODE=0, MUXMODE=0

Table 9: Microprocessor Interface Timing Requirements - Read; PROCMODE=0, MUXMODE=0

Notes:

1) The microprocessor interface can be asynchronous to CLK. The above timings indicate the required setup and
hold to allow for fastest microprocessor accesses.

2) Write cycle begins when both MCSN and MRDN_DSN are low and meet setup to rising edge of CLK.

3) MC SN may be held low continuously for back to back accesses.

4) Neither MRDN_DSN nor MWRN_RWN may pulse high or low for less than one CLK period.

5) Tcp = clock period. (ns)

6) Asynchronous operation only.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 MCSN/MRDN_DSN setup to CLK rising edge 5 ns 1,2,3,4
2 CLK rising e dge to MDATA[7:0] valid 11 ns
3 MCSN low to MRDY_DTACKN active 12 ns
4 MRDN_DSN low to MRDY_DTACKN low 15 ns
5 MA[2:0] valid from MRDN_DSN low 1 Tcp−3ns ns 5
6 MRDN_DSN high to MDATA[7:0] tristate 2 12 ns
7 MA[2:0] hold from MRDN_DSN 0 ns
8 MCSN high to MRDY_DTACKN tristate 12 ns
9 CLK rising edge to MRDY_DTACKN high 3 15 ns

10 MCSN low setup to MRDN_DSN low 2 ns 6

CLK

MCSN

(In)

MRDN_DSN

(In)

MA[2:0]

(In)

MDATA[7:0]

(Out)

1

Data

MRDY_DTACKN

(Out)

1

5

2

3

8

1

Address

7

6

9

4

10

PS4501-1100 Page 29 of 36

Advanced Hardware Architectures, Inc.

Figure 22: Microprocessor Interface Timing (Write); PROCMODE=0, MUXMODE=1

Table 10: Microprocessor Interface Timing Requirements - Write; PROCMODE=0, MUXMODE=1

Notes:

1) The microprocessor interface can be asynchronous to CLK. The above timings indicate the required setup and
hold to allow for fastest microprocessor accesses.

2) Write cycle begins when both MCSN and MWRN_RWN are low and meet setup to rising edge of CLK.

3) MC SN may be held low continuously for back to back accesses.

4) Neither MRDN_DSN nor MWRN_RWN may pulse high or low for less than one clock period.

5) Asynchronous operation only.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 Address hold from MALE falling edge 10 ns
2 Address setup to MALE falling edge 7 ns
3 MCSN/MWRN_RWN setup to CLK rising edge 10 ns 1,2,3,4
4 MALE hold from MWRN_RWN rising edge 0 ns
5 MALE setup to MWRN_RWN falling edge 10 ns
6 Write data setup to MWRN_RWN falling edge 0 ns

7

MDATA[7:0] and CSN hold from MWRN_RWN
rising edge

0ns

8 MWRN_RWN low width 2 clocks

9 MALE high width 10 ns
10 M CSN low to MRDY_DTACKN active 12 ns
11 CLK rising edge to MRDY_DTACKN high 15 ns
12 M CSN high to MRDY_DTACKN tristate 12 ns
13 MCSN low setup to MWRN_RWN low 2 ns

CLK

MALE

(In)

MDATA[7:0]

(In)

MCSN

(In)

MWRN_RWN

(In)

Data

MRDY_DTACKN

(Out)

3

2

6

5

11

Addr

1

3

3

10

8

12

7

4

9

13

Page 30 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

Figure 23: Microprocessor Interface Timing (Read); PROCMODE=0, MUXMODE=1

Table 11: Microprocessor Interface Timing Requirements - Read; PROCMODE=0, MUXMODE=1

Notes:

1) The microprocessor interface can be asynchronous to CLK. The above timings indicate the required setup and
hold to allow for fastest microprocessor accesses.

2) Write cycle begins when both CSN and MRDN_DSN are low and meet setup to rising edge of CLK.

3) CSN may be held low continuously for back to back accesses.

4) Neither MRDN_DSN nor MWRN_RWN may pulse high or low for less than one CLK period.

5) Tcp = clock period. (ns)

6) Asynchronous operation only.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 MCSN/MRDN_DSN setup to CLK rising edge 10 ns 1,2,3,4
2 MALE hold from MRDN_DSN rising edge 0 ns
3 MALE setup to MRDN_DSN falling edge 10 ns
4 Address setup to MALE falling edge 7 ns
5 Address hold from MALE falling edge 10 ns
6 MCSN hold from MRDN_DSN rising edge 0 ns
7 MRDN_DSN low width 2 clocks 5
8 MRDN_DSN falling edge to MDATA[7:0] valid 2 Tcp+11 ns ns 5

9 MRDN_DSN high to MDATA[7:0] tristate 2 12 ns
10 Rising edge of CLK to MDATA[7:0] valid 11 ns
11 MALE high width 10 ns
12 MCSN low to MRDY_DTACKN active 12 ns
13 MRDN_DSN low to MRDY_DTACKN low 15 ns
14 MCSN high to MRDY_DTACKN tristate 12 ns
15 CLK rising edge to MRDY_DTACKN high 3 15 ns
16 MCSN low setup to MRDN_DSN low 2 ns 6

CLK

MALE

(In)

MCSN

(In)

MRDN_DSN

(In)

MDATA[7:0]

(In/Out)

1

Data

MRDY_DTACKN

(Out)

1

4

14

3

2

9

10

13

Addr

5

12

1

8

15

7

11

6

16

PS4501-1100 Page 31 of 36

Advanced Hardware Architectures, Inc.

Figure 24: Microprocessor Interface Timing (Write); PROCMODE=1, MUXMODE=0

Table 12: Microprocessor Interface Timing Requirements - Write; PROCMODE=1, MUXMODE=0

Notes:

1) The microprocessor interface can be asynchronous to CLK. The above timings indicate the required setup and
hold to allow for fastest microprocessor accesses.

2) Write cycle begins when both MCSN and MWRN_RWN are low and meet setup to rising edge of CLK.

3) MC SN may be held low continuously for back to back accesses.

4) Neither MRDN_DSN nor MWRN_RWN may pu lse high o r low for l ess tha n one clock period . Only required to be
recognized on current clock edge. If less than this number, cycle will be recognized on the next clock.

5) Tcp = clock period. (ns)

6) Asynchronous operation only.

NUMBER PARAMETER MIN MAX UNITS NOTES

1

MCSN, MRDN_DSN, MWRN_RWN setup to
CLK rising edge

5 ns 1,2,3,4

2 MRDN_DSN low to MDATA[7:0] va lid 1 Tcp−3ns ns 5
3 MRDN_DSN low to MA[2:0] valid 1 Tcp−3ns ns 5
4 MCSN low to MRDY_DTACKN active 12 ns
5 MRDN_DSN low to MRDY_DTACKN high 15 ns
6 CLK rising edge to MRDY_DTACKN low 15 ns
7 MCSN high to MRDY_DTACKN tristate 0 ns
8 MCSN low setup to MRDN_DSN low 2 ns 6

CLK

MRDN_DSN

(In)

MA[2:0]

(In)

MCSN

(In)

MWRN_RWN

(In)

Address

MRDY_DTACKN

(Out)

1

4

2

MDATA[7:0]

(In)

Data

1

3

5

6

7

1

8

Page 32 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

Figure 25: Microprocessor Interface Timing (Read); PROCMODE=1, MUXMODE=0

Table 13: Microprocessor Interface Timing Requirements - Read; PROCMODE=1, MUXMODE=0

Notes:

1) The microprocessor interface can be asynchronous to CLK. The above timings indicate the required setup and
hold to allow for fastest microprocessor accesses.

2) Write cycle begins when both MCSN and MRDN_DSN are low and meet setup to rising edge of CLK.

3) MC SN may be held low continuously for back to back accesses.

4) Neither MRDN_DSN nor MWRN_RWN may pulse high or low for less than one CLK period.

5) Tcp = clock period. (ns)

6) Asynchronous operation only.

NUMBER PARAMETER MIN MAX UNITS NOTES

1

MCSN, MRDN_DSN, MWRN_RWN setup to
CLK rising edge

5 ns 1,2,3,4

2 MCSN low to MRDY_DTACKN active 12 ns
3 MRDN_DSN low to MRDY_DTACKN high 15 ns
4 Address valid from MRDN_DSN low 1 Tcp−3ns ns 5
5 CLK rising e dge to MDATA[7:0] valid 11 ns
6 CLK rising edge to MRDY_DTACKN low 3 15 ns
7 MRDN_DSN high to MRDY_DTACKN tristate 12 ns
8 MCSN low to MRDN_DSN low 2 ns 6

CLK

MRDN_DSN

(In)

MCSN

(In)

MWRN_RWN

(In)

MDATA[7:0]

(Out)

1

MRDY_DTACKN

(Out)

1

3

7

MA[2:0]

(In)

Data

4

2

Address

5

6

1

8

PS4501-1100 Page 33 of 36

Advanced Hardware Architectures, Inc.

Figure 26: Interrupt Timing

Table 14: Interrupt Timing Requirements

Figure 27: Clock Timing

Ta ble 15: Clock Timing Requirements

Notes:

1) Not tested in production.

Figure 28: Power On Reset Timing

Table 16: Power On Reset Timing Requirements

Notes:

1) RESETN signal can be asynchronous to the clock signal. It is internally synchronized to the rising edge of clock.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 MINTN_INTR delay time 12 ns
2 MINTN_INTR hold time 2 ns

NUMBER PARAMETER MIN MAX UNITS NOTES

1 Clock rise time 2 ns 1
2 Clock fall time 2 ns 1
3 Clock high time 8 ns
4 Clock low time 8 ns
5 Clock period 20 ns

NUMBER PARAMETER MIN MAX UNITS NOTES

1 RESETN low pulsewidth 4 cl ocks
2 RESETN setup to clock rise 6 ns 1
3 RESETN hold time 3 ns 1

CLK

MINTN_INTR

1 2

(Out)

CLK

1

34

5

2

2.0V

1.4V

0.8V

CLK

RESETN

2

3

1

Page 34 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

9.0 PACKAGING

Figure 29: AHA4501 Package Specifications – 100 MQFP

Table 17: PQFP (Plastic Quad Flat Pack) 14 × 20 mm Package Dimensions

JEDEC Outline MO-112

(All dimensions are in mm)

SYMBOL

NUMBER OF PIN AND SPECIFICATION DIMENSION

100

RB

MIN NOM MAX
(LCA) 20
(LCB) 30

A3.1
A1 0.1 0.23 0.36
A2 2.57 2.71 2.87

D 23.65 23.9 24.15
D1 19.9 20 20.1

E 17.65 17.9 18.15

E1 13.9 14 14.1

L 0.73 0.88 1.03
P0.65
B 0.22 0.3 0.33

AHA4501A-050 PQC

TM

D1

P

D

B

E1PE

(LCA)

(LCB)

81
82
83
84
85

96
97
98
99

100

3029282726

L

A

A2

A1

PS4501-1100 Page 35 of 36

Advanced Hardware Architectures, Inc.

10.0 ORDERING INFORMATION

10.1 AVAILABLE PARTS

10.2 PART NUMBERING

Device Number:

4501

Revision Letter:

A

Speed Designation:

50 MHz

Package Material Codes:

P Plastic

Package Type Codes:

QQuad

Test Specifications:

C Commercial 0°C to +70°C

PART NUMBER DESCRIPTION

AHA4501-050 PQC AHA4501 Astr o 36 Mbi ts/sec Turbo Product Code Encoder/Decoders, 3.3 V

AHA 4501 A 050 P Q C

Manufacturer

Device

Number

Revision

Level

Speed

Designation

Package
Material

Package

Type

Test

Specification

Page 36 of 36 PS4501-1100

Advanced Hardware Architectures, Inc.

11.0 RELATED PUBLICATIONS

This product and the algorithm are covered under multiple applied patents.

PART NUMBER DESCRIPTION

PB4501

AHA Product Brief – AHA4501 Astro 36 Mbits/sec Turbo Product Code

Encoder/Decoder
PB4501EVM AHA Product Brief – AHA4501 TPC EVM ISA Evaluation Module
PB4501EVSW AHA Product Brief – AHA4501 TPC Windows Evaluation Software

PB4540

AHA Product Brief – AHA4540 Ast ro OC-3 155 Mbi ts/sec T urbo Prod uct Code

Encoder/Decoder
PBGALAXY

AHA Product Brief – Galaxy Core Generator Turbo Product Code Decoder

Cores
PBGALAXY_EVSW AHA Product Brief – AHA Galaxy TPC Windows Evaluation Software
PBGALAXY_STK AHA Product Brief – AHA Galaxy Simulation Tool Kit

PS4540

AHA Product Specification – AHA4540 Astro OC-3 155 Mbits/sec Turbo

Product Code Encoder/Decoder
ANTPC01 AHA Application Note – Primer: Turbo Product Codes

ANTPC02

AHA Application Note – Use and Performance of Shortened Codes with the

AHA4501 Turbo Product Code Encoder/Decoder
ANTPC03

AHA Application Note – Use and Pe rforman ce of th e AHA4501 Turbo Product

Code Encoder/Decoder with Quadrature Amplitude Modulation (QAM)
ANTPC04

AHA Application Note – Use and Pe rforman ce of th e AHA4501 Turbo Product

Code Encoder/Decoder with Differential Phase Shift Keying (DPSK)
ANTPC05

AHA Application Note – AHA4501 Turbo Product Code Encoder/Decoder

Designer’s Guide
ANTPC06

AHA Application Note – AHA4501 Turbo Product Code Encoder/Decoder

Frequently Asked Questions (FAQ)
ANTPC07 AHA Application Note – Turbo Product Codes for LMDS

ANTPC08

AHA Application Note – Using Multiple AHA4501 Devices in Parallel for

Higher Data Rates
TPCEVAL

AHA Evaluation Software – Turbo Product Codes - Windows Evaluation
Software