Page 1
Pr oduct Specification
AHA4011C
10 MBytes/sec Reed-Solomon
Error Correction Device
Advanced Hardware
Architectures, Inc.
2365 NE Hopkins Court
Pullman, WA 99163-5601
509.334.1000
Fax: 509.334.9000
e-mail: sales@aha.com
http://www.aha.com
TM
Advanced Hardware
Architectures
The Data Coding Leader
PS4011C-0200
Page 2
Table of Contents
Advanced Hardware Architectures, Inc.
1.0 Introduction
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2.1 Definition of Correction Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.0 Functional Description
2.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.2 Correcting Capability and Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.5 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.5.1 Shortened Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.6 Reset and Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.6.1 Initialization Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.7 Encode, Decode or Pass-Through Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.8 Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.9 Data Rates and Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.9.1 Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.0.1 Continuous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 Reed-Solomon (ECC) Module and Error Rate Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Determining Decoder Performance Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.3 Erasures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.0 Operational Description
3.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.4 Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5
4.0 Signal Specifications
4.1 Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2 Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3 Power & Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.4 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.5 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.0 Packaging
6.0 Ordering Information
6.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.3 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
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Appendix A
Appendix B
PS4011C-0200
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
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Advanced Hardware Architectures, Inc.
Figures
Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 2: Typical Applications Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3: Data Input and Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4: Burst and Continuous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5: Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes . . . . . . . . . . . . . . . . .11
Figure 6: CLK Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7: Initialization and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 8: Data Input - Buffer Always Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 9: Data Input - Buffer Not Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 10: Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11: CRTN Timing - Reverse Order Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
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Advanced Hardware Architectures, Inc.
Tables
Table 1: Initialization Register Settings for Encode, Decode and Pass-Through Operations . . . . . . . . . . . . . . . . . .7
Table 2: Burst Operation Using 40 MHz Clock and 1 Clock/Byte, Forward Order Output. . . . . . . . . . . . . . . . . . . . .9
Table 3: Continuous Operation Using 40 MHz Clock and Specified Clocks/Byte, Forward Outp u tOrder. . . . . . . .10
Table 4: Continuous Operation for IESS-308 Codes Using 40 MHz Clock and Specified Clocks/Byte,
Forward Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PS4011C-0200
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Advanced Hardware Architectures, Inc.
1.0 INTRODUCTION
The AHA4011C is a single chip integrated
circuit that implements a high speed Reed-Solomon
Forward Error Correction alg orithm. The
AHA4011C is a member of the AHA PerFEC
family of high speed for ward error correction (FEC)
devices conforming to the Intelsat IESS-308
specification.
The device supports several programmable
parameters, including, block size, error threshold,
number of check bytes, order of out put and mode of
operations. Shortened blocks are suppor ted without
requirement of zero padding typically required in
Reed Solomon decoders. The data in put port is used
to initialize the programmable parameters and the
two on-chip buffers are used to input and output
data. Discontinu ities in data flow may be controlled
by dedicated control pins.
High operating frequenc y, in put and output data
rate flexibility, low processing latency and various
programmable parameters make this device ideal
for many applications including: DTV, DBS,
ADSL, Satellite Communications, ISDN, High
Performance Modems and networks.
This specification provides full electrical and
mechanical information to help a system engineer
develop a system using AHA4011C. This
document contains descriptions on correction
terms, pinout, functions and features, DC and AC
characteristi cs, package and mechanical
specifications, ordering information and Related
Technical Publications. Software simulation of the
RS code as implemented in the device is also
available. Please contact AHA or its authorized
sales representatives worldwide for copies of
Related Technical Publications and software
simulation.
1.1 FEATURES
HIGH PERFORMANCE
• Polynomial complies to Intelsat IESS-308;
RTCA DO-217 Appendix F, Revision D and
proposed ITU-TS SG-18 (Formerly CCITT SG-
18) standards
• 40 MBytes/sec burst transfer rate with a 40 MHz
clock for all block lengths
• Maximum channel ra te of 10 MBytes/sec
continuous for block l engths from 54 bytes throug h
255 bytes using a 40 MHz clock
• Processing latency time less than 15.2 µsec in
continuous operati on for block lengths of 100
bytes
FLEXIBILITY
• Programmable t o corr ect f rom 1 to 10 error bytes
or 20 erasure bytes per block
• Block lengths programmable from 3 to 255 bytes
• Encode, decode or pass-t hr ough capability inline with data flow
• Outputs corrected data or correction vectors in
forward or reverse order
• Continuous or burst data transfer
• Programmable error thres ho ld to help determ in e
channel performance
SYSTEM INTERFAC E
• Byte wide synchronous I/O ports with internal
buffering on both ports
• Dedicated control pins permit discontinuities in
system data flow
OTHERS
• 44 pin PLCC; 50 mil lead pitch
• Pin and plug compatible with lower performance
AHA4012B
• Software emulation of the algorithm available
1.2 CONVE NTIONS, NOTATIONS AND
DEFINITIONS
– Certain signals are logically true at a voltage
defined as “low” in the dat a sheet. All such signals
have an “N” appended to the end of the signal
name. For example, RSTN and DSON.
– “Signal assertion” means the output signal is
logically true.
– Hex values are defined with a prefix of “0x”, such
as “0x10”.
– A range of signal names is denoted by a set of
colons between t he number s. Most sign ific ant bi t
is always shown first, followed by least significan t
bit. For example, DI[7:0] represents Data Input
Bus 7 through 0.
– A product of two variables is expressed with an
“×”, for example, N × C
Length multiplied by Input clocks/byte.
– Mega Bytes per second is referred to as
MBytes/sec or MB/sec.
– Channel Rate is define d as transfer rate incl uding
user data and error correction check bytes.
represents Codeword
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PS4011C-0200 Page 1 of 24
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Advanced Hardware Architectures, Inc.
1.2.1 DEFINITION OF CORRECTION TERMS
TERM
K
R
N
Message Length (user
data or message bytes)
Check Symbols
(parity or redundancy)
Codeword Length
(block lengt h)
NAME
(other references)
t Error Corrections
P Error Threshold
e Number of Errors
E Number of Erasures
G Burden of Correct ion
DEFINITION
Number of user data symbols in one message
block. Size of a symbol in AHA4011C is 8-bits.
Message length is K = N − R. The first message
byte is referred to as X
.
X
0
Symbols appended to the user data to detect and
correct errors. The number of check symbols
required in a syst em is R ≥ E + 2e.* The first check
symbol is referred to as Y
symbol is Y
.
0
Sum of message and check symbols. N = K + R.
Maximum number of error corr ections per formed
by the device. The value is t = Integer .
The threshold limit to determine uncorrectability
of a Codeword and the number of check bytes
allocated for correction-only purposes (not for
detection).
An error is defined as an erroneous byte whose
correct value and positi on within the message
block are both unknown.
An erasure is de fined as an e rror whose posi tion is
known within the message block.**
A measure of the burden of correction being
placed on the capabilities of the device for that
message block. The value G = 2e + E.
; the last message byte is
K−1
; the last check
R−1
NK–
-------------2
RANGE
(number of bytes)
1 through 253
(1, 2, 3, 4 . . . 253)
2 through 20 in
increments of 1
(2, 3, 4 . . . 20)
3 through 255
(3, 4, 5, 6 . . . 255)
1 through 10
(1, 2, 3 . . . 10)
2 through 20
(2, 3, 4 . . . 20)
0 through N
0 through N
0 through R
* For every 2 check bytes, the AHA4011C can correct either 2 erasures or 1 error.
** An erasure is detected by a parity detector or a signal dropout detector. The presence of an erasure is indicated
by asserting the ERASE signal when the erased byte is cl ocked into the AHA4011C.
2.0 FUNCTIONAL DESCRIPTION
capable of corre cting up to 10 (t =10) byt e-error s or
20 (t=10) erasures in a RS block.
This section describes an architectural
overview of the chip and its many functions,
features and operations. The block diagram for the
chip shows the Reed-Solomon ECC module, the
Input and Output Buffers, and their associated
control. All input an d output data are cl ocked on the
rising edge of CLK.
2.1 FUNCTIONAL OVERVIEW
The ECC core has three phases of operation:
Data In, Calculation and Data Out. Data to be
processed is first input into a single ported Input
Buffer using a control signal DSIN. ECC core
arbitrates for the input data out of the Input Buffer.
ECC core has access to the Input Buffer on clock
edges where DSIN is not asserted.
Each block is processed within the ECC core
and calculations are made. The entire block is
processed through the ECC core, and transferred
into the Output Buf fer. The device asserts RDYON
The AHA4011C Reed-Solomon codec
(coder/decoder) is a member of the AHA PerFEC™
family of high speed for ward error correction (FEC)
devices. This single chip, three-layer metal, CMOS
device can operate in encode, decode or passthrough modes.
The ECC core implements a full error
correcting Reed-Sol omon decoder. This code i s
signal and holds active until the Output Buffer is
completely emptied.
The ECC core loads the Output Buffer in
reverse order for either operation. Data may be
strobed out of the device in forward or reve rse order .
If forward order is desir ed, output data cannot be
strobed out of the device until the entire block has
been loaded in to the Output Bu ffer.
Page 2 of 24 PS4011C-0200
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Advanced Hardware Architectures, Inc.
The use of internal buffers is restricted per the
rules defined in Section 2.9
Latencies
.
Data Rates and
Maximum delay required for each block of a
given length to pass through t he device is fixed, and
does not vary with the location or the number of
errors received. This delay (or latency), expressed
in the number of clocks is discussed in a later
section.
2.2 CORRECTING CAPABILITY AND
P OLYNOMIALS
Compared w ith other codes , RS codes require
relatively few “overhead” check bytes to be added
to the data stream to achieve a high degree of er ror
detection and correction. Since the AHA4011C
deals with bytes (or symbols) rather than with
individual bits, when a byte is in error it does not
matter how many bits within the byt e are corrupted;
it is counted as one error.
The Reed-Solomon code is defined over the
finite field G F (2
polynomial is:
8
). The field defining primitive
P(x) = x
8
+ x7 + x2 + x + 1
already known for “er asures”. The correction abil ity
of the code is bounded as:
R ≥ # erasures + 2(# errors)
Valid block length (N) is defined by the
relationship:
R + 1 ≤ N ≤ 255
where R ranges from 2 to 20.
A complete codeword can therefore ra nge from
a minimum of 3 bytes to a maximum of 255 bytes.
For further discussion on error rate
performance, refer to Section 2.1
(ECC) Module and Error Rate Performa nce
Reed-Solomon
.
Figure 1: Block Diagram
RDYIN
RDYIN
ERASE DI[7:0] CLK
DI
REGISTER
INPUT BUFFER
367x9
CLK
and the generator polynomial , dep endent on the
variable R, is given by:
119 R+
Gx() x αi–()
=
∏
i 120=
where R ∈ {2, 3, 4, 5,. . . 20} for the AHA4011C.
This polynomial is specifie d in international
standards, Intelsat IESS 308; RTCA DO-217
Appendix F (Rev D) and the proposed CCITT
SG-18.
For every 2 check bytes, the decoder corrects
either 2 erasures or 1 error. An erasure can be
determined with a parity detector or a signal dropout
detector external to the chip. An erasure is indicated
by the ERASE signal when the erased byte is
clocked in the device.
Correcting “erasure s” takes only half as much
of the correction capability of the RS code as it takes
to correct “err ors”, since the p osition informa tion is
Figure 2: Typical Applications Diagram
ENCODER COMMUNICATIONS DECODER
DATA SOURCE
8 8 8 8
A
AHA4011C
ECC COPROCESSOR
B C
CHANNEL
1 TO x BITS WIDE
RSTN
RSTN
DSIN
DSON
DSIN
DSON
CONTROL
RDYON
RDYON CRTN DO[7:0] ERR
ECC CORE
OUTPUT BUFFER
REGISTER
CRTN
256x9
DO
A typical system bloc k diagram is shown in the
following figure.
AHA4011C
ECC COPROCESSOR
DATA SINK
GND
VDD
GND
VDD
BLOCK FORMAT AT:
A
KDATA PLUS R “DUMMY” BYTES
B
SYSTEM
CONTROLLER
KDATA PLUS R CHECK BYTES
C
KDATA BYTES
SYSTEM
CONTROLLER
PS4011C-0200 Page 3 of 24
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2.3 SIGNAL DESCRIPTIONS
Input Pins
DI[7:0] Data Input Bus. The in put byte and ERASE
are latched on the rising edge of the clock
when both DSIN and RDYIN are active. I f
either DSIN or RDYIN are inactive, the DI
and ERASE are ignored.
DSIN Data Input Strobe. Enables data from DI to
be loaded into the chip. When RDYIN is
active, DSIN being active on the rising
edge of the cl ock loads the input data i n the
device. DSIN must be activ e for o ne c lock
edge only per each input byte. DSIN is
ignored if RDYIN is inactive. Signal is
active low.
DSON Data Output Strobe. This input strobe
acknowledges to the chip that data
available on the Outpu t Bus, DO, has be en
received by the system. The device uses
this strobe to increment its internal address
counter to the next data location. DSON
must be active for one clock edge only p er
each output byte. DSON is ignored if
RDYON is inactive. Active low.
ERASE Erasure input flag for symbol currently on
DI. Signal is active high. ERASE signal is
used for marking all check Bytes as
erasures (dummy check Bytes) during
encode operation. It is also used to mark
input symbols that contain errors during
decoding. If not used, conn ect this signal to
ground.
RSTN Reset. Input pin. When RSTN is active and
DSIN and DSON are inactive, the device
forces all internal control circuitry into a
known state and initializes all data path
elements. RSTN is active during
Initialization Phase. In this phase, internal
registers are progr ammed by usi ng DI and
DSIN. Signal is active low.
CLK Clock. System clock input. Refer to
Section 4.4
AC Electrical Characteristics
for clock requirements.
Output Pins
DO[7:0]Data Output. The output byte is available
on this bus. The val ue of the outpu t byte is
undefined if RDYON is inactive. Requ ires
an acknowledge strobe, DSON, at a rising
edge of the clock to increment internal
address counter and output the next
location in the buffer. DO bus is al w ays
driven and is not tristated by the device.
RD YO NReady Output. This output pin indicates the
chip’s ability to generate outpu t data. If
active, DSON is allowed to increment the
internal address counter for the next data
byte. When inactive DSON is ignored and
DO is undefined. Signal is active low.
CRTN Correctable. The output pin when active
indicates the blo ck did not exceed th e error
threshold programmed by P. Error
threshold must be programmed with the
same value as the number of chec k symbols
R if erasures are not used. This signal is
valid when the fir st message b yte, X
the block is available out of the chip.
During all other times the signal is
undefined. Signal is valid for at least one
clock. Active low.
ERR Error. Output pin indicates the current
value on DO[7:0] is a corrected byte.
Active high.
2.4 PINOUT
INPUT
DI0
DI1
DI2
DI3
DI4
DI5
65432
7
VDD
8
GND
9
VDD
10
GND
11
GND
12
VDD
13
*NC
*NC
VDD
GND
GND
AHA4011C-040 PJC
14
15
16
17
1819202122232425262728
1
CLK
DI6
DI7
GND
DISN
4443424140
39
38
37
36
35
34
33
32
31
30
29
K−1
VDD
VDD
GND
VDD
RSTN
ERASE
DSON
RDYIN
RDYON
GND
GND
, of
RDYIN Ready Input. Indicates the chip's ability to
accept data input on DI. If active, DSIN is
allowed to enable t he loadin g of in put data
on DI. When inactive, DSIN is ignored.
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
VDD
ERR
CRTN
OUTPUT
*NC = No connect, reserved for future considerations.
Signal is active low.
Page 4 of 24 PS4011C-0200
Page 9
Advanced Hardware Architectures, Inc.
ECC
Core
Data Available
Reverse Order Forward Order
Data Available
.
.
.
.
.
.
X
0
Y
0
R-1
Y
K-1
X
.
.
.
.
.
.
Y
0
X
0
R-1
Y
K-1
X
Last Byte Out
First Byte Out
First
Byte
In
Last
Byte
In
. . . . . .
X
1
Y1Y
0
X
0R-2YR-1
Y
K-2XK-1
X
INPUT
BUFFER
OUTPUT
BUFFER
2.5 DATA FLOW
The device is first initialized for various
programmable parameters including: Erasure
Multiplier, Error Threshold, Number of Check
bytes, Number of Message bytes per block, Block
Length and a Control byte. Following t his six-byte
initialization, the device may be used to encode,
decode or pass-through multiple blocks of data. The
device requires reinitialization when the parameters
are changed or a reset is required.
The device processes data as “blocks”
containing Message and Check Bytes. Order of
input bytes must be fi rst message byte X
last message byte X
through last check byte Y0. The device
Y
R−1
, followed by first check byte
0
processes the block in this manner:
- a block is clocked into the Input Buffer;
- transferred into the ECC module;
- passed to the Output Buf fer in the rev erse order
from what was received at the Input Port; and
Figure 3: Data Input and Output Order
through
K−1
- clocked out through the Output Port via the
Output Buffer. Consecutive blocks may be
input into the Input Buffer while the Output
Buffer is be ing emptied.
Data is available through the Output Port in
forward or reverse order. Forward order clocks out
the block the same as in put and reverse order c locks
the check byte Y
through check bytes Y
0
followed by message by te X
.
X
K−1
through message byte
0
R−1
2.5.1 SHORTENED BLOCKS
This device allows for shortened RS blocks,
thus not requiring zero padding when decoding.
During encoding, conversely, zero padding is not
performed. When the device is programmed to
decode a block of less than 255 Bytes, only the
message Bytes followed by check Bytes are sent.
Prepending with zero value Bytes to fill out the
block to 255 Bytes is not required.
2.6 RESET AND INITIALIZATION SEQUENCE
The chip must be reset and initialized any time
a reset is necessary.
Caveat: All six registers must be in itialized
correctly for proper operation of the chip. The
Reset and initialization first requires pulling the
RSTN low signal for at least two clocks wh ile the
DSIN and DSON signals a re held inactive, i.e., high.
Following this sequence, the six internal
registers, refer red to as “Initializ ation Registers” are
device has no provisions for reading back
Initializati on Register settings. Thi s sequence mu st
be used if the device needs to be reset or any one
register needs updating, i.e., all registers must be
reinitialized for a change to any one register.
strobed by DSIN. These byte s are loaded in orde r of
1 through 6.
The RSTN must be active low for at least two
clocks before the fi rst initialization byte is strobed
in and remain active for at least one clock after the
final byte. RSTN must be high for at least two
clocks before the first message byte can be strobed
into the device. For a detailed timing diagram, see
Figure 7
: Initialization and Reset Timing
PS4011C-0200 Page 5 of 24
.
Page 10
Advanced Hardware Architectures, Inc.
2.6.1 INITIALIZATION REGISTERS
BYTE 1, ERASURE MULTIPLIER:
[7:0] Multiplier value that must be programmed
as shown in Appendix A. The table sho ws a
value to be programmed corresponding to
the block length selected.
BYTE 2, ERROR THRESHOLD:
[4:0] The threshold for determining
uncorrectability of a data block, and the
number of check bytes allocated for
correction only purposes. When not using
erasures, set to the same value as BYTE 3,
CHECK BYTES. Minimum value of 0x02
sets the Threshold t o 2 and 0x14 sets to the
maximum, 20.
[6:5] Reserved. Set to 0.
[7] Not used. Don't care.
BYTE 3, CHECK BYTES:
[4:0] Number of check bytes in RS code, R.
Minimum setting of 0x02 indicates two
check bytes for R = 2 an d 0x14 indicates the
maximum of 20.
[6:5] Reserved. Set to 0.
[7] Not used. Don't care.
BYTE 4, MESSAGE BYTES:
[7:0] Number of message bytes in code, K.
Minimum setting of 0x01 ind ic ates 1 byte,
setting to 0xFD indicat es the maximum 253
message bytes.
BYTE 5, BLOCK LENGTH:
[7:0] Number of bytes in block, N. Setting to
0x03 indicates 3 bytes, setting to 0xFF
indicates 255 bytes.
BYTE 6, CONTROL BYTE:
[0] RES Reserved. Set to 0.
[1] NOPAR Parity Symbol Control
0 Check bytes are output
following the message bytes.
1 Check bytes are not output
following the message bytes.
Correction will be done
regardless depending upo n the
bit 4, RAW, setting.
[2] CRCTS Correction Control
0 Outputs correction vectors; to
obtain corrected data,
externally XOR the co rrect ion
vector with the corresponding
message or check byte.
1 Outputs corrected data
[3] FOR Forward Order Control
0 Outputs the block in reverse
order
1 Outputs the block in forward
order
[4] RAW Raw Data
0 Outputs corrections or
corrected data per t he CRCTS
bit
1 Outputs uncorrected, raw input
data or 0's depending upon the
CRCTS bit setting (See table
below). NOPAR bit and
CHECK BYTE register
settings are ignored.
[5] ERC Erasure Rejection Control.
This bit is only used by the
device when the Erasures
exceed the ERROR
THRESHOLD or R settings.
This bit is ignored when the
Erasures are less than or equal
to ERROR THRESHOLD or
R.
0 If Erasures are g reater tha n the
ERROR THRESHOLD or R
then erasures a re discarded and
full correction is performed.
The block is flagged
uncorrectable and the output
CRTN will be high during the
last output byte of the block.
1 If Erasures are greater than
ERROR THRESHOLD or R
then erasures a re discarded and
full correction is performed.
The output CRTN will be high
only when the block is
uncorrectable.
[7:6] Reserved, Set to 0.
RAW CRCTS Output
0 0 Correction vectors
0 1 Corrected data
10 Zero
1 1 Uncorrected raw input data
Page 6 of 24 PS4011C-0200
Page 11
Advanced Hardware Architectures, Inc.
2.7 ENCODE, DECODE OR PASS-THROUGH OPERATIONS
The device performs three functions: encoding,
decoding and pass-through. As an encoder the
device outputs the message block followed by
“corrected ” check bytes. As a decoder, the device
outputs the corrected message bytes or correction
vectors with or without check bytes following the
message. In pass-through ope ration, the device
passes the input data as it is received. In all three
operations, the input block flows thr ough the Input
Buffer into the ECC module and out of the Output
Buffer. Latencies for all three operations are the
same.
The device is ini tialized for t he three operati ons
as shown in the table below.
Table 1: Initialization Register Settings for Encode, Decode and Pass-Through Operations
INITIALIZATION
REGISTER
ERASURE MULTIPLIER [7:0] Appendix A value Appendix A value Appendix A value
ERROR THRESHOLD [7:0] Set to R R or less R
CHECK BYTES [7:0] Set to R R R
MESSAGE BYTES [7:0]
BLOCK LENGTH [7:0]
CONTROL BYTE
BIT(S) ENCODE DECODE PASS-THROUGH
Set to the Number
of Message Bytes
in block, K
Set to the total of
Message and
Check bytes, N
0 (RESV) 0 0 0
1 (NOPAR) 0 System specific 0
2 (CRCTS) 1 System specific 1
3 (FOR) System specific System specific System specific
4 (RAW) 0 0 1
5 (ERC) 0 0 0
[7:6] Reserved 0 0 0
KK
NN
As an encoder, the device is used with the
Erasures featur e enabled in t he following s equence.
(Asserting the ERASE signal high enables the
Erasure feature . )
1) After initialization, the device receives the
message data followed by “d ummy” check
bytes. “Dummy” check bytes are clocked
into the device with the ERASE signal
asserted. The number of “dummy” check
bytes must equal R.
2) The ECC core processes the block by
“correcting” the check bytes and feeding
the codeword into the Output Buffer in
reverse order.
3) The block is then made available on the
output bus, DO. The state of the output
RDYON determines the availability of
data. ERR signal is asserted while the
“corrected check bytes” are output on the
output bus, DO. CRTN is asserted low
during the last byte out of the chip
indicating that the previous block did not
exceed the error threshold.
As a decoder, the device works similar to the
encode operation in the following sequence.
1) Following initialization, the system clocks
the message data and the check bytes into the
Input Buffer. ERASE signal may be asserted
as desired by the system. State of the output
signal, RDYIN determines the chip’s ability
to accept data input on the DI bus.
2) The ECC Core processes the block by
performing necessary corrections, and
feeds the cod eword into the Output Buffer
in reverse order.
3) The data is available on the output por t. The
state of the output signal, RDYON
determines the availa bility of valid data. An
output byt e wh ich has bee n corrected is
indicated by the device asserting ERR.
CRT N may be high or low depending up on
the THRESHOLD Register and ERC bit
programmed and the errors encountered.
PS4011C-0200 Page 7 of 24
Page 12
Advanced Hardware Architectures, Inc.
In pass-through operation, data flows through
the device similar to the encode and decode
operations. During initialization the device is
programmed as shown above. Check Bytes are
programmed in the range of 0x02 to 0x14.5. The
Block length here i s the sum of Mes sage Byt es an d
Check Bytes like encode and decode modes of
operation even thou gh the device passes through t he
block of data unchanged.
1) Following initialization, the system clocks
the codeword into the In put Buffer.
2) The codeword is processed by the ECC
module and passed on to the Out put Buf fer
without correction.
3) The uncorrected codeword is available at
the output port. State of the RDYON
determines the availability of valid data.
The ERASE input is ignored during the
Input phase and ERR and CRTN outputs
are not valid.
Caveat: The device has no provis ions for indicating
the start and/or en d of mess age or c heck byt es. It is
the system designer s responsi bility t o keep track of
message and check bytes transitions, if required.
2.8 BUFFERS
The Input Port contains a single-ported 367x9
buffer. The Output Port contains a single-ported
256x9 buffer. These buffers store input and output
data during the correc tion process and help maintain
the desired system data rate. A Reset operation as
described in the Initialization Sequence secti on
clears the buffers.
The use of internal buffers is restricted per the
rules defined in Section 2.9
Latencies
using the buf fers to temporarily stor e more than one
block. It is highly recommended that the system
designer clearly understand these rules prior to
designing the system.
bus when the ECC module is in the calculat ion or in
data-out phases at the desired system rate. The
ability of the Input Buffer t o accept data is indicated
by RDYIN.
the ECC during the data-out phase. RDYON is
asserted low when the Output Buffer is able to
output data.
or continuous rates. The number of clocks per byte
used to input or output determines burst or
continuous operat ing conditions. Figure 4 sho ws the
two operations.
. These rules define the limitations of
The Input Buffer receives input data on the DI
The Output Buffer accept s corre cted data fr om
Data flow through the device may occur in burst
Data Rates and
Burst operation permits data to be clocked in
and out of the device at the maximum rate, i.e., 1
clock per byte. In burst opera ti on, cons ecuti ve d ata
blocks are clocked into the device following a
processing latency period. Data is input into the
Input Buffer and processed through the ECC core.
After a processing l atency period the ent ire block of
data is transferred to the Output Buffer. While the
Output Buffer is being emptied, the Input Buffe r i s
simultaneously filled with the following block at the
maximum rate. Input a nd output rates are c ontrolled
by the clock speed and clocks/byte.
Continuous operation requi res a mini mum of 4
clocks/byte depending upon the block size.
Maximum data transfer rates for continuous rate
vary accordingly. Blocks may be processed
continuously through the device. If the chip is
operated with contin uous data stream s, the RDYIN
and RDYON pins will always be active (after the
initial latency). Therefore, they need not be used.
Caveat: System designe r should be awa re that data
is put into the Output Buffer in reverse order
Therefore, RDYON may become inactive bet ween
blocks in forward order
Output Buffer is filled.
if data is output faster than
.
2.9 DATA RATES AND LATENCIES
This section descri bes data rates and proces sing
latencies for burst and continuous operations.
Processing latenci es are the same in encode, decode
or pass-through operations. The number of clocks
used to clock in and ou t of the device determ ines the
operation. The input a nd output rates need not be th e
same. No registers are requi red to program the
device for either operation.
Continuous block fl ow is achieved by us ing the
appropriate number of clocks per byte and block
length. Alternatively, data flow into and out of the
device is controlled usi ng control signals, DSIN and
DSON.
Page 8 of 24 PS4011C-0200
Page 13
2.9.1 BURST OPERATION
R
60
NC
m
×
C
m
1–
-----------------++
C
i
----------------------------------------
N
367≤+
Advanced Hardware Architectures, Inc.
Maximum processing latency , i n forward order ,
expressed in number of clocks, for burst operatio n is
determined by: N × C
+ R + 60 + N
i
Definitions:
= input clock rate per byte. If Ci= 1, use a value
C
i
of 2 in the latency equation
for C
i
N = block length
R = number of check bytes
Processing Latency = Delay from first input byte to
first output byte
In reverse order, processing latency is
approximately N clocks less than above.
For a 40 MHz system using 1 clock per byte,
latencies and data rates for forward order output are
Output Burst Rates in all cases will be 40
MBytes/sec. Note: Other fr equency operations may
be derived similarly.
Output Buffer may be used to hold data from
one block while the Input Buf fer is being filled wi th
the following block. Two rules listed in the caveats
are required to accomplish this. These are illustrated
in Figure 4.
Caveats:
1. Output of block i must start coincident
with or before the input of block i + 1.
2. Output of block i must be complete:
Processing Latency − N − 8 clocks
after the start of block i + l on the input.
shown in the table for burst operation. Input and
Table 2: Burst Operation Using 40 MHz Clock and 1 Clock/Byte, Forward Order Output
CHECK BYTES ‘R’ = 20 CHECK BYTES ‘R’ = 2
BLOCK
LENGTHS ‘N’
MAXIMUM
LATENCY
(# of clocks)
25 155 3.88 6.45 137 3.43 7.30
50 230 5.75 8.70 212 5.30 9.43
100 380 9.50 10.50 362 9.05 11.00
150 530 13.30 11.30 512 12.80 11.70
200 680 17.00 11.80 662 16.60 12.10
255 845 21.10 12.10 827 20.70 12.30
MAXIMUM
LATENCY
(µsecs)
Average Rate
AVERAGE
RATE
(MBytes/sec)
--------------------------------------------------------------- -=
Maximum Latency µsec()
MAXIMUM
LATENCY
(# of clocks)
N
MAXIMUM
LATENCY
(µsecs)
AVERAG E
RATE
(MBytes/sec)
2.0.1 CONTINUOUS OPERATION
A. Conditions for Continuous Operation
The allowable input and output data rates are
Multiple blocks of data may be processed
through the device conti nuously as shown in Figure
4. Consecutive blocks are input into the device at
the rate of C
clocks/byte. The output data stream
i
may or may not be continuous depending on
related to the Reed-Solomon block length by the
following two inequalities. C
, Co, N and K must be
i
chosen so that these equations are satisfied.
Equation 1:
whether parity is being output (controlled by
NOPAR) and the choice of C
operation is described by several equations. The
following terms are used in these equations:
- Input clock rate per byte: Ci ≥ 4 for
C
i
continuous operation
- Output clock rate per byte: Co ≥ 2
C
o
- Minimum of Ci and Co: If Ci < Co then
C
m
= Ci else Cm= C
C
m
N - Reed-Solomon block length
K - Reed-Solomon message length
R - Reed-Solomon parity length (R = N − K)
L - Output data length: If parity is being output
from the chip (NOPAR = 0), L = N; else if
the parity is not being output (NOPAR = 1)
. Continuous
o
o
Equation 2:
N
1–()
×
C
i
48
R
×
NC
---------------
C
i
i
1–
×
NC
m
-----------------++ +≥
1–
C
m
B. Processing Latency
Processing latency is the time from the
beginning of a blo ck on the i nput to the block being
ready for output. Maximum processing latency,
expressed in number of clocks, for continuous
operation is:
Equation 3:
Latency
1–()
×=60
N
C
i
×
NC
m
-----------------+++
R
C
m
1–
L = K
PS4011C-0200 Page 9 of 24
Page 14
Advanced Hardware Architectures, Inc.
C. Start and End of Output
Similar to the burst ope ration, Output Buffer
may be used to temporarily “hold” data from one
block while the Input Buffer is being filled.
However, these conditions must be satisfied: the
output of a data block must start after the latency
equation (Equation 3) is satisfied, but before the
Data of one block must b e fully emptied L × C
clocks after the start of empty process.
All of the conditions on the maximum delay
given in Equation 4 must be satisfied. If any are not,
the output data stream will begin to inhibit ECC
processing. Eventually this will cause the input
buffer to over fill and R DYIN to bec o me inactive .
maximum delay is reached . The maximu m delay is :
Equation 4:
×
NC
maximum_delay 3
if maximum_delay
---------------------------------------------
C
i
if maximum_delay
---------------------------------------------
C
i
××
i
LC
o
NC
367, then maximum_delay 367
2N, then maximum_delay× 2
---------------–×–=
C
i
i
1–
×=≥
NC
C
i
××=>
i
Figure 4: Burst and Continuous Operations
(Note: Blocks are shown from right to left as they are input into and output from the chip in Forward Order.
Block i is the first input block, block i + 1 is second input block. X
is the last input check symbol of a block. Notes 1 and 2 in burst operation are described in Section 2.9.1 Burst
Y
o
is the first input message byte of a block.
K − 1
Operation - Caveats.)
Burst Operation
Input Data:
Output Data:
Y
Block i+1 Block i
. . . . . . . . . .
Y
0
X
K-1
. . . . . . . . . . . . . . . . . .
Y
0
. . . . . . . . . .
0 K-1
X
2
1
X
K-1
Block iBlock i+1
. . . . . . . . . .
Y
0
X
K-1
o
Processing Latency
Continuous Operation
Input Data:
Output Data:
Block i+3 Block i+2 Block i+1 Block i
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y
0
X
For a 40 MHz system using the re quired cl ocks per byte, maximum l atencies and data rates f or forwar d
order output are shown in th e tab le f or con ti nuous operation. Input and Output rates are ass umed the same
in this table. Note: Other frequency operations are also possible.
Block i+3 Block i+2 Block i+1 Block i
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y
0
Y
0
K-1
Y
X
0
K-1
Y
X
0
K-1
Y
X
0
K-1
Y
X
0
K-1
X
K-1
X
K-1
Y
0
X
K-1
Table 3: Continuous Operation Using 40 MHz Clock and Specified Clocks/Byte, Forward
Output Order
CHECK BYTES ‘R’ = 20 CHECK BYTES ‘R’ = 2
BLOCK
LENGTHS ‘N’
MINIMUM
REQUIRED
(clocks/byte)
25 6 6.67 6.35 5 8 5.33
50 5 8 9.69 5 8 9.24
100 4 10 15.23 4 10 14.78
150 4 10 21.90 4 10 21.45
200 4 10 28.57 4 10 28.12
225 4 10 31.90 4 10 31.45
255 4 10 35.90 4 10 35.45
For Intelsat IESS-308, Rev F, Inner FEC Rates, use Table 4 for a system with 40 MHz clock.
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(µsecs)
MINIMUM
REQUIRED
(clocks/byte)
Note: Other frequency operations are also possible.
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(µsecs)
Page 10 of 24 PS4011C-0200
Page 15
Advanced Hardware Architectures, Inc.
T able 4: Continuous Operation for IESS-308 Codes Using 40 MHz Clock and Specified Clocks/Byte,
Forward Output Order
BLOCK
LENGTHS ‘N’
MESSAGE
LENGTH ‘K’
ERROR
CAPABILITY ‘t’
MINIMUM
REQUIRED
(clocks/byte)
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(# of clocks)
MAXIMUM
LATENCY
(µsecs)
126 112 7 4 10 742 18.55
194 178 8 4 10 1107 27.67
208 192 8 4 10 1181 29.53
219 201 9 4 10 1242 31.05
225 205 10 4 10 1276 31.90
Appendix B shows a spreadsheet table of block lengths vs. latencies for a 40 MHz clock system.
2.1 REED-SOLOMON (ECC) MODULE AND ERROR RATE PERFORMANCE
The module implements a full error correcting
Reed-Solomon (RS) decoder whose function is to
perform the necessary corrections on the input
blocks. The code used by the decoder is capable of
generating c orrections fo r up to 10 (t = 10) byteerrors in an RS bloc k over the bloc k length betwee n
R + 1 to 255 bytes. The number of message bytes in
an RS block, K, is equal to the RS block length
minus R (K = N − R). The RS code implemented
uses the primitive polynomial
8
P(x) = x
+ x7 + x2 + x + 1
to generate GF(256). The generator polynomial for
the code is:
Gx() x αi–()
119 R+
=
∏
i 120=
An RS block consists of message and
redundancy bytes. The numbe r of messa ge bytes i n
the block, K, is programmable dur ing initializati on.
The number of check bytes is R and can be
programmed during in itialization to b e 2 through 20
in increments of 1.
The ECC Module may be programmed to
output corrections or corrected data. If
“corrections” is selected, to obtain corrected data,
externally XOR the output correction vector with
the corresponding message or check byte. For
example, if “corrections” is selected for a block of
200 bytes with errors in locations 100, 123, 153, 17 6
and 199; output block will be 0’s for all locations
except for thos e positions. The bytes outpu t at these
positions are referred to as correction vectors and
are XOR’d externally with the message bytes to
obtain the correct value. If the output of the
AHA4011C is programmed to output corrected
data, the correcti on vector is applied inter nally and
the corrected data is output.
The Symbol Error Rate Performa nce of the
Reed Solomon code used is shown in Figure 5.
Figure 5: Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes
-0
10
-2
10
-4
10
-6
10
-8
10
P
-10
10
-12
10
-14
10
-16
10
-0 -3
10
-1
-2
10
10
t=10
t=8
t=5
-4
10
t=3
-5
10
10
P
PS4011C-0200 Page 11 of 24
t=1
-6
-7
10
-8
1010
Page 16
Advanced Hardware Architectures, Inc.
The most common measures of per formance for
Reed-Solomon code are P
, PSE, and C
UE
BER
. PSE is
the probability of symbol errors and is the ratio of
the number of received symbol errors to the total
number of received symbols. In the AHA4011C
device the symbol length, m, is equal to 8 bits. P
UE
is the probability of an unco rrectable error and is the
ratio of the number of uncor rectable cod e blocks to
the total number of received code blocks. An
uncorrecta ble error occur s when more th an t
received symbols are in err or . C
Bit Error Rate. The C
is the reciprocal of
BER
expected number of correct bits between errors.
If input noise is random, .
If with , and
P
SE
7–
10
C
------------------4.910
BER
8255×
4–
810
×=t5=P
11–
.
×==
is the Corrected
BER
P
BER
UE
-------------- -=
mN×
C
UE
107–=
The figure shows probability of symbol error
and uncorrectable error for block size (N) of 255. It
shows the ability of variou s levels of Reed-Solomon
error correction to resto re the integri ty of the
corrupted data. For example, using 255 byte blocks,
if 1 out of 1000 of the re ceived bytes have one or
more bit errors, RS correction with t = 5 will restore
the data to 1 error in 2 million blocks (510 million
bytes).
For a detailed discussion on error rate
performance of Reed-Solomon c ode, ref er to AHA
Application Note,
Correction Codes (ECC)
Primer: Reed-Solomon Error
, (ANRS01).
2.2 DETERMINING DECODER
PERFORMANCE BOUNDARIES
AHA4011C supports a programmable feature
that allows a system designer to determine the
channel performance. This prog rammable feature,
referred to as error threshold, P, sets a number of
errors to be allowed by the chip prior to flagging the
block uncorrectable. Erasure Rejection Control bit
of the Control Byte register determines the
condition of CRTN output pin.
P and R are both independently selectable by
the user during the Init ializat ion Con trol Sequ ence.
The various configur ations of P and R are des cribed
as follows:
P > R This is not a sensible choice since this
implies that more check bytes are allocated
for (correction-only) purposes than there
are total check bytes (for both correction
and detection). The device will work as if P
was set equal to R.
P = R This configuration maximizes the ability to
correct errors, particularly if R itself ha s
been chosen to be its maximum value of 20.
This is the usual choice. T his situati on
causes the CRTN output to flag a message
block as uncorrectable at an error level
exceeding that of which the device is
capable.
P < R This increases the level of error detection
capability. This situatio n causes the CRTN
output to flag a message block as
uncorrectable at an error level below tha t of
which the device is capable. This mode
only works with erasures.
Caveat: Output block may be corrupted if a block
exceeds the correction abi lity of the ECC module.
2.3 ERASURES
The chip is capable of utilizing erasure
information. R erasures may be corrected in any
block assuming there are no unmarked errors.
The correction capability is: E + 2e ≤ R
Where E = number of erasures (marked errors)
e = number of unmarked errors
R= number of check symbols
If there are more than P or R erasures the
erasure information is discarded, and full error
correction is attempted. The chip can be
programmed to either call such a block
uncorrectable or not. If pr ogr ammed not to call the
block uncorrectable (ERC bi t set to 1), the ECC will
utilize the full error correction capability to decide if
the block is correctable.
3.0 OPERATIONAL DESCRIPTION
This section describes the relationship of
associated signals for various functions of the chip.
3.1 CLOCK
The clock input to the chip must meet th e timing
requirements shown in Fig ure 6. The chip is entirely
static thus allowing the clock to stop in either the
active or inactive state for an indefinite period
without loss of stored information.
Page 12 of 24 PS4011C-0200
Page 17
Advanced Hardware Architectures, Inc.
CLK
12 3
4
5
1
Figure 6: CLK Characteristics
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 CLK rise time 5 nsec
2 CLK high time 8 nsec
3 CLK fall time 5 nsec
4CLK low time 8 nsec
5 CLK period 25 nsec
All timing diagrams in this specification use the clock at the CLK pin as the reference point.
3.2 INITIALIZATION
This section describes the Reset and Initialization Sequence timing. For a detailed discussion on these
sequences, refer to Section 2.6
Reset and Initialization Sequence
.
Figure 7: Initialization and Reset Timing
CLK
112 2
RSTN
DSIN
DSON
3
DI
at least 2
clock edges I n put 6 bytes da ta for initialization
RESET
23 61
45
INITIALIZE
at least 1
clock edge
at least 2
clock edges
Data
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 RSTN and DSIN setup time 10 nsec
2 RSTN and DSIN hold time 0 nsec
3 RSTN and DSIN assertion 2 Clock edges
Initialization bytes are strobed into the device
while RSTN and DSIN are low d uring risi ng edges
of CLK. The RSTN must be active low for at least
two clocks b ef o re the first initialization byte is
strobed in and remain active for at least one clock
after the final byte. Initialization register data may
be strobed at a minimum of 1 clock per byte. After
power-on the initializing registers’ contents are
undefined.
For a detailed description of the Initialization
Registers, refer to Section 2.6
Initialization Sequence
PS4011C-0200 Page 13 of 24
.
Reset and
3.3 DATA INPUT
The chip latches the input data on the DI pins on
the rising edge of t he CLK when DSIN and RDYIN
are both active. The two figures below show the
timing diagrams for buffer Ready and buffer Not
Ready conditions.
Page 18
Advanced Hardware Architectures, Inc.
1 1
1
22
22
22
22
22
111
1
11
1
valid valid
valid valid valid
valid
CLK
DI
DSIN
RDYIN
ERASE
RSTN
high = era s e
1
1
22
2
2
22
2
1
1
11
1
valid
valid valid valid
valid
CLK
DI
DSIN
RDYIN
3
3
3
3
RSTN
Figure 8: Data Input - Buffer Always Ready
If RSTN is low during write, message bytes are treated as being part of the initialization sequence. If
RSTN is high, the data is treated as being part of RS block. In the example above ERASE is asserted high
in four sample clocks.
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DI, ERASE and DSIN setup time 10 nsec
2 DI, ERASE and DSIN hold time 0 nsec
Figure 9: Data Input - Buffer Not Ready
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DI, ERASE and DSIN setup time 10 nsec
2 DI, ERASE and DSIN hold time 0 nsec
3 RDYIN output delay 15 nsec
Any input data clocked while RDYIN is inactive are ignored. This is shown in Figure 9.
Page 14 of 24 PS4011C-0200
Page 19
Advanced Hardware Architectures, Inc.
3.4 DATA OUTPUT
The DO pins are driven from a register clocked on the rising edge of CLK.
Valid data on the DO pi ns is indic ated by RDYON being acti ve. When RDYON is inact ive, data on t he
DO pins is undefined, and DSON is i gnored. The DSON signal a cknowledges receivin g the data and is us ed
by the device to i nternally incr ement the addr ess counter and output the next location in the buffer . This data
output timing is shown in Figure 10.
Figure 10: Data Output
CLK
3
DO, ERR
DSON
3
RDYON
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DSON setup time 10 nsec
2 DSON hold time 2 nsec
3 DO and RDYON output delay 15 nsec
33
valid
12 111111 122
val id valid valid valid
2
3
22 22
33
CRTN is valid for an RS block when the first message byte, X
, is strobed out of the chip. Figure 11
K−1
shows Reverse Order output . In thi s opera tion, CRTN is valid on the l ast by te of t he block from the Outpu t
Buffer. In this example only message bytes are output, no check bytes.
Figure 11: CRTN Timing - Reverse Order Output
CLK
DO
3 33
Block m
Byte X
K-3
12 11111 122 22 22
Block m
Byte X
Block m
Byte X
K-2
K-1
3
Block m+1
Byte X
0
DSON
error
3
CRTN
3 33
VALID
See Note
correctable
RDYON
Note: CRTN is active (low) if RS block m is correctable. If the number of errors detected in block m exceeds the
error thr eshold, P, CRTN is inactive (high).
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DSON setup time 10 nsec
2 DSON hold time 2 nsec
3 DO and RDYON output delay 15 nsec
PS4011C-0200 Page 15 of 24
Page 20
Advanced Hardware Architectures, Inc.
4.0 SIGNAL SPECIFICATIONS
4.1 INPUT SPECIFICATIONS
PIN
NUMBER
43 DI[7] 10 10 0 CLK
44 DI[6] 10 10 0 CLK
1 DI[5] 10 10 0 CLK
2 DI[4] 10 10 0 CLK
3 DI[3] 10 10 0 CLK
4 DI[2] 10 10 0 CLK
5 DI[1] 10 10 0 CLK
6 DI[0] 10 10 0 CLK
42 DSIN 10 10 0 CLK
33 DSON 10 10 2 CLK
35 RSTN 10 10 0 CLK
41 CLK 10 N/A N/A N/A
34 ERASE 10 10 0 CLK
N/A = Not Applicable
SIGNAL
NAME
(Refer to Section 4.5
SELF LOAD
(maximum in pF)
DC Electrical Characteristics
4.2 OUTPUT SPECIFICATIONS
TSETUP
(min in nsec)
THOLD
(min in nsec)
for pad specifications)
STROBE
PIN
NUMBER
26 DO[7] 60 0 15 CLK
24 DO[6] 60 0 15 CLK
23 DO[5] 60 0 15 CLK
22 DO[4] 60 0 15 CLK
21 DO[3] 60 0 15 CLK
20 DO[2] 60 0 15 CLK
19 DO[1] 60 0 15 CLK
18 DO[0] 60 0 15 CLK
31 RDYON 60 0 15 CLK
32 RDYIN 60 0 15 CLK
28 CRTN 60 0 15 CLK
27 ERR 60 0 15 CLK
SIGNAL
NAME
(Refer to Section 4.5
(maximum in pF)
LOAD CAP
TDEL
(min in nsec)
DC Electrical Characteristics
TDEL
(max in nsec)
for pad specifications)
STROBE
REF
Page 16 of 24 PS4011C-0200
Page 21
Advanced Hardware Architectures, Inc.
4.3 POWER & GROUND PINS
PIN NUMBER SIGNAL NAME
8, 10, 11, 16, 17, 29, 30, 37, 40 GND
7, 9, 12, 15, 25, 36, 38, 39 VDD
4.4 AC ELECTRICAL CHARACTERISTICS
CLOCK RATE
Symbol Characteristic Min Max Units Test Conditions
Fclock Clock frequency 0 40 MHz
Tlow Clock low time 8 nsec
Thigh Clock high time 8 nsec
Trise Clock rise time 5 nsec Vil to Vih
Tfall Clock fall time 5 nsec Vil to Vih
INPUTS
Symbol Characteristic Min Max Units Test Condi tions
Tsetup Input setup time 10 nsec See
Thold Input hold time 0 nsec See
Notes:
1) Setup and hold times measured from a valid high [2.4V] on the clock input pin.
2) DSON has a 2 nsec hold time.
Note 1
Notes 1 and 2
OUTPUTS
Symbol Characteristic Min Max Units Test Conditions
Tout Output delay 0 15 nsec See
Note: Output delay measured fr om val id high [2.4V] o n the cloc k input pad. The outp ut loads for the AC test are
given in Section 4.2 Output Specifications.
Note
PS4011C-0200 Page 17 of 24
Page 22
Advanced Hardware Architectures, Inc.
4.5 DC ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM STRESS RATINGS
Symbol Characteristic Min Max Units Test Conditions
Tstg Storage temperature -55 150 deg C
Vdd Supply voltage -0.5 6.0 V
Vin Input voltage Vss-0.5 Vdd+0.5 V
Package: 44-pin PLCC (JEDEC Standard)
OPERATING CONDITIONS
Symbol Characteristic Min Max Units Test Conditions
Vdd Supply voltage 4.75 5.25 V
Idd Supply current 1.0 mA
Idd Supply current 135 mA Vdd=5V
Ta Operating temperature 0 70 deg C
P Power 0.71 W Vdd=5V
Static; Clock
stopped externally
INPUTS
Symbol Characteristic Min Max Units Test Conditions
Vih Input high voltage 2.0 Vdd V
Vil Input low voltage Vss 0.8 V 40 MHz
Iil Input leakage -10 10 µΑ 0<Vin<Vdd
Cin Capacitance 10 pF Not 100% tested
OUTPUTS
Symbol Characteristic Min Max Units T est Conditions
Voh Output high voltage 2.4 Vdd V Ioh=8mA
Vol Output low voltage Vss 0.4 V Iol=8mA
Ioh Output high current -8 mA Voh=2.4V
Iol Output low current 8 mA Vol=0.4V
Page 18 of 24 PS4011C-0200
Page 23
5.0 PACKAGING
PLCC Dimension s
A
.050
(1.27)
Packaging
B
min/max
.685/.695
(17.40/17.65)
Advanced Hardware Architectures, Inc.
Inches
(Millimeters)
C
min/max
.650/.656
(16.51/16.66)
D
min/max
.165/.180
(4.19/4.57)
Pin 1 Identification
E
min
.020
(0.51)
F
±
.002
(0.051)
G
±
.0035
(0.089)
AHA4011C-040 PJC
YYWWD-(COUNTRY OF ORIGIN)
E
F = Lead Planarity
:
YYWWD = Data Code
Note
LLLL = Lead Skew
Complete Package Drawing Available Upon Request.
6.0 ORDERING INFORMATION
LLLLL
A
TM
G = Lead Skew
C
B
D
6.1 AVAILABLE PARTS
PART NUMBER DESCRIPTION
AHA4011C-040 PJC Reed-Solomon ECC Integrated Circuit
PS4011C-0200 Page 19 of 24
Page 24
Advanced Hardware Architectures, Inc.
6.2 PART NUMBERING
AHA 4011 C- 040 P J C
Manufacturer
Device
Number
Revision
Level
Speed
Designation
Package
Material
Package Type
Device Number:
4011C
Package Material Codes:
P Plastic
Package Type Codes:
J J - Leaded Chip Carrier
Test Specifications:
C Commercial 0°C to +70°C
6.3 RELATED TECHNICAL PUBLICATIONS
Test
Specification
PART NUMBER DESCRIPTION
PB4011C
PS4012B
PS4013
ABRS03 AHA Application Brief - AHA4011 and AHA4012 Device Differences
ABRS04 AHA Application Brief - Reed-Solomo n Evaluation Software Version 3.0
ABRS06 AHA Application Brief - AHA4011 and AHA4013 Device Differences
ABRS07 AHA Application Brief - AHA4011B and AHA4011C Device Differences
ABSTD1
ANRS01 AHA Application Note - Primer: Reed-Solomon Error Correction Codes (ECC)
ANRS02 AHA Application Note - Interleaving for Burst Error Correction
ANRS03 AHA Application Note - Reed-Solomon Evaluation Software Version 3.0
ANRS05 AHA Appl ica tio n Note - Serial I/O Interface to AHA4011/AHA4012
ANRS12
ANRS13
RSEVAL Reed-Solomon Evaluation Software Version 3.0 (Windows)
IESS-308,
Appendix F
AHA Product Brief - AHA4011C 10 MBytes/sec Reed-Solomon Error
Correction Device
AHA Product Specification - AHA4012B 1.5 MBytes/sec Reed-Solomon Error
Correction Device
AHA Product Specification - AHA4013 12.5 MBytes/sec Reed-Solomon Error
Correction Device
AHA Application Brief - AHA Data Compression a nd Forward Err or Correcti on
Standards
AHA Application Note - Frequently Asked Questions and Answers About the
AHA4011/AHA4012
AHA Application Note - Converting from LSI Logic’s L647xx Device to
AHA4011/12
Concatenation of Reed-Solo mon (RS) Outer Coding with the Exis ting Inner FEC
Not available from AHA
(
)
Page 20 of 24 PS4011C-0200
Page 25
APPENDIX A
Table of Elements
Advanced Hardware Architectures, Inc.
BLOCK
SIZE ‘N ’
13 dd 14 3d 15 7a 16 f4
17 6f 18 de 19 3b 20 76
21 ec 22 5f 23 be 24 fb
25 71 26 e2 27 43 28 86
29 8b 30 91 31 a5 32 cd
33 1d 34 3a 35 74 36 e8
37 57 38 ae 39 db 40 31
41 62 42 c4 43 f 44 1e
45 3c 46 78 47 f0 48 67
49 ce 50 1b 51 36 52 6c
53 d8 54 37 55 6e 56 dc
57 3f 58 7e 59 fc 60 7f
61 fe 62 7b 63 f6 64 6b
65 d6 66 2b 67 56 68 ac
69 df 70 39 71 72 72 e4
73 4f 74 9e 75 bb 76 f1
77 65 78 ca 79 13 80 26
81 4c 82 98 83 b7 84 e9
85 55 86 aa 87 d3 88 21
89 42 90 84 91 8f 92 99
93 b5 94 ed 95 5d 96 ba
97 f3 98 61 99 c2 100 3
101 6 102 c 103 18 104 30
105 60 10 6 c0 107 7 108 e
109 1c 110 38 111 70 112 e0
113 47 114 8e 115 9b 116 b1
117 e5 118 4d 119 9a 120 b3
121 e1 122 45 123 8 a 124 93
125 a1 126 c5 127 d 128 1 a
129 34 13 0 68 131 d0 132 27
133 4e 134 9c 135 bf 136 f9
137 75 13 8 e a 139 53 1 40 a6
141 cb 142 11 143 22 144 44
145 88 14 6 97 147 a 9 148 d5
149 2d 15 0 5a 151 b4 152 ef
153 59 15 4 b2 155 e 3 156 41
157 82 15 8 83 159 81 160 85
161 8d 16 2 9d 163 bd 164 fd
165 7d 16 6 fa 167 73 168 e6
169 4b 17 0 96 171 a b 172 d1
173 25 17 4 4a 175 94 176 af
177 d9 17 8 35 179 6 a 180 d4
181 2f 182 5e 183 bc 184 ff
185 79 18 6 f 2 187 63 188 c6
HEX
VALUE
11223448
510 620 740 880
9871089119512ad
BLOCK
SIZE ‘N ’
HEX
VALUE
BLOCK
SIZE ‘N’
HEX
VALUE
BLOCK
SIZE ‘N’
HEX
VALUE
PS4011C-0200 Page 21 of 24
Page 26
Advanced Hardware Architectures, Inc.
BLOCK
SIZE ‘N ’
189 b 190 16 191 2c 192 58
193 b0 194 e7 195 49 196 92
197 a3 198 c1 199 5 200 a
201 14 202 28 203 50 204 a0
205 c7 206 9 207 12 208 24
209 48 210 90 211 a7 212 c9
213 15 214 2a 215 54 216 a8
217 d7 218 29 219 52 220 a4
221 cf 222 19 223 32 224 64
225 c8 226 17 227 2e 228 5c
229 b8 230 f7 231 69 232 d2
233 23 234 46 235 8c 236 9f
237 b9 238 f5 239 6d 240 da
241 33 242 66 243 cc 244 1f
245 3e 246 7c 247 f8 248 77
249 ee 250 5b 251 b6 252 eb
253 51 254 a2 255 c3
For example, for a block size of 205, the value to be programed in Byte 1 of the Initialization Register
is 0xc7.
/*This is a C progr am to g enerat e Table of Elements. Pass a value of bloc k leng th, N i n deci mal to th is,
and obtain the Element value in hex.*/
int alpha(n)
int n;
{
int i,b,c;
c=01;
for (i=1;i<n;i++) {
b=c<<1;
if (b>0377)
c=b;
}
return c;
}
HEX
VALUE
b=b^0607;
BLOCK
SIZE ‘N ’
HEX
VALUE
BLOCK
SIZE ‘N’
HEX
VALUE
BLOCK
SIZE ‘N’
VALUE
HEX
main()
{
int i;
printf("Enter N--> ");
scanf("%d",&i);
if(i<1 || i>25 5)
printf("1<=N<=255");
else
printf("\nN = %d\tALPHA = %2x\n\n", i, alpha(i));
}
Page 22 of 24 PS4011C-0200
Page 27
Advanced Hardware Architectures, Inc.
APPENDIX B
AHA4011C Data Rate Calculations in Continuous Operation
Assumptions and Equations:
1) 40 MHz Clock is used.
2) Input Rate (C
3) Latency =
4) Data Rate = 40 MHz/C
5) GOOD or BAD based on inequality equation:
6) GOOD or BAD based on inequality equation:
7) Check symbols are input into and output from the chip along with message symbols.
Note: The following tables show examples of Data Rates and Latencies for various block sizes. Other block sizes
are also possible.
) = Output Rate (Co)
i
1–()
CiN
R
clocks/byte
i
N
C
60+()
1–()
--------------
N
×++×
C
i
R60N
-------------------------------------------------
×
C
R48N
i
C
i
i
1–
----------------
×++
C
C
m
1–
m
×
C
--------------
C
i
367≤+
N
i
1–
C
m
----------------
×++ +≥
N
1–
C
m
(5)
(6)
CLOCKS
/BYTE
NT
MAXIMUM LATENCY
CLOCKSµSECONDS
DATA RATE
(MB/sec)
EQUATION 5 EQUATION 6
4 25 10 209 5.23 10.00 GOOD BAD
4 50 10 343 8.57 10.00 GOOD BAD
4 53 10 359 8.97 10.00 GOOD BAD
4 75 10 476 11.9 10.00 GOOD G OOD
4 100 10 609 15.2 10.00 GOOD GOOD
4 126 7 742 18.6 10.00 GOOD GOOD
4 194 8 1107 27.7 10.00 GOOD GOOD
4 208 8 1181 29.5 10.00 GOOD GOOD
4 219 9 1242 31.1 10.00 GOOD GOOD
4 200 10 1143 28.6 10.00 GOOD GOOD
4 225 10 1276 31.9 10.00 GOOD GOOD
4 250 10 1409 35.2 10.00 GOOD GOOD
4 255 10 1436 35.9 10.00 GOOD GOOD
CLOCKS
/BYTE
NT
MAXIMUM LATENCY
CLOCKSµSECONDS
DATA RATE
(MB/sec)
EQUATION 5 EQUATION 6
4 25 5 199 4.98 10.00 GOOD BAD
4 50 5 333 8.32 10.00 GOOD GOOD
4 75 5 466 11.7 10.00 GOOD GOOD
4 100 5 599 15.0 10.00 GOOD GOOD
4 125 5 733 18.3 10.00 GOOD GOOD
4 150 5 866 21.7 10.00 GOOD GOOD
4 175 5 999 25.0 10.00 GOOD GOOD
4 200 5 1133 28.3 10.00 GOOD GOOD
4 225 5 1266 31.7 10.00 GOOD GOOD
4 250 5 1399 35.0 10.00 GOOD GOOD
4 255 5 1426 35.7 10.00 GOOD GOOD
PS4011C-0200 Page 23 of 24
Page 28
Advanced Hardware Architectures, Inc.
CLOCKS
/BYTE
4 25 3 195 4.88 10.00 GOOD BAD
4 50 3 329 8.22 10.00 GOOD GOOD
4 75 3 462 11.6 10.00 GOOD GOOD
4 100 3 595 14.9 10.00 GOOD GOOD
4 125 3 729 18.2 10.00 GOOD GOOD
4 150 3 862 21.6 10.00 GOOD GOOD
4 175 3 995 24.9 10.00 GOOD GOOD
4 200 3 1129 28.2 10.00 GOOD GOOD
4 225 3 1262 31.6 10.00 GOOD GOOD
4 250 3 1395 34.9 10.00 GOOD GOOD
4 255 3 1422 35.6 10.00 GOOD GOOD
CLOCKS
/BYTE
4 25 1 191 4.78 10.00 GOOD BAD
4 50 1 325 8.12 10.00 GOOD GOOD
4 75 1 458 11.5 10.00 GOOD GOOD
4 100 1 591 14.8 10.00 GOOD GOOD
4 125 1 725 18.1 10.00 GOOD GOOD
4 150 1 858 21.5 10.00 GOOD GOOD
4 175 1 991 24.8 10.00 GOOD GOOD
4 200 1 1125 28.1 10.00 GOOD GOOD
4 225 1 1258 31.5 10.00 GOOD GOOD
4 250 1 1391 34.8 10.00 GOOD GOOD
4 255 1 1418 35.5 10.00 GOOD GOOD
NT
NT
MAXIMUM LATENCY
CLOCKSµSECONDS
MAXIMUM LATENCY
CLOCKSµSECONDS
DATA RATE
(MB/sec)
DATA RATE
(MB/sec)
EQUATION 5 EQUATION 6
EQUATION 5 EQUATION 6
Page 24 of 24 PS4011C-0200
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