Datasheet AHA3540A-040PTC Datasheet (Advanced Hardware Architectures)

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PS3540-1100

2365 NE Hopkins Court

Pullman, WA 99163-5601

tel: 509.334.1000

fax: 509.334.9000

e-mail: sales@aha.com

www.aha.com

advancedhardwarearchitectures

PRELIMINARY *

Product Specification

AHA3540

40 MBytes/sec ALDC Data

Compression Coprocessor IC

* This specification represents a product still in the design cycle, undergoing testing processes, any specifications

are based on design goals only. Parameters may be subject to change pending completion of characterization.

Advanced Hardware Architectures, Inc.

PS3540-1100 i

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.4.1 Port A and Port B Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.4.2 Data Expansion During Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.4.3 Multiple Records. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.4.4 Byte Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.0 Compression Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.1 Compression Pass Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.2 Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3.0 Decompression Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1 Decompression Pass Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2 Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.3 Decompression Output Disabled Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.0 Microprocessor Interface and Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.1.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.1.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4.1.3 Port A Interface FIFO Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4.2 Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.3 Pausing / Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

5.0 Port A and Port B Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

6.0 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

6.1 Status 0 (STAT0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

6.2 Status 1 (STAT1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

6.3 Port A Configuration 0 (ACNF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

6.4 Port A Configuration 1 (ACNF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

6.5 Port B Configuration 0 (BCNF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

6.6 Port B Configuration 1 (BCNF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

6.7 Identification (ID0, ID1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

6.8 Port A Polarity (APOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

6.9 Port B Polarity (BPOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6.10 Port A Transfer Count (ATCL0, ATCL1, ATCH0, ATCH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6.11 Record Count (RCL0, RCL1, RCH0, RCH1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.12 Port B Compare Count (BCCL0, BCCL1, BCCH0, BCCH1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.13 Port B Transfer Count (BTCL0, BTCL1, BTCH0, BTCH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

6.14 Port A FIFO Data Access (AFIF0, AFIF1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

6.15 Compressed Bytes Processed (CBPL0, CBPL1, CBPH0, CBPH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6.16 Port A FIFO Control (AFCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6.17 Error Status (ERRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

6.18 Interrupt Status 0 (INTS0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

6.19 Interrupt Status 1 (INTS1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

6.20 Command (CMND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

6.21 Record Length (RLL0, RLL1, RLH0, RLH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6.22 Data Disabled Count (DDCL0, DDCL1, DDCH0, DDCH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6.23 Error Mask (EMSK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

6.24 Interrupt Mask 0 (IMSK0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.25 Interrupt Mask 1 (IMSK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

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7.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7.2 Port A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4

7.3 Port B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4

8.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5

9.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

9.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

9.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

9.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

10.0 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

11.0 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

12.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

12.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 6

12.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

13.0 AHA Related Technical Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Appendix A: Differences between the AHA3540 and IBM ALDC1-20S-LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

A.1 Status and Interrupt Status Register Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

A.2 Input/Output Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

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Figures

Figure 1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 2: Multiple Record Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Figure 3: Port A Interface Input Padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 4: TQFP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 5: Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 6: Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 7: Processor Read Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 8: Processor Write Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 9: Processor Read Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 10: Processor Write Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 11: Port A Burst Write Timing, Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 12: Port A Burst Read Timing, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 13: Port B Burst Read Timing, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 14: Port B Burst Write Timing, Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 15: Port A Write Timing, FAS368 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 16: Port A Read Timing, FAS368 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 17: Port B Read Timing, FAS368 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 18: Port B Write Timing, FAS368 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 19: Port A Write Timing, 43C97 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 20: Port A Read Timing, 43C97 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 21: Port B Read Timing, 43C97 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 22: Port B Write Timing, 43C97 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 23: AHA3540 TQFP Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

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iv PS3540-1100

Tables

Table 1: Microprocessor Interface Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 2: Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 3: Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 4: Processor Read Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 5: Processor Write Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 6: Processor Read Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 7: Processor Write Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 8: Port A Burst Write Timing, Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9: Port A Burst Read Timing, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 10: Port B Burst Read Timing, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 11: Port B Burst Write Timing, Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 12: Port A Write Timing, FAS368 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 13: Port A Read Timing, FAS368 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 14: Port B Read Timing, FAS368 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 15: Port B Write Timing, FAS368 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 16: Port A Write Timing, 43C97 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 17: Port A Read Timing, 43C97 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2

Table 18: Port B Read Timing, 43C97 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 19: Port B Write Timing, 43C97 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 20: TQFP (Thin Quad Flat Pack) 14 × 14 mm Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

PS3540-1100 Page 1 of 47

Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

AHA3540 is a single ch ip lossles s compression and decompression in tegrated circu it implementing the industry standard lossless adaptive data compression algorit hm, also k nown as ALDC. Th e device compresses, de compresses or passes throug h data unchanged depending on the operating mode selected. This device achieves an average compression ratio of 2:1 on typical computer files. The flexible hardware interface makes this part suitable for many applicat ion s.

AHA3540 is algorithm com patible to the IBM



ALDC device, ALDC1-20S-LP, as well as AHA’s first generation ALDC device, AHA3520. Files compressed on one device can be intercha nged and decompressed on other devices.

Content Addressable Memory (CAM) within the compression/decompression engine eliminates the need for external SRAMS.

Included in this specification is a functional overview, operation modes, register descriptions, DC and AC Electrical characteristics, ordering information, and a listing of related technical publications. It is intended for hardware and software engineers d esigning a compressi on system using AHA3540.

AHA designs and develops lossless compression, forward error correction and data storage formatter/controller ICs. Technical publications are available upon request.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

– Active low signals have an “N” appended to the

end of the signal name. For example, CSN and WRITEN.

– “Signal assertion” means the signal is logically

true.

– Hex values are represent ed wi th a prefix of “0x”,

such as Register “0x00”. Binary values do not contain a prefix, for example, MMODE = 1.

– A prefix or suffix of “x” in dicates a lett er missing

in a register name or signal name. For example, xCNF0 refers to the ACNF0 or BCNF0 register.

– A range of signal names or register bits is denoted

by a set of colons between the numbers. Most significant bit is always shown first, followed by least significant bit. For exampl e, MDATA[7:0] indicates signal names MDATA7 through MDATA0.

– Mega Bytes per second is referred to as MBytes/

sec or MB/sec.

– IBM is a registered tr ademark of IBM.

1.2 FEATURES

PERFORMANCE:

• 40 MB/s data compression, decompression or pass-through rate wi th a single 80 MHz cl ock; 20 MB/s data compression, decompression or passthrough rate with a single 40 MHz clock

• 2:1 average compression ratio

• A four byte Recor d Len gth register allows record lengths up to 4 gigabytes

• Four byte Record Count register allows multiple record transfers

• Error checking in decompression mode reportable via an interrupt

FLEXIBILITY:

• Polled or interrupt driven I/O

• Programmable polarity for DMA control signals

• DMA FIFO access via microprocessor port at Port A Interf ace

SYSTEM INTERF ACE:

• Single chip data compression solution

• Two selectable micr oprocessor interfaces

• Programmable Interrupts

• Interfaces directly with industry standard SCSI chips, FAS368, AIC-43C97C and AIC-33C94C

OTHERS:

• Open standard ALDC adaptive lossless compression algorithm

• Complies to QIC-154, ECMA 222, ANSI X3.280-1996 and ISO 15200 standard specifications

• Algorithm compatible to I BM ALDC1-20S-HA, IBM ALDC1-20S-LP and AHA3520

• 100 pin package in 14 × 14 mm TQFP body

• Lower power 3.3 Volt device

1.3 APPLICATIONS

•Tape drives

• Network Communications – wired and wireless

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Advanced Hardware Architectures, Inc.

1.4 FUNCTIONAL DESCRIPTION

AHA3540 is a compression/decompression device residing between the host interface, usually SCSI, and the buffer manager ASIC. Major blocks in this device are the Microproce ssor Interface, P ort A Interface, Port B Interface, and the Compression/ Decompression Engine. The Microprocessor Interface provides status and control information by register access. Port A and Port B Interfaces are configurable for polarity, handshaking modes, and other options. The operating mode establishes the direction of both the Port A and Port B Interfaces. Compression or Compression P ass Through sets the Port A Interface as an input and the Port B Interface as an output. Conversely Decompression or

Decompression Pass Through sets the Port A Interface as an output and the Port B Inter face as an input. Decompression Output Disabled mode allows the device to dec ompress a user programmed number of records while dumping the uncompressed data, then automatically begin outputting the remaining uncompressed records.

A four byte Record Length register and a four byte Record Count register allow the user to partition the data into multiple records. Compression Pass Through mode and Decompression Pass Through modes allow data transfers through the device without changing the data. Both interfaces, Port A and Port B, have selectable transfer modes.

Figure 1: Functional Block Diagram

PORT A

DMA

STATE

MACHINE

CLOCK

GENERATION

PORT B

DMA

STATE

MACHINE

PROCESSOR INTERFACE STATE MACHINE

PROCESSOR INTERFACE

ALDC CORE

APARITY[1:0]

ADATA[15:0]

CLOCK

PORT A

INTERFACE

PORT B

INTERFACE

AHA3540 Compression Chip

ACOUT

ARD

BPARITY[1:0]

BDATA[15:0]

BCOUT BCIN

MCIN[1:0]

WAITN

ADDR[4:0]

MMODE

RESETN

IREQN

AWR

ACIN

MDATA[7:0]

IBM



IBM is a registered trademark of IBM.

BWR

BRD

PS3540-1100 Page 3 of 47

Advanced Hardware Architectures, Inc.

1.4.1 PORT A AND PORT B INTERFACES

Both Port A and Port B Interfaces are independently configurable via the Port A Configuration register (ACNF), the Port A Polarity register (APOL), the Port B Configuration register (BCNF), and the Port B Polarity register (BPOL). Port A may be configured to operate in burst mode (20 MB/sec, Slave), 43C97C mode (40 MB /s ec, Slave) or FAS368 mode (40 MB/sec, Slave). Port B may be configured to operate in burst mode (20 MB/ sec, Master), 43C97C mode (40 MB/sec, Master) or FAS368 mode (40 MB/sec, Master).

Burst mode is an asynchronous DMA transfer mode requiring a request followed by one or more acknowledges. Data is latched on the trailing edge of the acknowledge pulses.

FAS368 mode is a DMA transfer mode compatible with FAS368 devices. In this mode DACKA (ACOUT) is asserted low for the entire burst transfer and 16- bit data is strobed into or out of Port A using ARD or AWR respectively. ACOUT, A WR an d ARD must be pro grammed as ac tive low signals in the APOL register. ACIN (DREQ) must be programmed as active high.

Port A and Port B Interfaces both contain sixteen-byte FIFOs.

1.4.2 DATA EXPANSION DURING

COMPRESSION

Data expansion occurs when the size of the data increases during a compression operation. This typically occurs when the d ata is compressed prior to input into the chi p.The EXPAND status bit is set if the Port B Transfer Count is larger than the Port A T ransfer Cou nt regis ter. If data e xpansio n caused the Port B T rans fer Count to exceed its maximum 4- byte value then the BTC Overflow Error status gets set. Worst case expansion allowable by the algorithm is 12.5% or (9/8 ti mes the uncompr essed Record Length).

1.4.3 MULTIPLE RECORDS

The AHA3540 device has two provisions to manage compressing a block of data into multiple records: automatic segmentation into multiple records at the Por t A interfa ce and the Res et histor y buffer command. During compression operation, the Port A interface autom atically partitions the uncompres sed data into equal length records according to the Record Count and Record Length registers. The two sets of registers determine the number of records and length of each record in the data transfer operati on. When compressing multiple records the devi ce retains the con tents of the hist ory buffer between records. This usually improves compression ratio by al lowing data from the current record to match against data from the previous record. During decompress ion, t he previ ous re cord must be deco mpressed prior to the current record unless the history buffer is reset just before compressing the curr ent record. For example, Figure 2 shows three records with a history buffer reset before record three. In this case, record three can be decompressed without previously decompressing records one and two. However, decompressing record two requires deco mpressing rec ord one first .

When processing multiple records (Record Count is greater tha n on e), the Record Length must be greater than 0x22.

1.4.4 BYTE ALIGNMENT

Both the Port A and Port B interfaces support the insertion and re moval of padding byte s to align data transfers to any byte bounda ry withi n a two -byte or four-byte wide memory system. Figure 3 shows the four padding possibilities. In this figure, padding bytes are designated P

, and normal data bytes are

designated D

. Four bits w ithin the command register are used to specify the desired input and output padding for a given command.

Pad bytes are no t counted by any of the counters.

Figure 2: Multiple Record Compression

History

Buffer Reset

Por t A

Uncompressed

Data

(optional)

RECORD 1

Compressed

History Buffer Reset

RECORD 1

Por t B

Compressed

Data

RECORD 2 RECORD 3

Compressed

RECORD 2

Compressed

RECORD 3

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Advanced Hardware Architectures, Inc.

Figure 3: Port A Interface Input Padding

2.0 COMPRESSION OPERA TION

2.1 COMPRESSION PASS THROUGH

Compression Pass Through mode allows data to enter the Port A Interface, transfer through the ALDC core, and exit through the Port B Interface unchanged. Pass through mode uses the Por t A Transf er c ount er, Port B T r ansfer counter an d R ecord Length and Record Count re gi st e rs . The DONE status bit and interrupt (if not masked) are set when the transfer completes.

2.2 COMPRESSION

During compression operation, uncompressed data flows into the Port A Interface, is compressed by the compression engine , and the compressed data transferre d out of the Port B Interface.

The device contains a Content Addressable Memory (CAM). The CAM is the h istory buffer during compression operation. The compressor appends an end marker control code to the end of the compressed data. It a lso pads the end of a transfer to a byte boundary with zeroes.

The compression engine constantly monitors the performance of compression for expansion during compression operation. When the Port B Transfer Count is la r ger th an t he Port A Transfe r Co un t the EXP AND bit in the Status 0 register is set indicating data expansion during compression operation.

Port A Interface count increments with each byte received and when this count equals the transfer size, all bytes in this transfer have been received into Port A.

A compression oper ation is c omple te whe n the last byte transfer s out of the Port B Int erface and the Record Length is zero and the Recor d Count is one, thus setting the DONE status bit and generating a Done Interrupt if it is not masked.

Port A Data Transfers

ADATA

[15:8] [7:0]

n+8 n+4

D11D10D9D

D7D6D5D

D3D2D1D

Part (a): Zero Bytes of Padding

Port A Data Transfers

ADATA

[15:8] [7:0]

n+8 n+4

D10D9D8D

D6D5D4D

D2D1D

Part (b): One Byte of Padding

Port A Data Transfers

ADATA

[15:8] [7:0]

n+8 n+4

D9D8D7D

D5D4D3D

D1D

Part (c): Two Bytes of Padding

Port A Data Transfers

ADATA

[15:8] [7:0]

n+8 n+4

D8D7D6D

D4D3D2D

Part (d): Three Bytes of Padding

PS3540-1100 Page 5 of 47

Advanced Hardware Architectures, Inc.

3.0 DECOMPRESSION OPERATION

3.1 DECOMP RESSION P ASS THRO UGH

Decompression Pass Through mode allows data to enter the Port B Interface, transfer through the ALDC core, and exit through the Port A Interface unchanged. Pass through mode uses the Port A Transfer counter, Port B Transfer counter, Record Length and Record Count registers. The DONE status bit and interrupt (i f not masked) are set when the transfer completes.

3.2 DECOMPRESSION

During Decompression mode, compressed data flows into the Port B Interface and is decompress ed. The resulting uncompressed data is transfer red out of the Port A Interface.

A decompression operation is complete when the last byt e transfers out of the Port A Interface, thus setting the DONE status bit and generating a Done Interrupt if it is not masked.

Decoder Control Code Errors are generated if invalid control codes are detected in the compressed data stream. This error is reported in the Error Status register.

Multiple records can be decompressed by programming the Record Count register. The Record Count register decrements every time an End of Record is decoded.

3.3 DECOMPRESSION OUTPUT DISABLED MODE

Decompression output disabled mode allows the user to program the number of records into the Data Disable Count register to deco mpress while discarding the output. The device then switches to normal decompression mode and continues to decompress the remaining records determined by the remaining number of records in the Record Count register , a nd trans fers thi s data out of Por t A.

4.0 MICROPROCESSOR INTER-

FACE AND REGISTER ACCESS

4.1 MICROPROCESSOR INTERFACE

Microprocessor Interface configuration is determined by the MMODE pin. If MMODE is t ied high, transfers are cont rolled by a chip se lect sign al (CSN) and a read/wri te signal (RWN), if MMODE is tied low, transfers are controlled by separate read (READN) and write (WRITEN) signals. Re fer to Section 10.0 Timing Specifications for timing diagrams.

Table 1: Micropr oces so r In te rface Control Signals

4.1.1 INTERRUPTS

IREQN is th e hardware interrupt signal. IREQN is a standard TTL output. When active, it indicates a n interrupt is set in the devi ce. The microprocessor can determine the cause of the interrupt by reading the Interrupt Status register.

Masking individual interrupts with the Interrupt Mask register disables particular interrupts from causing the interrupt signal pin to assert (IREQN).

The interrupt signals are reset to their inactive state when either a hardware or software reset occurs, new compression operation begins, or by writing a zero to the Interrupt Status bit.

In general, the Interrupt Status and Status bits get set even if the Interrup t Mask bits are set. The exceptions are the One Byte at Port B, End of Record at Port B, One Byte at Port A, and End of Record at Port A. If these interrupt s are masked, this status information can only be provided at the end of transfer, not at end of records because the ALDC core does not identify end of records in the data stream.

PIN NAME MMODE TIED LOW MMODE TIED HIGH

MCIN[0] READN CSN MCIN[1] WRITEN RWN WAITN WAITN WAITN

ADDR[0]

ADDR[0] = 0 selects register bits 7:0 ADDR[0] = 1 selects register bits 15:8

ADDR[0] = 0 selects register bits 15:8 ADDR[0] = 1 selects register bits 7:0

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Advanced Hardware Architectures, Inc.

4.1.2 RESETS

There is a hardware reset signal and a software reset. When the RESETN signal is asserted all registers are r eset, current operat ions a re cance lled, and the history buf fer is cleared . The so ftware reset via the Command register does not affect the

Configuration registers (ACNF or BCNF), Identification register (ID), the Polarity registers

(APOL or BPOL), or the Command register (CMND). Al l other registers are reset, current operations cancelled and the history buffer cleared.

Section 6.0 Register Description lists the register values after a hardware reset, software reset command, and after a transfer command.

A new transfer command doe s not reset the data path; therefore, a hardware reset or software r eset is generally required prior to issuing a new transfer command.

4.1.3 PORT A INTERFACE FIFO ACCESS

It is possible to access the Port A Interface FIFO from the microprocessor interface. T his allows the uncompressed data stream to be altere d from the microprocessor. This may be useful to properly handle exception conditions. Both read and write accesses are available. Only the Port A Interface FIFO is accessible from the microprocessor interface. In order to access the FIFO from th e microprocessor interf ace, data tr ansfers on the Port A interface must be suspended. The DMA device attached to the Port A interface must deactivate the DREQA line before attempting to access the FIFO from the microprocessor interface. Unpredictable results occ ur if DREQA is active during FIFO access from the microprocessor interface.

Two registers are used to control access to the FIFO: the Port A FIFO Contr ol (AFCT) register and the Port A FIFO Data (AFIF) register. AFIF is a two-byte register used to hold data to be written to the Port A Interface FIFO during compression operations and to hold data read from the Port A Interface FIFO during decompression operations. Two bits within AFCT are defined: Access Port A FIFO (ACCF) and Request Port A FIFO (REQF). The Access Port A FIFO bit must be set for the entire duration of a read or write access to the Port A FIFO. This bit controls whether the Port A FIFO is accessed from the Port A interface or the microprocessor int erface. The REQF bit is used as a semaphore to reques t a read or a writ e to the P ort A Interface FIFO. Read or write is determined by the current command being executed. The FIF O can be read only during deco mpression commands and can be written only during compression commands.

Writing to the Port A Interface FIFO, assuming a compression or compression bypass operation is being executed, requires the following:

1) Suspend transfers on Port A Interface

(DREQA input must be deasserted).

2) Write a Select Port A Command.

3) Set ACCF.

4) Place data to be written to the original data

interface FIFO in AFIF.

5) Set REQF.

6) Read REQF until REQF returns to a zero.

7) Repeat steps 3 to 5 as necessary.

8) Clear ACCF and resume DMA operations.

Reading from the Port A Interface FIFO, assuming a decompression bypass, decompression or decompression output disabled operation is being executed, requires the following:

1) Suspend transfers on Port A Interface

(DREQA input must be deasserted).

2) Write a Select Port A Command.

3) Set ACCF.

4) Set REQF.

5) Read REQF until REQF returns zero.

REQF is reset when two bytes have been read

from the Port A Interface FIFO and placed in

AFIF.

6) Read data from AFIF.

7) Repeat steps 3 to 5 as necessary.

8) Clear ACCF and resume DMA operations.

All Port A interface status indicators are updated exactly as if the data is read from or written to the Port A i nterface data bus. For instance:

• The Port A Interface Transfer Count (ATC)

will increment as b yte s are transferred th rou gh

the microprocessor interface.

• All Status bits (STAT0 and STAT1) and

Interrupt Status bits (INTS) will operate when

data is transferred through the microprocessor

interface.

• Padding bytes are supported at command

boundaries.

• Padding bytes may have to be inserted to

ensure that the last transfer from the

micropro cessor ends on an even-byte

boundary.

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Advanced Hardware Architectures, Inc.

4.2 REGISTER ACCESS

MMODE determines whet her ADDR[0] selects even or odd addressed registers. When MMODE = 1 and ADDR[0]=0, odd addressed registers are accessible. MMODE=1 causes ADDR[0] input signal to be inverted.

The registers may not be stable if PAUSED is not set. Registers should onl y be written when they are stable.

When writing to register s th at a re de fi ned as 16bit registers, both bytes mus t be writ te n bef ore t he register is updated. When writing t he 16-bit Command register , t h e co mmand is e xecut ed whe n the most significant byte is writt en. ADDR[0] selects between the upper and lower bytes of 16-bit r egisters.

Registers i n the ALDC core require longer to access than the external microprocessor interface permits. Therefore, if back to back writes to the same address ever occur, they must be separated by a minimum of 8 clocks.

4.3 PAUSING / RESUME

When a Pause command is issued or an unmasked data transfer interrupt occurs, the device pauses at the next break in the DMA handshaking. The following unmasked int errupts cause the device to pause: ODT (Output Disable Terminated), EORPA (End of Record at Port A), BPA (One Byte at Port A), EORPB (End of Recor d at Port B) , BPB (One Byte at Port B), BCMP (Port B Interface Compare), and EORD (End of Record at Decoder). A Slave port pauses after ACOUT (DACKA) deasserts. For a Master port, the PAUSED status bit will get set even if BCOUT (DREQB) is asserted. The master port may have several transfers in its output pipe. Therefore, several transfers could occur before the interface pauses and DREQB remains deasserted. Once paused and the last transfer is complet e, the d ata bus ses ar e put i n high impedance. Operation is continued by issuing a resume command

Registers i n the ALDC core require longer to access than the external microprocessor interface permits. Therefore, these registers must be prefetched for external reads. To assure that the values read from these registers are current, it is recommended that a Pause comman d be iss ued and Paused Status read prior to reading these registers. When a pause command is received, it takes up to 40 clock cycles to update these registers. The PAUSED status bit is not set until the registers are updated. Additional microprocessor accesses during this time will delay the pre fetched reads and

Paused status. Registers that must be prefetched include the Compressed Bytes Processed, Error

Status, Interrupt Status, Record Count and Data Disable Count registers.

5.0 PORT A AND PORT B CONFIGURATION

Port A and Port B are both 16-bit bidirectional data ports with pa rity checki ng and gener ation. The ports are controlled by the configuration registers ACNF[15:0] and BCNF[15:0], and polarity registers APOL[7:0] and BPOL[7:0].

Page 8 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

6.0 REGISTER DESCRIPTION

ADDR[4:0]

MNEMONIC REGISTER NAME R/W

N O T E S

A G E

MMODE

= 0

MMODE

= 1

HARDWARE

RESET

COMMAND

NEW TRANSFER COMMAND

0x00 0x01 STAT0 Stat u s , B y te 0 R 1 0x00 0x00 0x80 9 0x01 0x00 STAT1 Status, Byte 1 R 1, 4 0x0C 0x0C 0000UU00 10 0x00 0x01 ACNF0 Port A Configur a t i on, Byte 0 R/W 2 0x00 unchanged unchanged 11 0x01 0x00 ACNF1 Port A Configur a t i on, Byte 1 R/W 2 0x00 unchanged unchanged 11 0x00 0x01 BCNF0 Port B C o nfigura tion, By t e 0 R/W 3 0x00 unchanged unchanged 11 0x01 0x00 BCNF1 Port B C o nfigura tion, By t e 1 R/W 3 0x00 unchanged unchanged 12 0x02 0x03 ID0 Identification 0 R 1 0x40 0x40 0x40 12 0x03 0x02 ID1 Identification 1 R 1 0x35 0x35 0x35 12 0x02 0x03 APOL Port A P olarity R/W 2 0xFF unchanged unchanged 12 0x03 0x02 res Reserved 0x02 0x03 BPOL Port B P olarity R/W 3 0xDF unchanged unchanged 13 0x03 0x02 res Reserved

0x04 0x05 ATCH0 Port A Transfer Count, Byte 2 R 1 0x00 0x00 0x00 13 0x05 0x04 ATCH1 Port A Transfer Count, Byte 3 R 1 0x00 0x00 0x00 13 0x04 0x05

RCH0 Record Count, Byte 2 R/W 2 0x00 0x00 0x00

14 0x05 0x04 RCH1 Record Count, Byte 3 R/W 2 0x00 0x00 0x00 14 0x04 0x05 BCCH0 Port B Compare Count, Byte 2 R/W 3 0x00 0x00 0x00 14 0x05 0x04 BCCH1 Port B Compare Count, Byte 3 R/W 3 0x00 0x00 0x00 14 0x06 0x07 ATCL0 Port A Transfer Count, Byte 0 R 1 0x00 0x00 0x00 13 0x07 0x06 ATCL1 Port A Transfer Count, Byte 1 R 1 0x00 0x00 0x00 13

0x06 0x07

RCL0 Record Count, Byte 0 R/W 2 0x00 0x00

0x00 14

0x07 0x06 RCL1 Record Count, Byte 1 R/W 2 0x00 0x00

0x00

14 0x06 0x07 BCCL0 Port B Compare Count, Byte 0 R/W 3 0x00 0x00 0x00 14 0x07 0x06 BCCL1 Port B Compare Count, Byte 1 R/W 3 0x00 0x00 0x00 14 0x08 0x09 BTCH0 Port B Transfer Count, Byte 2 R 1 0x00 0x00 0x00 15 0x09 0x08 BTCH1 Port B Transfer Count, Byte 3 R 1 0x00 0x00 0x00 15 0x08 0x09

AFIF0 Por t A F IF O D at a A cc e s s, B y te 0 R/W 2 0x00 0x00 0x00

15 0x09 0x08 AFIF1 Po rt A F IF O D a ta A c c es s , By t e 1 R/W 2 0x00 0x00 0x00 15

0x08 0x09 CBPH0

Compressed Bytes Processed, Byte 2

R 3 0x00 0x00 0x00 16

0x09 0x08

CBPH1

Compressed Bytes Processed, Byte 3

R 3 0x00 0x00 0x00

0x0A 0x0B BTCL0 Port B Transfer Count, Byte 0 R 1 0x00 0x00 0x00 15 0x0B 0x0A BTCL1 Port B Transfer Count, Byte 1 R 1 0x00 0x00 0x00 15 0x0A 0x0B AFCT Po r t A F I F O Contro l R/W 2 0x00 0x00 0x00 16 0x0B 0x0A res Reserved 2

0x0A 0x0B CBPL0

Compressed Bytes Processed, Byte 0

R 3 0x00 0x00 0x00 16

0x0B 0x0A

CBPL1

Compressed Bytes Processed, Byte 1

R 3 0x00 0x00 0x00

0x0C 0x0D ERRS Err o r Status R 1 0x00 0x00 0x00 17 0x0D 0x0C res Reserved 0x0E 0x0F INTS0 Interrupt Status, Byte 0 R/W 1 0x00 0x00 0x00 17

0x0F 0x0E INTS1 Interrupt Status, Byte 1 R/W 1 0x00 0x00 0x00 18 0x10 0x11

CMND0 Command 0

R/W

0x00 0x00 0x00

19 0x11 0x10 CMND 1 C o m m a n d 1 R/W 0x00 0xA0 0x00 19 0x12 0x13

res Reserved

0x13 0x12 res Reserved 0x14 0x15 RLH0 Record L e n g th, Byte 2 R/W 0x00 0x00 unchanged 20 0x15 0x14 RLH1 Record L e n g th, Byte 3 R/W 0x00 0x00 unchanged 20

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Advanced Hardware Architectures, Inc.

Notes:

1) When CMND is not a Selection Command.

2) When CMND is a Select Port A Configuration Command.

3) When CMND is a Select Port B Configuration Command.

4) U identifies a bit that is unchanged.

6.1 STATUS 0 (STAT0)

Read Only Hardware Reset Value = 0x00 Reset Command = 0x00

Any status bit which is active when the device pauses, due to an interrupt or Pause Command, will remain active until t here is a Resume Command. See Appendix A.1 for dif ference s between AHA3540 an d IBM ALDC1-20S-LP.

BUSY - Busy. This bit is set when a data transfer operation begins. It is cleared when the data transfer

operation completes successfully, when an unmasked error occurs, when a reset occurs.

PAUSED - Paused. Th is bit is set wh en a data transf er operation is currently paused. It is cleared when a

paused data transfer operation is resumed, when a reset occurs, or on a new transfer.

OUTDIS - Out put Disabled. This bit i s set when Port A Interfac e output is disabled. I t is cleared when Port

A Interface output is re-enabled, when a reset occurs, or on a new transfer.

BYP ASS - Bypass. This bit is set after a Start Compres sion Bypass or a Start Decompression Bypass

command is written to the Command register. It is cleared after a Start Compression, Start Decompression, St art Decompression Output Disable, when a reset occurs , when an unmasked error occurs, or when a transfer is complete.

EXP AND - Expansion. This bit i s set when the Port B Transfer Count register is larger than the Port A

Tr ansfer Count re gister . It may toggle many times d uring a compress ion operation. It is cleared

when another data transfer operation begins or when a reset occurs.

ANYINT - Any Interrupt. This bit is set while an unmasked interr upt is ac ti ve. Cl ear ed on a ne w tra nsf er,

and when all unmasked interrupts have been cleared.

ANYERR - Any Error. This bit is set when an unmasked error occurs. It is cleared when a data transfer

operation begins or when a reset occurs.

DONE - Done. This bit is set when the curr ent data transfer operatio n is complete. It is cleared when a

data transfer operation begins or when a reset occurs.

0x16 0x17 RLL0 Record Length, B y t e 0 R/W 0x00 0x00 unchanged 20 0x17 0x16 RLL1 Record Length, B y t e 1 R/W 0x00 0x00 unchanged 20 0x18 0x19 DDCH0 Data Disabled Count, Byte 2 R/W 0x00 0x00 unchanged 20

0x19 0x18 DDCH1 Data Disabled Count, Byte 3 R/W 0x00 0x00 unchanged 20 0x1A 0x1B DDCL0 Data Disabled Count, Byte 0 R/W 0x00 0x00 unchanged 20 0x1B 0x1A DDCL1 Data Disabled Count, Byte 1 R/W 0x00 0x00 unchanged 20 0x1C 0x1D EMSK Error Mask R/W 0x00 0x00 unchanged 21 0x1D 0x1C res Reserved 0x1E 0x1F IMSK0 Inter r u p t M a s k 0 R/W 0x00 0x00 unchanged 22

0x1F 0x1E IMSK1 Inte r r u p t M a s k 1 R/W 0x00 0x00 unchanged 22

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x00 0x01 BUSY PAUSED OUTDIS BYPASS EXPAND ANYINT ANYERR DONE

ADDR[4:0]

MNEMONIC REGISTER NAME R/W

N O T E S

A G E

MMODE

= 0

MMODE

= 1

HARDWARE

RESET

COMMAND

NEW TRANSFER COMMAND

Page 10 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

6.2 STATUS 1 (STAT1)

Read Only Hardware Reset Value = 0x0C Reset Command = 0x0C

The Status bits BPB, EORP B, BPA and EORPA will only get set after the last word i s transferr ed if the

following Interrupt Mask bits are set: BPBM, EORPBM, BPAM and EORPAM. If these bits are set, the ALDC core provides end of transfer information, but no end of record information. See Appendix A.1 for differences between AHA3540 and IBM ALDC1-20S-LP.

EORD - End of Record at Decoder. This bit is set when the ALDC decoder detects an End of Record

control code in the compressed data stream or when an ALDC Decoder Control Code Error occurs. This bit is cleared af ter reset, when the de coder begins processi ng the first code word of the next record, or when a ne w data transfer op eration begins. It i s valid for Decompre ssion and Decompression Output Disable modes.

BCMP - Port B Interface Compare. Thi s bit is set whe n Port B T rans fer Count is gr eater than or equa l to

Port B Interface Compare Count. Othe rwise, it is cleare d. This bit is cleared af ter reset or when a new data transfer operation begins. This bit is valid for all modes of operation.

BPB - One Byte at Port B. During com pression bypass a nd compression opera tions, this bit is set at the

same time th e End of Record at Port B (STAT1[4] and INTS1[4]) is set if only one byte at the Port B Interface is part of the current record. During decompression bypass operation, this bit is set during the las t da ta tra nsf er of the record at the Port B Interface if only one byte be longs to the current r eco rd. This bit is clear ed aft er reset, when a new data t ransfer operation beg ins , or when the first byte of the next record is transferred. Not valid during Decompression and Decompression Output Disable modes.

EORPB - End of Record at Por t B. During compression bypass and c ompression ope rations, t his bit i s set

when the last byte of a compressed record is transferred out of the Po rt B interface. During decompression bypass oper ations, this bit is set when the last by te of a record is tr ansferred into the Port B interface. This bit is cleare d after reset, when a new dat a transfer operation begins, or when the first byte of the next record is transferred. Not valid during Decompression and Decompression Output Disable modes.

EMPB - Empty at Port B. This bit is set when there is no data in the Port B interface data path. This bit

must be set when writing to the Recor d Lengt h register during Dec ompression bypass operat ion and when writing to the Record Count register during Decompression and Decompression Output disabled operations. Set after reset.

EMP A - Empty at Port A. This bit is set when there is no data in the Port A interface data path. This bit

must be set when writing to t he Reco rd Length or Record Count register s du ri ng Compr es si on and Compression Bypass operations. S et after reset.

BP A - One Byte at Port A. During compression bypass and compression operations, this bit is set during

the last data transfer of the record at the Port A interface if only one byte belongs to the current record. During decompression bypass, decompression, and decompression output disabled modes, this bit is set the same time the End of Record at Port A interface bit (STAT1[0] and INTS1[0]) is set if only one byte at the Port A interface is part of the current record. This bit is cleared after reset, when a new data transfer operation begins, or when the first byte of the next record is transferred.

EORP A - End of Record at Por t A. During compression by pass and compression operations, this bi t is set

each time the Record Length (RL) is decremented to zero. During decompression bypass, decompression, and decompre ssion output disabled oper ations, this bit is set whe n the last byt e of a record is trans ferred out the P ort A interf ace. This bit is cle ared after res et, when a new dat a transfer operation begins, or when the first byte of the next record is transferred.

MMODE =

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

0x01 0x00 EORD BCMP BPB EORPB EMPB EMPA BPA EORPA

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6.3 PORT A CONFIGURATION 0 (ACNF0)

Reserved Hardware Reset Value = 0x00 Reset Command = unchanged

6.4 PORT A CONFIGURATION 1 (ACNF1)

Read/Write Hardware Reset Value = 0x00 Reset Command = unchanged

PARITY - Parity. When set, parity checking is enabled for the ADATA[15:0] data bus. When cleared,

parity checking is disabled for the ADATA[15:0] bus.

ODD - Odd. Setting this bit along with PARITY enables odd parity checking and generation on the

ADA TA[15:0] data bus. When cleared with P ARITY se t even parity check ing and generation is enabled on the ADATA[15:0] data bus.

SLAVE - Slave. Must always be written with a one. MODE[2:0]-DMA Mode. These bits conf igure the in terface DMA mode of the Por t A Interface wit h values

as defined below.

6.5 PORT B CONFIGURATION 0 (BCNF0)

Reserved Hardware Reset Value = 0x00 Reset Command = unchanged

MMODE =

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

0x00 0x01 reserved

MMODE =

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

0x01 0x00 PARITY O DD SLAVE MODE[2:0 ] reserved

MODE[2:0] DMA TYPE

000 Reserved 001 FAS368 mode 010 43C97 ATA 011 Burst 100 Reserved 101 Reserved 110 Reserved 111 Reserved

MMODE =

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

0x00 0x01 reserved

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6.6 PORT B CONFIGURATION 1 (BCNF1)

Read/Write Hardware Reset Value = 0x00 Reset Command = unchanged

PARITY - Parity. When set, parity checking is enabled for the BDATA[15:0] data bus. When cleared,

parity checking is disabled for the BDATA[15:0] bus.

ODD - Odd. When set , odd parity checking and generation is us ed on the BDATA[15:0] data bus. When

cleared, even parity checking and generation is used on the BDATA[15:0] data bus.

MODE[1:0]-DMA Mode. These bits conf igure the inte rface DMA mode of the Port B Interface wit h values

as defined below.

6.7 IDENTIFICATION (ID0, ID1)

Read Only Hardware Reset Value = 0x3540 Reset Command = 0x3540

ID[15:0]- The bits of this registe r correspond to the identification code of the chip. This register is

accessible when CMND is not a Selection Command.

6.8 PORT A POLARITY (APOL)

Read/Write Hardware Reset Value = 0xFF Reset Command = unchanged

The bits of this register correspond to Port A Interface signals. A set bit programs the corresponding signal to be active low. A cleared bit programs the corresponding signal to be active high. This register is only accessible when CMND is Select Port A Configuration.

MMODE =

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

0x01 0x00 PARITY O DD reserved MODE[2:0] reserved

MODE[2:0] DMA TYPE

000 Reserved 001 FAS368 mode 010 43C97 ATA 011 Burst 100 Reserved 101 Reserved 110 Reserved 111 Reserved

MMODE =

0x02 0x03 ID[7:0] 0x03 0x02 ID[15:8]

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x02 0x03 ACIN reserved ACOUT AWR ARD reserved reserved

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Advanced Hardware Architectures, Inc.

6.9 PORT B POLARITY (BPOL)

Read/Write

Hardware Reset Value = 0xDF

Reset Command = unchanged

The bits of this register correspond to Port B Interface signals. A set bit programs the corresponding signal to be active low. A cleared bit programs the corresponding signal to be active high.This register is only accessible when CMND is Select Port B Configuration.

6.10 PORT A TRANSFER COUNT (ATCL0, ATCL1, ATCH0, ATCH1)

Read Only

Hardware Reset Value = 0x00000000

Reset Command = 0x00000000

Port A Transfer Count Low

Port A Transfer Count High

A TC[31:0]-Port A Transfer Count. These registers provide status information on the number of bytes

transferred for a current data transfer operation. During a compression operation, ATC is incremented as each ori ginal data byte is received by th e Port A Interface. When ATC equals the product of the Record Count and Record Length during compression, all bytes in the compression operation have been received by the AHA3540. During a decompression operation, ATC is incremented as ea ch decompr es sed dat a byte is sen t by the Por t A Inte rfac e. This register is only accessible when CMND is not a Selection Command.

In the case where onl y one byte is re quired to complet e a transfer operation (i.e. , an odd number of bytes in the transfer), the ATC is incremented by one after the byte transfers. ATC should not be used to dete rmine the decompr ession operation is complete. I nstead, use the DONE status bit and/or interrupt. Data blocks of Record Count times Record Length must be smaller t he (2

−

1) to prevent overf low of this 4 -byte T ransf er Count register. Reset on new transfer commands. Pad bytes are not counted.

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x02 0x03 BCIN reserved BCOUT BWR BRD reserved

MMODE =

0x06 0x07 A TCL[7:0] 0x07 0x06 A TCL[15:8]

MMODE =

0x04 0x05 ATCH[7:0] 0x05 0x04 ATCH[15:8]

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6.11 RECORD COUNT (RCL0, RCL1, RCH0, RCH1)

Read/Write

Hardware Reset Value = 0x00000000

Reset Command = 0x00000000

Record Count Low

Record Count High

RC[31:0]- Record Count indicates the number of records to be compressed or decompressed. Record

Count must be set to 0x00 000001 d uring Decompres sion By pass. I f th e Recor d Count must be written to durin g a compr ession oper ation, the n the Empt y at Port A (EMPA) Status bit must be set. If the Record Count must be writ te n to dur i ng a dec o mpre ssi on operation, then the Empty at Port B (EMPB) Status bit must be set.

6.12 PORT B COMPARE COUNT (BCCL0, BCCL1, BCCH0, BCCH1)

Read/Write

Hardware Reset Value = 0x00000000

Reset Command = 0x00000000

Port B Compare Count Low

Port B Compare Count High

BCC[31:0] Port B compare count register is used t o paus e the device aft er a s pecified number of byt es are

transferred at the Port B interface. Port B Compare Count is a four byte register with the two most significant bytes contained in Port B Compare Count High (BCCH), and the two least significant bytes contained in the Port B Compare Count Low register (BCCL).

MMODE =

0x06 0x07 RCL[7:0] 0x07 0x06 RCL[15:8]

MMODE =

0x04 0x05 RCH[7:0 ] 0x05 0x04 RCH[15:8]

MMODE =

0x06 0x07 BCCL[7:0] 0x07 0x06 BCCL[15:8]

MMODE =

0x04 0x05 BCCH[7:0] 0x05 0x04 BCCH[15:8]

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6.13 PORT B TRANSFER COUNT (BTCL0, BTCL1, BTCH0, BTCH1)

Read Only

Hardware Reset Value = 0x00000000

Reset Command = 0x00000000

Port B Transfer Count Low

Port B Transfer Count High

BTC[31:0] -Port B Transfer Count. These registers provide status information on the number of bytes

transferred for a current data transfer operation. During a compression operation, BTC is incremented as each compressed data byte is sent by the Port B Interface. During a decompression operati on, BTC is incr emented as each compres sed data by te is rec eived by th e Port B Interface. This register is only accessible when CMND is not a Selection Command.

In the special case where only one byte i s required to co mplete a transfer operation (i .e., an odd number of bytes in the transfer), the BTC is incremented by one after the byte transfers. BTC should not be used to determine the decompression operation is complete. Instead, use the DONE status bit and/or interrupt. Data blocks of Record Count times Record Length must be smaller than (2

−1) to prevent overflow of this 4-byte transfer count register.

Reset by a new compression mode transfer command, but not by a new decompression mode transfer. Pad bytes are not counted.

6.14 PORT A FIFO DATA ACCESS (AFIF0, AFIF1)

Read/Write

Hardware Reset Value = 0x0000

Reset Command = 0x0000

FA[15:0]- Port A FIFO Data regi ster is a tempora ry hol ding regi ster for dat a to b e writte n to or read from

the Port A interfac e FIFO. During co mpressi on bypass and compress ion opera tions, t he Port A FIFO indicates it has received the data by resetting REQF in the AFCT register. During decompression bypass, decompression, and decompression output disabled operations, data may be read from this register after the Port A FIFO re sets REQF in t he AFCT register. This register is only accessible when CMND is a Select Port A Configuration Command. This register is reset by a new transfer.

MMODE =

0x0A 0x0B BTCL[7:0] 0x0B 0x0A BTCL[15:8]

MMODE =

0x08 0x09 BTCH[7:0] 0x09 0x08 BTCH[15:8]

MMODE =

0x08 0x09 FA[7:0] 0x09 0x08 FA[15:8]

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6.15 COMPRESSED BYTES PROCESSED (CBPL0, CBPL1, CBPH0, CBPH1)

Read/Write

Hardware Reset Value = 0x00000000

Reset Command = 0x00000000

Compressed Bytes Processed Low

Compressed Byte s Processed High

CBPL[31:0] -Compressed Bytes Processed counter. Counts the total number of bytes processed by the

ALDC decoder during decompress ion and deco mpression outpu t disabled ope rations. It can be used in conjunction with the Port B Transfer Count to determine the number of compressed bytes, if any, that reside in the Port B in terface and ALDC core.

6.16 PORT A FIFO CONTROL (AFCT)

Read/Write

Hardware Reset Value = 0x00

Reset Command = 0x00

ACCF - Access FIFO. When set, access to the Port A FIFO is redirected from the Port A interface to the

microprocessor interface. This bit is cleared after reset or a new transfer.

REQF - Request to FIFO. During compre ssion bypa ss and compr ession ope rations , this bi t is set to one

requesting a write to the Port A FIFO. During decompression bypass, decompression, and decompression output dis abled ope rati ons, thi s bit is set to on e reques ting a read from t he Port A interface FIFO. This bit is cleared when th e Port A FIFO has completed the re quest or after a reset. This regist er is only acces sible when CMND is a Sele ct Port A configu ration command. Reset by a new transfer.

MMODE =

0x0A 0x0B CBPL[7:0] 0x0B 0x0A CBPL[15:8]

MMODE =

0x08 0x09 CBPH[7:0] 0x09 0x08 CBPH[15:8]

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x0A 0x0B reserved ACCF REQF

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Advanced Hardware Architectures, Inc.

6.17 ERROR STATUS (ERRS)

Read Only

Hardware Reset Value = 0x00

Reset Command = 0x00

The Err or Status register provides error status bits t o the microprocessor. These bits are set regardless of the error mask settings. Reset by a new compression mode transf er.

APERR - Port A Interface Parity Error. This bit is set when a parity error is detected during a transfer into

ADATA[15:0] and the Port A Interface Parity bit is set. It is cleared when a new compression mode transfer begins or when a reset occurs.

BPERR - Port B Interface Parity Error . This bit is se t when a parit y error is det ected durin g a transfer into

BDATA[15:0] and the Port B Interface Parity bit is set. It is cleared when a new compression mode transfer begins or when a reset occurs.

BTCO - Port B Transfer Count Overflow Error. This bit is set when a carry out is detected on the Port

B Tr ansfe r Count r egist er. It is cleared when a new compressi on mode t ransf er begi ns or whe n

a reset occurs.

ATCO - Port A Transfer Count Overflow Error. This bit is set when a carry out is detected on the Port

A Tr ansfe r Count r egist er. It is cleared when a new compressi on mode t ransf er begi ns or whe n

a reset occurs.

ADCC - ALDC Decoder Control Code Error. This bit is set during decompression when an invalid

control code is detected in the compressed data stream. It is cleared when a new compression mode transfer begins or when a reset occurs.

6.18 INTERRUPT STATUS 0 (INTS0)

Read Only

Hardware Reset Value = 0x00

Reset Command = 0x00

Interrupt Status bits are reset by writing a zero. This is referred to as an interrupt reset. Writing a one has no effect. See Appendix A.1 for differences between AHA3540 and IBM ALDC1-20S-LP.

DONE - Done Interrupt. This bit is set when data transf er has completed on the Port B I nterface during

compression and when data transfer has completed on the Port A Interface during decompression. It is cleared when a new compression mode transfer begins, when a reset occurs, or by an interru pt reset.

PAUSED - Paused Interrupt. This bit is set by a Pause command, or an unmasked data transfer interr upt. It is

cleared when a new compression mode tra nsfer begins, when a reset occurs, or by an int errupt reset.

ODT - Output Disabled T er minated. This bit i s set when the end of record of the la st suppressed re cord

is processed by the ALDC decoder. This bit is cleared after reset, after an interrupt reset is written, or when a new compression mode transfer begins.

ERROR - Error Interrupt. This bit is set when an unmasked error occurs. It is cleared when a new

compression mode transfer begins or when a reset occurs. The Error Status register is used to determine the cause of the error.

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x0C 0x0D reserved APERR BPERR reserved BTCO A TCO ADCC reserved

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x0E 0x0F DONE PAUSED ODT reserved ERROR

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6.19 INTERRUPT STATUS 1 (INTS1)

Read/Write

Hardware Reset Value = 0x00

Reset Command = 0x00

The Interrupt Status bits BPB, EORPB, BPA and EORP A will only get set after the last word is transferred if the fol lowing Interrupt Mask bits are set: BPBM, EORPBM, BPAM and EORP AM. If these mask bits are set, the ALDC core provides end of transfer information, but no end of record information. See Appendix A.1 for differences between AHA3540 and IBM ALDC1-20S-LP.

EORD - End of Record at Decoder, This bit is set when the ALDC decoder detects an End of Record

control code in the compressed data stream or when an ALDC Decoder Control Code Error occurs. This bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins.

BCMP - Port B Interface Compare. Thi s bit is set whe n Port B T rans fer Count is gr eater than or equa l to

Port B Interface Compare Count. This bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins.

BPB - One Byte at Port B. During com pression bypass a nd compression opera tions, this bit is set at the

same time th e End of Record at Port B (STAT1[4] and INTS1[4]) is set if only one byte at the Port B Interface is part of the current record. During decompression bypass operation, this bit is set during the las t da ta tra nsf er of the record at the Port B Interface if only one byte be longs to the current record. Thi s bit is cleared after reset, when an interru pt reset is written, or when a new compression mode transfer begins.

EORPB - End of Record at Por t B. During compression bypass and c ompression ope rations, t his bit i s set

when the last byte of a compressed record is transferred out of the Po rt B interface. During decompression bypass oper ations, this bit is set when the last by te of a record is tr ansferred into the Port B interface. Thi s bit i s clea red aft er re set, when a n in terru pt res et is wr itte n, or when a new compression mode transfer begins.

BP A - One Byte at Port A. During compression bypass and compression operations, this bit is set

during the last dat a trans fer of the r ecord a t th e Port A inter face i f only one byte bel ongs to t he current record. During decompression bypass, decompression, and decompression output disabled modes, this bit is set the same time the End of Record at Port A interface bit (ST AT1[0] and INTS1[0]) is set if only one byte at the Port A interface is part of the current record. This bit is cleared after reset, when an interr upt reset is written, or when a new compression mode transfer begins.

EORP A - End of Record at Por t A. During compression by pass and compression operations, this bi t is set

each time the Record Length (RL) is decremented to zero. During decompression bypass, decompression, and decompre ssion output disabled oper ations, this bit is set whe n the last byt e of a record is transferred out the Port A interface. This bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begi ns.

MMODE =

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

0x0F 0x0E EORD BCMP BPB EORPB reserved BPA EORPA

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6.20 COMMAND (CMND)

Read/Write

Hardware Reset Value = 0x0000

Reset Command = 0xA000

Unspecified opcodes are reserved and may not be writt en. CMND[15:0]-Command.This register provides for operation as described in the following table.

MMODE =

0x10 0x11 CMND[7:0] 0x11 0x10 CMND[15:8]

CMND[15:0] ACTION

SELECTION COMMANDS

0xC100

Select Port A Configuration . The Port A Configura tion and Port A Polarity regist ers are enabled for reads and writes.

0xC200

Select Port B Configuration . The Port B Configuration an d Port B Polarity registers are enabled for reads and writes.

TRANSFER COMMANDS

(Described in Sections 2.0 and 3.0)

0x5000-0x500F

Start Compression Bypass.

– CMND[3:2] determines the number of pad bytes to expect at the Port A interface. – CMND[1:0] determines the number of pad bytes to insert at the Port B interface.

0x5800-0x580F

Start Compression.

– CMND[3:2] determines the number of pad bytes to expect at the Port A interface. – CMND[1:0] determines the number of pad bytes to insert at the Port B interface.

0x6000-0x600F

Start Decompression Bypass.

– CMND[3:2] determines the number of pad bytes to expect a t the Port B interface. – CMND[1:0] determines the number of pad bytes to insert at the Port A interface.

0x6800-0x680F

Start Decompression.

– CMND[3:2] determines the number of pad bytes to expect a t the Port B interface. – CMND[1:0] determines the number of pad bytes to insert at the Port A interface.

0x6C00-0x6C0F

Start Decompression Output Disabled.

– CMND[3:2] determines the number of pad bytes to expect a t the Port B interface. – CMND[1:0] determines the number of pad bytes to insert at the Port A interface.

CONTROL COMMANDS

0x4200

Pause. When a data transfer ope ration i s in progre ss, any curr ent operat ion steps a re completed and the Port A I nte rface and Port B Interfa ce data busses are pla ced int o a high impedance stat e. The Paused In terrupt and P aused St atus bits ar e then set. All data currently being processed by the data transfer operation is preserved.

0x4400-0x440F

Resume. A previously paused data transfer operation resumes processing. The Paused Interrupt and Paused status bits are cleared and the Busy status bit is set.

– RESUME[3:2] determines the number of pad bytes to expect at the Port B interface. – RESUME[1:0] determines the number of pad bytes to insert at the Port A interface.

0xA000

Software Reset. The Port A Configuration, Port B Configuration, Identification, Port A Polarity, and Port B Polarity registers are not affected by this command. All other registers are reset, current operations are cancelled, and the history buffer is cleared. T welve clocks are re quired to comple te the reset operation. Suspe nd writing to any registers during this time.

0xA400 Reset the history buffe r. Only use between compression operations.

MISCELLANEOUS COMMANDS

0x0000 NOP, no operation is performed.

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6.21 RECORD LENGTH (RLL0, RLL1, RLH0, RLH1)

Read/Write

Hardware Reset Value = 0x00000000

Reset Command = 0x00000000

Record Length Low

Record Length High

RL[31:0]- The Record Length register indicates the number of Bytes contai ned in each uncompress ed data

record for compres sion bypass and c ompression opera tions. This regi ster decrement s with each Byte transferred into Port A. When the Record Length reaches zero, the Port Interface bits STA T1[ 8] a nd I N TS1[8 ] ar e s et. During decompression bypass operations, the Reco rd Le ngt h register indicates the total number of bytes to transfer. Record Length is not used for decompression and decompression output disabled operations.

When processing mult iple records (Record Co unt is g reater than one) , the Reco rd Length must be greater than 0x22. If Record Length = 0x 00000000 when a ne w transfer or r esume command are written, the counter rolls over to 0x10000000. When Record Count is greater than 1, then Record Length must be greater than 0x22. Pad bytes are not counted.

6.22 DATA DISABLED COUNT (DDCL0, DDCL1, DDCH0, DDCH1)

Read/Write

Hardware Reset Value = 0x00000000

Reset Command = 0x00000000

Data Disabled Count Low

Data Disabled Count High

DDC[31:0]- Data Disabled Count.The Data Disabled Count register provides the microprocessor control of

the number of records skipped dur ing a S tart Decompres sion Output Dis abled opera tion. If the Data Disabled Count is s et to z ero dur ing a Start Decompression Output Disabled opera tion or the DDC is greater than the Record Count during a Start Decompression Output Disabled operation, then the Port A Interface output is disabled for the entire transfer.

MMODE =

0x16 0x17 RLL[7:0] 0x17 0x16 RLL[15:8]

MMODE =

0x14 0x15 RLH[7:0] 0x15 0x14 RLH[15:8]

MMODE =

0x1A 0x1B DDCL[7:0] 0x1B 0x1A DDCL[15:8]

MMODE =

0x18 0x19 DDCH[7:0] 0x19 0x18 DDCH[15:8]

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6.23 ERROR MASK (EMSK)

Read/Write

Hardware Reset Value = 0x00

Reset Command = 0x00

The Error Mask reg ister provides error report ing configurat ion to the micro processor. If an unmasked error status bit is active, ANYERR status and ERROR interrupts are set. Errors are masked by setting the appropri ate mask bit to one.

APERRM -Port A Interface Parity Error Mask. BPERRM -Port B Interface Parity Error Mask. BTCOM - Port B Transfer Count Over flow Error Mask. ATCOM - Port A Transfer Count O verflow Error Mask. ADCCM - ALDC Decoder Control Code Error Mask.

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x1C 0x1D reserved APERRM BPERRM reserved BTCOM ATCOM ADCCM reserved

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6.24 INTERRUPT MASK 0 (IMSK0)

Read/Write

Hardware Reset Value = 0x00

Reset Command = 0x00

The Interrupt Ma sk 0 register masks the individual interrupts all owing the user t o control which one s may cause the Interrupt signal pin (IREQN) to asse rt. For exampl e, if DONEM and PAUSEDM are set with ERRORM cleared, only an ERROR interrupt will cause the Interrupt signal pin t o assert. I nterrupts are masked by setting the appropriate mask bit t o one.

DONEM - Done Interrupt Mask. PAUSEDM -Paused Interrupt Mask. ODTM - Output Disabled Terminated Mask. ERRORM -Error In terrupt Mask.

6.25 INTERRUPT MASK 1 (IMSK1)

Read/Write

Hardware Reset Value = 0x00

Reset Command = 0x00

The Interrupt Mask 1 register masks the indi vidual interr upts allowing the user to control which ones may cause the Interrup t signal pin ( IREQN) to assert. I nterrupts a re masked by setti ng the appropr iate mask bit to one.

EORDM - End of Record at Decoder Interrupt Mask. BCMPM - Port B Interface Compare Interrupt Mask. BPBM - One Byte at Port B Interrupt Mask. EORPBM -End of Record at Port B Interrupt Mask. BP AM - One Byt e at Port A Interru pt Mask. EORP AM -End of Record at Port A Interrupt Mask.

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x1E 0x1F DONEM PAUSEDM ODTM reserved ERRORM

MMODE =

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

0x1F 0x1E EORDM BCMPM BPBM EORPBM reserved BP AM EORPAM

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7.0 SIGNAL DESCRIPTIONS

This section contains descriptions for all the pins. Each signal has a type code associated with it. The type codes are described in the following table.

7.1 MICROPROCESSOR INTERFACE

TYPE CODE DESCRIPTION

I Input only pin

O Output only pin

I/O Input/Output pin

MICROPROCESSOR INTERFACE

SIGNAL TYPE DESCRIPTION

DEFAULT

AFTER RESET

MDATA[7:0] I/O Microprocessor data bus Hi-Z MCIN[0] I

Microprocessor interface control pin [0]. If MMODE is high this pin is CSN. If MMODE is low this pin is READN.

Input

MCIN[1] I

Microprocessor interface control pin [1]. If MMODE is high this pin is RWN. If MMODE is low this pin is WRITEN.

Input

WAITN O

Microprocessor output signal. WAITN is driven during CSN and then goes to tristate with a resistive pullup.

High

ADDR[4:0] I

Microprocessor Interface address bus, used to select internal registers.

Input

MMODE I Microprocessor Interface mode selector pin. Input RESETN I Hardware reset signal. Input IREQN O Interrupt request output signal. High CLOCK I Clock input Input

+TIE I These pins must be tied high in the system. Input

−TIE I These pins must be tied low in the system. Input

Page 24 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

7.2 PORT A INTERFACE

Note: Refer to Section 5.0 Port A and Port B Configuration for configuration of Port A control signals.

7.3 PORT B INTERFACE

Note: Refer to Section 5.0 Port A and Port B Configuration for configuration of Port B control signals.

PORT A INTERFACE

SIGNAL TYPE DESCRIPTION

DEFAULT

AFTER RESET

ACIN I

Port A Interface Control Input signal. This signal functions as DREQA. Polarity is programmed by APOL[7].

Input

ACOUT O

Port A Interface Control Outp ut signa l. This s ignal f uncti ons as DACKA. Polarity is programmed by APOL[5].

High

AWR O

Port A Interface Control Output signal. Polarity is controlled by APOL[4].

High

ARD O

Port A Interface Control Output signal. Polarity is controlled by APOL[3].

High

APARITY[1:0] I/O

When enabled, this pin checks parity on input and generates parity for output for the AD bus. APARITY[0] is used for AD[7:0], and APARITY[1] is used for AD[15:8]. Setting ACNF[15]=1 enables AP ARIT Y . Wh en disabled these pins may be tied high, tied low or not connected.

Hi-Z

ADATA[15:0] I/O Port A Interface Data bus. Hi-Z

PORT B INTERFACE

SIGNAL TYPE DESCRIPTION

DEFAULT

AFTER RESET

BCIN I

Port B Interface Control Input signal. This signal functions as DACKB. Polarity is programmed by BPOL[7].

Input

BCOUT O

Port B Interface Contr ol Output signal. This signal functions as DREQB. Polarity is programmed by BPOL[5].

Low

BWR I

Port B Interface Control Input signal. Polarity is controlled by BPOL[4].

Input

BRD I

Port B Interface Control Input signal. Polarity is controlled by BPOL[3].

Input

BPARITY[1:0] I/O

When enabled, this pin checks parity on input and generates parity for output for the BD bus. BPARITY[0] is used fo r BD[7:0], and BPARITY[1] is used for BD[15:8]. Setting BCNF[15]=1 enables BPARITY. When disabled these pins may be tied high, tied low or not connected.

Hi-Z

BDATA[15:0] I/O Port B Interface Data bus. Hi-Z

PS3540-1100 Page 25 of 47

Advanced Hardware Architectures, Inc.

8.0 PINOUT

PIN TQFP SIGNAL PIN TQFP SIGNAL

99 No Connect 49 ACIN

100 VDD 50 VDD

1 GND 51 GND 2 BDATA[7] 52 ADATA[7] 3 BDATA[6] 53 ADATA[6] 4BDATA[5] 54+TIE 5 BDATA[4] 55 ADATA[5] 6 BDATA[3] 56 ADATA[4] 7 BDATA[2] 57 ADATA[3] 8 VDD 58 VDD

9 GND 59 GND 10 BDATA[1] 60 ADATA[2] 11 No Connect 61 ARD 12 No Connect 62 No Connect 13 BDATA[0] 63 ADATA[1] 14 BDATA[15] 64 ADATA[0] 15 BDATA[14] 65 ADATA[15] 16 BDATA[13] 66 ADATA[14] 17 BDATA[12] 67 ADATA[13] 18 VDD 68 VDD 19 GND 69 GND 20 BDATA[11] 70 ADATA[12] 21 BDATA[10] 71 ADATA[11] 22 BDATA[9] 72 ADATA[10] 23 BDATA[8] 73 ADATA[9] 24 BPARITY[0] 74 ADATA[8] 25 BPARITY[1] 75 APARITY[0] 26 VDD 76 VDD 27 GND 77 GND 28 No Connect 78 APARITY[1] 29 IREQN 79 MDATA[7] 30 No Connect 80 +TIE 31 WAITN 81 VDD 32 BRD 82 MDATA[6] 33 BWR 83 MDATA[5] 34 BCOUT 84 MDATA[4] 35 RESETN 85 MDATA[3] 36 +TIE 86 ACOUT 37 CLK 87 AWR 38 GND 88 GND 39 VDD 89 VDD 40 ADDR[4] 90 MCIN[0] 41 ADDR[3] 91 MCIN[1] 42 No Connect 92 MDATA[2] 43 BCIN 93 MDATA[1] 44 −TIE 94 MDATA[0] 45 +TIE 95 No Connect 46 ADDR[2] 96 +TIE 47 ADDR[1] 97 +TIE 48 ADDR[0] 98 MMODE

Page 26 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 4: TQFP Pinout

Notes:

1) See Appendi x A.2 for differences in pinout requirements betw een the AHA354 0 and IBM ALDC1- 20S-LP.

2) IBM is a registered tradem ark of IBM

75747372717069686766656463626160595857565554535251

APARITY[0]

ADATA[8]

ADATA[9]

ADATA[10]

ADATA[11]

ADATA[12]

GND

VDD

ADATA[13]

ADATA[14]

ADATA[15]

ADATA[0]

ADATA[1]NCARD

ADATA[2]

GND

VDD

ADATA[3]

ADATA[4]

ADATA[5]

+TIE

ADATA[6]

ADATA[7]

GND

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

VDD ACIN ADDR[0] ADDR[1] ADDR[2] +TIE –TIE BCIN NC ADDR[3] ADDR[4] VDD GND CLK +TIE RESETN BCOUT BWR BRD

WAITN 30 29 28 27 26

IREQN

GND

VDD

12345678910111213141516171819202122232425

GND

BDATA[7]

BDATA[6]

BDATA[5]

BDATA[4]

BDATA[3]

BDATA[2]

VDD

GND

BDATA[1]

BDATA[0]

BDATA[15]

BDATA[14]

BDATA[13]

BDATA[12]

VDD

GND

BDATA[11]

BDATA[10]

BDATA[9]

BDATA[8]

BPARITY[0]

BPARITY[1]

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

VDD

GND

APARITY[1]

MDATA[7]

+TIE

VDD MDATA[6] MDATA[5] MDATA[4] MDATA[3]

ACOUT

AWR

GND

VDD

MCIN[0]

MCIN[1] MDATA[2] MDATA[1] MDATA[0]

96 97 98 99 100

+TIE +TIE

MMODE

VDD

NC = No Connect

AHA3540A-040 PTC

PS3540-1100 Page 27 of 47

Advanced Hardware Architectures, Inc.

9.0 ELECTRICAL SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

9.2 RECOMMENDED OPERATING CONDITIONS

9.3 DC SPECIFICATIONS

Notes:

1) Test Conditions: worst case compression current; 0mA loads.

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Vdd Power supply voltage 3.6 Volts

Vpin Voltage applied to any signal pin 0 5.5 Volts

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Vdd Power supply voltage 3.0 3.6 Volts

Ta Ambient temperature 0 +70 °C Tc Case temperature +95 °C

DC SPECIFICATIONS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES

Vil Input low voltage 0 0.8 Volts Vih Input high voltage 2.0 3.3 5.5 Volts Vol Output low voltage Iol = 4.0 mAmps 0 0 0.4 Volts

Voh Output high voltage I oh = -0.4 mAmps 2.4 3.3 Vdd Volts

Iil Input low current Vin = 0 Volts 5 µAmps

Iih Input high current Vin = Vdd Volts 5 µAmps

Iozl Output tristate low current Vout = 0 Volts 20 µAmps

Iozh Output tristate high current Vout = Vdd Volts 20 µAmps

IddA Active Idd current Vdd = 3.6 Volts TBD mAmps 1

Idd Supply current (static) TBD mAmps

Iol Low level output current TBD mAmps Ioh High level output current TBD mAmps Cin Input capacitance 3 pF

Cout Output capacitance 6 pF

Page 28 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

10.0 TIMING SPECIFICATIONS

Notes:

1) All AC timings are referenced to 1.4 Volts.

Figure 5: Clock Timing

Table 2: Clock Timing

Notes:

1) All AC Timings are referenced to 1.4 Volts

2) Rise and fall times are between0.1 Vdd and 0.9 Vdd.

Figure 6: Reset Timing

Table 3: Reset Timing

NUMBER PARAMETER MIN MAX UNITS NOTES

1 CLK period 12.5 ns 1 2 CLK low pulsewidth 5 ns 1 3 CLK high pulsewidth 5 ns 1 4 CLK rise time 3 ns 2 5 CLK fall time 3 ns 2

NUMBER PARAMETER MIN MAX UNITS NOTES

1 RESETN pulsewidth 5 clocks 2

RESETN delay to CSN, READN or WRITEN

3clocks

4 5

3 2

CLOCK

RESETN

MCIN[0] or MCIN[1]

(CSN, READN or WRITEN)

PS3540-1100 Page 29 of 47

Advanced Hardware Architectures, Inc.

Figure 7: Processor Read Timing, MMODE = 1

Table 4: Processor Read Timing, MMODE = 1

Note:

1) When WAITN causes CSN to deassert, ignore number 3, otherwise ignore number 6.

2) The device latches ADDR on the falling edge of CSN. The user should latch MDATA on the rising edge of CSN.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 RWN setup to CSN asserted 4 ns 2 RWN hold from CSN asserted 4 ns 3 CSN pulsewidth 3 clocks 1 4 Delay from CSN deasserted until next CSN 1 clock+5 ns 5 CSN asserted to WAITN asserted 18 ns 6 CSN hold from WAITN deasserted 0 ns 1 7 WAITN deasserted from CSN asserted 2 clocks 3 clocks+18 ns 8 ADDR setup to CSN asserted 2 ns 2 9 ADDR hold from CSN asserted 6 ns 2

10 MDATA valid from CSN asserted 2 clocks+15 ns

11 MDATA tristate from CSN deasserted 3 20 ns 12 MDATA hold from CSN deasserted 3 20 ns 13 CSN asserted to MDATA driven 1 clock 14 CSN deasserted to WAITN tristate 10 ns

MCIN[1] (RWN)

MCIN[0] (CSN)

WAITN

MDATA

ADDR

Valid

3 4

5 6

8 9

Tristate Tristate

Page 30 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 8: Processor Write Timing, MMODE = 1

Table 5: Processor Write Timing, MMODE = 1

Notes:

1) When WAITN causes CSN to deassert, ignore number 3, otherwise ignore number 6.

2) When a read to a r egister immediately follows a write to that same r egister or to the command regis ter, CSN must deassert for a minimum of 3 clocks after the write.

3) The device latches ADDR on the falling edge of CSN.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 RWN setup to CSN asserted 4 ns 2 RWN hold from CSN asserted 4 ns 3 CSN pulsewidth 2 clocks 1 4 Delay from CSN deasserted until next CSN 1 clock+5 ns 2 5 CSN asserted to WAITN asserted 18 ns 6 CSN hold from WAITN deasserted 0 ns 1 7 WAITN deasserted from CSN asserted 1 clock 2 clocks+18 ns 8 ADDR setup to CSN asserted 2 ns 3 9 ADDR hold from CSN asserted 6 ns 3

10 MDATA valid before CSN deasserted 4 ns

11 MDATA hold from CSN deasserted 4 ns

12 CSN deasserted to WAITN tristate 10 ns

MCIN[1] (RWN)

MCIN[0] (CSN)

WAITN

MDATA

ADDR

Valid

3 4

5 6

8 9

PS3540-1100 Page 31 of 47

Advanced Hardware Architectures, Inc.

Figure 9: Processor Read Timing, MMODE = 0

Table 6: Processor Read Timing, MMODE = 0

Notes:

1) When WAITN causes READN to deassert ignore number 1, otherwise ignore number 4.

2) The device latches ADDR on the falling edge of READN. The user should latch MDATA on the rising edge of READN.

3) WRITEN must be deasserted during register reads.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 READN pulsewidth 3 clocks 1 2

Delay from READN deasserted until next READN

2clocks

3 READN asserted to WAITN asserted 18 ns 4 READN hold from WAITN deasserted 0 ns 1 5 WAITN deasserted from READN asserted 2 clocks 3 clocks+18 ns 6 ADDR setup to READN asserted 2 ns 2 7 ADDR hold from READN asserted 6 ns 2 8 MDATA valid from READN asserted 2 clocks+15 ns 9 MDATA tristate from READN deasserted 20 ns

10 MDATA hold from READN deasserted 3 ns

11 MDATA asserted from READN asserted 1 clock

12 READN deasserted to WAITN tristate 10 ns

MCIN[0] (READN)

WAITN

ADDR

MDATA

Valid

Tristate Tristate

(Note 3)

Page 32 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 10: Processor Write Timing, MMODE = 0

Table 7: Processor Write Timing, MMODE = 0

Notes:

1) When WAITN causes WRITEN to deassert ignore number 1, otherwise ignore number 4.

2) The device latches ADDR on the falling edge of WRITEN.

3) READN must be deasserted during register writes.

NUMBER PARAMETER MIN MAX UNITS NOTES

1 WRITEN pulsewidth 2 clocks 1 2

Delay from WRITEN deasserted until next WRITEN

3clocks

3 WRITEN asserted to WAITN asserted 18 ns 4 WRITEN hold from WAITN deasserted 0 ns 1 5 WAITN deasserted from WRITEN asserted 1 clock 2 clocks+18 ns 6 ADDR setup to WRITEN asserted 2 ns 2 7 ADDR hold from WRITEN asserted 6 ns 2 8 MDATA valid before WRITEN deasserted 4 ns 9 MDATA hold from WRITEN d easserted 4 ns

10 WRITEN deasserted to WAITN tristate 10 ns

MCIN[1] (WRITEN)

WAITN

ADDR

MDATA

Valid

(Note 3)

PS3540-1100 Page 33 of 47

Advanced Hardware Architectures, Inc.

Figure 11: Port A Burst Write Timing, Slave Mode

Table 8: Port A Burst Write Timing, Slave Mode

Notes:

1) These timings are valid for inverted signal polarities.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 40 MHz.

NUMBER PARAMETER MIN MAX NOTES

Last DACKA asserted to DREQA deasserted, end of burst

0 ns 2 clocks−10 ns 1, 2

DREQA asserted to first DACKA asserted, start of burst

1 clock 1, 2

3 DACKA pulsewidth 2 clocks−8 ns 2 clocks+8 ns 1, 2 4 DACKA deasserted to DACKA asserted 2 clocks−8 ns 1, 2

Last DACKA deasserted to next DREQA asserted, next burst

2 clocks 1, 2

6 ADATA (output) driven from DACKA asserted 1 clock−5 ns 1, 2 7 ADATA (output) hold from DACKA deasserted 1 clock−10 ns 1 clock+5 ns 1, 2 8 ADATA (out put) val id from DACKA asser ted 1 clock+10 ns 1, 2

ACIN (DREQA input)

ACOUT (DACKA output)

AWR (output)

ADATA (output)

Tristate Tristate

Valid Valid Valid

Page 34 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 12: Port A Burst Read Timing, Slave Mode

Table 9: Port A Burst Read Timing, Slave Mode

Notes:

1) These timings are valid for inverted signal polarities.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 40 MHz.

NUMBER PARAMETER MIN MAX NOTES

Last DACKA asserted to DREQA deasserted, end of burst

0 ns 1 clock+15 ns 1, 2

DREQA asserted to first DACKA asserted, start of burst

1 clock 1, 2

3 DACKA pulsewidth 2 clocks−8 ns 2 clocks+8 ns 1, 2 4 DACKA deasserted to DACKA asserted 2 clocks−8 ns 1, 2

Last DACKA deasserted to next DREQA asserted, n ext burst

2 clocks 1, 2

6 ADATA (input) valid after DACKA asserted 2 clocks−18 ns 1, 2 7 ADATA (inp ut) hold from DACKA deasserte d 0 1, 2

ACIN (DREQA input)

ACOUT (DACKA output)

ARD (output)

ADATA (input)

Valid Valid Valid

Tristate Tristate

PS3540-1100 Page 35 of 47

Advanced Hardware Architectures, Inc.

Figure 13: Port B Burst Read Timing, Master Mode

Table 10: Port B Burst Read Timing, Master Mode

Notes:

1) These timings are valid for inverted signal polarities.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 40 MHz.

NUMBER PARAMETER MIN MAX NOTES

Last DACKB asserted to DREQB deasserted, end of burst

1 clock+15ns 1, 2

DREQB asserted to first DACKB asserted, start of burst

1 clock 1, 2

3 DACKB pulsewidth 2 clocks 1, 2 4 DACKB deasserted to DACKB asserted 2 clocks 1, 2

Last DACKB deasserted to next DREQB asserted, next burst

2 clocks 1, 2

6 BDATA (output) driven from DACKB asserted 2 ns 1, 2 7 BDATA (output) hold from DACKB deassert ed 2 ns 23 ns 1, 2 8 DACKB cycle time 4 clocks 1, 2 9 BDATA (output) val id f rom DACKB asser ted 23 ns 1, 2

BCOUT (DREQB output)

BCIN (DACKB input)

BDATA (read, output)

Valid

Tristate Tristate

4 8

Valid Valid

Page 36 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 14: Port B Burst Write Timing, Master Mode

Table 11: Port B Burst Write Timing, Master Mode

Notes:

1) These timings are valid for inverted signal polarities.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 40 MHz.

NUMBER PARAMETER MIN MAX NOTES

Last DACKB asserted to DREQB deasserted, end of burst

1 clock+15ns 1, 2

DREQB asserted to first DACKB asserted, start of burst

1 clock 1

3 DACKB pulsewidth 2 clocks 1 4 DACKB deasserted to DACKB asserted 2 clocks 1

Last DACKB deasserted to next DREQB asserted, next burst

2 clocks 1

6 BDATA (input) valid before DACKB deasserted 4 ns 1 7 BDATA (input) hol d from DACKB deasserte d 8 ns 1 8 DACKB cycle time 4 clocks 1

BCOUT (DREQB output)

BCIN (DACKB input)

BDATA (wri te, input)

Valid Valid Valid

Tristate Tristate

4 8

PS3540-1100 Page 37 of 47

Advanced Hardware Architectures, Inc.

Figure 15: Port A Write Timing, FAS368 Slave Mode

Table 12: Port A Write Timing, FAS368 Slave Mode

Notes:

1) The unit clock refers to the clock input. For this interface the maximum clock frequency is 80 MHz.

NUMBER PARAMETER MIN MAX NOTES

1 DREQA asserted to DACKA asserted 2 clocks 2 2 DACKA deasserted to DREQA asserted 2 ns 3 AWR asserted to DREQA deasserted 12 ns 2 4 DACKA deasserted to DACKA asserted 4 clocks−5 ns 2 5 AWR asserted to AWR asserted 4 clocks−4 ns 2 6 DACKA asserted to AWR asserted 4 clocks−5 ns 2 7 AWR asserted pulsewidth 2 clocks−2 ns 2 8 AWR deasserted pulsewidth 2 clocks−2 ns 2 9 AWR deasserted to DACKA deasserted 2 clocks−2 ns 2

10 AWR asserted to ADATA write valid 10 ns 11 AWR deasserted to ADATA write invalid 5 ns 12 DACKA deasserted to ADATA write tristate 15 ns

AWR

ADATA

Tristate Tristate

(output)

(write, output)

6 7 8

ACIN

(DREQA input)

ACOUT

(DACKA output)

Page 38 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 16: Port A Read Timing, FAS368 Slave Mode

Table 13: Port A Read Timing, FAS368 Slave Mode

Notes:

1) The unit clock refers to the clock input. For this interface the maximum clock frequency is 80 MHz.

NUMBER PARAMETER MIN MAX NOTES

1 DREQA asserted to DACKA asserted 2 clocks 2 2 DACKA deasserted to DREQA asserted 2 ns 3 ARD asserted to DREQA deasserted 12 ns 2 4 DACKA deasserted to DACKA asserted 4 clocks−5 ns 2 5 ARD asserted to ARD asserted 4 clocks−4 ns 2 6 DACKA asserted to ARD asserted 4 clocks−5 ns 2 7 ARD asserted pulsewidth 2 clocks−2 ns 2 8 ARD deasserted pulsewidth 2 clocks−2 ns 2 9 ARDR deasserted to DACKA deasserted 2 clocks−2 ns 2

10 DACKA asserted to ADATA read driven 2 ns 11 ADATA read setup to ARD deasserted 10 ns 12 ADATA read hold from ARD deasserted 5 ns

ARD

ADATA

(outputs)

(read, input)

Tristate Tristate

6 7 8

11 12

ACIN

(DREQA input)

ACOUT

(DACKA output)

PS3540-1100 Page 39 of 47

Advanced Hardware Architectures, Inc.

Figure 17: Port B Read Timing, FAS368 Master Mode

Table 14: Port B Read Timing, FAS368 Master Mode

Notes:

1) After DREQx becomes inactive, additional BRD strobes are ignored and no more transfers occur into or out of the port regardless of DACKx operation.

2) Timing 9 plus Timing 7 must be greater than Timing 5.

NUMBER PARAMETER MIN MAX NOTES

1 DREQB asserted to DACKB asserted 0 2 DACKB deasserted to DREQB asserted 2 ns 3 BRD asserted to DREQB deasserted 12 ns 1 4 DACKB deasserted to DACKB asserted 40 ns 5 BRD asserted to BRD asserted 40 ns 6 DACKB asserted to BWR asserted 40 ns 7 BRD asserted pulsewidth 15 ns 8 BRD deasserted pulsewidth 15 ns

9 BRD deasserted to DACKB deasserted 15 ns 2 10 BRD asserted to BDATA write valid 10 ns 11 BDATA read hold from BRD deasserted 5 ns 12 DACKB deasserted to BDATA read tristate 15 ns

BRD

BDATA

Tristate Tristate

(input)

(read, output)

6 7 8

BCOUT

(DREQB output)

BCIN

(DACKB input)

Page 40 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 18: Port B Write Timing, FAS368 Master Mode

Table 15: Port B Write Timing, FA S368 Master Mode

Notes:

1) After DREQx becomes inactive, additional BWR strobes are ignored and no more transfers occur into or out of the port regardless of DACKx operation.

2) Timing 9 plus Timing 7 must be greater than Timing 5.

NUMBER PARAMETER MIN MAX NOTES

1 DREQB asserted to DACKB asserted 0 2 DACKB deasserted to DREQB asserted 20 ns 3 BWR asserted to DREQB deasserted 12 ns 1 4 DACKB deasserted to DACKB asserted 40 ns 5 BWR asserted to BWR asserted 40 ns 6 DACKB asserted to BWR asserted 40 ns 7 BWR asserted pulsewidth 15 ns 8 BWR deasserted puls ewi dth 15 ns

9 BWR deasserted to DACKB deasserted 15 ns 2 10 DACKB asserted to BDATA write driven 2 ns 11 BDATA write setup to BWR deasserted 10 ns 12 BDATA write hold from BWR deasserted 2 ns

BWR

BDATA

(input)

(write, input)

Tristate Tristate

6 7 8

11 12

BCOUT

(DREQB output)

BCIN

(DACKB input)

PS3540-1100 Page 41 of 47

Advanced Hardware Architectures, Inc.

Figure 19: Port A Write Timing, 43C97 Slave Mode

Table 16: Port A Write Timing, 43C97 Slave Mode

Notes:

1) In 43C97 AT A mode, one more transfer can occur after DREQx is deasserted. In other wor ds , one more transfer controlled by DACKx is allowed after DREQx deasserts.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 80 MHz.

NUMBER PARAMETER MIN MAX NOTES

1 DREQA asserted to DACKA asserted 2 clocks 2 2 DACKA deasserted to DREQA asserted 2 clocks−5 ns 3 ARD or AWR asserted to DREQA deasserted 2 clocks+5 ns 1 4 DACKA deasserted to DACKA asserted 2 clocks−5 ns 2 5 ARD or AWR asserted to ARD or AWR asserted 4 clocks−4 ns 2 6 DACKA asserted to ARD or AWR asserted 1 clock−5 ns 2 7 ARD or AWR asserted pulsewidth 2 clocks−2 ns 2 8 ARD or AWR deasserted pulsewidth 2 clocks−2 ns 2 9 ARD or AWR deasserted to DACKA deasserted 1 clock−5 ns 2

10 AWR asserted to ADATA write valid 10 ns 11 AWR deasserted to ADATA write invalid 5 ns 12 DACKA deasserted to ADATA write tristate 10 ns

AWR

ADATA

Tristate Tristate

(output)

(write, output)

6 7 8

ACIN

(DREQA input)

ACOUT

(DACKA output)

Page 42 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 20: Port A Read Timing, 43C97 Slave Mode

Table 17: Port A Read Timing, 43C97 Slave Mode

Notes:

1) In 43C97 AT A mode, one more transfer can occur after DREQx is deasserted. In other wor ds , one more transfer controlled by DACKx is allowed after DREQx deasserts.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 80 MHz.

NUMBER PARAMETER MIN MAX NOTES

1 DREQA asserted to DACKA asserted 2 clocks 2 2 DACKA deasserted to DREQA asserted 2 clocks−5 ns 2 3 ARD asserted to DREQA deasserted 2 clocks+5ns 1, 2 4 DACKA deasserted to DACKA asserted 2 clocks−5 ns 2 5 ARD asserted to ARD asserted 4 clocks−4 ns 2 6 DACKA asserted to ARD asserted 1 clock−5 ns 2 7 ARD asserted pulsewidth 2 clocks−2 ns 2 8 ARD deasserted pulsewidth 2 clocks−2 ns 2 9 ARD deasserted to DACKA deasserted 1 clock−5 ns 2

10 DACKA asserted to ADATA read driven 0 ns 11 ADATA read setup to ARD deasserted 10 ns 12 ADATA read hold from ARD deasserted 5 ns

ARD

ADATA

(output)

(read, input)

Tristate Tristate

6 7 8

11 12

ACIN

(DREQA input)

ACOUT

(DACKA output)

PS3540-1100 Page 43 of 47

Advanced Hardware Architectures, Inc.

Figure 21: Port B Read Timing, 43C97 Master Mode

Table 18: Port B Read Timing, 43C97 Master Mode

Notes:

1) After DREQx becomes inactive, additional BRD strobes are ignored and no more transfers occur into or out of the port regardless of DACKx operation.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 80 MHz.

NUMBER PARAMETER MIN MAX NOTES

1 DREQB asserted to DACKB asserted 0 2 DACKB deasserted to DREQB asserted 2 clocks−5 ns 2 3 BRD asserted to DREQB deasserted 12 ns 1 4 DACKB deasserted to DACKB asserted 2 clocks−5 ns 2 5 BRD asserted to BRD asserted 4 clocks 2 6 DACKB asserted to BRD asserted 5 ns 7 BRD asserted pulsewidth 2 clocks−5 ns 2 8 BRD deasserted pulsewidth 2 clocks−5 ns 2

9 BRD deasserted to DACKB deasserted 5 ns 10 DACKB asserted to BDATA read driven 0 11 BRD asserted to BDATA read valid 10 ns 12 BDATA read hold from BRD deasserted 5 ns 13 DACKB deasserted to BDATA read tristate 10 ns

BRD

BDATA

Tristate Tristate

(input)

(read, output)

6 7 8

BCOUT

(DREQB output)

BCIN

(DACKB input)

Page 44 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

Figure 22: Port B Write Timing, 43C97 Master Mode

Table 19: Port B Write Timing, 43C97 Master Mode

Notes:

1) After DREQx becomes inactive, additional BWR strobes are ignored and no more transfers occur into or out of the port regardless of DACKx operation.

2) The unit clock refers to the clock input. For this interface the maximum clock frequency is 80 MHz.

NUMBER PARAMETER MIN MAX NOTES

1 DREQB asserted to DACKB asserted 0 2 DACKB deasserted to DREQB asserted 2 clocks−5 ns 2 3 BWR asserted to DREQB deasserted 12 ns 1 4 DACKB deasserted to DACKB asserted 2 clocks−5 ns 2 5 BWR asserted to BWR asserted 4 clocks 2 6 DACKB asserted to BWR asserted 5 ns 7 BWR asserted pulsewidth 2 clocks−5 ns 2 8 BWR deasserted pulsewidth 2 clocks−5 ns 2

9 BWR deasserted to DACKB deasserted 5 ns 10 DACKB asserted to BDATA[15:0] write driven 0 11 BDATA[15:0] write setup to BWR deasserted 10 ns 12 BDATA[15:0] write hold from BWR deasserted 2 ns 13 DACKB asserted to BDATA[15:0] write tristate 0 30 ns

BWR

BDATA

(input)

(write, input)

Tristate Tristate

6 7 8

11 12

BCOUT

(DREQB output)

BCIN

(DACKB input)

PS3540-1100 Page 45 of 47

Advanced Hardware Architectures, Inc.

11.0 PACKAGING

Figure 23: AHA3540 TQFP Package Specifications

Table 20: TQFP (Thin Quad Flat Pack) 14 × 14 mm Package Dimensions

JEDEC Outline MO-136

(All dimensions are in mm)

SYMBOL

NUMBER OF PIN AND SPECIFICATION DIMENSION

100

MIN NOM MAX (LCA) 25 (LCB) 25

A1.7 A1 0.05 0.15 A2 1.35 1.4 1.45

D 15.80 16.0 16.20 D1 13.90 14.0 14.10

E 15.80 16.0 16.20 E1 13.90 14.0 14.10

L 0.50 0.60 0.75

P0.50

B 0.17 0.22 0 .27

(LCA) E1

(LCB)

76 77 78 79 80

96 97 98 99

100

2524232221

AHA3540A-040 PTC

Page 46 of 47 PS3540-1100

Advanced Hardware Architectures, Inc.

12.0 ORDERING INFORMATION

12.1 AVAILABLE PARTS

12.2 PART NUMBERING

Device Number:

3540

Revision Letter:

Package Material Codes:

P Plastic

Package Type Codes:

T T - Thin

Test Specifications:

C Commercial 0°C to +70°C

13.0 AHA RELATED TECHNICAL PUBLICATIONS

* Document in development

PART NUMBER DESCRIPTION

AHA3540A-040 PTC

40 MBytes/sec ALDC Data Compression Coprocessor IC with Enhanced Features, TQFP

AHA 3540 A- 040 P T C

Manufacturer

Device

Number

Revision

Level

Speed

Designation

Package Material

Package

Type

Test

Specification

DOCUMENT # DESCRIPTION

PB3540

AHA Product Brief – AHA3540 40 MBytes/sec ALDC Data Compression Coprocessor IC

ABDC17

AHA Application Brief – Differ ences between AHA3540 and IBM ALDC1-20 S-LP

Devices ANDC18 AHA Application Note – Differences between AHA and IBM Devices ANDC24 * AHA Application Note – AHA3540 Designer’s Guide

PS3540-1100 Page 47 of 47

Advanced Hardware Architectures, Inc.

APPENDIX A: DIFFERENCES BETWEEN THE AHA3540 AND IBM ALDC1-20S-LP

A.1 STATUS AND INTERRUPT STATUS REGISTER DIFFERENCES

If the Interrupt Mask bits BPB M (One Byte at P ort B Mask), EORPBM (End of R ecord at Port B Mask), BP AM (One Byte at Po rt A Mask), EORPAM (End of Record at Port A Mask) are s et, then the status bits BPB (One Byte at Port B), EORPB (End of Record at Port B), BPA (One Byte at Port A), EORPA (End of Record at Port A), and the Interrupt Status bits of the same name are only generated at the end of a transfer and not at End of Records. If the Interrupts are not masked then these Status bits and Interrupt Status bits will get set at End of Records and the device will generated an Interrupt and Pause.

There are two new status bits, EMPA (Empty at Port A) and EMPB (Empty at Port B). These bits are asserted when there is no data between the pins of the device and the ALDC core.

A.2 INPUT/OUTPUT DIFFERENCES

There are two new inputs BRD (Pin 32) and BWR (Pin 33) required for the FAS368 Master mode on Port B. In a system that does not use these inputs, they must be tied high or low. They can not be left unconnected. The IBM device requires that these pins be left unconnected. One possible solution for a board that uses both devices is to tie the pins to ground through an appropriate sized resistor.

Datasheet AHA3540A-040PTC Datasheet (Advanced Hardware Architectures)

Specifications and Main Features

Frequently Asked Questions

User Manual