Datasheet AHA3411A-033PQC Datasheet (Advanced Hardware Architectures)

Product Specification

TM

AHA3411 StarLite

33 MBytes/sec Simultaneous

Compressor / Decompressor IC

2365 NE Hopkins Court

Pullman, WA 99163-5601

tel: [phone]

fax: [phone]

e-mail: [e-mail]

www.aha.com

advancedhardwarearchitectures

PS3411-0600

Advanced Hardware Architectures, Inc.

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.3 Pad Word Handling in BurstMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4 DMA Request Signals andStatus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.1 FIFO Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.2 Request During an End-of-Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.1 Compression Input and Pad Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1

3.6.2 Compression Output and PadBytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.3 Decompression Input, Pad Bytes and Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.4 Decompression Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.7 Video Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.7.1 Video Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.7.2 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.8 Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.9 Compression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.10 Decompression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.11 Prearming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.13 Duplex Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.14 Blank Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.15 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.16 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5

4.1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.5 Compression Ports Status, Address 0x04 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.6 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.7 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.8 Interrupt Status/Control 1, Address 0x07 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.9 Interrupt Mask 1, Address 0x09 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.10 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.11 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . .22

4.12 Compression Record Length, Address 0x10, 0x11, 0x12, 0x13 - Read/Write . . . . . . . . . . . . . . . . . . . . . .22

4.13 Compression Control, Address 0x14 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.14 Compression Reserved, Address 0x15 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.15 Compression Line Length, Address 0x16, 0x17 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.16 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

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4.17 Decompression Reserved, Address 0x1A - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.18 Decompression Line Length, Address 0x1C, 0x1D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.19 Compression Record Count, Address 0x20, 0x21 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.20 Interrupt Status/Control 2, Address 0x27 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.21 Interrupt Mask 2, Address 0x29 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.22 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.23 Compression Byte Count, Address 0x30, 0x31, 0x32, 0x33 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . .26

4.24 Compression Control Prearm, Address 0x34 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.25 Pattern, Address 0x35 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.26 Decompression Control Prearm, Address 0x38 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.27 Decompression Reserved, Address 0x3A - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

5.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

5.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7.0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3

7.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

7.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

8.0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4

9.0 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

10.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

10.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

11.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Appendix A: Additional Timing Diagrams for DMA Mode Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Appendix B: Sequential Register Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

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Figures

Figure 1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .7

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .7

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=100. . . . . . . .7

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=100 . . . . . . .8

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=100. . . . . . .8

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=100. . . . . . .8

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 14: Timing Diagram, Video Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 15: Timing Diagram, Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 16: Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 17: Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=0. . . . . . . . . . . . . . . . . . . . . . . .34

Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=1. . . . . . . . . . . . . . . . . . . . . . . .35

Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 21: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 22: Output Enable Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 23: Video Input Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 24: Video Output Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 25: Microprocessor Interface Timing (PROCMODE[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 26: Microprocessor Interface Timing (PROCMODE[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 27: Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 28: Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 29: Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .43

Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .43

Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=000. . . . . . .43

Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=000 . . . . . .44

Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=000. . . . . .44

Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000. . . . . .44

Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=010 . . . . . . . . . . . . . . . . . . . . . .45

Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition ofDSC=010 . . . . . . . . . . . . . . . . . . . . . .45

Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=010. . . . . . .45

Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=010 . . . . . .46

Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=010. . . . . .46

Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=010. . . . . .46

Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .47

Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .47

Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011. . . . . . .47

Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=011 . . . . . .48

Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=011. . . . . .48

Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=011. . . . . .48

Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .49

Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .49

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Tables

Table 1: Data Bus and FIFO Sizes Supported by AHA3411. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 2: AHA3411 Connection to Host Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 3: Microprocessor Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 4: Internal Strobe Conditions for DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 5: Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 6: Data Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 7: Request vs. EOR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 8: Output Enable Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6

Table 9: Video Input Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 10: Video Output Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 11: Microprocessor Interface Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 12: Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 13: Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 14: Power On Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

iv PS3411-0600

Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

AHA3411 is a lossless compression
coprocessor IC for hardcopy systems on many
standard platforms, including PCI Bus. The device
is targeted for high throughput and high resolution
hardcopy s ystems.

Multiple record counters, higher clock
frequency, advanced banding and duplex printing
features enhance this product from the first
StarLite introduction, AHA3410. Identical
compression algori th m and simi lar firmware
considerations ease migration to this second
generation device.

Blank band generation in real time and
prearming registers between records enable
advanced banding techniqu es. Bands may be in raw
uncompressed, compressed or blank format in the
frame buffer. The device processes all three formats
and outputs the raster data to the printer engine.
Appropriate register s are prearmed when switch ing
from one type to the next. Separate byte ordering
between the Compressor and the Decompressor
with bit order control in to the compressor allow ful l
reversal of the image data for duplex printing
support. A system may use mult iple record counters
and End-of-Transfer interrupts to easily handle
pages partitioned into smaller records or bands.

This document contains f unctional des cription,
system configurations, register descriptions,
electrical characteristics and ordering information.
It is intended for system de signers considering a
compression coprocessor in their embedded
applications. Software simulation and an analysis of
the algorithm for printer and copier images of
various com plexity are also available for
evaluation. A comprehensive Designer’s Guide
complements this document to assist with the
system design. Section 1 1.0 contains a list of related
technical publications.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

– Active low signals h ave an “N” appended to the

end of the signal name. For example, CSN and
RDYN.

– A “bar” over a signal name indicates an inverse of

the signal. For example, SD
of SD. This terminology is used only in logic
equations.

–“Signal assertion” means the output signal is

logically true.

– Hex values are represented with a prefix of “0x”,

such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.

indicates an inverse

– A range of signal names or re gister bits is denoted

by a set of colons between the numbers. Most
significant bit i s always shown first, followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.

– A logical “AND” function of two signals is

expressed with an “&” between variables.

– Mega Bytes per second is referred to as MBytes/

sec or MB/sec.

– In re ferencing micropr ocessors, an x, xx or xxx is

used as suffix to indicate more than one
processor. For example, Motorola 68xxx
processor family includes various 68000
processors from Motorola.

– Reserved bits in registers are referred as “
– REQN or ACKN ref er to either CI, DI, CO or DO

Request or Acknowledge signals, as applicable.

res”.

1.2 FEATURES

PERFORMANCE:

• 33 MBytes/sec burst rate, 33 MBytes/sec
maximum sustained

• 132 MBytes/sec burst data rate over a 32-bit data bus

• 33 MBytes/sec synchronous 8-bit video in and

video out ports

• Simultaneous compression and decompres sion at
full bandwidth

• Average 15 to 1 compression ratio for 1200 dpi
bitmap image data

• Advanced banding support: blank bands, prea rmng

FLEXIBILITY:

• Big Endian or Little Endian; 32 or 16-bit bus
width and data bit/byte reordering for duplex
printing support

• Programmable Record Lengt h, Record Count and
Scan Length Registers may be prearmed

• Scan line length up to 2K bytes

• Interfaces directly with various MIPS, Motorola

68xxx and Cold FIRE, Intel i960, and Am29K
embedded processors

• Pass-through mode passes raw data through
compression and decompression engines

• Counter checks errors in decompression

SYSTEM INTERFACE:

• Single chip compression/ decompre ssion soluti on
– no external SRAM required

• Four 16 × 32-bit FIFOs with programmable

threshold counters facilitate burst mode transfers

OTHERS:

• Low power modes

• Software emulation program available

• 128 pin quad flat package

PS3411-0600 Page 1 of 50

Advanced Hardwar e Architectures, Inc.

Figure 1: Functional Block Diagram

CIACKN

DOREQN

COREQN

DIREQN

CIREQN

SD

DOACKN

COACKN

DIACKN

(From Scanner)

VIREQN
VID[7:0]
VIACKN

D[31:0]

DRIVEN

VID

PORT

DATA
PORT

8

32

32 32

TEST

CLOCK

CLK

CI

FIFO

16x32

DI

FIFO

16x32

RSTN

DATA PORT CONTROL

8 8

PROCMODE[1:0]

COMPRESSOR

DECOMPRESSOR

MICROPROCESSO R INT ERFACE

8

PD[7:0]

1.3 FUNCTIONAL OVERVIEW

The coprocessor device has three external high
speed synchronous data ports capable of transferring
once every 33 MHz clock. These are a 32-bit
bidirectional data port, an 8-bit Video Input Data
(VID) port and a Video Output Data (VOD) port.
The 32-bit port is capable of transferring up to 132
MBytes/sec. The VID and VOD are capable of up to
33 MBytes/sec each.

The device accepts uncompressed data through
the 8-bit VID port or the 32-bit data port into its
Compression In FIFO (CI FIFO). The 32-bit data
port may be configured for 16-bit transfers.
Compressed data is available through the 32-bit data
port via the Compressed Output FIFO (CO FIFO).
The sustained data rate through the compression
engine is 33 MBytes/sec.

CO

FIFO

16x32

DO

FIFO

16x32

888

VOD

PORT

COEORN
COEOTN

(To Printer)

VOEOTN
VOEORN
VOREQN
VOD[7:0]
VOACKN

AHA3411

StarLiteTM

6

CSN

DIR

RDYN

PA[5:0]

INTRN

Decompression data may be simultaneously
processed by the device. Decompression data is
accepted through the 32-bit data port, buffered in
the Decomp ression Input FIFO (DI FIFO) and
decompressed. The output da ta is made available on
the 32-bit d ata port via the Decompres sion Output
FIFO (DO FIFO) or the 8-bit Video Output port.
The decompression engine runs on the 33 MHz
clock and is capable of processing an unco mpressed
byte every clock, i.e., 33 MB/sec.

The four FIFOs are organized as 16×32 each.
For data transfers through the three ports, the
“effective” FI FO sizes dif fer according to their data
bus widths. The table below shows the size of the
data port and the “effective” FIFO size for the
various configurations supported by the device.

Table 1: Data Bus and FIFO Sizes Supported by AHA3411

OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE

Compression Data In 8 Video In 16 x 8
Compression Data In/O ut 32 Data Port 16 x 32
Compression Data In/O ut 16 Data Port 16 x 16
Decompression Data In/Out 32 Data Port 16 x 32
Decompression Data In/Out 16 Data Port 16 x 16
Decompressed Data Out 8 Video Out 16 x 8

Page 2 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Table 2: AHA3411 Connection to Host Microprocessors

PIN NAME i960Cx i960Kx IDT3081

PA A LAD Latched Address Latched Address

CSN

DIR

PD D LAD A/D A/D[7:0]
SD

RDYN No Connect

DRIVEN

CLOCK PCLK No Connect

Movement of data for compression or
decompression is performed using synchronous
DMA over the 32-bit data port. The Video ports
support synchronous DMA mode transfers. The
DMA strobe conditions are co nfigurabl e for the 32 ­bit data port depending upon the system processor
and the available DMA controller.

Data transfer for compres sion or
decompression is synchronous over the three data
ports functioning as DMA masters. To initiate a
transfer into or out of the Video ports, the device
asserts VxREQN, the external device responds with
VxACKN and begins to t ra nsf er da ta over the VID
or VOD busses on each succeeding rising edge of
the clock until VxREQN is deasserted. The 32-bit
port relies on the FIFO Threshold settings to
determine the transfer.

The sections below describe the various
configurations, programming and other special
considerations in developing a compressi on system
using AHA3411.

CS

W/R

WAIT

DEN

CS

W/R WR R/W

READY
READY

System Dependent

2.0 SYSTEM CONFIGURATION

This section provides information on
connecting AHA341 1 to variou s micro processors.

2.1 MICROPROCESSOR INTERFACE

The device is capable of interfacing directly to
various processors for embedde d application. T able 2
and Table 3 show how AHA341 1 s houl d be
connected to various host micr oprocessors.

All register accesses to AHA3411 are
performed on the 8-bit PD bus. The PD bus is the
lowest byte of the 32-bit microprocessor bus.
During reads of the internal registers, the upper 24
bits are not driven. System designers should
terminate these lines with Pullup resis tors.

the microprocesso r port. Both active high and a ctive
low write enable si gnals are al lowed a s well as two
modes for chip select. T he mode of oper atio n is set
by the PROCMODE[1:0] pins. The
PROCMODE[1] signal selects when CSN must be
active and also how long an access lasts.

determines the le ngth of the acces s. CSN must be at
least 5 clocks in length. On a read, valid data is
driven onto PD[7:0] during th e 5th clock. If CSN is
longer than 5 clocks, t hen valid data c ontinues to be
driven out onto PD[7:0]. When CSN goes inactive
(high), PD[7:0] goes tristate (asynchronously) and
RDYN is driven high as ynchronously . CSN must be
high for at least t wo clocks. RDYN is always drive n
(it is not tristated when P RO CM OD E [1 ] is high). The
mode is typical of processors such as the Motorola
68xxx.

fixed at 5 clocks, PD[7:0] is onl y driven dur ing the
fifth clock, and RDYN is driven high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock after CSN is sampled low. Accesses may
be back to back with no delays in between. This
mode is typical of RISC processors s uch as the i960
and Am29K.

DIR pin. If PROCMODE[0] is high, then the DIR
pin is an active low write enable. If PROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.

micropro cessors, refer to AHA Application Note
(ANDC16), Designer’ s Guide for StarLi te
Products. AHA Applications Engineering is
available to supp ort with other pr ocessors not i n the
Designer’s Guide.

System Dependent

System Dependent

System Dependent System Dependent

SYSCLK

AHA3411 provi des four modes of operat ion for

When PROCMODE[1] is high, CSN

When PROCMODE[1] is low, accesses are

PROCMODE[0] determines the polarity of the

For additional notes on interfacing to various

Motorola

MCFS102(ColdFIRE)

Decoded Chip Select

System Dependent

ACK TA

BCLOCK

TM

Family

PS3411-0600 Page 3 of 50

Advanced Hardwar e Architectures, Inc.

Table 3: Microprocessor Port Configuration

PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR

00 Active high write fixed i960
01 Active low write fixed
10 Active high write variable
11 Active low write variable 68xxx, MIPS R3000

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

D0 D1

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)

CLOCK

PA[5:0]

CSN

DIR

A0

A1

A1

A2

PD[7:0]

RDYN

D0

D1

Page 4 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure 4: Microprocessor Port Write (PROCM OD E [1:0 ] = “11”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

D0

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”)

CLOCK

PA[5:0]

CSN

A0

A1

A1

DIR

PD[7:0]

RDYN

D0

PS3411-0600 Page 5 of 50

Advanced Hardwar e Architectures, Inc.

ACKN()& SD()

ACKN()& SD()

ACKN

delayed

()& SD

delayed

()

ACKN

delayed

()& SD

delayed

()

ACKN()& ACKN

delayed

()

ACKN()& ACKN

delayed

()

3.0 FUNCTIONAL DESCRIPTION

This section describes the various data ports,
special handling, data formats and clocking
structure.

3.1 DATA PORTS

AHA3411 cont ains two data input po rts, CI and
DI, and two data output ports, CO and DO on the
same 32-bit data bus, D[31:0]. Data transfers are
controlled by external DMA control. The logical
conditions under which data is written to the input
FIFOs or read from the output FIFOs are set by t he
DSC (Data Strobe Condition) field of the

Configuration 1 register.

A strobe condition defines under what logical
conditions the input FIFOs ar e written or the output
FIFOs read. CIACKN, COACKN, DIACKN,
DOACKN, and SD pins combine to strobe data in a
manner similar to DMA controllers. The DMA
Mode sub-section descr ibes t he var ious da ta st robe
options.

System

3.2 DMA MODE

On the rising edge of CLOCK when the stro be
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert
acknowledge at any one time. Table 4 shows the
various conditions that may be programmed into
register DSC.

Figure 6 through Figure 11 illustrate the DMA
mode timings for single, four word and eight word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appe ndix A. Note that
the only differe nce between odd and eve n values of
DSC is the polarity of SD. Waveforms are only
shown for polari ties of SD correspondi ng to specific
systems.

Table 4: Internal Strobe Conditions for DMA Mode

DSC[2:0] LOGIC EQUATION SYSTEM CONFIGURATION

ACKN

)& ACKN

000
001 No specifi c system

ACKN

()& SD()

)& ACKN

()& SD()

delayed

delayed

010 General purpose DMA controller

011

100 No specifi c system
101 No specifi c system

110 No specific sy stem
111 No specific syst em

CKN

SD

i960Cx with internal DMA contro ller. SD is co nnected to
WAITN.

i960Kx with external, bus master type DMA controller.
SD is connected to RDYN.

delayed

delayed

ACKN delayed 1 clock=
SD delayed 1 cloc k=

Page 6 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

PS3411-0600 Page 7 of 50

Advanced Hardwar e Architectures, Inc.

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Page 8 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

3.3 PAD WORD HANDLING IN
BURST MODE

The StarLite compr ession algorit hm appends

a 15 bit End-of-Record codeword to terminate a
compression record. If a word containing an End­of-Record comes out during a bur st read, the words
following the End-of-Record are invalid (pad)
words. This prevents a burst read from crossing
record boundaries. The first word of the next burst
read is the first word of the next record. Any pad
words not previously removed must be deleted.

T wo methods are available to delete pad words.
During decompression pad words may be deleted by
using the Decompression Pause on Record
Boundaries bit (DPOR), in the Decompression
Control register. After the part is paused, the DI FIFO
must be reset by asserting the DIRST bit in the Port
Control register. Decompressor must also be reset by
asserting DDR bit in Decompression Control register.
The COEOTN signal is asserted when an End-of­Record is present on the output of the CO FIFO and
the compression record counter has decremented to
zero, thus indicating the end of a transfer comprised
of one or more compressed records.

Another method to remove pad words during
compression is to read the Compressed Byte Count
register after pausing at an End-of-Record and
subtract this from the system’s received word count.
This difference is the number of pad words that
must be removed from the end of the compressed
record.

The COEORN signal is asserted when an End­of-Record is present on the out put of the CO FIFO.
COEORN is deasserted after the transfer. In some
systems COEORN can be used to generate a DMA­done condition if conditioned with the
acknowledge.

3.4 DMA REQUEST SIGNALS

AND STATUS

AHA3411 requests data using request pins
(CIREQN, DIREQN, CO REQN, DOR EQN ). The
requests are controlled by programmable FIFO
thresholds. Both input and output FIFOs have
programmable empty and full thresholds set in the

Input FIFO Thr esho ld

registers. By requesting only when a FIFO can sustain
a certain burst size, the bus is used more efficiently.

Operation of these request signals should not be
confused with the request signals on the video ports.
CIREQN or DIREQN active indicates space
available in the particular input FIFO, and COREQN
or DOREQN active indicates data is available in the
particular output FIFO. These request signals inactive

and Output FIFO Threshold

does not prevent data transfers. The data transfers are
controlled solely with the particular acknowledge
signal being active.

The input requests, CIREQN and DIREQN,
operate under the fol lowing priori tize d ru les, li sted
in order of highest to lowest:

1) If the FIFO reset in the
register is active, the request is inactive.

2) If a FIFO overflow interrupt is active, the
request is inactive.

3) If the FIFO is at or below the empty
threshold, the request remai ns active.

4) If the FIFO is at or above the full threshold,
the request stays inactive.

The output requests, COREQN and DOREQN,
operate under the fol lowing priori tize d ru les, li sted
in order of highest to lowest:

1) If the FIFO reset in the
register is active, the request is inactive.

2) If the output FIFO underflow interrupt is
active, the request is inactive.

3) If an EOR is pres ent in the output FIFO, th e
request goes active.

4) If the output FIFO is at or above the full
threshold, the request goes acti ve.

5) If an EOR is read (strobed) out of the FI FO,
the request goes inactive during the same
clock as the strobe (if ERC=0), otherwi se it
goes inactive on the next clock.

6) If the output FIFO i s at or below the empt y
threshold, the request goes inact ive.

Port Control

Port Control

3.4.1 FIFO THRESHOLDS

For maximum efficiency, the FIFO t hresholds
should be set in such a way that the compressor
seldom runs out of data from the CI FIFO or
completely fills the output FIFO. The FIFOs are 16
words deep.

For example, in a system with fixed 8-word
bursts, good values for the thresholds are:

IET=3, IFT=4, OFT=D, OET=C

Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request deasserts as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 clocks. This should be ke p t in mi nd wh e n
programming threshold values. Refer to Section 4.0
of AHA Applicat i o n Not e ( AND C1 6) , Designer’s

Guide for StarLite

thorough discussion of FIFO thresholds. The
following figure shows an example of an input FIFO
crossing its full threshold.

TM

Family Products for a more

PS3411-0600 Page 9 of 50

Advanced Hardwar e Architectures, Inc.

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)

CLOCK

3

234

45

6

5

7

6

8

78

9

CIACKN

CIREQN

Threshold

Counter

D

1

1

2

Note: CIREQN deasserted when threshold counter exceeds IFT=4, but additional words are reading as long as

ACKN is asserted.

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010

CLOCK

ACKN

D

EOR-2

EOR-1

EOR

REQN

(ERC=0)

REQN

(ERC=1)

EORN

3.4.2 REQUEST DURING AN END-OF-RECORD

The request deasserts at an EOR in one of two
ways. If ERC bit in System Conf igurati on 1 is zero,
the request deasserts as ynchronously during the
clock where the EOR is strobed out of the FIFO.
This leads to a lo ng output delay for REQN, but may
be necessary in some systems. For DSC values of 4
or 5, the request deasserts the first clock after the
acknowledge pulse for the EOR. If ERC is set to
one, then the request deasserts synchronously the
clock after the EOR is strobed out. The minimum
low time on the request in this case is one clock.

The request delay varies between the different
strobe conditions. See Section 8.0 AC Electrical
Specifications for further details.

3.4.3 REQUEST STATUS BITS

An externa l microproc essor can also read the
value of each reque st using the CIREQ and COREQ
bits in the Compression Port Status register and the
DIREQ and DOREQ bits in the Decompression
Port Status register. Please note the request status
bits are active high while the pins are active low.

Page 10 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

3.5 DATA FORMAT

The width of the D bus is selected with the
WIDE bit in System Configuration 0. If WIDE=1,
then D is a 32-bit bus. If WIDE=0, D is a 16-bit bus.
If the bus is configured to be 16-bits wide
(WIDE=0), all data tran sfe rs occur on D[15:0] and
the upper 16 bits of the bus, D[31:16], should be
terminated with Pullup resistors. If WIDE=0, the
FIFO is sixteen words deep.

Since the compression algorithm is byte oriented,
it is necessa ry for AHA34 1 1 t o know t he orde ring of
the bytes within the word. The COMP and DECOMP
BIG bits in System Configuration 0 select bet wee n
big endian and little endian byte ordering for the
compression and decomp re ssi on chann el. Lit tle
endian stores the first byte in the lower eight bits of a
word (D[7:0]). Big endian stores the first byte in the
uppermost eight bits of a word (D[31:24] for
WIDE=1, D[15:8] for WIDE=0) for the
decompression e ngi ne o r c ompression engin e.

REVERSE BYTE in the System Configuration
0 register allows the bit order into the compression
engine to be swapped. This control is useful for
reversing a page of data for duplex printing
applications and has no significant impact on
compression ratio performanc e.

3.6 ODD BYTE HANDLING

All data transfers to or from either the
compression or decompression engines are performed
on the D bus on word boundaries. Since no provision
is made for single byte transfers, occasionally words
will contain pad bytes. Following is a description of
when these pad bytes are necessary for each of the
data interfaces.

3.6.1 COMPRESSION INPUT AND PAD BYTES

Uncompressed data input into AHA3411 is
treated as re cords. The length of these records is
fixed by the value in the Record Length or RLEN
register. This register contains the number of
uncompressed bytes in each record. If the value in
RLEN is not an integer multiple of number of bytes
per word as selec ted by WIDE, the fi nal word in the
transfer of the record contains pad bytes. The
compression engine s imply discards these pad bytes
and has no effect on either the dictionary or the
output data stream. The next re cord must begin on a
word boundary.

The minimum value for RLEN is 4 bytes.

3.6.2 COMPRESSION OUTPUT AND
PAD BYTES

If a record ends on a byte other than the l ast byte
in a word, the final word contains 1, 2 or 3 pad bytes.
The pad bytes have a value of 0x00. Th is appli es to
the 32-bit data port only.

3.6.3 DECOMPRESSION INPUT, PAD BYTES

AND ERROR CHECKING

This port recognizes th e end of a re cord by the
appearance of a special End-of- Record sequence in
the data stream. Once this is seen, the remaining
bytes in the current word are treated as pad bytes
and discarded. The word following the end of the
record is the beginning of the next record.

When operating in decompression mode, the
Decompression R ecord Length (DRLEN) register
can be used to provid e error checking. The e xpected
length of the decompressed record is programmed
into the DRLEN register. The decompressor then
counts down from the value in DRLEN to zero.

A DERR interrupt is issued if an EOR is not
read out of the decompressor when the counter
expires or if an EOR occurs before the counter
expires (i.e., when the record length s do not match).
If the DERR interrupt is mask ed, use of the DRLEN
register is optional.

When operating in pass-t hrough mode, there is
no End-of-Record codeword for the decompressor
to see. In pass-through mode, the user must set the
record length in the DRLEN register.

3.6.4 DECOMPRESSION OUTPUT AND

PAD BYTES

When the decompressor detects an End-of­Record codeword, it will add enough pad bytes of
value 0x00 to complete the current word as defined
by the WIDE bit in the System Configuration 0
register. For example, if a record ends on a byte
other than the last byte in a word, the final word
contains 1, 2 or 3 pad bytes. This applies to the 32­bit data port only, not th e VOD port. The VOD port
never outputs pad bytes since it is 8-bits wide.

PS3411-0600 Page 11 of 50

Advanced Hardwar e Architectures, Inc.

Figure 14: Timing Diagram, Video Input

CLOCK

VIREQN

VIACKN

VID[7:0]

don’t

care

0 3

1 2

3.7 VIDEO INTERFACES

3.7.1 VIDEO INPUT

The video input port is enabled by the VDIE bit
in the System Configuration 1 register . The port use s
VIREQN to indicate that the port can accept another
byte. The value on VID[7:0] is written into
AHA3411 each clock that VIREQN and VIACKN
are both low.

The video input port as serts VIREQN whenever
there is room in the CI FIFO. The value s in IET and
IFT are all ignored. Th e compressi on input FI FO is
16 bytes
transfer up to one byte per clock (33 MB/sec). The
DMA interface cannot acce ss the compression input
FIFO when VDIE is set.

3.7.2 VIDEO OUTPUT

bit in the System Configuration 1 regist er. The port
uses VOREQN to indicate that the byte on

deep in this mode. The video in put port can

The video output port is enabled by the VDOE

don’t care

4 5

VOD[7:0] is valid. An 8-bit word is re ad each clock
when both VOREQN and VOACKN are sampled
low on a rising edge of CLOCK. Pad bytes at an end
of record are discarde d by the video outp ut port and
do not appear on VOD[7:0]. When the byte on
VOD[7:0] is the last by te in a record, the VOEORN
signal goes low. To use VOEORN as an End-of­Record indicator, it should be conditioned with
VOREQN and VOACKN. Unlike a DMA transfer,
there are no pad bytes after an End-of-Record.

VOEOTN operates similar to VOEORN. It
flags the end of an output transfer of one or more
decompressed records. VOEOTN is as ser te d when
the End-of-Record is at the out put of the DO FIFO
and the decompression record count has
decremented to zero.

The port requests whenever a valid byte is
present on the output. The values in OET and OFT
are all ignored. The decompression output FIFO is
16 bytes

deep in this mode. The video output port
can output up to one byte per clock (33 MB/sec).
The DMA interface cannot access the
decompression output FIFO when VD OE is set.

don’t

care

Figure 15: Timing Diagram, Video Output

CLOCK

VOREQN

VOACKN

VOD[7:0]

VOEORN,

VOEOTN

Page 12 of 50 PS3411-0600

0 31 2 4 5

Advanced Hardware Architectures, Inc.

3.8 ALGORITHM

AHA3411 compressi on is an efficient
implementation of an algorithm opti mized for
bitonal images. For some comp ari son data ref er to
the AHA Application Note ( AN D C 1 3 ),

Compression
Performance: StarLiteTM: ENCODEB2 on
Bitonal Images. A software emulation of the

algorithm is availabl e fo r eva lua tion.

3.9 COMPRESSION ENGINE

The compression engine supports either
compression or pass-through processes. The
compression engine is enabled with the COMP bit in
the Compr ession Contr ol register . When the engine is
enabled, it takes data from the CI F I F O as it becomes
available. This data is either compressed by the engine
or passed through unaltered. This pass-through mode
is selected with the CPASS bit in the Compr essi on
Control register . The CP ASS bit may only be changed
when COMP is set to ‘0’. The contents of the
dictionary are preserved when COMP is changed.
However, when CPASS is changed, the contents are
lost. Consequently, the device cannot be changed
from pass-through mode to compression mode or vice
versa without losing the contents of the dictionary.

The compressor can be instr uct ed to ha lt at t he
end of a record or an end of multiple-record
transfer. If the CPOR bit is set, the compressor stops
taking data out of the CI FIFO immediately after the
last byte of a record, and the COMP bit i s cleared. If
the CPOT bit is set the compressor halts at the end
of the multip le-record transfer. The CEMP bit
indicates the compressor has emptied all data.
Compressio n is restarted by setting the C OMP bit.

The compression engine takes dat a fr om the
compression input FIFO at a maximu m rate of 33
MBytes/sec. Two conditions cause the data rate to
drop below the maximum. The first is caused by the
compression input FIFO running empty of dat a to be
compressed. The second conditi on i s ca used by the
output FIFO filling. Whe n thi s occ urs , the engine
halts and waits for the FIFO. While halted, the engine
goes into a low power standby mode. Refe r to the
table in Section 7.1 for the e xte nt of power savings.

The compression byt e counter counts the number
of bytes output from the CO data port. The counter is
valid to read after a compression end of transfer
interrupt (CEOT), or pausing after End-of-Record.

3.10 DECOMPRESSION ENGINE

The decompression engine is enabled with the
DCOMP bit in the Deco mpr ession Contr ol register .
When the engine is enabled, it takes data from the
DI FIFO as it becomes available. This dat a is either

decompressed by the engine or passed through
unaltered. Pass-through mode is selected with the
DPASS bit. DPASS may only be changed when
DCOMP is set to zero and DEMP is set to one. The
contents of the dictionary are preserved when
DCOMP is changed. However, when DPASS is
changed, the contents are lost. Consequently,
AHA3411 cannot be changed from pass-through
mode to decompression mode or vice versa without
losing the contents of the dictionary.

The decompressor can be i nstructed to halt at the
end of a record or an end of multiple- record tr ansfer.
If the DPOR bit is set, the de compressor stops taking
data out of the DI FIFO immediat ely a ft er t he l ast
byte of a record, and the DCOMP bit is cl ear ed. I f
DPOT bit is set the decompressor halts at the end of
the multiple-record trans fer . The DEMP bit indicates
the decompressor has emptied of a ll data . Decom­pression is restarted by s et tin g the DCOMP bit. If
DPOR or DPOT is set and data from a second r ecord
enters the FIFO immediately aft er t he f ir st r ecord,
bytes from the second record wil l ha ve en ter ed t he
decompressor prior to decoding the EOR. An impli­cation of this is that bytes from the second record will
remain in the decompressor and pr event DEMP from
setting after all o f t he dat a f rom the first record has
left the decompressor. This differs f rom operatio n of
the compression engine. In eit her mode , a DEOR
interrupt is generated wh en t he l ast byt e of a decom­pressed record is read out o f th e chip, and DEOT
when the last byte of a transfer is read out of the chip.

The decomp ressor takes data from the
decompression input FIFO at a maximum rate of
33 MBytes/sec. AHA3411 can maintain this data
rate as long as th e deco mpression i nput FIFO i s not
empty or the decompression out put FIFO is not full.

Caveat: Changing the mode for the
decompressor between r ecords or multiple-record
transfers must be done with the data of t he following
record or transfer held off until the DEOR status bit
is true for the current record and the Decompression
Control regist ers have been reprogrammed. This
reprogramming can occur automatically with
prearming.

3.11 PREARMING

Prearming is the ability to write certain
registers that apply to the next record w hile the
device is processing the current record. These
registers may be prearmed for record bounda ri es.
Prearming is automatic, meani ng there is no way to
disable it. If a prearmable register is written while
the part is bus y processing a re cord, at the end o f the
record the part takes its program from the register
value last written. Compression Control and
Decompression Control registers each have
separate corresponding prearm registers.

PS3411-0600 Page 13 of 50

Advanced Hardwar e Architectures, Inc.

The lower 3 bytes of both the Compression

Record Length and the Decompression Length

registers are prearmable. They may be changed and
the new values loaded into the respective counter at
the next End-of-Record. If the most significant byte
is written in either of the Record Length registers, the
counter is immediately reloaded with the new 4 byte
value in the particular register .

3.12 INTERRUPTS

Nine conditions are reported in the Interrupt

Status/ Cont rol 1 and Status/Control 2 registers as

individual bits. All interrupts are maskable by
setting the corres ponding bits in the In terrupt Mas k
register . A one in the Interrupt Mask register means
the corresponding bit in th e Interrupt Status /Control
register is masked and does not affect the interrupt
pin (INTRN). The INTRN pin is active whenever
any unmasked interrupt bit is set to a one.

An End-of-Record interrupt is posted when a
word containing an end-of-record is strobed out of
the compression or decompression output FIFO
(CEOR and D EOR respectively). A DEOR inter­rupt is also reported if an end-of-record is read from
the video output po rt. A compression or decompres­sion end of transfer interrupt will also be posted if
this is the la st record of a t ransfer.

End-of-Transfer interrupts are posted when an
EOR occurs that c auses the c ounter to decrement to
zero. These are CEOT and DEOT, and they apply to
both the compression and decompression engines
respectively.

Four FIFO error conditions are also reported.
Overflowing the input FIFOs generates a CIOF or
DIOF interrupt. An ove rflow can only be cleared by
resetting the respective FIFO via the Port Control
register.

Underflowing the output FIFOs (readi ng when
they are not ready) generates a COUF or DOUF.
Underflow interru pts are cleared b y writing a one to
COUF or DOUF. In the event of an underflow, the
respective FIFO mus t be reset. Note that in systems
using fixed length b ursts which rearbit rate duri ng a
burst, the CO FIFO may reques t another burst when
the record actually finishes near the end of the
current burst. In this scenario a second burst takes
place causing a FIFO under flow . As long as a pause
on End-of-Record is used, d ata is not corrupted. The
FIFO simply must be reset.

3.13 DUPLEX PRINTING

the compressor . Bit order control allows revers al of
the data bits within each byte of data. For example,
reverse order means bi t-7 is swapped wit h bit-0, bit-

6 is swapped with bit-1, et c.... Duri ng compres sion

operation of th e back side of the p age the data words
are sent to the AHA3411 device in reverse order.
The byte order is swapped if necessary by the
COMP BIG bit in the System Configuration 0
Register. The bit order within each byte is revers ed
with the REVERSE BYTE bit in this same register.

During decompression of th is reversed page the
DECOMP BIG bit in this register must be
programmed to the same value used when this p age
of data was compressed. Use of this feature has
virtually no effect on the compression ratio when
compared to compressing in forward order.

3.14 BLANK BANDS

Setting DBLANK in the Decompression
Control regist er causes the nex t record outpu t from

the Decompressor to be comprised of a repeating 8­bit pattern defined by the Pattern register.
DBLANK automatically clears at the end of the
next record. This command bit may be prearmed by
writing to the Decompression Control Prearm
register . When pr ogramming the device to generate
blank records the system must not send data to be
decompressed until the device has reached the end
of record for the blank record.

3.15 LOW PO WER MODE

The AHA34 11 is a data-driven system. When
no data transfers are tak ing place, only the clock and
on-chip RAMs including the FIFOs require power.
To reduce power consumption to its absolute
minimum, the user can stop the clock when it is
high. With the system clock stopped and at a high
level, the current consumption is due to leakage.
Control and Status registers are preserved in this
mode. Reinitialization of Control registers are not
necessary when switching fr om Low Power to
Normal operating mode.

3.16 TEST MODE

In order to facilitate board level testing, the
AHA3411 provides the ability to tristat e all out puts.
When the TEST0 pin is high, all outputs of the chip
are tristated. When TEST0 is low, the chip returns to
normal operation.

Duplex Printing is the ability to print on both
sides of the page. AHA3411 supports this with
separate endian control for the Compressor and
Decompressor, and bit order control at the input to

Page 14 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

4.0 REGISTER DESCRIPTIONS

The microprocessor configures, controls and monitors IC operation through the use of the registers
defined in this section. All registers are reset to zero on RSTN unless otherwise stated. The bits labeled “
are reserved and must be set to zero when writing to registers unless otherwise noted.

A summary of registers is listed below.

Table 5: Internal Registers

DEFAULT

ADDRESS R/W DESCRIPTION FUNCTION

AFTER

RSTN

PREARM

res”

0x00 R/W System Configuration 0

0x01 R/W System Configuration 1

0x02 R/W Input FIFO Thresholds

0x03 R/W Output FIFO Thresholds

0x04 R Compression Ports Status

0x05 R Decompression Ports Status
0x06 R/W Port Control Reset Individual FIFOs 0x0F No

0x07 R/W Interrupt Status/Control 1 EOR, Overflow, Underflow 0x00 No
0x09 R/W Interrupt Mask 1 Interrupt Mask bits 0xFF No
0x0A R Version Die Version Number 0x21 No

0x0C R/W

0x0D R/W

0x0E R/W

0x0F R/W

0x10 R/W Compression Record Length 0
0x11 R/W Compression Record Length 1 " " , Byte 1 Undefined Yes

0x12 R/W Compression Record Length 2 " " , Byte 2 Undefined Yes
0x13 R/W Compression Record Length 3 " " , Byte 3 Undefined No

0x14 R/W Compression Control

0x15 R/W Compression Reserved Reserved 0x00 No
0x16 R/W Compression Line Length 0

0x17 R/W Compression Line Length 1

Decompression Record
Length 0
Decompression Record
Length 1

Decompression Record
Length 2
Decompression Record
Length 3

Big Endian vs. Little Endian,
32-bit vs. 16-bit, Reverse Byte
Data Strobe Condition, EOR
Request Control, VDO Port
Enable, VDI Port Enable

Input FIFOs Empty
Threshold, Full Threshold

Output FIFOs Empty
Threshold, Full Threshold
FIFO Status, Request St at us,
EOR Status
FIFO Status, Request St at us,
EOR Status

Bytes Remaining, Byte 0
Bytes Remaining, Byte 1 0xFF Yes

Bytes Remaining, Byte 2 0xFF Yes

Bytes Remaining, Byte 3 0xFF No
Length of Uncompressed Data

in Bytes, Byte 0

Pause on Record Boundaries,
Enable Compression, Com­pression Engine Empty S tatus,
Compression Dictionary
Reset, Select Pass-Through
Mode

Line Length Register Lower
8bits
Line Length Register Upper
3bits

Undefined No

0x00 No

Undefined No

Undefined No

Undefined No

Undefined No

0xFF Yes

Undefined Yes

0x04 Yes

Undefined No

Undefined No

PS3411-0600 Page 15 of 50

Advanced Hardwar e Architectures, Inc.

DEFAULT

ADDRESS R/W DESCRIPTION FUNCTION

Pause on Record Boundaries,
Enable Decompression

0x18 R/W Decompression Control

0x1A R/W Decompression Reserved 1 Reserved 0x00 No
0x1C R/W Decompression Line Length 0

0x1D R/W Decompression Line Length 1

0x20 R/W Compression Record Count 0

0x21 R/W Compression Record Count 1

0x27 R/W Interrupt Status/ Control 2

0x29 R/W Interrupt Mask 2

0x2C R/W Decompression Record Count 0

0x2D R/W Decompression Record Count 1

0x30 R Compression Byte Count 0

0x31 R Compression Byte Count 1

0x32 R Compression Byte Count 2

0x33 R Compression Byte Count 3

0x34 R/W Compression Control Prearm

0x35 R/W Pattern

0x38 R/W Decompression Control Prearm
0x3A R/W Decompression Reserved 2 Reserved 0x00 No

0x3F Reserved Reserved 0x0F No

Engine, Decompression
Engine Empty Status,
Dictionary Reset, Enable
Pass-Through Mode

Line Length Register Lower
8bits
Line Length Register Upper
3bits

Compressor number of
records in a transfer

Compressor number of
records in a transfer
Compression EOT Interrupt,
Decompression EOT Interr upt
Interrupt Mask bits for CEOT,
DEOT

Decompressor number of
records in a transfer
Decompressor number of
records in a transfer
Compressed byte count,
byte 0

Compressed byte count,
byte 1
Compressed byte count,
byte 2
Compressed byte count,
byte 3

Prearm Register for
Compression Control
8-bit pattern for blank record
generation
Prearm Register for
Decompression Control

AFTER

RSTN

0x04 Yes

Undefined No

Undefined No

0xFF No

0xFF No

0x00 No

0xFF No

0xFF No

0xFF No

0x00 No

0x00 No

0x00 No

0x00 No

0x00 No

Undefined No

0x00 No

PREARM

Page 16 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

4.1 SYSTEM CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE

Address

0x00

After reset, its c ontents are undefined . It must be written be fore any input or out put data movement may
be performed.

COMP BIG-Selects between little or big endian byte order for the compressor. See table.
DECOMP BIG-Selects between little or big endian byte order for the decompressor. See table.
REVERSE BYTE- When this bit is one the byte data entering the compressor is re ver sed. Bit0 is swapped

res - Bits must always be written with zeros.
WIDE - Selects between 32 and 16-bit D buses.

COMP BIG or
DECOMP BIG

0 0 Little Endian data order 16-bit words

0 1 Little Endian data order 32-bit words

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

res

with bit7, bit1 is swapped with bit6, bit2 is swapped with bit5, etc. . .

WIDE

res

REVERSE

BYTE

DECOMP

BIG

WIDE DESCRIPTION

D[15:8] D[7:0]

Byte 1 Byte 0

D[31:24] D[23:16] D[15:8] D[7:0]

Byte 3 Byte 2 Byte 1 Byte 0

COMP

BIG

1 0 Big Endian data order 16-bit words

D[15:8] D[7:0]

Byte 0 Byte 1

1 1 Big Endian data order 32-bit words

D[31:24] D[23:16] D[15:8] D[7:0]

Byte 0 Byte 1 Byte 2 Byte 3

4.2 SYSTEM CONFIGURATION 1, ADDRESS 0x01 - READ/WRITE

Address

0x01

This register is cleared by reset.
DSC[2:0] - Data Strobe Condition. Control the condition used to str obe da ta into and out of the data ports

res - Bits must always be written with zeros.
ERC - EOR Request Control. Determines when COREQN and DOREQN deassert at an End-of-

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

res

on the D bus. T a ble 4 shows the p rogramming for t he strobe cond ition for va rious DMA modes.

Record. If ERC=0, then the req uest deasser ts asynchronou sly during the clock when an EOR is
strobed out. If ERC=1, then the request deasserts synchronously the clock after an EOR is
strobed out. See Figure 18 through Figure 21.

VDIE VDOE ERC

res

DSC[2:0]

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Advanced Hardwar e Architectures, Inc.

VDOE - VDO Port Enable. When this bit is set, the data from the decompression output FIFO goes to

the VDO port. When the bit is clear, the decompressed data is read by DMA on the D bus.

VDIE - VDI Port Enable. When this bit is s et, the VDI port handshakes data and writes it into the

compression input FIFO. Whe n the bit is clea r , the compres sion input FIFO is wri tten by DMA
from the D bus.

4.3 INPUT FIFO THRESHOLDS, ADDRESS 0x02 - READ/WRITE

Address

0x02 IFT[3:0] IET[3:0]

After reset, its c ontents are undefined . It must be written be fore any input or out put data movement may
be performed.

IET[3:0] - Empty threshold for input FIFOs. If the number of words in the input FIFO (CI or DI) is less

IFT[3:0] - Full threshold for input FIFOs. If the number of words in the input FIFO (CI or DI) is greater

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

than or equal to this numb er, the request for that channel is asserted.

than or equal to this number, the re quest for the channel is deas serted.

4.4 OUTPUT FIFO THRESHOLDS, ADDRESS 0x03 - READ/WRITE

Address

0x03 OFT[3:0] OET[3:0]

After reset, its c ontents are undefined . It must be written be fore any input or out put data movement may
be performed.

OET[3:0] - Empty threshold for output FIFOs. If the numb er of words in the output FIF O (CO or DO) is

OFT[3:0] - Full threshold for output FIFOs. If the number of words in the output FIFO (CO or DO) is

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

less than or equal to this number , the reques t for the chann el is deassert ed (except in the ca se of
an End-of-Record).

greater than or equal to th is number, the request for that channel is asserted.

4.5 COMPRESSION PORTS STATUS, ADDRESS 0x04 - READ ONLY

Address

0x04 COEMP CIEMP res CEOR COREQ COET CIREQ CIFT

This is a read only register. Writing to this re giste r has no eff ect. Af ter re set, its content s are undef ined.
CIFT - Compression input FIFO full thr esh old. This signal is active when the CI FIFO is greater th an

CIREQ - Compression input request signal state. Reports the current state for the CIREQN pin. Notice

COET - Compression output FIFO empty th reshold. This bit is acti ve when the CO FIFO is l ess than or

Page 18 of 50 PS3411-0600

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

or equal to the programmed FIFO full threshold. After reset and the Input FIFO Threshold
register has been written, this bit contains a zero.

that this bit is active high while the pin is active low. Therefore, the value of this bit is always
the inverse of the value of the signal. After reset this bit contains a zero.

equal to the programmed FIFO empty threshold. After reset and the Output FIFO Threshold
register has been written, this bit contains a one.

Advanced Hardware Architectures, Inc.

COREQ - Compression output request signal state. Repor ts the current stat e for the COREQN pin. Notice

that this bit is active high while the pin is active low. Therefore, the value of this bit is always
the inverse of the value of the signal. After reset this bit contains a zero.

CEOR - Compression output end of record. Thi s bit is act ive when the output FIF O contai ns the end-of -

record code. After reset this bit contains a zero.
res - Bits must always be written with zeros.
CIEMP - Compression input empty. This bit is active when the CI FIFO is empty. After reset this bit

contains a one.
COEMP - Compression output empty. This bit is active when the CO FIFO is empty. After reset this bit

contains a one.

4.6 DECOMPRESSION PORTS STATUS, ADDRESS 0x05 - READ ONLY

Address

0x05 DOEMP DIEMP res DEOR DOREQ DOET DIREQ DIFT

This is a read only register. Writing to this re giste r has no eff ect. Af ter re set, its content s are undef ined.

DIFT - Decompression input FIFO full th reshold. This signal i s active when the DI FIFO i s at or a bove

DIREQ - Decompression input request signal st ate. Reports t he current stat e for the DIREQN pi n. Notice

DOET - Decompression output FIFO empty threshold. This bit is active when the D O FIFO is at or

DOREQ - Decompression output request signal state. Reports the current state for the DOREQN pin.

DEOR - Decompression output end of record. This bit is active when th e output FIFO contai ns the End-

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

the progra mmed FIFO full threshold. After reset and the Input FIFO Threshold register has

been written, this bit contains a zero.

that this bit is active high while the pin is active low. Therefore, the value of this bit is always

the inverse of the value of the signal. After reset this bit contains a zero.

below the programmed FIFO empty threshold. After reset and the Output FIFO Threshold

register has been written, this bit contains a one.

Notice that this bit is active high while the pin is active low. Therefore, the value of this bit is

always the inverse of the value of the signal. After reset this bit contains a zero.

of-Record code. After reset this bit contains a zero.

DIEMP - Decompression input empty. This bit is active when the DI FIFO is empty. After reset this bit

contains a one.
DOEMP - D ecompression output empty. This bit is active when the DO FIFO is empty . After reset this bit

contains a one.

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Advanced Hardwar e Architectures, Inc.

4.7 PORT CONTROL, ADDRESS 0x06 - READ/WRITE

Address

0x06 res DORST DIRST CORST CIRST

This register is initialized to 0x0F after reset.

CIRST - Compression input reset. Setting this bit to a one resets the CI FIFO and clears state machines

CORST - Compression output reset. Setting this bit to a one resets the CO FIFO and clears state machines

DIRST - Decompression input reset. Setting this bit to a one resets the DI FIFO and clears the state

DORST - Decompression output reset. Setting this bit to a one resets the DO FIFO and clears the state

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

on the compression input port. The reset condition remains active until the microprocessor

writes a zero to this bit.

on the compression output port. The reset condition remains active until the microprocessor

writes a zero to this bit.

machines in the decompression input port. The reset condition remains active until the

microprocessor writes a zero to this bit.

machines in the decompression output port. The reset condition remains active until the

microprocessor writes a zero to this bit.

4.8 INTERRUPT STATUS/CONTROL 1, ADDRESS 0x07 - READ/WRITE

Address

0x07 DOUF COUF DIOF CIOF res DERR DEOR CEOR

This register is initialized to 0x00 after reset.

CEOR- Compression End-of-Record interrupt. This bit is set when an End-of-Record codeword is

DEOR - Decompression End-of-Recor d interrupt. This bit is set when the last byte of a recor d is strobed

DERR - Decompression Error. This bit is set if an EOR leaves the decompressor before DRLEN has

res - Bits must always be written with zeros.
CIOF - Compression Input FIFO Overflow. This interrupt is gen er ate d when a write to an already full

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

strobed out of the com pression output port. The microprocessor must write a one to this bit to

clear this interrupt.

out of the decompression DMA or video output port. The microprocessor must write a one to

this bit to clear this interrupt.

counted down to zero or if DRLEN counts to zero and the last byte is not an EOR. DERR is

only active in decompression mode (DPASS=0). The microprocessor must write a one to this

bit to clear this interrupt.

CI FIFO is performed. Data written in this condit ion is lost. The only means of recovery fr om

this error is to reset the FIF O with the CIRST bit. Resettin g the FIFO causes this interrupt to

clear. CIREQN is inactive while the interrupt is set.
DIOF - Decompression Input FIFO Overflow. This interrupt is generated when a write to an already

full DI FIFO is performed . Data written in this condition is lost. The only means of recovery

from this error is to reset the FIFO with the DIRST bit. Resetting the FIFO causes this interrupt

to clear. DIREQN is inactive while the interrupt is set.

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COUF - Compression Output FIFO underflow. This interrupt is generated when a read from an empty

CO FIFO is performed. Once this interrupt is set, the CO FIFO must be reset with the CORST

bit. The micropro cessor must wri te a one t o this bit, to clear this inter rupt. COREQN is ina ctive

while the interrupt is set.
DOUF - Decompression Output FIFO underflow . Th is interrupt is generated when a read from an empt y

DO FIFO is performed. Once this interrupt is set, the DO FIFO must be reset with the DORST

bit. The microprocessor mus t write a one to this bit, to clear this interrupt. DOREQN is inacti ve

while the interrupt is set.

4.9 INTERRUPT MASK 1, ADDRESS 0x09 - READ/WRITE

Address

0x09 DOUFM COUFM DIOFM CIOFM res DERRM DEORM CEORM

This register is initiali zed to 0xFF after reset.

CEORM - Compression End-of-Recor d Interrupt Mas k. When set to a one, prevent s Compression End-of-

DEORM - Decompression End-of-Record Interrupt Mask. When set to a one, prevents Decompression

DERRM - Decompression Error Mask. When set to a one, prevents a decompressi on er ro r (DERR) fro m

res - Bits must always be written with zeros.
CIOFM - Compression Input FIFO Overflow Mask. When set to a one, prevents a compression input

DIOFM - Decompression Input FIFO Overflow Mask. When set to a one, prevents a decompression

COUFM - Compression Output FIFO Underflow Mask. When se t to a one, prevents a compress ion output

DOUFM - Decompression Output FIFO Underflow Mask. When set to a one, prevents a decompression

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Record from causing INTRN to go active.

End-of-Record from causing INTRN to go active.

causing INTRN to go active.

FIFO overflow (CIOF) from causing INTRN to go active.

input FIFO overflow (DIOF) from causing INTRN to go acti ve.

FIFO underflow (COUF) from causing INTRN to go active.

output FIFO underflow (DOUF) from causing INTRN to go active.

4.10 VERSION, ADDRESS 0x0A - READ ONLY

Address

0x0A VERSION[7:0]

VERSION[7:0] - Contains version number of the die.

PS3411-0600 Page 21 of 50

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Advanced Hardwar e Architectures, Inc.

4.11 DECOMPRESSION RECORD LENGTH, ADDRESS 0x0C, 0x0D, 0x0E, 0x0F -

READ/WRITE

Address

0x0C DRLEN[7:0]
0x0D DRLEN[15:8]
0x0E DRLEN[23:16]
0x0F DRLEN[31:24]

These registers are initialized to 0xFF after reset.

DRLEN[31:0]-Decompression Record Length. Contains the number of bytes in a decompressed record.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

These registers provide different functions depending on whether the decompressor is in pass-

through or decompression mode. In decompress mode, the data itself contains EOR

information and DRLEN is only used for error checking. DRLEN is decremented each time a

byte leaves the decompressor.

In decompression mode, a DERR interrupt is issued if an EOR is not read out of the

decompressor when the counter expires or if an EOR occurs before the counter expires (i.e.,

when the record lengths do not match). If the DERR interrupt is masked, use of the DRLEN

register is optional in decompression mode.

In pass-through mode, DRLEN determines the size of records read out of the decompressor.

The counter is decremented for each byte read into the decompressor.

In either mode, the counter reloads when it reaches zero or when DRLEN[31:24] is written.

Reading DRLEN returns the number of bytes left in the count. The lower three bytes of this

register may be prearmed since the counter is automatically reloaded at the end of a record

when the part is not progra mmed to pause on End-of-Re cord. The upper byte i s not prearmable

since writing to this byte triggers an immediate reload to the counter.

4.12 COMPRESSION RECORD LENGTH, ADDRESS 0x10, 0x11, 0x12, 0x13 - READ/

WRITE

Address

0x10 RLEN[7:0]
0x11 RLEN[15:8]
0x12 RLEN[23:16]
0x13 RLEN[31:24]

These regi sters are unde fined after reset.

RLEN[31:0]-Record Length. Length of an uncompressed record in bytes. Writing these addresses sets a

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

register containi ng the l ength of a reco rd. Readi ng thes e addre sse s retu rns a co unter i ndica ting

the number of bytes remaining in the current record. The counter is decremented each time a

byte leaves the CI FIFO. The counter automatically reloads from the register at the end of a

record. The counter is also reloaded when RLEN[31:24] is written. The re cord length register

is also valid during pass-through operation. The lower three bytes of this register may be

prearmed since the cou nter is aut omatically r eloaded at the end of a re cord when the pa rt is not

programmed to pause on End-of -Record. The upp er byte is not prearmable si nce writing to t his

byte triggers an immediate reload to the counter.

The minimum value for RLEN is 4.

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4.13 COMPRESSION CONTROL, ADDRESS 0x14 - READ/WRITE

Address

0x14 CPREARM res CPOT CPASS CDR CEMP COMP CPOR

This register is initialized to 0x04 after reset.

CPOR - Compression Pause on record boundaries. When this bit is set to one, the compressor stops

COMP - Compression. Setting this bit to a one enables the data compression engine (or pass-through

CEMP - Compression engine empty. This bit is set to a one when no data is present inside the

CDR - Compression Dictionary Reset. Setti ng this bit immediate ly resets the compress or including th e

CPASS - Compression pass-through mode. While this bit is set, data is passed directly through the

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

taking data from the input FIFO once a record boundary is found. A record boundary is

indicated by the RLEN register decrementing to zero. Upon finding the record boundary,

COMP is cleared. This bit may only be changed when COMP is set to zero. After system reset,

this bit is cl eared.

mode if CP ASS is set) to take data from the compression input FIFO. If this bit is cleared,

compression stops. The bit is automatically cleared at the end of a record if CPOR is set or at the

end of a transfer if CPOT is set. The compression can be restarted without loss of data by setting

COMP. After reset, this bit is cleared.

compressor. Writing to this bit has no effect. After system re set, this bit i s set.

compression dictionary. The reset condition remains active until the microprocessor writes a

zero to this bit.

compression engine without any effect on either the dictionary or the data itself. This bit may

only be changed when compression is disabled (COMP=0) and the compression engine is

empty of data (CEMP=0). The p ass -through operation is started by setti ng COMP. To s top the

pass-through operat ion, COMP should be cleared (t o pause opera tion) and then CPASS may be

cleared.
CPOT - Compression Pause on Transfer boundaries. When this bit is set the compressor stops taking

data from the input FIFO once the end of transfer is reached indicated by the Record Counter

decrementing to zero. Upon finding the End of Transfer boundary the COMP bit is cleared.

CPOT can only be set when COMP is cl eared.
res - Bits must always be written with zeros.
CPREARM -Prearm Enable. When this bit is set, Compression Control Prearm register is loaded into the

Compression Control regi ster when the next end of record leaves the compressor. The prearm

does not occur if there is any data in the compressor to prevent data corruption.

4.14 COMPRESSION RESERVED, ADDRESS 0x15 - READ/WRITE

Address

0x15 res

This register is used for production testing. Must be written with zero if at all. Resets to zero.

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

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4.15 COMPRESSION LINE LENGTH, ADDRESS 0x16, 0x17 - READ/WRITE

Address

0x16 LINE[7:0]
0x17 res LINE[10:8]

This register contains information necessary for the compression operation. It must be set prior to any
compression operation. It should only be changed when COMP is cleared and CEMP is set. After changing
compression configuration, the compressor should be reset using CDR. These registers are undefined after reset.

res - Bits must always be written with zeros.
LINE[10:0]-Line length. The number of bytes in the scan line is programmed here.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Minimum value is 16.

4.16 DECOMPRESSION CONTROL, ADDRESS 0x18 - READ/WRITE

Address

0x18 DPREARM DBLANK DPOT DPASS DDR DEMP DCOMP DPOR

This register is initialized to 0x04 after reset. This register can be prearmed.
DPOR - Decompression Pause on record boundaries. When th is bit is set to on e, the decompressor sto ps

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

taking data from the input FIFO once a record boundary is found. Upon finding the record
boundary , DCOMP is cleared . This bit may only be changed wh en DCOMP is set to zero. After
system reset or DDR, this bit is cleared.

DCOMP - Decompression. Setting this bit to a one enables the decompression engine (or pass-through

mode if DPASS is set) to take data from the decompression input FIFO. If this bit is cleared,
decompression stops. The bit is automatically cleared at the end of a record if DPOR is set.
Decompression can be r est ar te d wit hout loss of data by setting DCOMP. After system reset o r
DDR, this bit is cleared.

DEMP - Decompression engine empty. This bit is set when the dec ompression engi ne is cleared of dat a.

Writing to this bit h as no effect. After system reset, this bit is set.

DDR - Decompression Dictionary Reset. Setting this bit immediately resets the decompressor

including the decompression dictionary. The reset condition remains active until the
microprocessor writes a zero to this bit.

DPASS - Decompression pass-through mode. While this bit is set, data is passed directly through the

decompression engine without any effect on the data. This bit may only be changed when
decompression is disabled (DCOMP=0) and the decompression engine is empty of data
(DEMP=1). The pass-th rough operat ion is sta rted by sett ing DCOMP. To stop t he pass-thr ough
operation, DCOMP should be cleared (to pause operation) and then DPASS may be cleared.

DPOT - Decompression Pause on Transfer Boundaries. When this bit is set the decompressor stops

taking data from the input FIFO once a decompression end of transfer boundary is found
indicated by the Decompression Record Counter decrementing to zero.

DBLANK -Decompression Blank record. The data in the next record output from the decompressor is a

repeating byte pattern using the 8-bit data defined in the PATTERN register. DBLANK
automatically clears at the end of the record when the Decompression Record Count
decrements to zero. When using DBLANK to generate a blank record the device must not
contain data to be decompressed an d the syste m must not send data to be dec ompressed for a ny
future records until the part has reached the End-of-Record for the blank record.

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DPREARM -Prearm Enable. When this bit i s set, Decompre ssion Control Prearm regi ster is lo aded into the

Decompression Control register when the next end of record leaves the decompressor. The
prearm does not occur if there is any data in the decompressor to prevent data corruption.

4.17 DECOMPRESSION RESERVED, ADDRESS 0x1A - READ/WRITE

Address

0x1A res
0x3A res

This regist er is used for production tes ting only. Must be written wi th zero if at all. Initialized to 0x00
after reset.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

4.18 DECOMPRESSION LINE LENGTH, ADDRESS 0x1C, 0x1D - READ/WRITE

Address

0x1C LINE[7:0]
0x1D res LINE[10:8]

This register conta ins information necessary for the decompression opera tion. It must be set prior to any
decompression operati on. It sho uld only be ch anged bet ween rec ords when DCOMP is clear ed and DEMP
is set. These registers are undefined af ter reset.

res - Bits must always be written with zeros.
LINE[10:0]-Line length. The number of bytes in the scan line is programmed here.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Minimum value is 16. For scan line lengths larger than the maximum allowed, set to 16.

4.19 COMPRESSION RECORD COUNT, ADDRESS 0x20, 0x21 - READ/WRITE

Address

0x20 RC[7:0]
0x21 RC[15:8]

These registers are initialized to 0xFFFF after reset.
RC[15:0] - Record Count is the number of records in the current transfer. This counter is decremented as

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

the last byt e of a record is compressed.

4.20 INTERRUPT STATUS/CONTROL 2, ADDRESS 0x27 - READ/WRITE

Address

0x27 res DEOT CEOT

This register is initialized to 0x00 after reset.
CEOT - Compression End-of-Transfer Interrupt. This bit is set when an end of transfer condition is

DEOT - Decompression End-of-Trans fer Interr upt. This bit is s et when a deco mpression end of transfer

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

reached indicated by the compression Record Counter counting down to zero. The
microprocessor must write a one to this bit to clear this interrupt.

condition is reached indicated by the Decompression Record Counter counting down to zero.
The microprocessor must w rite a one to this bit to clear this interrupt.

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4.21 INTERRUPT MASK 2, ADDRESS 0x29 - READ/WRITE

Address

0x29 res DEOTM CEOTM

This register is initiali zed to 0xFF after reset.
CEOTM - Compression En d-of-Transfer Interrupt Mask. When set to a one, prevents Compression End-

DEOTM - Decompression End-of-Transfer Interrupt Mask. When set to a one, prevents Decompression

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

of-Transfer from causing INTRN to go active.

End-of-Transfer from causing INTRN to go active.

4.22 DECOMPRESSION RECORD COUNT, ADDRESS 0x2C, 0x2D - READ/WRITE

Address

0x2C DRC[7:0]
0x2D DRC[15:8]

These registers are initialized to 0xFFFF after reset.
DRC[15:0] -Decompression Record Count is the number of records in the current transfer. Expiration of

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

this counter causes a CEOT interrupt to be posted.

4.23 COMPRESSION BYTE COUNT, ADDRESS 0x30, 0x31, 0x32, 0x33 - READ/WRITE

Address

0x30 BCNT[7:0]
0x31 BCNT[15:8]
0x32 BCNT[23:16]
0x33 BCNT[31:24]

BCNT[31:0]-Compressed Byte Count is the number of bytes output from the CO FIFO, rounded up to a

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

word boundary defined by WIDE, for the current record. Systems may use this data to remove
pad words from the compressed data stream. The count gets reset at the beginning of each
record and when CORST is active.

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4.24 COMPRESSION CONTROL PREARM, ADDRESS 0x34 - READ/WRITE

Address

0x34 NCPREARM

This register is initialized to 0x04 after reset.
res - Bits must always be written with zeros.

See Compression Control register for bit descriptions. This register is the prearm register for the
Compression Control register.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

res

NCPOT NCPASS NCDR

res

NCOMP NCPOR

4.25 PATTERN, ADDRESS 0x35 - READ/WRITE

Address

0x35 PATTERN[7:0]

This register is undefined after reset.
P ATTERN[7:0]-Pattern is the 8-bit data used to generate blank bands or rec ords. If DBLANK is set, t he part

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

outputs this register value repeatedly for the entire record (or band).

4.26 DECOMPRESSION CONTROL PREARM, ADDRESS 0x38 - READ/WRITE

Address

0x38 NDPREARM NDBLANK NDPOT NDPASS NDDR res NDCOMP NDPOR

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

This register initializes to 0x00 after reset.
res - Bits must always be written with zeros.

4.27 DECOMPRESSION RESERVED, ADDRESS 0x3A - READ/WRITE

Address

0x1A res
0x3A res

This regist er is used for production tes ting only. Must be written wi th zero if at all. Initialized to 0x00
after reset.

res - Bits must always be written with zeros.

See Decompression Control re gister for bit descriptions. This register is the prearm register for the
Decompression Control register.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

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5.0 SIGNAL DESCRIPTIONS

This section contains descriptions for all the pins. Each signal has a type code associated with it. The
type codes are described in the following table.

TYPE CODE DESCRIPTION

I Input only pin

O Output only pin

I/O Input/Output pin

S Synchronous signal

A Asynchronous signal

5.1 MICROPROCESSOR INTERFACE

MICROPROCESSOR INTERFACE

SIGNAL TYPE DESCRIPTION

PD[7:0] I/O

S

PA[5:0] I

S

CSN I

S

DIR I

S

RDYN O

A,S

INTRN O

S

PROCMODE[1:0] I

S

Processor Data. Data for all microprocessor reads and writes of
registers within AHA34 11 are performed on this bus. This bus ma y
be tied to the Data bus, D[31:0], provided microprocessor accesses
do not occur at the same time as DMA accesses.

Processor Address Bus. Used to address internal registers within
AHA3411.

Chip Select. Selects AHA3411 as the source or destination of the
current microprocesso r bus c ycle. CSN needs only be ac tive for one
clock cycle to start a microprocessor access.

Direction. This signal indicates whether the access to the register
specified by the P A bus is a read or a write. The polarity of this signal
is programmed with the PROCMODE0 pin.
Ready. Indicates valid data is on the data bus during read operation
and completion of write operation. Its operation depends on
PROCMODE[1:0] settings.
Interrupt. The compression and decompression processes generate
interrupts that are reported with this signal. INTRN is low whenever
any non-masked bits are set in the Interrupt Status/Control

Microprocessor Port Confi guration Mode. Selects the polarity of the
DIR pin and operation of the CSN pin. Refer to Section 2.1

Microprocessor Interface for details. (Figure 2 through Figure 5)

register.

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5.2 DATA INTERFACE

DATA INTERFACE

SIGNAL TYPE DESCRIPTION

D[31:0] I/O

S

DRIVEN I

A

SD I

S

CIREQN O

S

CIACKN I

S

COREQN O

A,S

COACKN I

S

COEORN O

S

COEOTN O

S

DIREQN O

S

DIACKN I

S

DOREQN O

A, S

DOACKN I

S

Data for all channels is transmitted on this bus. The ACKN is used to
distinguish between the four channels. Dat a being written to AHA341 1 is
latched on the rising edge of CLOCK when the strobe condition is met.
Data setup and hold times a re relative to CLOCK. If the bus is configured
to 16-bit transfers (WIDE=0), data is carried on D[15:0]. In this case,
D[31:16] should be terminated with pullup resistors.
Drive Enable. Active low output dri ver enable. Thi s input must be low in
order to drive data onto D[31:0] in accordance with the current strobe
condition.

Strobe Delay . Active high. Allows insertion of wait states for DMA
access to the FIFOs. The strobe condition, as programmed in the DSC
field of System Configuration 1, enables this signal and selects its
polarity.

Compression Input Data Request , active low. This signal, when active,
indicates the ability of the CI FIFO to accept data.

Compression Input Data Acknowle dge. Active low. This signal, when
active, indicates the data on D is for the compression input FIFO. Data on
D is latched on the rising edge of CLOCK when the strobe condition is
met.

Compressio n Output Data Request, active low. When this signal is
active, it indicates the a bility of the CO FIFO to tran smit data.

Compression Output Data Acknowledge. Active low. The defi nition of
COACKN varies with the data strobe condition in System
Configuration 1. See Table 4.
Compression Output End-of-Record, active low. COEORN is active
when the word curren tl y on the out put of the CO FIFO contains an End­of-Record.
Compression Output End-of-Transfer, active low. COEOTN is active
when the word currentl y on the out put of the CO FIFO c ontains t he End­of-Transfer.

Decompression Input Data Request, active low. When this signal is
active, it indicates the ability of the DI port to accept data.

Decompression Input Data Acknowledge. Active low decompression
data input. When t his signa l is acti ve, it ind icate s the dat a on D is for the
decompression input port. Data on D is latched on the rising edge of
CLOCK when the strobe condition is met.

Decompression Output Data Request, active low. When this signal is
active, it indicates the ability of the DO port to transmit data.

Decompression Output Data Acknowledge . The definition of DOACKN
varies with the data strobe condition in System Configuratio n 1. See
Table 4.

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5.3 VIDEO INTERFACE

VIDEO INTERFACE

SIGNAL TYPE DESCRIPTION

VIREQN O

S

VIACKN I

S

VID[7:0] I

S

VOREQN O

S

VOACKN I

S

VOD[7:0] O

S

VOEORN O

S

VOEOTN O

S

Video Input Request. Active low output indicating that the VDI port is
ready to accept another byte on VID[7:0].

Video Input Acknowledge. Active low input indicating that VID[7:0] is
being driven with a valid byte.

Video Input Data. The value on this input bus is written into AHA3411
when both VIREQN and VIACKN are active.

Video Output Request. Active low output indicating that the byte on
VOD[7:0] is valid.

V ideo Output Acknowledge. Active l ow input indicating that the external
system is ready to read VOD[7:0].

Video Output Data. The value on this output bus is read when both
VOREQN and VOACKN are low.

Video Output End of Record is active low indicating the byte on
VOD[7:0] contains the last byte in a record.

Video Output End of Transfer is active low indicating the byte on
VOD[7:0] contains the last byte in a multi-record transfer.

5.4 SYSTEM CONTROL

SYSTEM CONTROL

SIGNAL TYPE DESCRIPTION

CLOCK I System Clock. This signal is connected to the clock of the

microprocessor. The Intel i960Cx calls this pin PCLK.

RSTN I

A

TEST0 I

A

TEST1 I

A

Power on Reset. Active l ow rese t si gnal. AHA3411 must be reset before
any DMA or microprocessor activity is attempted. RSTN should be a
minimum of 10 CLOCK periods.

Board Test mode. When TEST is high, all outputs are tristated. When
TEST is low, the chip performs normally.

Used for production tests. This input should always be tied low.

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6.0 PINOUT

PIN SIGNAL PIN SIGNAL PIN SIGNAL

1 VID[4] 44 VSS 87 VOD[7]
2 VID[3] 45 VSS 88 COEORN
3 VID[2] 46 VDD 89 VDD
4 VID[1] 47 CLOCK 90 VSS
5 VID[0] 48 VSS 91 VOACKN
6 INTRN 49 VDD 92 TEST0
7 VSS 50 VDD 93 PA[0]
8 VDD 51 VSS 94 PA[1]

9 DRIVEN 52 VDD 95 PA[2]
10 SD 53 D[15] 96 PA[3]
11 DOACKN 54 D[16] 97 VDD
12 COACKN 55 D[17] 98 PA[5]
13 DIACKN 56 D[18] 99 VSS
14 CIACKN 57 D[19] 100 PA[4]
15 VSS 58 D[20] 101 COEOTN
16 VDD 59 D[21] 102 VOEOTN
17 DOREQN 60 D[22] 103 PROCMODE[1]
18 COREQN 61 D[23] 104 PROCMODE[0]
19 DIREQN 62 D[24] 105 CSN
20 CIREQN 63 VSS 106 VDD
21 VIREQN 64 VDD 107 VSS
22 D[0] 65 D[25] 108 DIR
23 VSS 66 D[26] 109 RSTN
24 VSS 67 D[27] 110 PD[7]
25 VDD 68 D[28] 111 PD[6]
26 VDD 69 D[29] 112 PD[5]
27 D[1] 70 D[30] 113 VDD
28 D[2] 71 VDD 114 VSS
29 D[3] 72 VDD 115 PD[4]
30 D[4] 73 VSS 116 PD[3]
31 D[5] 74 VSS 117 PD[2]
32 D[6] 75 D[31] 118 PD[1]
33 D[7] 76 VOREQN 119 PD[0]
34 D[8] 77 VOEORN 120 VDD
35 D[9] 78 VOD[0] 121 VSS
36 D[10] 79 VOD[1] 122 RDYN
37 D[11] 80 VOD[2] 123 VIACKN
38 VSS 81 VDD 124 VID[7]
39 VDD 82 VSS 125 VID[6]
40 D[12] 83 VOD[3] 126 VID[5]
41 D[13] 84 VOD[4] 127 VDD
42 D[14] 85 VOD[5] 128 VSS
43 TEST1 86 VOD[6]

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Figure 16: Pinout

Advanced Hardwar e Architectures, Inc.

PA[3]

PA[2]

PA[1]

PA[0]

TEST0

VOACKN

VSS

VDD

COEORN

VOD[7]

VOD[6]

VOD[5]

VOD[4]

VOD[3]

VSS

VDD

VOD[2]

VOD[1]

VOD[0]

VOEORN

VOREQN

D[31]

VSS

VSS

VDD

VDD

D[30]

D[29]

D[28]

D[27]

D[26]

D[25]

VDD

PA[5]

VSS

PA[4]
COEOTN
VOEOTN

PROCMODE[1]
PROCMODE[0]

CSN
VDD

VSS

DIR
RSTN
PD[7]
PD[6]
PD[5]

VDD

VSS
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]

VDD

VSS

RDYN

VIACKN

VID[7]
VID[6]
VID[5]

VDD

VSS

96959493929190898887868584838281807978777675747372717069686766

97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

AHA3411A-033 PQC

65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VDD
VSS
D[24]
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
VDD
VSS
VDD
VDD
VSS
CLOCK
VDD
VSS
VSS
TEST1
D[14]
D[13]
D[12]
VDD
VSS
D[11]
D[10]
D[9]
D[8]
D[7]

12345678910111213141516171819202122232425262728293031

SD

VSS

VID[4]

VID[3]

VID[2]

VID[1]

VDD

VID[0]

INTRN

DRIVEN

DOACKN

COACKN

DIACKN

CIACKN

VSS

VDD

DOREQN

COREQN

D[0]

VSS

VIREQN

DIREQN

CIREQN

D[1]

D[2]

D[3]

VSS

VDD

VDD

D[4]

32

D[5]

D[6]

Page 32 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

7.0 DC ELECTRICAL SPECIFICATIONS

7.1 OPERATING CONDITIONS

OPERATING CONDITIONS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Vdd Supply voltage 4.75 5.25 V

Idd Supply current (active) 380 mA 4
Idd Supply current (standby) 80 mA 1, 4, 5
Idd Supply current (low power) 1 mA 2, 4

Ta Ambient temperature 0 70 °

Input low voltage:

Vil

Vih

Iil Input leakage current -10 10 µA

Vol Output low voltage (Iol=-4mA) 0.4 V

Voh Output high voltage (Ioh=4mA) 2.4 V
Voh Output high voltage (Ioh=100µA) Vdd-0.8 V

Iol Output low current 4 mA

Ioh Output high current -4 mA
Ioz Output leakage current during tristate -10 10 µA

Cin Input capacitance 5 pF

Cout Output capacitance 7 pF

Cio Input/Output capacitance 7 pF

Comax

PROCMODE[1:0], TEST0, TEST1
Other signals

Input high voltage:

PROCMODE[1:0], TEST0, TEST1
Other signals

Maximum capacitance load for all
signals (including self loading)

Vss-0.5
Vss-0.5

0.7×Vdd

2.0

0.3×Vdd

0.8

Vdd+0.5
Vdd+0.5

50 pF 3

C

V
V

V
V

Notes:

1) Dynamic current; no data transfers

2) Static current (clock high)

3) Timings referenced to this load

4) ILOAD=0 mA

5) Not tested in Production

7.2 ABSOLUTE MAXIMUM STRESS RATINGS

ABSOLUTE MAXIMUM STRESS RATINGS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Tstg Storage temperature -50 150 °C
Vdd Supply voltage -0.5 7 V

Vin Input voltage Vss-0.5 Vdd+0.5 V

PS3411-0600 Page 33 of 50

Advanced Hardwar e Architectures, Inc.

8.0 AC ELECTRICAL SPECIFICATIONS

Notes:

1) Production test condition is 50 pF. Output delay is decreased 2 ns with 25 pF load guaranteed by design or
characterization.

2) All timings are referenced to 1.4 volts.

Figure 17: Data Interface Timing

CLOCK

1 2

ACKN,

SD

3 4

Valid

6

Valid 1

REQN

D, COEORN,

COEOTN

D

5

7

8

Valid 0

Table 6: Data Port Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 CIACKN, DIACKN, COACKN, DOACKN and SD setup time 8 ns
2 CIACKN, DIACKN, COACKN, DOACKN and SD hold time 2 ns
3 D-bus input setup time 8 ns
4 D-bus input hold time 2 ns
5 REQN delay (non-EOR case) 18 ns
6 REQN hold (non-EOR case) 2 ns
7 D-bus, COEORN, COEOTN output delay 16 ns
8 D-bus, COEORN, COEOTN output hold 3 ns

Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=0

CLOCK

SD

ACKN

1

2

REQN

D

EOR-1 EOR

Page 34 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=1

CLOCK

SD

ACKN

2

REQN

D

EOR-1 EOR

Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0

CLOCK

SD

ACKN

2

REQN

D

EOR-1 EOR

Figure 21: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1

CLOCK

SD

ACKN

2

REQN

D

EOR-1 EOR

PS3411-0600 Page 35 of 50

Advanced Hardwar e Architectures, Inc.

Tab le 7: Request vs. EOR Timing

NUMBER PARAMETER MIN MAX UNITS

1 ACKN, SD to REQN ERC=0 16 ns
2 CLOCK to REQN ERC=0 16 ns

Figure 22: Output Enable Timing

CLOCK

ACKN

DRIVEN

D

1 3 4 5

2

Tab le 8: Output Enable Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 DRIVEN to D valid 15 ns
2 DRIVEN to D tristate 10 ns
3 Signal to D valid 15 ns
4 Signal to D trista te 10 ns
5 CLOCK to D tristate (DSC=100, 101) 15 ns

Figure 23: Video Input Port Timing

CLOCK

VIREQN

1

VIACKN

3

VID[7:0]

2

4

65

Table 9: Video Input Port Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 VIREQN delay 16 ns
2 VIREQN hold 2 ns
3 VIACKN setup 8 ns
4 VIACKN hold 2 ns
5VID setup 8 ns
6 VID hold 2 ns

Page 36 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure 24: Video Output Port Timing

CLOCK

VOREQN

VOACKN

VOD[7:0]

1 2

43

5

6

VOEORN,

VOEOTN

7 8

T a ble 10: Video Output Port Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 VOREQN delay 16 ns
2 VOREQN hold 2 ns
3 VOACKN setup 8 ns
4 VOACKN hold 2 ns
5 VOD delay 16 ns
6 VOD hold 2 ns
7 VOEORN, VOEOTN hold 2 ns
8 VOEORN, VOEOTN delay 16 ns

Figure 25: Microprocessor Interface Timing (PROCMODE[1]=0)

234512

CLOCK

11212

PA

Valid

3 4

4

3

CSN

7

8

tristate

9 10

READ

RDYN

6

9

10

DIR

12 13

Valid

tristate

910

WRITE

PD

910

DIR

15

PD

14

Valid

PS3411-0600 Page 37 of 50

Advanced Hardwar e Architectures, Inc.

Figure 26: Microprocessor Interface Timing (PROCMODE[1]=1)

123 5N4

CLOCK

1

PA

3

A0

CSN

RDYN

READ

DIR

PD

14

WRITE

PD

9

15

Valid

DIR

Table 11: Microprocessor Interface Timing Requirements

2

4

7

12

Valid

16

17

13

tristate

10

NUMBER PARAMETER MIN MAX UNITS

1 PA setup time 8 ns
2 PA hold time 2 ns
3 CSN setup time 8 ns
4 CSN hold time 2 ns
6 CSN to valid RDYN 15 ns
7 RDYN valid delay 16 ns
8 RDYN drive disable 10 ns

9 DIR setup time 8 ns
10 DIR hold time 2 ns
12 P D valid delay 16 ns
13 P D drive disable 12 ns
14 PD setup time 8 ns
15 PD hold time 2 ns
16 CSN high to PD tristate 10 ns
17 CSN high to RDYN high 15 ns

Page 38 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure 27: Interrupt Timing

CLOCK

INTRN

1 2

Table 12: Interrupt Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 INTRN delay time 15 ns

2 INTRN hold time 2 ns

Figure 28: Clock Timing

1

CLK

34

2

2.0V

1.4V

0.8V

5

Table 13: Clock Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 CLOCK rise time 2 ns

2 CLOCK fall time 2 ns

3 CLOCK high time 12 ns

4 CLOCK low time 12 ns

5 CLOCK period 30 ns

Figure 29: Power On Reset Timing

CLOCK

2

RSTN

1

3

Table 14: Power On Reset Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 RSTN low pulsewidth 10 clocks

2 RSTN setup to CLOCK rise 15 ns

3 RSTN hold time 2 ns

Notes:

1) RSTN signal can be asynchronous to the CLOCK signal. It is internally synchronized to the rising edge of
CLOCK.

PS3411-0600 Page 39 of 50

Advanced Hardwar e Architectures, Inc.

9.0 PACKAGE SPECIFICATIONS

P

B

DETAIL A

D

D1

A

A2

A

L

A1

(LCA)

100

125
126
127
128

97
98
99

AHA3411A-033 PQC

E1

E

P

(LCB)

3231302928

JEDEC outline is MO-108

Page 40 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

PLASTIC QUAD FLAT PACK PACKAGE DIMENSIONS

NUMBER OF PIN AND SPECIFICATION DIMENSION

SYMBOL

MIN NOM MAX
(LCA) 32
(LCB) 32

A 3.7 4.07
A1 0.25 0.33
A2 3.2 3.37 3.6

D 30.95 31.2 31.45
D1 27.99 28 28.12

E 30.95 31.2 31.45

E1 27.99 28 28.12

L 0.73 0.88 1.03

P0.8

B 0.3 0.35 0.4

128

SB

10.0 ORDERING INFORMATION

10.1 AVAILABLE PARTS

PART NUMBER DESCRIPTION

AHA3411A-033 PQC

10.2 PART NUMBERING

AHA 3411 A- 033 P Q C

Manufacturer

Device Number:

3411

Revision Letter:

A

Package Material Codes:

P Plastic

Device

Number

33 MBytes/sec Simultaneous Lossless Data Compression/
Decompression Coprocessor IC

Revision

Level

Speed

Designation

Package

Material

Package

Type

Test

Specification

Package Type Codes:

Q Quad Flat Pack

Test Specifications:

C Commercial 0°C to +70°C

PS3411-0600 Page 41 of 50

Advanced Hardwar e Architectures, Inc.

11.0 RELATED TECHNICAL PUBLICATIONS

DOCUMENT # DESCRIPTION

TM

PB3410C

PB3411

AHA Product Brief – AHA3410C StarLite
Compression/Decompression Coprocessor IC
AHA Product Brief – AHA3411 StarLite
Decompressor IC

PB3422 AHA Product Brief – AHA3422 StarLite
PB3431

PS3410C

PS3422

PS3431

AHA Product Brief – AHA3431 StarLite
Decompressor IC, 3.3V
AHA Product Specification – AHA3410C St a r L i t e
Lossless Data Compression/Decompression Coprocessor IC
AHA Product Specification – AHA3422 StarLite
Decompressor IC
AHA Product Specification – AHA3431 StarLite

Compressor/Decompressor IC, 3.3V
ABDC18 AHA Application Brief – AHA3410C, AHA3411 and AHA3431 Device Differences
ANDC12 AHA Application Note – AHA3410C StarLite
ANDC13 AHA Application Note – Compression Performance on Bitonal Images
ANDC14 AHA Application Note – StarLite

TM

Evaluation Software

ANDC15 AHA Application Note – ENCODEB2 Compression Algorithm Description
ANDC16
ANDC17 AHA Application Note – StarLite

AHA Application Note – Designer’s Guide for StarLite

AHA3422 and AHA3431

TM

Compression on Continuous Tone Images
GLGEN1 General Glossary of Terms
STARSW StarLite

TM

Evaluation Software (WindowsTM)

T. Summers, “Applying Compression/Decompression in High-Performance Printers

PCTP127

and Copiers”, Conference Proceeding: The 1995 Silicon Valley Personal Computer

Design Conference and Exposition

T. Summers, “Compression T echnologies in Printers”, A paper presentation at Seybold
Conference, 1995

25 MBytes/sec Simultaneous Lossless Data

TM

33 MBytes/sec Simultaneous Compressor/

TM

16 MBytes/sec Lossless Decompressor IC

TM

40 MBytes/sec Simultaneous Compr es s o r /

TM

25 MBytes/sec Simultaneous

TM

16 MBytes/sec Lossless

TM

40 MBytes/sec Simultaneous

TM

Designer’s Guide

TM

Family Products: AHA3411,

Page 42 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

APPENDIX A: ADDITIONAL TIMING DIAGRAMS FOR DMA MODE TRANSFERS

Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

PS3411-0600 Page 43 of 50

Advanced Hardwar e Architectures, Inc.

Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Page 44 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=010

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=010

CLOCK

CLOCK

ACKN

ACKN

SD

SD

DRIVEN

DRIVEN

D0 D2D1 D3

D

D

D0 D2D1 D3

PS3411-0600 Page 45 of 50

Advanced Hardwar e Architectures, Inc.

Figure A10: DMA Mode Timing for Four Word Burst Read, One Wa it State, Strobe Condition

of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D2D1 D3 D4 D5 D6 D7D0

Page 46 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=011

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

PS3411-0600 Page 47 of 50

Advanced Hardwar e Architectures, Inc.

Figure A16: DMA Mode Timing for Four Word Burst Read, One Wa it State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D2D1 D3 D4 D5 D6 D7D0

Page 48 of 50 PS3411-0600

Advanced Hardware Architectures, Inc.

Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=111

CLOCK

ACKN

SD

DRIVEN

D

D0 D1 D2

Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition ofDSC=111

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2

PS3411-0600 Page 49 of 50

Advanced Hardwar e Architectures, Inc.

APPENDIX B: SEQUENTIAL REGISTER TABLE

ADDRESS DESCRIPTION

00 System Configuration 0
01 System Configuration 1
02 Input FIFO Thresholds
03 Output FIFO Thresholds
04 Compression Ports Stat us
05 Decompression Ports Status
06 Port Control
07 Interrupt Status/Control 1

09 Interrupt Mask 1
0A Version
0C Decompression Record Length 0
0D Decompression Record Length 1

0E Decompression Record Length 2

0F Decompression Record Length 3

10 Compression Record Length 0

11 Compression Record Length 1
12 Compression Record Length 2
13 Compression Record Length 3
14 Compression Control
15 Compression Reserved
16 Compression Line Length 0
17 Compression Line Length 1
18 Decompression Control

1A Decompression Reserved 1
1C Decompression Configuration 0
1D Decompression Configuration 1

20
21 Compression Record Count 1
27 Interrupt Status/Control 2
29 Interrupt Mask 2

2C Decompression Record Count 0
2D Decompression Record Count 1

30 Compression Byte Count 0
31 Compression Byte Count 1
32 Compression Byte Count 2
33 Compression Byte Count 3
34 Compression Control Prearm
35 Pattern
38 Decompression Control Prearm

3A Decompression Reserved 2

3F Reserved

Compression Record Count 0

Page 50 of 50 PS3411-0600