Datasheet ADV7314 Datasheet (Analog Devices)

Multiformat 216 MHz

Video Encoder with Six NSV

™

14-Bit DACs

ADV7314

FEATURES
High Definition Input Formats

8-/10-,16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:

SMPTE 293M (525p)
BTA T-1004 EDTV2 525p
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3  10-Bit 4:4:4 Input Format

HDTV RGB Supported:

RGB and RGBHV
Other High Definition Formats Using Async
Timing Mode

High Definition Output Formats

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1

CGMS/WSS
Closed Captioning

GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes

Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.

On-Board Voltage Reference
Six 14-Bit NSV Precision Video DACs
2-Wire Serial I

2C®

Interface
Dual Input/Output Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product

APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video Systems

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

O
V
E
R
S
A
M
P
L

I
N
G

INTERFACE

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

I2C

Y9–Y0
C9–C0
S9–S0

HSYNC
VSYNC
BLANK

CLKIN_A
CLKIN_B

ADV7314

D
E
M
U
X

TIMING

GENERATOR

PLL

GENERAL DESCRIPTION

The ADV®7314 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes six high speed NSV video
D/A converters with TTL compatible inputs.

The ADV7314 has separate 8-/10-/16-/20-bit input ports that
accept data in high definition and/or standard definition video
format. For all standards, external horizontal, vertical and
blanking signals, or EAV/SAV timing codes control the inser­tion of appropriate synchronization signals into the digital data
stream and therefore the output signal.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADV7314

P
P
P

DETAILED FEATURES
High Definition Programmable Features (720p/1080i)

2 Oversampling (148.5 MHz)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)

Programmable Features (525p/625p)

8 Oversampling (216 MHz Output)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)

Standard Definition Programmable Features

16 Oversampling (216 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction

Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable

Gain/Attenuation
PrPb SSAF
Separate Pedestal Control on Component and

Composite/S-Video Outputs
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1

CGMS/WSS

Closed Captioning

Standards Directly Supported

Frame Rate Clk Input

Resolution (Hz) (MHz) Standard

720480 29.97 27 ITU-R BT.656
720576 25 27 ITU-R BT.656
720483 59.94 27 SMPTE 293M
720480 59.94 27 BTA T-1004
720576 50 27 ITU-R BT.1362
1280720 60 74.25 SMPTE 296M
19201080 30 74.25 SMPTE 274M
19201080 25 74.25 SMPTE 274M*

Other standards are supported in Async Timing mode.
*SMPTE 274M-1998: System no.6

DETAILED FUNCTIONAL BLOCK DIAGRAM

HD PIXEL

INPUT

CLKIN_B

_HSYNC
_VSYNC
_BLANK

S_HSYNC
S_VSYNC
S_BLANK

CLKIN_A

SD PIXEL

INPUT

DEINTER-

LEAVE

DEINTER-

LEAVE

Y

TEST

CR

PATTERN

CB

CB

TEST

CR

PATTERN

Y

TIMING

GENERATOR

TIMING

GENERATOR

SHARPNESS

AND

ADAPTIVE

FILTER

CONT

ROL

DNR

GAMMA

Y COLOR
CR COLOR
CB COLOR

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

INSERTION

4:2:2

TO

4:4:4

SYNC

U

UV SSAF

V

LUMA

CHROMA

FILTERS

AND

2 OVER-

SAMPLING

RGB

MATRIX

F

SC

MODULA-

TION

CGMS

WSS

PS 8

HDTV 2

SD 16

DAC

DAC

DAC

DAC

DAC

DAC

REV. 0–2–

TABLE OF CONTENTS

ADV7314

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 17

REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 18

INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 31

Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 31

Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 31

Simultaneous Standard Definition

and Progressive Scan or HDTV . . . . . . . . . . . . . . . . . . 32

Progressive Scan At 27 Mhz (Dual Edge)

or 54 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 34

TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 35

HD Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SD Real-Time Control, Subcarrier Reset,

and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 39

SD Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . 39

Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 41

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 42

COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 46

HD/PS Y Level, Cr Level, Cb Level . . . . . . . . . . . . . . . . 46

HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 46

SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 46

SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 48

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

HD Sharpness Filter Control and Adaptive Filter

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

HD Sharpness Filter and Adaptive Filter Application

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

SD DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . 53

Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . 54

DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . 55

SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . . 55

BOARD DESIGN AND LAYOUT CONSIDERATIONS . 56

DAC Termination and Layout Considerations . . . . . . . . 56

Video Output Buffer and Optional Output Filter . . . . . . . 56

PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 58

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 58

Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 58

APPENDIX 1—COPY GENERATION MANAGEMENT

SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

PS CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 60

SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 60

Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . . 62

APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . . 63

APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . . 64

APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . . 67

Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 69

Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 71

Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 72

APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . . 73

APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . . 74

HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 74

RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . . 80

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 82

REV. 0

–3–

ADV7314–SPECIFICATIONS

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; V
V

= 1.235 V, R

REF

= 3040 , R

SET

= 150 . All specifications T

LOAD

(0C to 70C), unless otherwise noted.)

= 2.375 V–3.6 V,

DD_IO

MIN

to T

MAX

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

1

Resolution 14 Bits
Integral Nonlinearity 2.0 LSB
Differential Nonlinearity
Differential Nonlinearity

2

, +ve 1.0 LSB

2

, –ve 3.0 LSB

DIGITAL OUTPUTS

Output Low Voltage, V
Output High Voltage, V

OL

OH

2.4 [2.0]

3

Three-State Leakage Current ± 1.0 mAV

0.4 [0.4]3VI
VI

= 3.2 mA

SINK

= 400 mA

SOURCE

= 0.4 V, 2.4 V

IN

Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V

IH

IL

Input Leakage Current 3 mAV
Input Capacitance, C

IN

2V

0.8 V

= 2.4 V

IN

2pF

ANALOG OUTPUTS

Full-Scale Output Current 4.1 4.33 4.6 mA
Output Current Range 4.1 4.33 4.6 mA

DAC-to-DAC Matching 1.0 %

Output Compliance Range, V
Output Capacitance, C

OC

OUT

0 1.0 1.4 V

7pF

VOLTAGE REFERENCE

Internal Reference Range, V
External Reference Range, V

Current

V

REF

4

REF

REF

1.15 1.235 1.3 V

1.15 1.235 1.3 V

± 10 mA

POWER REQUIREMENTS

Normal Power Mode

5

I

DD

170 mA SD Only [16]
110 mA PS Only [8]

I

DD_IO

I

AA

7, 8

95 mA HDTV Only [2]
172 190

1.0 mA
39 45 mA

6

mA SD [16, 10 Bit] + PS [8, 20 Bit]

Sleep Mode

I

DD

I

AA

I

DD_IO

200 mA
10 mA
250 mA

Power Supply Rejection Ratio 0.01 %/%

NOTES

1

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

2

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.

3

Value in brackets for V

4

External current required to overdrive internal V

5

IDD, the circuit current, is the continuous current required to drive the digital core.

6

Guaranteed maximum by characterization.

7

IAA is the total current required to supply all DACs including the V

8

All DACs on.

Specifications subject to change without notice.

= 2.375 V–2.75 V.

DD_IO

REF

.

circuitry and the PLL circuitry.

REF

REV. 0–4–

ADV7314

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; V

DYNAMIC SPECIFICATIONS

Parameter Min Typ Max Unit Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz
Chroma Bandwidth 5.8 MHz
SNR 65.6 dB Luma Ramp Unweighted
SNR 72 dB Flat Field Full Bandwidth

HDTV MODE

Luma Bandwidth 30 MHz
Chroma Bandwidth 13.75 MHz

STANDARD DEFINITION MODE

Hue Accuracy 0.44 ∞
Color Saturation Accuracy 0.20 %
Chroma Nonlinear Gain 0.84 ± %Referenced to 40 IRE
Chroma Nonlinear Phase –0.2 ±∞
Chroma/Luma Intermodulation 0 ±%
Chroma/Luma Gain Inequality 97.5 ± %
Chroma/Luma Delay Inequality 0 ns
Luminance Nonlinearity 0.1 ± %
Chroma AM Noise 84 dB
Chroma PM Noise 75.3 dB
Differential Gain 0.09 % NTSC
Differential Phase 0.12 ∞ NTSC
SNR 63.5 dB Luma Ramp
SNR 77.7 dB Flat Field Full Bandwidth

Specifications subject to change without notice.

3040 , R

= 150 . All specifications T

LOAD

MIN

= 2.375 V–3.6 V, V

DD_IO

to T

(0C to 70C), unless otherwise noted.)

MAX

= 1.235 V, R

REF

SET

=

REV. 0

–5–

ADV7314

TIMING SPECIFICATIONS

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; V
3040 , R

= 150 . All specifications T

LOAD

MIN

= 2.375 V–3.6 V, V

DD_IO

to T

(0C to 70C), unless otherwise noted.)

MAX

= 1.235 V, R

REF

Parameter Min Typ Max Unit Conditions

MPU PORT

1

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t

1

2

3

0.6 ms

1.3 ms

0.6 msThe first clock is generated after

this period

Setup Time (Start Condition), t

4

0.6 msRelevant for repeated start

condition
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

5

6

7

8

100 ns

300 ns
300 ns

0.6 ms

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

2

7ns

Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT

f

CLK

f

CLK

Clock High Time t
Clock Low Time t
Data Setup Time t
Data Hold Time t
SD Output Access Time t
SD Output Hold Time t
HD Output Access Time t
HD Output Hold Time t

PIPELINE DELAY

9

10

1

11

1

12

13

14

13

14

4

3

27 MHz Progressive Scan Mode

81 MHz HDTV Mode/ASYNC Mode
40 % of one clk cycle
40 % of one clk cycle

2.0 ns

2.0 ns

15 ns

5.0 ns

14 ns

5.0 ns

63 clk cycles SD [2, 16]

76 clk cycles SD Component Mode [16]

35 clk cycles PS [1]

41 clk cycles PS [8]

36 clk cycles HD [2, 1]

NOTES

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

Data: C [9:0]; Y [9:0], S[9:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.

4

SD, PS = 27 MHz, HD = 74.25 MHz.

Specifications subject to change without notice.

SET

=

REV. 0–6–

CLKIN_A

ADV7314

t

12

t

13

t

14

CONTROL

INPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

P_HSYNC,
P_VSYN
P_BLANK

Y9–Y0

C9–C0

CONTROL
OUTPUTS

t

t

9

10

C,

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

t11

Figure 1. HD Only 4:2:2 Input Mode [Input Mode 010]; PS Only 4:2:2 Input Mode [Input Mode 001]

CLKIN_A

t

12

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

t

t

9

10

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cb1 Cb2 Cb3 Cb4 Cb5

t

11

Cr0 Cr1 Cr2 Cr3 Cr5

Cr4

t

13

t

14

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

C9–C0

S9–S0

Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001]

REV. 0

–7–

ADV7314

CONTROL

INPUTS

CLKIN_A

P_HSYNC,
P_VSYNC,
P_BLANK

t

t

9

10

t

12

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Y9–Y0

C9–C0

S9–S0

G0 G1 G2 G3 G4 G5

B0 B1 B2 B3 B4 B5

t

11

R0 R1 R2 R3 R4 R5

Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010]

CLKIN_B*

t9

t10

CONTROL

INPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y

CONTROL

OUTPUTS

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

0

t12

t11

*CLKIN_B MUST BE USED IN THIS PS MODE.

Figure 4. PS 4:2:2 110-Bit Interleaved at 27 MHz

t

13

t

14

t12

t11

t13

t14

HSYNC/VSYNC

Input Mode [Input Mode 100]

REV. 0–8–

CONTROL

INPUTS

CLKIN_A

P_HSYNC,
P_VSYNC,
P_BLANK

t9

ADV7314

t10

Y9–Y0

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Figure 5. PS 4:2:2 110-Bit Interleaved at 54 MHz

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

t11

CLKIN_B*

Y9–Y

CONTROL

OUTPUTS

t12

t

t

9

3FF 00 00 XY Cb0 Y0 Cr0 Y1

0

t

12

t

11

*CLKIN_B USED IN THIS PS ONLY MODE.

10

t13

t14

HSYNC/VSYNC

t

12

t

11

t

13

t

14

Input Mode [Input Mode 111]

Figure 6. PS Only 4:2:2 110-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]

REV. 0

CLKIN_A

t10

t9

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Y9–Y0

3FF 00 00 XY Cb0 Y0 Cr0 Y1

t11

t12

NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT 1

t13

t14

Figure 7. PS Only 4:2:2 110-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]

–9–

ADV7314

CONTROL

INPUTS

CLKIN_B

P_HSYNC,
P_VSYNC,
P_BLANK

t

t

t

10

9

12

CONTROL

INPUTS

Y9–Y0

C9–C0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

Y0 Y1

Cb0 Cr0 Cb2

t

t

9

10

Cb0 Y0 Cr0

Y2

t

11

Y3 Y4 Y5

Cr2

Y1

t

11

t

12

Cb4 Cr4

Cb1 Y2

Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101]; SD Oversampled
[Input Mode 110] HD Oversampled

CLKIN_B

t12

Y2

Y3 Y4 Y5

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

t10

t9

Y0 Y1

HD INPUT

SD INPUT

PS INPUT

CONTROL

INPUTS

C9–C0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

Cb0 Cr0 Cb2

t11

t9

t10

Cb0 Y0 Cr0

t11

Cr2

Y1

Cb4 Cr4

t12

Cb1 Y2

Figure 9. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode [Input Mode 011]

SD INPUT

REV. 0–10–

CONTROL

INPUTS

CONTROL

INPUTS

CONTROL

INPUTS

CLKIN_B

t

10

PS INPUT

Crxxx Yxxx

t

12

t

11

t

t

10

12

Y1

t

11

Cb1 Y2

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

t

9

Cb0 Y0 Cr0 Y1

t

12

t

11

t

9

Cb0 Y0 Cr0

Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100]

CLKIN_A

t

12

S_HSYNC,
S_VSYNC,
S_BLANK

t

t

9

10

ADV7314

SD INPUT

IN SLAVE MODE

S9–S0/Y9–Y0*

CONTROL

OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000]

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

t

11

t

13

t

14

IN MASTER/SLAVE MODE

REV. 0

–11–

ADV7314

P

CONTROL

INPUTS

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

t

t

9

10

t

12

IN SLAVE MODE

S9–S0/Y9–Y0*

C9–C0

CONTROL

OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000]

_HSYNC

P_VSYNC

P_BLANK

Y9–Y0

C9–C0

Y0 Y2 Y3

Cb0 Cr0 Cb2 Cr2

t

11

A

Y1

t

13

t

14

Y0 Y1

Cb0 Cr0

IN MASTER/SLAVE MODE

Y2 Y3

Cr1 Cb1

B

A = 16 CLK CYCLES FOR 525p
A = 12 CLK CYCLES FOR 626p
A = 44 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
A = 70 CLK CYCLES FOR 720p
AS RECOMMENDED BY STANDARD

B (MIN) = 122 CLK CYCLES FOR 525p
B (MIN) = 132 CLK CYCLES FOR 625p
B (MIN) = 236 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
B (MIN) = 300 CLK CYCLES FOR 720p

Figure 13. HD 4:2:2 Input Timing Diagram

REV. 0–12–

P

_HSYNC

P_VSYNC

P_BLANK

ADV7314

a

Y9–Y0

a = 32 CLK CYCLES FOR 525p
a = 24 CLK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLK CYCLES FOR 525p
b(MIN) = 264 CLK CYCLES FOR 625p

Figure 14. PS 4:2:2 110-Bit Interleaved Input Timing Diagram

S_HSYNC

S_VSYNC

PAL = 24 CLKCYCLES
NTSC = 32 CLKCYCLES

S_BLANK

S9–S0/Y9–Y0*

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 15. SD Timing Input for Timing Mode 1

Cb Y

Cr Y

Cr Y

Cb Y

b

PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES

t

3

t

4

t

8

SDA

SCLK

t

3

t

6

t

2

t

5

t

1

t

7

Figure 16. MPU Port Timing Diagram

REV. 0

–13–

ADV7314

ABSOLUTE MAXIMUM RATINGS*

VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

V

DD

V

to IO_GND . . . . . . . . . . . . –0.3 V to V

DD_IO

Ambient Operating Temperature (T
Storage Temperature (T

) . . . . . . . . . . . . . . .–65∞C to +150∞C

S

A

) . . . . . . . . . 0∞C to 70∞C

DD_IO

to +0.3 V

Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . . 260∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

The ADV7314 is a Pb-free environmentally friendly product. It is
manufactured using the most up-to-date materials and processes.
The coating on the leads of each device is 100% pure Sn electro­plate. The device is suitable for Pb-free applications and is able to
withstand surface-mount soldering at up to 255∞C [± 5∞C]. In
addition, it is backward compatible with conventional SnPb solder­ing processes. This means that the electroplated Sn coating can
be soldered with Sn/Pb solder pastes at conventional reflow tem­peratures of 220∞C to 235∞C.

ORDERING GUIDE*

Model Package Description Package Option

THERMAL CHARACTERISTICS

JC = 11∞C/W

= 47∞C/W



JA

ADV7314KST Plastic Quad Flatpack ST-64

(LQFP)

*Analog output short circuit to any power supply or common can be of an indefi-

nite duration.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7314 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–14–

PIN CONFIGURATION

K

DD

GND_IO

CLKN_BS9S8S7S6S5DGND

V

S4S3S2S1S0

S_HSYNCS_VSYNC

49505152535455565758596061626364

ADV7314

V

DD_IO

V

DGND

1

PIN 1

2

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

DD

Y8

Y9

C0

C1

C2

10

11

12

13

14

15

16

3

4

5

6

7

8

9

IDENTIFIER

2

C3

C4

C
I

ALSB

SDA

ADV7314

LQFP

TOP VIEW

(Not to Scale)

SCLK

P_VSYNC

P_BLANK

P_HSYNC

C5C6C7C8C9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32313029282726252423222120191817

CLKIN_A

RTC_SCR_TR

S_BLAN

R

SET1

V

REF

COMP1

DAC A

DAC B

DAC C

V

AA

AGND

DAC D

DAC E

DAC F

COMP2

R

SET2

EXT_LF

RESET

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Input/Output Function

11, 57 DGND G Digital Ground.

40 AGND G Analog Ground.

32 CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only

(27 MHz).

63 CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan

mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This

clock is only used in dual modes.

36, 45 COMP2, COMP1 O Compensation Pin for DACs. Connect 0.1 mF capacitor from COMP pin

to V

.

AA

44 DAC A O CVBS/Green/Y/Y Analog Output.

43 DAC B O Chroma/Blue/U/Pb Analog Output.

42 DAC C O Luma/Red/V/Pr Analog Output.

39 DAC D O In SD Only Mode: CVBS/Green/Y Analog Output.

In HD Only mode and simultaneous HD/SD mode: Y/Green [HD] Analog

Output.

38 DAC E O In SD Only Mode: Luma/Blue/U Analog Output.

In HD Only mode and simultaneous HD/SD mode: Pr/Red Analog Output.

37 DAC F O In SD Only Mode: Chroma/Red/V Analog Output.

In HD Only mode and simultaneous HD/SD mode: Pb/Blue [HD] Analog

Output.

23 P_HSYNC IVideo Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode

and HD.

24 P_VSYNC IVideo Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode

and HD.

25 P_BLANK I Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD.
48 S_BLANK I/O Video Blanking Control Signal for SD only.

REV. 0

–15–

ADV7314

Pin No. Mnemonic Input/Output Function

50 S_HSYNC I/O Video Horizontal Sync Control Signal for SD Only.
49 S_VSYNC I/O Video Vertical Sync Control Signal for SD Only.

2–9, 12–13 Y9–Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for inter-

leaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data
input, LSB is set up on Y2.

14–18, 26–30 C9–C0 I Progressive Scan/HDTV Input Port. In 4:4:4 Input mode, this port is used for

the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB
is set up on C2.

51–55, 58–62 S9–S0 I SD or Progressive Scan/HDTV Input Port for Cr [Red/V] Data in 4:4:4 Input

Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2.

33 RESET IThis input resets the on-chip timing generator and sets the ADV7314 into

default register setting. RESET is an active low signal.

35, 47 R

22 SCLK I I

21 SDA I/O I

20 ALSB I TTL Address Input. This signal sets up the LSB of the I

1V

10, 56 V

41 V

46 V

34 EXT_LF I External Loop Filter for the Internal PLL.

SET2

DD_IO

DD

AA

REF

, R

SET1

IA 3040 W resistor must be connected from this pin to AGND and is used

to control the amplitudes of the DAC outputs.

2

C Port Serial Interface Clock Input.

2

C Port Serial Data Input/Output.

2

C address. When

this pin is tied low, the I

2

C filter is activated, reducing noise on the I2C

interface.

PPower Supply for Digital Inputs and Outputs.

PDigital Power Supply.

PAnalog Power Supply.

I/O Optional External Voltage Reference Input for DACs or Voltage Reference

Output (1.235 V).

31 RTC_SCR_TR I Multifunctional Input. Real-time control (RTC) input, timing reset input,

subcarrier reset input.

19 I

CIThis input pin must be tied high (V

over the I

2

C port.

) for the ADV7314 to interface

DD_IO

2

64 GND_IO Digital Input/Output Ground.

TERMINOLOGY

SD Standard definition video, conforming to ITU-R BT.601/656.

HD High definition video, such as progressive scan or HDTV.

PS Progressive scan video, conforming to SMPTE 293M, ITU-R BT.1358, BTA T-1004 EDTV2, BTA 1362

HDTV High definition television video, conforming to SMPTE 274M or SMPTE 296M.

YCrCb SD, HD, or PS component digital video.

YPrPb HD, SD, or PS component analog video.

REV. 0–16–

ADV7314

MPU PORT DESCRIPTION

The ADV7314 supports a 2-wire serial (I2C compatible) micro­processor bus driving multiple peripherals. Two inputs, serial
data (SDA) and serial clock (SCL), carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7314 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 17. The
LSB sets either a read or write operation. Logic 1 corresponds
to a read operation, while Logic 0 corresponds to a write opera­tion. A1 is set by setting the ALSB pin of the ADV7314 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater
input bandwidth on the I
transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I
less than 50 ns will not pass into the I

2

C lines, which allows high speed data

2

C lines, which means that pulses of

2

C internal controller.

This mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 17. ADV7314 Slave Address = D4h

To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA, while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are transferred from MSB down to LSB. The periph­eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known as
an acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is
when the device monitors the SDA and SCL lines waiting for
the start condition and the correct transmitted address. The
R/W bit determines the direction of the data.

A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.

The ADV7314 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits wide, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility, which allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.

Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7314 will not issue an acknowledge and will return to the
idle condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action will be taken:

1. In read mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is when the SDA line is not
pulled low on the ninth pulse.

2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7314, and the part will return to the idle condition.

REV. 0

–17–

ADV7314

Before writing to the subcarrier frequency registers, the ADV7314
must have been reset at least once since power-up.

The four subcarrier frequency registers must be updated start­ing with subcarrier frequency register 0 through subcarrier
frequency register 3. The subcarrier frequency will not update
until the last subcarrier frequency register byte has been received
by the ADV7314.

Figure 18 illustrates an example of the data transfer for a write
sequence and the start and stop conditions.

Figure 19 shows bus write and read sequences.

REGISTER ACCESS

The MPU can write to or read from all of the registers of the
ADV7314 except the subaddress registers, which are write-only
registers. The subaddress register determines which register the

SDATA

SCLOCK

S

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

9

1–7 8 9

Figure 18. Bus Data Transfer

next read or write operation accesses. All communications with
the part through the bus start with an access to the subaddress
register. A read/write operation is then performed from/to the
target address, which increments to the next address until a stop
command on the bus is performed.

Register Programming

The following section describes the functionality of each register.
All registers can be read from as well as written to unless other­wise stated.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write-only register. After
the part has been accessed over the bus and a read/write opera­tion is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.

1–7

89

P

WRITE

SEQUENCE

READ

SEQUENCE

S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P

LSB = 0

S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT
P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER

LSB = 1

A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER

Figure 19. Write and Read Sequence

REV. 0–18–

ADV7314

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

00h Power

Mode
Register

Mode Select

01h

Register

Sleep Mode. With this control enabled, the current
consumption is reduced to
the internal PLL cct are disabled. I
be read from and written to in sleep mode.

PLL and Oversampling Control. This control
allows the internal PLL cct to be powered down
and the oversampling to be switched off.

DAC F. Power on/off.

DAC E. Power on/off.

DAC D. Power on/off.

DAC C. Power on/off.

DAC B. Power on/off.

DAC A. Power on/off.

BTA T-1004 or 1362 Compatibility

Clock Edge

Reserved 0 38h

Clock Align

Input Mode

Y/S Bus Swap



A level. All DACs and

2

C registers can

0 DAC F off

1 DAC F on

0 DAC E off

1 DAC E on

0 DAC D off

1 DAC D on

0 DAC D off

1 DAC C on

0 DAC B off

1 DAC B on

0 DAC A off

1 DAC A on

0

1 Must be set if the phase

000 SD input only

001 PS input only

010 HDTV input only

011 SD and PS [20-bit]

100 SD and PS [10-bit]

101 SD and HDTV [SD

110 SD and HDTV [HDTV

111 PS only [at 54 MHz]

0 10-bit data on S Bus

1 10-bit data on Y Bus

0Sleep Mode off FCh

1Sleep Mode on

0 PLL on

1 PLL off

0Disabled

1 Enabled

0 Cb clocked on rising edge

1Y clocked on rising edge

delay between the two
input clocks is <9.25 ns or
>27.75 ns.

oversampled

oversampled]

Register Reset
Value (Shaded)

Only for PS dual
edge clk mode

Only for PS
interleaved input at
27 MHz

Only if two input
clocks are used

SD Only. 10-Bit/
20-Bit Input mode

REV. 0

–19–

ADV7314

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

02h Mode Register 0 Reserved 00 Zero must be written to

Test Pattern Black Bar 0 Disabled

RGB Matrix 0 Disable Programmable

Sync on RGB

RGB/YUV Output 0 RGB component outputs

SD Sync 0 No Sync output

HD Sync 0 No Sync output

03h RGB Matrix 0 xx LSB for GY 03h
04h RGB Matrix 1 x x LSB for RV F0h

05h RGB Matrix 2 x xxxxxxxBit 9–2 for GY 4Eh
06h RGB Matrix 3 x xxxxxxxBit 9–2 for GU 0Eh
07h RGB Matrix 4 x xxxxxxxBit 9–2 for GV 24h

08h RGB Matrix 5 x xxxxxxxBit 9–2 for BU 92h
09h RGB Matrix 6 x xxxxxxxBit 9–2 for RV 7Ch
0Ah DAC A,B,C Output

0Bh DAC D,E,F Output

0Ch 0 0110011Note 3 00h
0Dh 1 1000000Note 3 00h

0Eh Reserved 00h
0Fh Reserved 00h

1

For more detail, refer to Appendix 7.

2

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

3

Must be written to after power-up/reset.

Level

Level

2

Positive Gain to DAC Output
Voltage

Negative Gain to DAC Output
Voltage

Positive Gain to DAC Output
Voltage

Negative Gain to DAC Output
Voltage

1

1 Output SD syncs on

1 Output HD syncs on

xx LSB for GU

0 00000000% 00h

0 0000001+0.018%
0 00000100.036%

0 0111111+7.382%
0 1000000+7.5%
1 1000000–7.5%

1 1000001–7.382%
1 0000010–7.364%

1 1111111–0.018%
0 00000000% 00h

0 0000001+0.018%
0 00000100.036%

0 0111111+7.382%
0 1000000+7.5%
1 1000000–7.5%

1 1000001–7.382%
1 0000010–7.364%

1 1111111–0.018%

0 No Sync
1 Sync on all RGB outputs

1 YUV component outputs

xx LSB for GV

1 Enabled

1 Enable Programmable

xx LSB for BU

these bits

RGB Matrix

RGB Matrix

S_HSYNC output, S_VSYNC
output, S_BLANK output

P_HSYNC output, P_VSYNC
output, P_BLANK output

………

……….

………

……….

Reset Value

20h

11h, Bit 2 must
be enabled also

REV. 0–20–

ADV7314

g

,

y

g

isabled

d

HD Sh

Fil

Disabled

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

10h HD Output Standard 0 0 EIA770.2 output 00h

HD Mode
Register 1

HD Input Control Signals 0 0

HD 625p 0 525p

HD 720p 0 1080i

HD BLANK Polarit

HD Macrovision for 525p/625p 0 Macrovision off

11h HD Pixel Data Valid 0Pixel data valid off 00h

HD Mode
Register 2

HD Test Pattern Enable 0 HD test pattern off

HD Test Pattern Hatch/Field 0 Hatch

HD VBI Open 0 D

HD Undershoot Limiter 0 0 Disabled

arpness

ter 0

1Macrovision on

1 Enabled

1720p

0
1

01 –11 IRE
10 –6 IRE

11 –1.5 IRE

01 EAV/SAV codes
10 Async timing mode
11 Reserved

1625p

1Field/Frame

1 Enable

01 EIA770.1 output
10 Output levels for full input

11 Reserved

0Reserved

1 HD test pattern on

ran

e

VSYNC, BLANK

HSYNC

BLANK active hi
BLANK active low

1Pixel data valid on

h

Reset Values

REV. 0

–21–

ADV7314

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

12h 0000 clk cycle 00h

HD Mode
Register 3

HD Mode

13h HD Cr/Cb Sequence 0

Register 4

14h HD Mode

Register 5

15h Reserved 0 0 must be written to this bit 00h

HD Mode
Register 6

NOTES

1

When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1 , the field/line

HD Y Delay with
Respect to Falling Edge
of HSYNC

HD with Respect to
Falling Edge of HSYNC

HD CGMS 0 Disabled

HD CGMS CRC 0 Disabled

Reserved 0 0 must be written to this bit
HD Input Format

Sinc Filter on DAC D,
E, F

Reserved 0 0 must be written to this bit
HD Chroma SSAF 0 Disabled

HD Chroma Input 0 4:4:4

HD Double Buffering

HD Timing Reset x A low-high-low transition resets the

1080i Frame Rate 0 0 30 Hz/2200 total samples/line

Reserved 0 0 0 0 should be written to these bits

HD VSYNC/Field
Input

Lines/Frame

HD RGB Input 0 Disabled

HD Sync on PrPb 0 Disabled

HD Color DAC Swap 0 DAC E = Pb; DAC F = Pr

HD Gamma Curve A/B 0 Gamma Curve A

HD Gamma Curve
Enable

HD Adaptive Filter
Mode

HD Adaptive Filter
Enable

1

2

2

1 Enabled

0Disabled
1 Enabled

0 Update Field/line counter
1Field/line counter free running

0Disabled

1 Enabled

00 0 0 clk cycle

00 1 1 clk cycle
01 0 2 clk cycle
01 1 3 clk cycle
10 0 4 clk cycle

1 Enabled

1 Enabled

14:2:2

0Field Input
1

1 Gamma Curve B

0Disabled

1 Enabled

0 Mode A

1 Mode B

0011 clk cycle
0102 clk cycle
0113 clk cycle
1004 clk cycle

Cb after falling edge of HSYNC

1

Cr after falling edge of HSYNC

08-bit input

1 10-bit input
0Disabled
1 Enabled

internal HD timing counters

01 25 Hz/2640 total samples/line

VSYNC Input

1 Enabled

1 Enabled

1 DAC E = Pr; DAC F = Pb

counters are free running and wrap around when external sync signals indicate so.

2

Adaptive Filter mode is not available in PS only @ 54 MHz input mode.

Reset Value

4Ch

00h

REV. 0–22–

ADV7314

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

16h

HD Y Level

17h

HD Cr Level

18h

HD Cb Level

1

1

1

xxxxx xx x Y color value A0h
xxxxx xx x Cr color value 80 h
xxxxx xx x Cb color value 8 0 h

Register
Setting

Reset Value

19h Reserved 00h
1Ah Reserved 00h
1Bh Reserved 00h
1Ch Reserved 00h
1Dh Reserved 00h
1Eh Reserved 00h
1Fh Reserved 00h
15h HD Mode

Register 6

HD Gamma Curve Enable

HD Adaptive Filter Mode

0 Disabled

1 Enabled
0Mode A
1Mode B

HD Adaptive Filter Enable

0 Disabled
1 Enabled

20h 0000Gain A = 0 00 h

HD Sharpness
Filter Gain

HD Sharpness Filter Gain Value A

0001Gain A = +1

.. .. .. .. … …

0111Gain A = +7
100 0 Gain A = –8

.. .. .. .. … …

111 1 Gain A = –1

HD Sharpness Filter Gain Value B

0000 Gain B = 0
0001 Gain B = +1

.. .. .. .. …… .

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. …… ..

2

HD CGMS HD CGMS Data Bits 0000C19C18C17C16CGMS 19–16 00 h

21h

1111 Gain B = –1

22h HD CGMS HD CGMS Data Bits C15 C14 C13 C12 C 11 C10 C9 C8 CGMS 15–8 00h
23h HD CGMS HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7–0 00 h
24h

HD Gamma A

1

HD Gamma Curve A Data Points xxxxx xx x A0 00h
25h HD Gamma A HD Gamma Curve A Data Points xxxxx xx x A1 00h
26h HD Gamma A HD Gamma Curve A Data Points xxxxx xx x A2 00h
27h HD Gamma A HD Gamma Curve A Data Points xxxxx xx x A3 00h
28h HD Gamma A HD Gamma Curve A Data Points xxxxx xx x A4 00h
29h HD Gamma A HD Gamma Curve A Data Points xxxxx xx x A5 00h
2Ah HD Gamma A HD Gamma Curve A Data Points xxxxxxx x A6 00h
2Bh HD Gamma A HD Gamma Curve A Data Points xxxxxxx x A7 00h
2Ch HD Gamma A HD Gamma Curve A Data Points xxxxx xx x A8 00h
2Dh HD Gamma A HD Gamma Curve A Data Points xxxxx xx x A9 00h
2Eh HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B0 00h
2Fh HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B1 00h
30h HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B2 00h
31h HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B3 00h
32h HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B4 00h
33h HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B5 00h
34h HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B6 00h
35h HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B7 00h
36h HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B8 00h

2

HD Gamma B HD Gamma Curve B Data Points xxxxx xx x B9 00h

37h

NOTES

1

Used for internal test pattern only.

2

Programmable gamma correction is not available in PS only mode @ 54 MHz operation.

REV. 0

–23–

ADV7314

SR7–SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Value

38h HD Adaptive Filter 0 0 0 0 Gain A = 0 00h

39h 00 0 0 Gain A = 0 00h

3Ah 00 0 0 Gain A = 0 00h

3Bh

Gain 1 00 0 1 Gain A = +1

HD Adaptive Filter
Gain 2

HD Adaptive Filter
Gain 3

HD Adaptive Filter
Threshold A

HD Adaptive Filter
Gain 1 Value A

HD Adaptive Filter
Gain 1 Value B

HD Adaptive Filter
Gain 2 Value A

HD Adaptive Filter
Gain 2 Value B

HD Adaptive Filter
Gain 3 Value A

HD Adaptive Filter
Gain 3 Value B

HD Adaptive Filter
Threshold A Value

.. .. .. .. ……

01 1 1 Gain A = +7
10 0 0 Gain A = –8

.. .. .. .. ……

11 1 1 Gain A = –1

0000 Gain B = 0
0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7

1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

00 0 1 Gain A = +1

.. .. .. .. ……

01 1 1 Gain A = +7
10 0 0 Gain A = –8

.. .. .. .. ……

11 1 1 Gain A = –1

0000 Gain B = 0
0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7

1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

00 0 1 Gain A = +1

.. .. .. .. ……

01 1 1 Gain A = +7

10 0 0 Gain A = –8

.. .. .. .. ……

11 1 1 Gain A = –1
0000 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

xxxxxx x x Threshold A 00h

3Ch

3Dh

HD Adaptive Filter
Threshold B

HD Adaptive Filter
Threshold C

HD Adaptive Filter
Threshold B Value

HD Adaptive Filter
Threshold C Value

xxxxxx x x Threshold B 00h

xxxxxx x x Threshold C 00h

REV. 0–24–

ADV7314

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

3Eh Reserved 00h
3Fh Reserved 00h
40h SD Mode Register 0 SD Standard 0 0

SD Luma Filter 0 0 0

SD Chroma Filter 0 0 0

41h Reserved 00h
42h SD Mode Register 1 SD UV SSAF 0

SD DAC Output 1 0

SD DAC Output 2 0

SD Pedestal 0

SD Square Pixel 0

SD VCR FF/RW Sync 0

SD Pixel Data Valid 0

SD SAV/EAV Step Edge
Control

43h SD Mode Register 2 SD Pedestal YPrPb Output 0

SD Output Levels Y 0

SD Output Levels PrPb 0 0

SD VBI Open 0

SD CC Field Control 0 0

Reserved 0 Reserved

001
010
011
100
101 Chroma CIF
110
111

1
0
1

01

10

11

00 1
01 0
01 1
10 0
10 1
11 0
11 1

1

1

1

01
10
11

1

01
10
11

1

1

1

Register Setting

NTSC
PAL B, D, G, H, I
PAL M
PAL N
LPF NTSC
LPF PAL
Notch NTSC
Notch PAL
SSAF Luma
Luma CIF
Luma QCIF
Reserved

1.3 MHz

0.65 MHz

1.0 MHz

2.0 MHz
Reserved

Chroma QCIF

3.0 MHz

Disabled

1

Enabled

Refer to Output
Configuration section

Refer to Output
Configuration section

Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
No pedestal on YUV

1 7.5 IRE pedestal on YUV

Y = 700/300 mV
Y = 714/286 mV

700 mV p-p[PAL]; 1000 mV
p-p[NTSC]

700 mV p-p
1000 mV p-p
648 mV p-p
Disabled
Enabled
CC disabled
CC on odd field only
CC on even field only
CC on both fields

Reset
Value

00h

08h

00h

REV. 0

–25–

ADV7314

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

44h SD Mode Register SD VSYNC–3H 0 Disabled 0 0h

SD RTC/TR/SCR* 00 Genlock disabled

01 Subcarrier reset
10 Timing reset
11 RTC enabled

SD Active Video Length 0 720 pixels

1 710 [NTSC]/702 [PAL]

SD Chroma 0 Chroma enabled

1 Chroma disabled

SD Burst 0 Enabled

1 Disabled

SD Color Bars 0 Disabled

1 Enabled

SD DAC Swap 0

1

45h Reserved 00h
46h Reserved 00h
47h SD Mode Register SD PrPb Scale 0 Disabled 00h

SD Y Scale 0 Disabled

SD Hue Adjust 0 Disabled

1 Enabled

SD Brightness 0 Disabled

1 Enabled

SD Luma SSAF Gain 0 Disabled

1 Enabled
Reserved 0 0 must be written to
Reserved 0 0 must be written to
Reserved 0 0 must be written to

48h SD Mode Register Reserved 00h

1

VSYNC = 2.5 lines [PAL]
VSYNC = 3 lines [NTSC]

DAC B = Luma, DAC C = Chroma
DAC B = Chroma, DAC C = Luma

1 Enabled

1 Enabled

Reset
Value

Reserved 0 0 must be written to
SD Double Buffering 0 Disabled

SD Input Format 0 0 8-bit input

01 16-bit input

10 10-bit input

11 20-bit input
SD Digital Noise 0 Disabled

1 Enabled

SD Gamma Control 0 Disabled

1 Enabled

SD Gamma Curve 0 Gamma Curve A

1 Gamma Curve B

49h SD Mode Register SD Undershoot Limiter 0 0 Disabled 00h

Reserved 0 0 must be written to
SD Black Burst Output 0 Disabled

SD Chroma Delay 0 0 Disabled

01 4 clk cycles
10 8 clk cycles

11 Reserved
Reserved 0 0 must be written to
Reserved 0 0 must be written to

1 Enabled

01 –11 IRE
10 –6 IRE
11 –1.5 IRE

1 Enabled

*See Figure 31, RTC Timing and Connections.

REV. 0–26–

ADV7314

BLANK

y

H

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

4Ah SD Timing Register 0 SD Slave/Master Mode 0 Slave mode 0 8h

SD Timing Mode 0 0 Mode 0

Input 0 Enabled

SD

SD Luma Delay 0 0 No delay

SD Min. Luma Value 0 –40 IRE

SD Timing Reset x 0000000A low-high-low transistion will

4Bh SD Timing Register 1

4Ch SD F
4Dh SD F
4Eh SD F
4Fh SD F
50h SD F
51h SD Closed Captioning Extended Data on Even

52h SD Closed Captioning Extended Data on Even

53h SD Closed Captioning Data on Odd Fields x xxxxxxxData Bit 7–0 00h
54h SD Closed Captioning Data on Odd Fields x xxxxxxxData Bit 15–8 00h
55h SD Pedestal Register 0 Pedestal on Odd Fields 17 16 15 14 13 12 11 10 0 0h
56h SD Pedestal Register 1 Pedestal on Odd Fields 25 24 23 22 21 20 19 18 0 0h
57h SD Pedestal Register 2 Pedestal on Even Fields 17 16 15 14 13 12 11 10 0 0h
58h SD Pedestal Register 3 Pedestal on Even Fields 25 24 23 22 21 20 19 18 0 0h

Register 0 x xxxxxx xSubcarrier Frequency Bit 7–0 1 6h

SC

Register 1 x xxxxxxxSubcarrier Frequency Bit 15–8 7Ch

SC

Register 2 x xxxxxxxSubcarrier Frequency Bit 23–16 F0 h

SC

Register 3 x xxxxxxxSubcarrier Frequency Bit 31–24 21 h

SC

Phase x xxxxxx xSubcarrier Phase Bit 9–2 00h

SC

SD HSYNC Width

SD HSYNC to VSYNC dela

SD HSYNC to VSYNC Rising
Edge Delay [Mode 1
only] VSYNC Width
[Mode 2 only]

HSYNC to Pixel Data
Adjust

Fields

Fields

00 0 clk cycles
01 1 clk cycle
10 2 clk cycles
11 3 clk cycles

x xxxxxxxExtended Data Bit 7–0 00 h

x xxxxxxxExtended Data Bit 15–8 00h

01 2 clk cycles
10 4 clk cycles
11 6 clk cycles

1 –7.5 IRE

x0 Tc = Tb
x1 Tc = Tb + 32 s
00 1 clk cycle

01 4 clk cycles
10 16 clk cycles
11 128 clk cycles

01 Mode 1
10 Mode 2
11 Mode 3

1Disabled

00 Tb = 0 clk cycle
01 Tb = 4 clk cycles
10 Tb = 8 clk cycles
11 Tb = 18 clk cycles

1Master mode

reset the internal SD timing
counters

00Ta = 1 clk cycle 00 h
01Ta = 4 clk cycles
10Ta = 16 clk cycles
11Ta = 128 clk cycles

Setting any of these bits to 1 will
disable pedestal on the line
number indicated by the bit
settings.

Reset
Value

LINE 313 LINE 314LINE 1

SYNC

VSYNC

t

A

t

t

B

C

Figure 20. Timing Register 1 in PAL Mode

REV. 0

–27–

ADV7314

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

59h SD CGMS/WSS 0 SD CGMS Data 19 18 17 16 CGMS Data Bits C19–C16 0 0h

Reset Value

SD CGMS CRC 0 Disabled

SD CGMS on Odd 0 Disabled

SD CGMS on Even 0 Disabled

SD WSS 0 Disabled

5Ah SD CGMS/WSS 1 SD CGMS/WSS Data 13 12 11 10 9 8 CGMS Data Bits C13–C8 or

5Bh SD CGMS/WSS 2 SD CGMS/WSS Data 7 6 5 4 3 2 1 0 CGMS/WSS Data Bits C7–C0 00 h
5Ch SD LSB Register SD LSB for Y Scale x x SD Y Scale Bit 1–0

5Dh SD Y Scale SD Y Scale Value x x x x x x x x SD Y Scale Bit 7–2 0 0 h
5Eh SD V Scale SD V Scale Value x x x x x x x x SD V Scale Bit 7–2 0 0 h
5Fh SD U Scale SD U Scale Value x x x x x x x x SD U Scale Bit 7–2 00 h
60h SD Hue Register SD Hue Adjust Value x x x x xxx xSD Hue Adjust Bit 7–0 0 0 h
61h SD Brightness Value x x x x x x x SD Brightness Bit 6–0 00 h

SD Brightness/
WSS

62h SD Luma SSAF 0 0 0 0 0 0 0 0 –4 dB 0 0 h

63h SD DNR 0 Coring Gain Border 0 0 0 0 No gain 00h

64h SD DNR 1 DNR Threshold 0 0 0 0 0 0 0 0 0h

SD LSB for U Scale x x SD U Scale Bit 1–0
SD LSB for V Scale x x SD V Scale Bit 1–0
SD LSB for FSC Phase x x Subcarrier Phase Bits 1–0

SD Blank WSS Data 0 Disabled Line 23

SD Luma SSAF
Gain/Attenuation

Coring Gain Data 0 0 0 0 No gain

Border Area 0 2 pixels

Block Size Control 08 pixels

1 Enabled

1 Enabled

15 14 CGMS Data Bits C15–C14 0 0h

1 Enabled

000001100 dB
00001100+4 dB

0001 +1/16 [–1/8]
0010 +2/16 [–2/8]
0011 +3/16 [–3/8]
0100 +4/16 [–4/8]
0101 +5/16 [–5/8]
0110 +6/16 [–6/8]
0111 +7/16 [–7/8]
1000 +8/16 [–1]

14 pixels

116 pixels

1 Enabled

1 Enabled

WSS Data Bits C13–C8

000 1+1/16 [–1/8]
001 0+2/16 [–2/8]
001 1+3/16 [–3/8]
010 0+4/16 [–4/8]
010 1+5/16 [–5/8]
011 0+6/16 [–6/8]
011 1+7/16 [–7/8]
100 0+8/16 [–1]

00000 11
…………… ……
11111 062
11111 163

00h

In DNR
Mode the
values in
brackets
apply

REV. 0–28–

ADV7314

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

65h SD DNR 2 DNR Input Select 0 01Filter A 0 0h

1 0 0 Filter D

DNR Mode 0 DNR mode

1 DNR Sharpness mode

DNR Block Offset 0 0 0 0 0 pixel offset

000 11 pixel offset
……… … …
111 0 14 pixel offset

111 1 15 pixel offset
66h SD Gamma ASD Gamma Curve A Data Points x x x xxxx x A0 00h
67h SD Gamma ASD Gamma Curve A Data Points x x x xxxx x A1 00h
68h SD Gamma ASD Gamma Curve A Data Points x x x xxxx x A2 00h
69h SD Gamma ASD Gamma Curve A Data Points x x x xxxx x A3 00h
6Ah SD Gamma ASD Gamma Curve A Data Points x x x xxxx x A4 00h
6Bh SD Gamma ASD Gamma Curve A Data Points x x x xxxx x A5 00h
6ChSD Gamma ASD Gamma Curve A Data Points x x x xxxx x A6 00h
6Dh SD Gamma A SD Gamma Curve A Data Points x x x xxxxx A7 00h
6Eh SD Gamma ASD Gamma Curve A Data Points x x x xxxx x A8 00h
6FhSD Gamma ASD Gamma Curve A Data Points x x x xxxx x A9 00h
70h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B0 00h
71h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B1 00h
72h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B2 00h
73h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B3 00h
74h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B4 00h
75h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B5 00h
76h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B6 00h
77h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B7 00h
78h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B8 00h
79h SD Gamma B SD Gamma Curve B Data Points x x x xxxxx B9 00h
7Ah SD Brightness Detect SD Brightness Value x x x xxxxxRead only
7Bh Field Count Register Field Count x x x Read only

Reserved 0 0 must be written to this
Reserved 0 0 must be written to this
Reserved 0 0 must be written to this
Revision Code x x Read Only

7Ch 10-Bit Input 0 0 0 00010Must write this for 10 bit

0 10Filter B
0 11Filter C

Data Input (SD, PS, HD)

Reset Value

00h

REV. 0

–29–

ADV7314

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

7Dh Reserved
7Eh Reserved
7Fh Reserved
80h Macrovision MV Control Bits x x xxxxxx 00h
81h Macrovision MV Control Bits x x xxxxxx 00h
82h Macrovision MV Control Bits x x xxxxxx 00h
83h Macrovision MV Control Bits x x xxxxxx 00h
84h Macrovision MV Control Bits x x xxxxxx 00h
85h Macrovision MV Control Bits x x xxxxxx 00h
86h Macrovision MV Control Bits x x xxxxxx 00h
87h Macrovision MV Control Bits x x xxxxxx 00h
88h Macrovision MV Control Bits x x xxxxxx 00h
89h Macrovision MV Control Bits x x xxxxxx 00h
8Ah Macrovision MV Control Bits x x xxxxxx 00h
8Bh Macrovision MV Control Bits x x xxxxxx 00h
8ChMacrovision MV Control Bits x x xxxxxx 00h
8Dh Macrovision MV Control Bits x x xxxxxx 00h
8EhMacrovision MV Control Bits x x xxxxxx 00h
8FhMacrovision MV Control Bits x x xxxxxx 00h
90h Macrovision MV Control Bits x x xxxxxx 00h
91h Macrovision MV Control Bit x 00 h

0000000 0 must be written to

bits

Reset Value

REV. 0–30–

ADV7314

INPUT CONFIGURATION

When 10-bit input data is applied, the following bits must be
set to 1:

Address 0x7C, Bit 1 (Global 10-Bit Enable)

Address 0x13, Bit 2 (HD 10-Bit Enable)

Address 0x48, Bit 4 (SD 10-Bit Enable)

Note that the ADV7314 defaults to simultaneous standard
definition and progressive scan on power-up. Address[01h]:
Input Mode = 011.

Standard Definition Only
Address [01h] Input Mode = 000

The 8-bit/10-bit multiplexed input data is input on Pins S9–S0
(or Y9–Y0, depending on Register Address 0x01, Bit7), with S0
being the LSB in 10-bit input mode. Input standards supported
are ITU-R BT.601/656.

In 16-bit input mode, the Y pixel data is input on Pins S9–S2,
and CrCb data is input on Pins C9–C2. The 27 MHz clock
input must be input on the CLKIN_A pin.

Input sync signals are optional and are input on the S_VSYNC,
S_ HSYNC, and S_BLANK pins.

ADV7314

S_VSYNC

3

MPEG2

DECODER

27MHz

S_HSYNC
S_BLANK

CLKIN_A

Progressive Scan Only or HDTV Only
Address [01h] Input Mode 001 or 010, Respectively

YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y9–Y0 and the CrCb data on Pins C9–C0. In
4:4:4 input mode, Y data is input on Pins Y9–Y0, Cb data on
Pins C9–C0, and Cr data on Pins S9–S0.

If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004/1362, the async timing mode must
be used.

RGB data can be input in 4:4:4 format in PS Input mode only
or in HDTV Input mode only when HD RGB input is enabled.
G data is input on Pins Y9–Y0, R data on S9–S0, and B data
on C9–C0.

The clock signal must be input on the CLKIN_A pin.

MPEG2

DECODER

YCrCb

INTERLACED

TO

PROGRESSIVE

27MHz

Cb

Cr

Y

ADV7314

CLKIN_A

10

C[9:0]

10

S[9:0]

10

Y[9:0]

P_VSYNC

3

P_HSYNC
P_BLANK

Figure 22. Progressive Scan Input Mode

YCrCb

*Selected by Address 0x01 Bit 7

10

S[9:0] or Y[9:0]*

Figure 21 . SD Only Input Mode

REV. 0

–31–

ADV7314

Simultaneous Standard Definition and
Progressive Scan or HDTV
Address [01h]: Input Mode 011(SD 40-Bit, PS 20-Bit) or
101 (SH and HD, SD Oversampled), 110 (SD and HD, HD
Oversampled)

YCrCb PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode, the HD Y data is input on
Pins Y9–Y0 and the HD CrCb data on C9–C0.

If PS 4:2:2 data is interleaved onto a single 10-bit bus, Y9–Y0 are
used for the input port. The input data is to be input at 27 MHz
with the data clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accordingly.

If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004, the Async Timing mode must
be used.

The 8-bit or 10-bit standard definition data must be compliant
to ITU-R BT.601/656 in 4:2:2 format.

Standard definition data is input on Pins S9–S0, with S0 being the
LSB. Using 8-bit input format, the data is input on Pins S9–S2.

The clock input for SD must be input on CLKIN_A, and the
clock input for HD must be input on CLKIN_B.

Synchronization signals are optional. SD syncs are input on pins
S_VSYNC, S_ HSYNC, and S_BLANK.

HD syncs are input on Pins P_VSYNC, P_ HSYNC, P_BLANK.

ADV7314

S_VSYNC

3

MPEG2

DECODER

YCrCb

27MHz

S_HSYNC
S_BLANK

CLKIN_A

10

S[9:0]

ALIGN bit [Address 01h, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.

CLKIN_A

CLKIN_B

t

9.25ns OR

DELAY

t

27.75ns

DELAY

Figure 25. Clock Phase with Two Input Clocks

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address [01h]: Input Mode 100 OR 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or 54
MHz. The input data is interleaved onto a single 8-/10-bit bus
and is input on Pins Y9–Y0. When a 27 MHz clock is supplied,
the data is clocked in on the rising and falling edge of the input
clock and CLOCK EDGE [Address 01h, Bit 1] must be set
accordingly.

The following figures show the possible conditions. (a) Cb data
on the rising edge and (b) Y data on the rising edge.

CLKIN_B

Y9–Y0

3FF 00 00 XY Y0 Y1Cr0

Cb0

Figure 26a. Clock Edge Address 01h, Bit 1
Should Be Set to 0

CLKIN_B

CrCb

10
INTERLACED TO
PROGRESSIVE

Y

27MHz

C[9:0]

10

Y[9:0]

P_VSYNC

3

P_HSYNC
P_BLANK

CLKIN_B

Figure 23. Simultaneous PS and SD Input

ADV7314

S_VSYNC

3

SDTV

DECODER

HDTV

DECODER

1080 i

720 p

27MHz

YCrC b

CrCb

Y

74.25MHz

S_HSYNC
S_BLANK

CLKIN_A

10

S[9:0]

10

C[9:0]

10

Y[9:0]

P_VSYNC

3

P_HSYNC
P_BLANK

CLKIN_B

Figure 24. Simultaneous HD and SD Input

If in simultaneous SD/HD input mode, the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK

Y9–Y0

3FF 00 00 XY Cb0 Cr0Y1

Y0

Figure 26b. Clock Edge Address 01h, Bit 1
Should Be Set to 1

With a 54 MHz clock, the data is latched on the every rising edge.

CLKIN

PIXEL INPUT

DATA

3FF 00 00 XY Cb0 Y0 Y1Cr0

Figure 26c. Input Sequence in PS Bit Interleaved
Mode, EAV/SAV Followed by Cb0 Data

MPEG2

DECODER

YCrCb

INTERLACED

TO

PROGRESSIVE

27MHz OR

54MHz

YCrCb

ADV7314

CLKIN_A

10

Y[9:0]

P_VSYNC

3

P_HSYNC
P_BLANK

Figure 27. 1 10-Bit PS at 27 MHz or 54 MHz

REV. 0–32–

Table I provides an overview of all possible input configurations.

Table I. Input Configurations

ADV7314

Input Format Total Bits Input Video Input Pins Subaddress Register Setting

ITU-R BT.656 01h 00h

PS Only 01h 10h

HDTV Only 16 4:2:2 Y Y9-Y2 [MSB = Y9] 01h 20h

HD RGB

ITU-R BT.656 and PS

ITU-R BT.656 and PS

ITU-R BT.656 and PS or HDTV

ITU-R BT.656 and PS or HDTV

8 4:2:2

10 4:2:2

16 Y S9-S2 [MSB = S9] 01h 00h

20 Y S9-S0 [MSB = S9] 01h 00h

8 YCrCb Y9-Y2 [MSB = Y9] 01h 80h

10 YCrCb Y9-Y0 [MSB = Y9] 01h 80h

8 [27 MHz clock] 4:2:2

10 [27 MHz clock] 4:2:2

8 [54 MHz clock] YCrCb Y9-Y2 [MSB = Y9]

16 Y Y9-Y2 [MSB = Y9] 01h 10h

20 Y Y9-Y0 [MSB = Y9] 01h 10h

24 4:4:4 Y Y9-Y2 [MSB = Y9] 01h 10h

30 4:4:4 Y Y9-Y0 [MSB = Y9] 01h 10h

20 4:2:2 Y Y9-Y0 [MSB = Y9] 01h 20h

24 4:4:4 Y Y9-Y2 [MSB = Y9] 01h 20h

30 4:4:4 Y Y9-Y0 [MSB = Y9] 01h 20h

24 4:4:4 G Y9-Y2 [MSB = Y9] 01h 10h or 20h

30 4:4:4 G Y9-Y0 [MSB = Y9] 01h 10h or 20h

8 4:2:2 YCrCb S9-S2 [MSB = S9] 01h 40h
8 4:2:2

10 4:2:2 YCrCb S9-S0 [MSB = S9] 01h 40h

10 4:2:2 YCrCb Y9-Y0 [MSB = Y9]

8 4:2:2 YCrCb S9-S2 [MSB = S9] 01h 30h or 50h or 60h
16 4:2:2 Y Y9-Y2 [MSB = Y9] 13h 60h

10 4:2:2 YCrCb S9-S0 [MSB = S9] 01h 30h or 50h or 60h

20 4:2:2 Y Y9-Y0 [MSB = Y9] 13h 60h

YCrCb S9-S2 [MSB = S9]

YCrCb S9-S0 [MSB = S9]

4:2:2

CrCb Y9-Y2 [MSB = Y9] 48h 08h

4:2:2

CrCb Y9-Y0 [MSB = Y9] 48h 18h

4:2:2

4:2:2

YCrCb Y9-Y2 [MSB = Y9]

YCrCb Y9-Y0 [MSB = Y9]

4:2:2

4:2:210 [54 MHz clock]

YCrCb Y9-Y0 [MSB = Y9]

4:2:2

CrCb C9-C2 [MSB = C9] 13h 40h

4:2:2

CrCb C9-C0 [MSB = C9] 13h 44h

Cb C9-C2 [MSB = C9] 13h 00h
Cr S9-S2 [MSB = S9]

Cb C9-C0 [MSB = C9] 13h 04h

Cr S9-S0 [MSB = S9]

CrCb C9-Y2 [MSB = C9] 13h 40h

CrCb C9-C0 [MSB = C9] 13h 44h

Cb C9-Y2 [MSB = C9] 13h 00h
Cr S9-S2 [MSB = S9]

Cb C9-C0 [MSB = C9] 13h 04h

Cr S9-S0 [MSB = S9]

BC9-C2 [MSB = C9] 13h 00h

R S9-S2 [MSB = S9] 15h 02h

BC9-C0 [MSB = C9] 13h 04h
R S9-S0 [MSB = S9] 15h 02h

YCrCb Y9-Y2 [MSB = Y9]

CrCb C9-C2 [MSB = C9] 48h 00h

CrCb C9-C0 [MSB = C9] 48h 10h

48h 00h

01h 00h
48h 10h

48h 00h

48h 10h

13h 40h

01h 10h

13h 44h
01h 70h

13h 40h
70h 10h

13h 44h

13h 40h

48h 00h

13h 44h
48h 10h

REV. 0

–33–

ADV7314

OUTPUT CONFIGURATION

These tables show which output signals are assigned to the DACs when the control bits are set accordingly.

Table II. Output Configuration in SD Only Mode

RGB/YUV
Output 02h,
Bit 5

000CVBS Luma Chroma G B R

001GBR CVBS Luma Chroma

010GLuma Chroma CVBS B R

011CVBS B R G Luma Chroma

100CVBS Luma Chroma Y U V

101YUV CVBS Luma Chroma

110YLuma Chroma CVBS U V

111CVBS U V Y Luma Chroma

SD DAC
Output 1
42h, Bit 2

SD DAC
Output 2
42h, Bit 1 DAC A DAC B DAC C DAC D DAC E

DAC F

0

1 Table above with all Luma/Chroma instances swapped

Luma/Chroma Swap 44h, Bit 7

Table as above

Table III. Output Configuration in HD/PS Only Mode

HD Input
Format

YCrCb 4:2:2 0 0 0 N /A N/A N/A G B R

YCrCb 4:2:2 0 0 1 N /A N/A N/A G R B

YCrCb 4:2:2 0 1 0 N /A N/A N/A Y Pb Pr

YCrCb 4:2:2 0 1 1 N /A N/A N/A Y Pr P b

YCrCb 4:4:4 0 0 0 N /A N/A N/A G B R

YCrCb 4:4:4 0 0 1 N /A N/A N/A G R B

YCrCb 4:4:4 0 1 0 N /A N/A N/A Y Pb Pr

YCrCb 4:4:4 0 1 1 N /A N/A N/A Y Pr P b

RGB 4:4:4 1 0 0 N /A N/ A N /A G B R

RGB 4:4:4 1 0 1 N /A N/ A N /A G R B

RGB 4:4:4 1 1 0 N /A N/ A N /A G B R

RGB 4:4:4 1 1 1 N /A N/ A N /A G R B

HD RGB
Input 15h,
Bit 1

RGB/YPrP
b Output
02h, Bit 5

HD Color
Swap 15h,
Bit 3 DAC A DAC B DAC C DAC D DAC E

Table IV. Output Configuration in Simultaneous SD and HD/PS Mode

Input Formats

ITU-R BT.656 and
HD YCrCb in 4:2:2

ITU-R BT.656 and
HD YCrCb in 4:2:2

ITU-R BT.656 and
HD YCrCb in 4:2:2

ITU-R BT.656 and
HD YCrCb in 4:2:2

RGB/YPrP
b Output
02h, Bit 5

00CVBS Luma Chroma G B R

01CVBS Luma Chroma G R B

10CVBS Luma Chroma Y Pb Pr

11CVBS Luma Chroma Y Pr Pb

HD Color
Swap 15h,
Bit 3 DAC A DAC B DAC C DAC D DAC E

DAC F

DAC F

REV. 0–34–

ADV7314

TIMING MODES

HD Async Timing Mode
[Subaddress 10h, Bit 3,2]

For any input data that does not conform to the standards
selectable in input mode, Subaddress 01h, asynchronous tim­ing mode can be used to interface to the ADV7314. Timing
control signals for HSYNC, VSYNC, and BLANK have to be
programmed by the user. Macrovision and programmable

CLK

P_HSYNC

P_VSYNC

P_BLANK

SET ADDRESS 10h,

BIT 6 TO 1

HORIZONTAL SYNC

oversampling rates are not available in async timing mode. When
using async mode, the PLL must be turned off [Subaddress
00h, Bit 1 = 1].

Figures 28a and 28b show an example of how to program the
ADV7314 to accept a different high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358. The truth table in Table V must be followed
when programming the control signals in async timing mode.

PROGRAMMABLE
INPUT TIMING

ACTIVE VIDEO

ANALOG
OUTPUT

Figure 28a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility

CLK

P_HSYNC

P_VSYNC

P_BLANK

SET ADDRESS 10h,

BIT 6 TO 1

ANALOG OUTPUT

81 66 66 243 1920

ab c

HORIZONTAL SYNC

ab c d e

d

ACTIVE VIDEO

e

Figure 28b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal

0

1

REV. 0

–35–

ADV7314

Table V. Async Timing Mode Truth Table

Reference in

P_HSYNC P_VSYNC P_BLANK* Figures 28a and 28b

1 -> 0 0 0 or 1 50% point of falling edge of tri-level horizontal sync signal a
00 -> 1 0 or 1 25% point of rising edge of tri-level horizontal sync signal b
0 -> 1 0 or 1 0 50% point of falling edge of tri-level horizontal sync signal c
10 or 1 0 -> 1 50% start of active video d
10 or 1 1 -> 0 50% end of active video e

*When async timing mode is enabled, P_BLANK [Pin 25] becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.

For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.

HD Timing Reset
[Subaddress 14h, Bit 0]

A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. On setting this bit back to 0,
the internal counters will commence counting again.

The minimum time the pin has to be held high is one clock
cycle, otherwise this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.

REV. 0–36–

ADV7314

SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2,1]

Together with the RTC_SCR_TR pin and SD Mode Register 3,
the ADV7314 can be used in timing reset mode, subcarrier phase
reset mode, or RTC mode.

Timing Reset Mode

A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set to
low), the internal counters will commence counting again, the
field count will start on Field 1, and the subcarrier phase will
be reset.

The minimum time the pin has to be held high is one clock
cycle; otherwise this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.

Subcarrier Phase Reset

A low-to-high transition on the RTC_SCR_TR pin (Pin 31) will
reset the subcarrier phase to zero on the field following the
subcarrier phase reset when the SD RTC/TR/SCR control bits
at Address 44h are set to 01.

DISPLAY

307 310

NO TIMING RESET APPLIED

START OF FIELD 4 OR 8 FSC PHASE = FIELD 4 OR 8

313 320

This reset signal will have to be held high for a minimum of one
clock cycle.

Since the field counter is not reset, it is recommended that the
reset signal should be applied in Field 7 [PAL] or Field 3
[NTSC]. The reset of the phase will then occur on the next
field, i.e., Field 1, being lined up correctly with the internal
counters. The field count register at Address 7Bh can be used to
identify the number of the active field.

RTC Mode

In RTC mode, the ADV7314 can be used to lock to an external
video source. The real-time control mode allows the ADV7314
to automatically alter the subcarrier frequency to compensate
for line length variations. When the part is connected to a device
that outputs a digital datastream in the RTC format (such as an
ADV7183A video decoder, see Figure 31), the part will auto­matically change to the compensated subcarrier frequency on a
line by line basis. This digital datastream is 67 bits wide and the
subcarrier is contained in Bits 0 to 21. Each bit is two clock
cycles long. 00h should be written into all four subcarrier
frequency registers when using this mode.

DISPLAY

START OF FIELD 1

307 1 2 3 4 5 6 7 21

TIMING RESET APPLIED

F

PHASE = FIELD 1

SC

Figure 29. Timing Reset Timing Diagram

DISPLAY

307 310 313 320

NO FSC RESET APPLIED

DISPLAY

307 310 313 320

FSC RESET APPLIED

START OF FIELD 4 OR 8

START OF FIELD 4 OR 8

Figure 30. Subcarrier Reset Timing Diagram

TIMING RESET PULSE

PHASE = FIELD 4 OR 8

F

SC

PHASE = FIELD 1

F

SC

F

SC

RESET PULSE

REV. 0

–37–

ADV7314

Reset Sequence

A reset is activated with a high-to-low transition on the RESET pin
[Pin 33] according to the timing specifications. The ADV7314
will revert to the default output configuration. Figure 32 illus­trates the RESET sequence timing.

SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]

In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync control bit can be used for non­standard input video, i.e., in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/field are reached. In rewind mode, this sync

CLKIN_A

COMPOSITE

VIDEO

e.g., VCR

OR CABLE

H/L TRANSITION

COUNT START

128

RTC

TIME SLOT 01

NOTES

1

FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7314 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0

PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7314.

2

SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE

3

SEQUENCE BIT
RESET ADV7314 DDS

LCC1

ADV7183A

VIDEO

DECODER

14 BITS

SUBCARRIER

PHASE

LOW

13 0

GLL

P19–P10

RESERVED

142119

4 BITS

RTC_SCR_TR

Y9-Y0/S9–S0*

signal usually occurs after the total number of lines/field are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming
video and one when the internal lines/field counters reach the
end of a field.

When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5] the lines/field counters are updated according to the
incoming VSYNC signal and the analog output matches the
incoming VSYNC signal.

This control is available in all slave timing modes except Slave
Mode 0.

ADV7314

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

PLL INCREMENT

F

SC

VALID

INVALID

SAMPLE

SAMPLE

*SELECTED BY REGISTER
ADDRESS 01h BIT 7

SEQUENCE

1

8/LINE

LOCKED

CLOCK

BIT

0

2

RESET

BIT

RESERVED

6768

5 BITS

RESERVED

3

RESET

DACs

A, B, C

DIGITAL TIMING

PIXEL DATA

VALID

XXXXXX

XXXXXX

Figure 31. RTC Timing and Connections

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

Figure 32.

RESET

Timing Sequence

VALID VIDEO

TIMING ACTIVE

REV. 0–38–

ADV7314

H

B

Vertical Blanking Interval

The ADV7314 accepts input data that contains VBI data [e.g.,
CGMS, WSS, VITS] in SD and HD modes.

For SMPTE 293M [525p] standards, VBI data can be inserted
on Lines 13 to 42 of each frame, or Lines 6 to 43 for ITU-R
BT.1358 [625p] standard. For SD NTSC, this data can be
present on Lines 10 to 20, and in PAL on Lines 7 to 22.

If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.

In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/
SAV code is overwritten; it is possible to use VBI in this timing
mode as well.

In Slave mode 1 or 2, the BLANK control bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7314; otherwise the ADV7314 automatically blanks the
VBI to standard.

If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.

ANALOG

VIDEO

SD Subcarrier Frequency Registers
[Subaddress 4Ch–4Fh]

Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated in using the following
equation:

Subcarrier Frequency gister

Re =¥

#

MHz clk cycles in one video line

#27

23

2

Subcarrier Frequency Value

For example, in NTSC mode,

227 5

.

Ê

ˆ

23

Subcarrier FrequencyValue =

Á
Ë

1716

2 569408542

¥=

˜
¯

SD FSC Register 0: 1Eh
SD F

Register 1: 7Ch

SC

Register 2: F0h

SD F

SC

Register 3: 21h

SD F

SC

Refer to the MPU Port Description section for more details on
how to access the subcarrier frequency registers.

Square Pixel Timing [Register 42h, Bit 4]

In square pixel mode, the following timing diagrams apply.

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

EAV CODE

C

FF0000X

Y

Y

r

4 CLOCK

4 CLOCK

END OF ACTIVE

VIDEO LINE

8

10801

0

Y

0

FF00FFABABA

ANCILLARY DATA

272 CLOCK

344 CLOCK

B

(HANC)

801

0

SAV CODE

8

10FF0

0

0

XYC

Y

0

0

b

4 CLOCK

4 CLOCK

START OF ACTIVE

VIDEO LINE

C

C

Y

Y

b

r

1280 CLOCK

1536 CLOCK

C

C

Y

b

r

Figure 33. EAV/SAV Embedded Timing

SYNC

FIELD

PAL = 44 CLOCK CYCLES

NTSC = 44 CLOCK CYCLES

LANK

PIXEL

DATA

PAL = 136 CLOCK CYCLES

NTSC = 208 CLOCK CYCLES

Cb Y

Cr Y

Figure 34. Active Pixel Timing

REV. 0

–39–

ADV7314

)

)

FILTER SECTION

Table VI shows an overview of the programmable filters avail­able on the ADV7314.

Table VI. Selectable Filters of the ADV7314

Filter Subaddress

SD Luma LPF NTSC 40h
SD Luma LPF PAL 40h
SD Luma Notch NTSC 40h
SD Luma Notch PAL 40h
SD Luma SSAF 40h
SD Luma CIF 40h
SD Luma QCIF 40h
SD Chroma 0.65 MHz 40h
SD Chroma 1.0 MHz 40h
SD Chroma 1.3 MHz 40h
SD Chroma 2.0 MHz 40h
SD Chroma 3.0 MHz 40h
SD Chroma CIF 40h
SD Chroma QCIF 40h
SD UV SSAF 42h
HD Chroma Input 13h
HD Sinc Filter 13h
HD Chroma SSAF 13h

HD Sinc Filter

0.5

0.4

0.3

0.2

0.1

0

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

Figure 35. HD Sinc Filter Enabled

0.5

0.4

0.3

0.2

0.1

0

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

10 15 20 25

FREQUENCY (MHz

10 15 20 25

FREQUENCY (MHz

3050

3050

Figure 36. HD Sinc Filter Disabled

REV. 0–40–

ADV7314

SD Internal Filter Response
[Subaddress 40h; Subaddress 42, Bit 0]

The Y filter supports several different frequency responses includ­ing two low-pass responses, two notch responses, an extended
(SSAF) response, with or without gain boost/attenuation, a CIF
response and a QCIF response. The UV filter supports several
different frequency responses, including six low-pass responses,
a CIF response and a QCIF response, as can be seen in the
Typical Performance Characteristics graphs.

If SD SSAF gain is enabled, there are 12 possible responses in
the range from –4 dB to +4 dB [Subaddress 47h, Bit 4]. The
desired response can be chosen by the user by programming the
correct value via the I2C [Subaddress 62h]. The variation of
frequency responses can be seen in the Typical Performance
Characteristics graphs.

Table VII. Internal Filter Specifications

Pass-Band Ripple 3 dB Bandwidth

Filter (dB) (MHz)

Luma LPF NTSC 0.16 4.24
Luma LPF PAL 0.1 4.81
Luma Notch NTSC 0.09 2.3/4.9/6.6
Luma Notch PAL 0.1 3.1/5.6/6.4
Luma SSAF 0.04 6.45
Luma CIF 0.127 3.02
Luma QCIF Monotonic 1.5
Chroma 0.65 MHz Monotonic 0.65
Chroma 1.0 MHz Monotonic 1
Chroma 1.3 MHz 0.09 1.395
Chroma 2.0 MHz 0.048 2.2
Chroma 3.0 MHz Monotonic 3.2
Chroma CIF Monotonic 0.65
Chroma QCIF Monotonic 0.5

1

Pass-band ripple refers to the maximum fluctuations from the 0 dB response in

the pass band, measured in dB. The pass band is defined to have 0 Hz to fc
(Hz) frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to
infinity for a notch filter, where fc, f1, f2 are the –3 dB points.

2

3 dB bandwidth refers to the –3 dB cutoff frequency.

In addition to the chroma filters listed in Table VII, the ADV7314
contains an SSAF filter specifically designed for and applicable
to the color difference component outputs, U and V.

This filter has a cutoff frequency of about 2.7 MHz and –40 dB
at 3.8 MHz, as can be seen in Figure 37. This filter can be
controlled with Address 42h, Bit 0.

If this filter is disabled, the selectable chroma filters shown in
Table VII can be used for the CVBS or Luma/Chroma signal.

EXTENDED UV FILTER MODE

0

–10

–20

–30

GAIN (dB)

–40

–50

–60

FREQUENCY (MHz)

6543210

Figure 37. UV SSAF Filter

REV. 0

–41–

ADV7314–Typical Performance Characteristics

PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 1. PS – UV 8 Oversampling Filter—Linear

Y RESPONSE IN PS OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 2. PS –Y 8 Oversampling Filter

PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 4. PS – UV 8 Oversampling Filter—SSAF

1.0

0.5

0

–0.5

–1.0

GAIN (dB)

–1.5

–2.0

–2.5

–3.0

Y PASSBAND IN PS OVERSAMPLING MODE

122468100

FREQUENCY (MHz)

TPC 5. PS – Y 8 Oversampling Filter—Pass Band

Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

TPC 3. HDTV – UV 2 Oversampling Filter

Y RESPONSE IN HDTV OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

14020 40 60 80 100 1200

–80

FREQUENCY (MHz)

14020 40 60 80 100 1200

TPC 6. HDTV – Y 2 Oversampling Filter

REV. 0–42–

ADV7314

)

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz

TPC 7. Luma NTSC Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

TPC 8. Luma NTSC Notch Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

121086420

–70

FREQUENCY (MHz)

121086420

TPC 10. Luma PAL Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

121086420

–70

FREQUENCY (MHz)

121086420

TPC 11. Luma PAL Notch Filter

REV. 0

Y RESPONSE IN SD OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

020406080100 120 140 160 180 200

FREQUENCY (MHz)

TPC 9. Y—16 Oversampling Filter

–43–

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

TPC 12. Luma SSAF Filter up to 12 MHz

121086420

ADV7314

)

)

4

2

0

–2

–4

–6

MAGNITUDE (dB)

–8

–10

–12

01234 7

FREQUENCY (MHz)

5

6

TPC 13. Luma SSAF Filter—Programmable Responses

1

0

–1

–2

MAGNITUDE (dB)

–3

5

4

3

2

MAGNITUDE (dB)

1

0

–1

01234 7

FREQUENCY (MHz

5

6

TPC 16. Luma SSAF Filter—Programmable Gain

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–4

–5

01234 7

FREQUENCY (MHz

5

6

TPC 14. Luma SSAF Filter—Programmable Attenuation

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 15. Luma QCIF LP Filter

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 17. Luma CIF LP Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 18. Chroma 3.0 MHz LP Filter

REV. 0–44–

ADV7314

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 19. Chroma 2.0 MHz LP Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 22. Chroma 1.3 MHz LP Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 20. Chroma 1.0 MHz LP Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 21. Chroma CIF LP Filter

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 23. Chroma 0.65 MHz LP Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 24. Chroma QCIF LP Filter

REV. 0

–45–

ADV7314

COLOR CONTROLS AND RGB MATRIX

HD/PS Y Level, Cr Level, Cb Level
[Subaddress 16h–18h]

Three 8-bit registers at Address 16h, 17h, 18h are used to program
the output color of the internal HD test pattern generator, whether
it is the lines of the cross hatch pattern or the uniform field test
pattern. They are not functional as color controls on external
pixel data input. For this purpose, the RGB matrix is used.

The standard used for the values for Y and the color difference
signals to obtain white, black, and the saturated primary and
complementary colors conforms to the ITU-R BT.601–4 standard.

Table VIII shows sample color values to be programmed into
the color registers when Output Standard Selection is set to
EIA 770.2.

Table VIII. Sample Color Values for
EIA770.2 Output Standard Selection

Sample Color Y Color CR Color CB
Color Value Value Value

White 235 (EB) 128 (80) 128 (80)
Black 16 (10) 128(80) 128 (80)
Red 81 (51) 240 (F0) 90 (5A)
Green 145 (91) 34 (22) 54 (36)
Blue 41 (29) 110 (6E) 240 (F0)
Yellow 210 (D2) 146 (92) 16 (10)
Cyan 170 (AA) 16 (10) 166 (A6)
Magenta 106 (6A) 222 (DE) 202 (CA)

HD RGB Matrix
[Subaddress 03h–09h]

When the programmable RGB matrix is disabled [Address 02h,
Bit 3], the internal RGB matrix takes care of all YCrCb to YUV
or RGB scaling according to the input standard programmed
into the device.

When the programmable RGB matrix is enabled, the color
components are converted according to the 1080i standard
[SMPTE 274M]:

Y' = 0.2126R' + 0.7152 G' + 0.0722 B'
CR' = [0.5/(1 – 0.0722)] (B'–Y')
CR' = [0.5/(1 – 0.2126)] (R'–Y')

This is reflected in the preprogrammed values for GY = 138Bh,
GU = 93h, GV = 3B, BU = 248h, RV = 1F0.

If another input standard is used, the scale values for GY, GU,
GV, BU, and RV have to be adjusted according to this input
standard. The user must consider that the color component
conversion might use different scale values. For example,
SMPTE 293M uses the following conversion:

Y' = 0.299 R' + 0.587 G' + 0.114 B'
CB' = [0.5 / (1 – 0.114)] (B'–Y')
CR' = [0.5 / (1 – 0.299)] (R'–Y')

The programmable RGB matrix can be used to control the HD
output levels in cases where the video output does not conform
to standard due to altering the DAC output stages such as ter­mination resistors. The programmable RGB matrix is used for
external HD data and is not functional when the HD test pattern
is enabled.

Programming the RGB Matrix

The RGB matrix should be enabled [Address 02h, Bit 3], the
output should be set to RGB [Address 02h, Bit 5], sync on
PrPb should be disabled [Address 15h, Bit 2], sync on RGB is
optional [Address 02h, Bit 4].

GY at Addresses 03h and 05h control the output levels on the
green signal, BU at 04h and 08h control the blue signal output
levels, and RV at 04h and 09h control the red output levels. To
control YPrPb output levels, YUV output should be enabled
[Address 02h, Bit 5]. In this case GY [Address 05h; Address 03,
Bit 0–1] is used for the Y output, RV [Address 09; Address 04,
Bit 0–1] is used for the Pr output and BU [Address 08h; Address
04h, Bit 2–3] is used for the Pb output.

If RGB output is selected the RGB matrix scaler uses the fol­lowing equations:

G = GY  Y + GU  Pb + GV  Pr
B = GY  Y + BU  Pb
R = GY  Y + RV  Pr

If YUV output is selected the following equations are used:

Y = GY  Y

U = BU  Pb

V = RV  Pr

On power-up, the RGB matrix is programmed with default values:

Table IX. RGB Matrix Default Values

Address Default

03h 03h
04h F0h
05h 4Eh
06h 0Eh
07h 24h
08h 92h
09h 7Ch

When the programmable RGB matrix is not enabled, the
ADV7314 automatically scales YCrCb inputs to all standards
supported by this part.

SD Luma and Color Control
[Subaddresses 5Ch, 5Dh, 5Eh, 5Fh]

SD Y scale, SD Cr scale, and SD Cb scale are 10-bit control
registers to scale the Y, U, and V output levels.

Each of these registers represents the value required to scale the
U or V level from 0.0 to 2.0 and Y level from 0.0 to 1.5 of its
initial level. The value of these 10 bits is calculated using the
following equation:

Y, U, or V Scalar Value = Scale Factor  512

For example:

Scale Factor = 1.18

Y, U, or V Scale Value = 1.18  512 = 665.6
Y, U, or V Scale Value = 665 (rounded to the nearest integer)
Y, U, or V Scale Value = 1010 0110 01b

Address 5Ch, SD LSB Register = 15h
Address 5Dh, SD Y Scale Register = A6h
Address 5Eh, SD V Scale Register = A6h
Address 5Fh, SD U Scale Register = A6h

REV. 0–46–

ADV7314

SD Hue Adjust Value
[Subaddress 60h]

The hue adjust value is used to adjust the hue on the composite
and chroma outputs.

These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during
the color burst. The ADV7314 provides a range of ±22.5∞ incre­ments of 0.17578125∞. For normal operation (zero adjustment),
this register is set to 80h. FFh and 00h represent the upper and
lower limit (respectively) of adjustment attainable.

(Hue Adjust) [∞] = 0.17578125∞  (HCRd –128), for positive
hue adjust value.

Ê
Á

0 17578125

.

Ë

*Rounded to the nearest integer.

ˆ

4

128 151 97

+= =dh*

˜
¯

To adjust the hue by –4∞, write 69h to the hue adjust value
register:

Ê

-

Á

0 17578125

.

Ë

*Rounded to the nearest integer.

SD Brightness Control
[Subaddress 61h]

ˆ

4

+= =

128 105 69

˜
¯

dh*

The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and
PAL, the setup can vary from –7.5 IRE to +15 IRE.

The brightness control register is an 8-bit register. Seven bits of
this 8-bit register are used to control the brightness level. This
brightness level can be a positive or negative value. For example:

Standard: NTSC with pedestal.
To add +20 IRE brightness level, write 28h to Address 61h, SD
brightness.

[]

SD BrightnessValue H

[.]

IREValue H

[. ][.]

20 2 015631 40 31262 28

¥=

2 015631

¥= =

HHH

=

Standard: PAL.
To add –7 IRE brightness level, write 72h to Address 61h, SD
brightness.

IRE Value

[]

¥

72015631 14 109417 0001110

..

[]

0001110 1110010 72

[]=[]

2 015631

¥

.

=

[]

o twos complement B h

int

Table X. Brightness Control Values*

=

=

b

=

Setup Setup
Level In Level In Setup
NTSC with NTSC No Level In SD
Pedestal Pedestal PAL Brightness

22.5 IRE 15 IRE 15 IRE 1Eh
15 IRE 7.5 IRE 7.5 IRE 0Fh

7.5 IRE 0 IRE 0 IRE 00h
0 IRE –7.5 IRE –7.5 IRE 71h

*Values in the range from 3Fh to 44h might result in an invalid output signal.

SD Brightness Detect
[Subaddress 7Ah]

The ADV7314 allows monitoring of the brightness level of the
incoming video data. Brightness detect is a read-only register.

Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]

Double buffered registers are updated once per field on the
falling edge of the VSYNC signal. Double buffering improves
the overall performance since modifications to register settings
will not be made during active video, but take effect on the start
of the active video.

Double buffering can be activated on the following HD registers:
HD Gamma A and Gamma B curves and HD CGMS registers.
Double buffering can be activated on the following SD regis­ters: SD Gamma A and Gamma B curves, SD Y scale, SD U
scale, SD V scale, SD brightness, SD closed captioning, and
SD Macrovision Bits 5–0.

REV. 0

NTSC WITHOUT PEDESTAL

100 IRE

0 IRE

VALUE ADDED

Figure 38. Examples for Brightness Control Values

NO SETUP

POSITIVE SETUP

VALUE ADDED

–47–

NEGATIVE SETUP

VALUE ADDED

+7.5 IRE

–7.5 IRE

ADV7314

PROGRAMMABLE DAC GAIN CONTROL

DACs A, B, and C are controlled by Register 0A.
DACs D, E, and F are controlled by Register 0B.

2

C control registers will adjust the output signal gain up or

The I
down from its absolute level.

CASE A

GAIN PROGRAMMED IN DAC O/P LEVEL

700mV

300mV

700mV

300mV

REGISTERS, SUBADDRESS 0Ah, 0Bh

CASE B

NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0Ah, 0Bh

Figure 39. Programmable DAC Gain—Positive
and Negative Gain

In case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the
signal is increased from the reference signal.

In case B, the video output signal is reduced. The absolute
level of the sync tip and blanking level both decrease with respect
to the reference video output signal. The overall gain of the signal
is reduced from the reference signal.

The range of this feature is specified for ± 7.5% of the nominal
output from the DACs. For example, if the output current of
the DAC is 4.33 mA, the DAC tune feature can change this
output current from 4.008 mA (–7.5%) to 4.658 mA (+7.5%).

The reset value of the vid_out_ctrl registers is 00h –> nominal
DAC output current. Table XI is an example of how the output
current of the DACs varies for a nominal 4.33 mA output current.

Table XI.

DAC
Register Current
0Ah or 0Bh (mA) % Gain

0100 0000 (40h) 4.658 7.5000
0011 1111 (3Fh) 4.653 7.3820
0011 1110 (3Eh) 4.648 7.3640

... ... ...

... ... ...

0000 0010 (02h) 4.43 0.0360
0000 0001 (01h) 4.38 0.0180
0000 0000 (00h) 4.33 0.0000 (I

2

C Reset Value,

Nominal)
1111 1111 (FFh) 4.25 –0.0180
1111 1110 (FEh) 4.23 –0.0360

... ... ...

... ... ...

1100 0010 (C2h) 4.018 –7.3640
1100 0001 (C1h) 4.013 –7.3820
1100 0000 (C0h) 4.008 –7.5000

REV. 0–48–

ADV7314

Gamma Correction

[Subaddress 24h–37h for HD, Subaddress 66h–79h for SD]

Gamma correction is available for SD and HD video. For each
standard there are 20 8-bit registers. They are used to program
the gamma correction curves A and B. HD gamma curve A is
programmed at Addresses 24h–2Dh, HD gamma curve B at
2Eh–37h. SD gamma curve A is programmed at addresses
66h–6Fh, and SD gamma curve B at Addresses 70h–79h.

Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wher­ever nonlinear processing is used.

Gamma correction uses the function

Signal Signal

=

()

OUT IN

g

where  = gamma power factor.

Gamma correction is performed on the luma data only. The
user has the choice to use two different curves, curve A or curve
B. At any time, only one of these curves can be used.

The response of the curve is programmed at 10 predefined
locations. In changing the values at these locations, the gamma
curve can be modified. Between these points linear interpolation
is used to generate intermediate values. Considering the curve
to have a total length of 256 points, the 10 locations are at 24,
32, 48, 64, 80, 96, 128, 160, 192, and 224. Location 0, 16,
240, and 255 are fixed and cannot be changed.

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

300

250

200

SIGNAL OUTPUT

0.5

For the length of 16 to 240, the gamma correction curve has to
be calculated as follows:



y = x

where:

y = gamma corrected output.
x = linear input signal.



= gamma power factor.

To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:

–16

g

˘

¥-

240 16 16

˙

-

()

˙

˚

+

È

x

n

y

n

()

=

Í

240 16

()

Í

Î

where:

x

= value for x along x-axis at points.

(n–16)

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.

y

= value for y along the y-axis, which has to be written into

n

the gamma correction register.

For example:
y
y
y
y
y
y
y
y
y

y

*rounded to the nearest integer

= [(8 / 224)

24

= [(16 / 224)

32

= [(32 / 224)

48

= [(48 / 224)

64

= [(64 / 224)

80

= [(80 / 224)

96

= [(112 / 224)

128

= [(144 / 224)

160

= [(176 / 224)

192

= [(208 / 224)

224

0.5

 224] + 16 = 58*

0.5

 224] + 16 = 76*

0.5

 224] + 16 = 101*

0.5

 224] + 16 =120*

0.5

 224] + 16 =136*

0.5

 224] + 16 = 150*

0.5

 224] + 16 = 174*

0.5

 224] + 16 = 195*

0.5

 224] + 16 = 214*

0.5

 224] + 16 = 232*

The gamma curves in Figure 41 are examples only; any user
defined curve is acceptable in the range of 16 to 240.

150

100

GAMMA CORRECTED AMPLITUDE

50

0

0

SIGNAL INPUT

50 100 150 200 250

LOCATION

Figure 40. Signal Input (Ramp) and
Signal Output for Gamma 0.5

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

300

250

200

150

100

GAMMA CORRECTED AMPLITUDE

50

0

0

VARIOUS GAMMA VALUES

0.3

0.5

1.5

SIGNAL INPUT

50 100 150 200 250

1.8

LOCATION

Figure 41. Signal Input (Ramp) and
Selectable Gamma Output Curves

REV. 0

–49–

ADV7314

HD Sharpness Filter Control and Adaptive Filter Control
[Subaddress 20h, 38h–3Dh]

There are three Filter modes available on the ADV7314:
sharpness filter mode and two adaptive filter modes.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 42, the following register settings must be used:
HD sharpness filter must be enabled and HD adaptive filter
enable must be disabled.

To select one of the 256 individual responses, the according gain
values for each filter, which range from –8 to +7, must be pro­grammed into the HD sharpness filter gain register at Address 20h.

HD Adaptive Filter Mode

The HD adaptive filter threshold A, B, C registers, the HD
adaptive filter gain 1, 2, 3 registers, and the HD sharpness filter
gain register are used in adaptive filter mode. To activate the
adaptive filter control, HD sharpness filter must be enabled and
HD adaptive filter gain must be enabled.

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

FREQUENCY (MHz)

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5

FILTER B RESPONSE (Gain Kb)

INPUT SIGNAL:

STEP

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5

FILTER A RESPONSE (Gain Ka)

Figure 42. Sharpness and Adaptive Filter Control Block Frequency Response in
Sharpness Filter Mode with Ka = +3 and Kb = +7

The derivative of the incoming signal is compared to the three
programmable threshold values: HD adaptive filter threshold
A, B, C. The recommended threshold range is from 16 to 235
although any value in the range of 0 to 255 can be used.

The edges can then be attenuated with the settings in HD adaptive
filter gain 1, 2, 3 registers and HD sharpness filter gain register.
According to the settings of the HD adaptive filter mode con­trol, there are two adaptive filter modes available:

1. Mode A is used when adaptive filter mode is set to 0. In this

case, Filter B (LPF) will be used in the adaptive filter block.
Also, only the programmed values for Gain B in the HD
sharpness filter gain, HD adaptive filter gain 1, 2, 3 are applied
when needed. The Gain A values are fixed and cannot be
changed.

2. Mode B is used when adaptive filter gain is set to 1. In this

mode, a cascade of Filter A and Filter B is used. Both set­tings for Gain A and Gain B in the HD sharpness filter gain,
HD adaptive filter gain 1, 2, 3 become active when needed.

1.6

1.5

1.4

1.3

1.2

1.1

MAGNITUDE RESPONSE (Linear Scale)

1.0

FREQUENCY (MHz)

024681012

FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7

FREQUENCY (MHz)

REV. 0–50–

ADV7314

HD Sharpness Filter and Adaptive Filter Application Examples

HD Sharpness Filter Application

The HD sharpness filter can be used to enhance or attenuate
the Y video output signal. The following register settings were
used to achieve the results shown in the figures below. Input
data was generated by an external signal source.

Table XII.

Register Reference in

Address Setting Figure 43

00h FCh
01h 10h
02h 20h
10h 00h
11h 81h
20h 00h a
20h 08h b
20h 04h c
20h 40h d
20h 80h e
20h 22h f

The effect of the sharpness filter can also be seen when using
the internally generated cross hatch pattern.

Table XIII.

Address Register Setting

00h FCh
01h 10h
02h 20h
10h 00h
11h 85h
20h 99h

In toggling the sharpness filter enable bit [Address 11h, Bit 7],
it can be seen that the line contours of the cross hatch pattern
change their sharpness.

d

e

f

R2

R4

1

CH1 500mV M 4.00s CH1

REF A 500mV 4.00s 1 9.99978ms

ALL FIELDS

a

1

b

R1

c

R2

CH1 500mV M 4.00s CH1

REF A 500mV 4.00s 1 9.99978ms

ALL FIELDS

Figure 43. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value

REV. 0

–51–

ADV7314

Adaptive Filter Control Application

Figures 44 and 45 show a typical signal to be processed by the
adaptive filter control block.

: 692mV
@: 446mV

: 332ns
@: 12.8ms

Figure 44. Input Signal to Adaptive Filter Control

: 692mV
@: 446mV

: 332ns
@: 12.8ms

Figure 45. Output Signal after Adaptive Filter Control

The following register settings were used to obtain the results
shown in Figure 45, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.

When changing the adaptive filter mode to Mode B, [Address
15h, Bit 6], the following output can be obtained:

: 674mV
@: 446mV

: 332ns
@: 12.8ms

Figure 46. Output Signal from Adaptive Filter Control

The adaptive filter control can also be demonstrated using the
internally generated cross hatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].

Table XV.

Address Register Setting

00h FCh
01h 38h
02h 20h
10h 00h
11h 85h
15h 80h
20h 00h
38h ACh
39h 9Ah
3Ah 88h
3Bh 28h
3Ch 3Fh
3Dh 64h

Table XIV.

Address Register Setting

00h FCh
01h 38h
02h 20h
10h 00h
11h 81h
15h 80h
20h 00h
38h ACh
39h 9Ah
3Ah 88h
3Bh 28h
3Ch 3Fh
3Dh 64h

*All other registers at normal settings.

REV. 0–52–

ADV7314

SD DIGITAL NOISE REDUCTION
[Subaddress 63h, 64h, 65h]

DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
[DNR input select]. The absolute value of the filter output is
compared to a programmable threshold value [DNR threshold
control]. There are two DNR modes available: DNR mode and
DNR sharpness mode.

In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount [coring gain border, coring gain data] of this noise
signal will be subtracted from the original signal.

In DNR sharpness mode, if the absolute value of the filter out­put is less than the programmed threshold, it is assumed to be
noise, as before. Otherwise, if the level exceeds the threshold,
now being identified as a valid signal, a fraction of the signal
[coring gain border, coring gain data] will be added to the origi­nal signal in order to boost high frequency components and to
sharpen the video image.

In MPEG systems, it is common to process the video information
in blocks of 8 pixels  8 pixels for MPEG2 systems, or 16 pixels
 16 pixels for MPEG1 systems [block size control]. DNR can
be applied to the resulting block transition areas that are known
to contain noise. Generally, the block transition area contains
two pixels. It is possible to define this area to contain four pixels
[border area].

It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the [DNR
block offset].

The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.

Coring Gain Border [Address 63h, Bits 3–0]

These four bits are assigned to the gain factor applied to
border areas.

In DNR mode, the range of gain values is 0–1, in increments of
1/8. This factor is applied to the DNR filter output, which lies
below the set threshold range. The result is then subtracted
from the original signal.

In DNR sharpness mode the range of gain values is 0–0.5, in
increments of 1/16. This factor is applied to the DNR filter
output which lies above the threshold range. The result is added
to the original signal.

Coring Gain Data [Address 63h, Bits 7-4]

These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.

In DNR mode the range of gain values is 0–1, in increments of
1/8. This factor is applied to the DNR filter output, which lies
below the set threshold range. The result is then subtracted
from the original signal.

In DNR sharpness mode, the range of gain values is 0–0.5, in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range. The result is added
to the original signal.

APPLY DATA
CORING GAIN

OXXXXXXOOXXXXXXO

APPLY BORDER
CORING GAIN

Y DATA

INPUT

Y DATA

INPUT

DNR MODE

NOISE
SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR
SHARPNESS
MODE

NOISE
SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA
BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

< THRESHOLD ?

FILTER OUTPUT

> THRESHOLD

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

> THRESHOLD ?

FILTER OUTPUT

< THRESHOLD

SUBTRACT SIGNAL
IN THRESHOLD
RANGE FROM
ORIGINAL SIGNAL

–

+

DNR OUT

ADD SIGNAL
ABOVE THRESHOLD
RANGE FROM
ORIGINAL SIGNAL

+

+

DNR OUT

OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING

DNR27 – DNR24 = 01H

OXXXXXXOOXXXXXXO

OXXXXXXOOXXXXXXO

Figure 48. DNR Block Offset Control

DNR Threshold [Address 64h, Bits 5–0]

These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.

Border Area [Address 64h, Bit 6]

In setting this bit to a Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to a Logic 0,
the border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.

720485 PIXELS

(NTSC)

88 PIXEL BLOCK 88 PIXEL BLOCK

2 PIXEL

BORDER

DATA

Figure 49. DNR Border Area

REV. 0

Figure 47. DNR Block Diagram

–53–

ADV7314

Block Size Control [Address 64h, Bit 7]

This bit is used to select the size of the data blocks to be processed.
Setting the block size control function to a Logic 1 defines a
16 pixel ¥ 16 pixel data block; a Logic 0 defines an 8 pixel ¥
8 pixel data block, where one pixel refers to two clock cycles at
27 MHz.

DNR Input Select Control [Address 65h, Bit 2–0]

Three bits are assigned to select the filter that is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that will be DNR processed. Figure 50
shows the filter responses selectable with this control.

1.0
FILTER D

0.8

FILTER C

0.6

MAGNITUDE

0.4

0.2

0

012 3456

FILTER B

FILTER A

FREQUENCY (Hz)

Figure 50. DNR Input Select

DNR Mode Control [Address 65h, Bit 4]

This bit controls the DNR mode selected. A Logic 0 selects
DNR mode; a Logic 1 selects DNR sharpness mode.

DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.

When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using extended SSAF filter).

Block Offset Control [Address 65h, Bits 7–4]

Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.

REV. 0–54–

ADV7314

SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]

When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the luma channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are ¥1/8, ¥1/2, ¥7/8. All
other active video passes through unprocessed.

LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED

100 IRE

0 IRE

Figure 51. Example for Active Video Edge Functionality

VOLTS

IRE:FLT

100

0.5

SAV/EAV Step Edge Control

The ADV7314 can control fast rising and falling signals at the
start and end of active video to minimize ringing.

An algorithm monitors SAV and EAV and governs when the
edges are too fast. The result will be reduced ringing at the start
and end of active video for fast transitions.

Subaddress 42h, Bit 7 = 1 enables this feature.

LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED

100 IRE

87.5 IRE

50 IRE

12.5 IRE
0 IRE

50

0

024

0

–50

Figure 52. Address 42h, Bit 7 = 0

VOLTS

0.5

IRE:FLT

100

50

0

0

F2
L135

681012

REV. 0

F2

–50

02–2 4 6 8 10 12

L135

Figure 53. Address 42h, Bit 7 = 1

–55–

ADV7314

BOARD DESIGN AND LAYOUT CONSIDERATIONS

DAC Termination and Layout Considerations

The ADV7314 contains an on-board voltage reference. The
ADV7314 can be used with an external V

The R

resistors are connected between the R

SET

(AD1580).

REF

SET

pins and
AGND and are used to control the full-scale output current and
therefore the DAC voltage output levels. For full-scale output,

must have a value of 3040 W. The R

R

SET

be changed. R

has a value of 150 W with a 4 gain stage

LOAD

values should not

SET

for full-scale output.

Video Output Buffer and Optional Output Filter

Output buffering on all six DACs is necessary in order to drive
output devices, such as SD or HD monitors. Analog Devices
produces a range of suitable op amps for this application, for
example the AD8061. More information on line driver buffering
circuits is given in the relevant op amp data sheets.

An optional analog reconstruction low-pass filter (LPF) may be
required as an anti-imaging filter if the ADV7314 is connected
to a device that requires this filtering. The filter specifications
vary with the application.

Table XVI. External Filter Requirements

Cutoff
Frequency Attenuation

Application Oversampling (MHz) –50 dB @ (MHz)

SD 2¥ >6.5 20.5
SD 16¥ >6.5 209.5
PS 1¥ >12.5 14.5
PS 8¥ >12.5 203.5
HDTV 1¥ >30 44.25
HDTV 2¥ >30 118.5

DAC OUTPUT

2.2H

22pF300

300

3

4

600

1.8k

75

1

Figure 54. Example for Output Filter for SD,



Oversampling

16

0

–5

–10

–15

–20

GAIN (dB)

–25

–30

–35

–40

1M 10M 100M

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

PHASE (Deg)

GROUP DELAY (sec)

FREQUENCY (Hz)

Figure 55. Filter Plot for Output Filter for SD,
16 Oversampling

BNC OUTPUT

0

16n

–30

14n

–60

12n

–90

10n

–120

8n

–150

6n

–180

4n

–210

2n

–240

0

REV. 0–56–

ADV7314

DAC OUTPUT

3.3H

22pF 300

22pF300

3

4

600

1.8k

1

BNC OUTPUT

75

Figure 56. Example for Output Filter for PS,

¥

Oversampling

8

DAC OUTPUT

300

3

4

75

1

220nH470nH

82pF33pF

75

3

4

500

BNC OUTPUT

1

500

Figure 57. Example for Output Filter for HDTV,

¥

Oversampling

2

Table XVII shows possible output rates from the ADV7314.

Table XVII.

Input Mode PLL Output
Address 01h, Bit 6–4 Address 00h, Bit 1 Rate

SD Only Off 27 MHz (2¥)

On 216 MHz (16¥)

PS Only Off 27 MHz (1¥)

On 216 MHz (8¥)

HDTV Only Off 74.25 MHz (1¥)

On 148.5 MHz (2¥)

0

–6

–12

–18

GROUP DELAY (sec)GROUP DELAY (sec)

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1M 10M 100M 1G

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

PHASE (Deg)

FREQUENCY (Hz)

Figure 58. Filter Plot for Output Filter for PS,
8

¥

Oversampling

0

–10

–20

GROUP DELAY (sec)

–30

GAIN (dB)

–40

PHASE (Deg)

–50

–60

1M 10M 100M 1G

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

FREQUENCY (Hz)

198

158

118

77.6

37.6

0

–42.4

–82.4

–122

–162

–202

480

360

240

120

0

–120

–240

20n

18n

16n

14n

12n

10n

8n

6n

4n

2n

0

18n

15n

12n

9n

6n

3n

0

Figure 59. Example for Output Filter HDTV,
2¥ Oversampling

REV. 0

–57–

ADV7314

PC BOARD LAYOUT CONSIDERATIONS

The ADV7314 is optimally designed for lowest noise perfor­mance, for both radiated and conducted noise. To complement
the excellent noise performance of the ADV7314, it is impera­tive that great care be given to the PC board layout.

The layout should be optimized for lowest noise on the ADV7314
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V

and GND_IO pins should be kept as short as possible to

V

DD_IO

and AGND, VDD and DGND, and

AA

minimized inductive ringing.

It is recommended that a 4-layer printed circuit board is used
with power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Com­ponent placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.

There should be a separate analog ground plane and a separate
digital ground plane.

Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, V

circuitry. The digital

REF

power plane should contain all logic circuitry.

The analog and digital power planes should be individually con­nected to the common power plane at one single point through a
suitable filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termi­nation resistors should be placed as close as possible to the
DAC outputs and should overlay the PCB’s ground plane. As
well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.

To avoid crosstalk between the DAC outputs, it is recommended
to leave as much space as possible between the tracks of the
individual DAC output pins. The addition of ground tracks
between outputs is also recommended.

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.

Optimum performance is achieved by the use of 10 nF and

0.1 mF ceramic capacitors. Each of group of V

, VDD, or V

AA

DD_IO

pins should be individually decoupled to ground. This should
be done by placing the capacitors as close as possible to the
device with the capacitor leads as short as possible, thus mini­mizing lead inductance.

A 1 mF tantalum capacitor is recommended across the V

supply

AA

in addition to a 10 nF ceramic capacitor. See Figure 60.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.

Due to the high clock rates used, long clock lines to the ADV7314
should be avoided to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not to the
analog power plane.

Analog Signal Interconnect

The ADV7314 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.

For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure 60. The termi­nation resistors should be as close as possible to the ADV7314
to minimize reflections.

For optimum performance, it is recommended that all decoupling
and external components relating to the ADV7314 be located on
the same side of the PCB and as close as possible to the ADV7314.

Any unused inputs should be tied to ground.

REV. 0–58–

V

AA

4.7k

4.7F

ADV7314

POWER SUPPLY DECOUPLING FOR

EACH POWER SUPPLY GROUP

ADV7314

V

AAVAA

3.9nF680

0.1F 0.1F

COMP2

COMP1

I2C

S0–S9

S_HSYNC

S_VSYNC

S

BLANK

C0–C9

Y0–Y9

CLKIN_B

P_HSYNC

P_VSYNC

P_BLANK

RESET

CLKIN_A

EXT_LF

GND_IO AGND DGND

AA

V

DD_IO

5k

V

AA

820pF

10, 56

VDDV

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

11, 57

VDD_

V

REF

SCLK

SDA

ALSB

R

SET2

R

SET1

10nF

IO

1F

10nF

10nF 0.1F

150

150

150

150

150

150

3040

3040

0.1F

100

100

V

AA

V

DD

V

DD_IO

VDD_

IO

5k

SELECTION HERE
DETERMINES
DEVICE ADDRESS

VDD_

IO

5k

VDD_

1.1k

100nF

IO

5k

V

AA

RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE

MPU
BUS

UNUSED INPUTS SHOULD BE GROUNDED.

Figure 60. ADV7314 Circuit Layout

REV. 0

–59–

ADV7314

APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM

PS CGMS Data Registers 2–0
[Subaddress 21h, 22h, 23h]

PS CGMS is available in 525p mode conforming to CGMS-A
EIA-J CPR1204-1, transfer method of video ID information using
vertical blanking interval (525p system), March 1998, and
IEC61880, 1998, Video systems (525/60)—video and accom­panied data using the vertical blanking interval—analog
interface.

When PS CGMS is enabled [Subaddress 12h, Bit 6 = 1],
CGMS data is inserted on line 41. The PS CGMS data registers
are at Addresses 21h, 22h, and 23h.

SD CGMS Data Registers 2–0
[Subaddress 59h, 5Ah, 5Bh]

The ADV7314 supports Copy Generation Management System
(CGMS), conforming to the standard. CGMS data is transmit­ted on Line 20 of the odd fields and Line 283 of even fields.
Bits C/W05 and C/W06 control whether or not CGMS data is
output on odd and even fields. CGMS data can be transmitted
only when the ADV7314 is configured in NTSC mode. The
CGMS data is 20 bits long, and the function of each of these bits
is as shown in Table XVIII. The CGMS data is preceded by a
reference pulse of the same amplitude and duration as a CGMS
bit; see Figure 62.

HD/PS CGMS [Address 12h, Bit 6]

The ADV7314 supports Copy Generation Management System
(CGMS) in HDTV mode (720p and 1080i) in accordance
with EIAJ CPR-1204-2.

The HD CGMS data registers can be found at Address 021h,
22h, 23h.

Function of CGMS Bits

Word 0–6 bits; Word 1–4 bits; Word 2–6 bits; CRC 6 bits
CRC polynomial = x

720p System

6

+ x + 1 (preset to 111111)

CGMS data is applied to Line 24 of the luminance vertical
blanking interval.

1080i System

CGMS data is applied to Line 19 and on Line 582 of the lumi­nance vertical blanking interval.

CGMS Functionality

If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC
[Subaddress 12h, Bit 7] is set to a Logic 1, the last six bits,
C19–C14, which comprise the 6-bit CRC check sequence, are
calculated automatically on the ADV7314 based on the lower
14 bits (C0–C13) of the data in the data registers and output
with the remaining 14 bits to form the complete 20 bits of the
CGMS data. The calculation of the CRC sequence is based on
the polynomial x

6

+ x + 1 with a preset value of 111111. If SD
CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC [Ad­dress 12h, Bit 7] is set to a Logic 0, all 20 bits (C0–C19) are
output directly from the CGMS registers (no CRC calculated,
must be calculated by the user).

Table XVIII.

Bit Function

WORD0 1 0
B1 Aspect ratio 16:9 4:3
B2 Display format Letterbox Normal
B3 Undefined

WORD0
B4, B5, B6 Identification information about video

and other signals (e.g., audio)

WORD1
B7, B8, B9, B10 Identification signal incidental to Word 0

WORD2
B11, B12, B13, B14 Identification signal and information

incidental to Word 0

REV. 0–60–

+700mV

70% 10%

0mV

–300mV

5.8s 0.15s
6T

REF

BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

21.2s 0.22s
22T

Figure 61. Progressive Scan CGMS Waveform

ADV7314

CRC SEQUENCE

T = 1/(fH  33) = 963ns
f

= HORIZONTAL SCAN FREQUENCY

H

T 30ns

+700mV

70% 10%

0mV

–300mV

+700mV

70% 10%

+100 IRE

+70 IRE

0 IRE

–40 IRE

11.2s

4T

3.128s 90ns

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

49.1s 0.5s

2.235s 20ns

Figure 62. Standard Definition CGMS Waveform

CRC SEQUENCE

REF

BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

T 30ns

17.2s 160ns
22T

1H

T = 1/(f

 1650/58) = 781.93ns

H

= HORIZONTAL SCAN FREQUENCY

f

H

Figure 63. HDTV 720P CGMS Waveform

CRC SEQUENCE

REF

BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

CRC SEQUENCE

0mV

–300mV

REV. 0

4T

4.15s 60ns

T 30ns

22.84s 210ns
22T

1H

T = 1/(f

 2200/77) = 1.038s

H

= HORIZONTAL SCAN FREQUENCY

f

H

Figure 64. HDTV 1080i CGMS Waveform

–61–

ADV7314

APPENDIX 2—SD WIDE SCREEN SIGNALING
[Subaddress 59h, 5Ah, 5Bh]

The ADV7314 supports wide screen signaling (WSS) conforming
to the standard. WSS data is transmitted on Line 23. WSS data
can be transmitted only when the ADV7314 is configured in PAL
mode. The WSS data is 14 bits long, and the function of each of
these bits is as shown in Table XIX. The WSS data is preceded

Table XIX. Function of WSS Bits

Bit Description

Bit 0–Bit 2 Aspect Ratio/Format/Position Bits

Bit 3 IS Odd Parity Check of Bit 0–Bit 2

B0, B1, B2, B3 Aspect Ratio Format Position
0 0 0 1 4:3 Full Format Not applicable
1 0 0 0 14:9 Letterbox Center
0 1 0 0 14:9 Letterbox Top

1 1 0 1 16:9 Letterbox Center
0 0 1 0 16:9 Letterbox Top
1 0 1 1 >16:9 Letterbox Center
0 1 1 1 14:9 Full Format Center
1 1 1 0 16:9 N/A N/A

B4
0Camera Mode
1Film Mode

B5
0 Standard Coding
1Motion Adaptive Color Plus

by a run-in sequence and a start code (see Figure 65). If SD
WSS [Address 59h, Bit 7] is set to a Logic 1, it enables the WSS
data to be transmitted on Line 23. The latter portion of Line 23
(42.5 ms from the falling edge of HSYNC) is available for the
insertion of video.

It is possible to blank the WSS portion of Line 23 with Subaddress
61h, Bit 7.

Bit Description

B6
0No Helper
1Modulated Helper

B7 Reserved

B9 B10
0 0 No Open Subtitles
1 0 Subtitles in Active Image Area
0 1 Subtitles out of Active Image Area
1 1 Reserved

B11
0No Surround Sound Information
1 Surround Sound Mode

B12 Reserved

B13 Reserved

500mV

11.0s

RUN-IN

SEQUENCE

START

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10

CODE

38.4s

42.5s

Figure 65. WSS Waveform Diagram

W11

W12

W13

ACTIVE

VIDEO

REV. 0–62–

ADV7314

APPENDIX 3—SD CLOSED CAPTIONING
[Subaddress 51h–54h]

The ADV7314 supports closed captioning conforming to the
standard television synchronizing waveform for color transmis­sion. Closed captioning is transmitted during the blanked active
line time of Line 21 of the odd fields and Line 284 of even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency- and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic Level 1 start bit. 16 bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits, and
one odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Address 53h–54h].

The ADV7314 also supports the extended closed captioning
operation, which is active during even fields and is encoded on
Scan Line 284. The data for this operation is stored in the SD
closed captioning registers [Address 51h–52h].

All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7314.
All pixels inputs are ignored during Lines 21 and 284 if closed
captioning is enabled.

10.5  0.25s 12.91s

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

50 IRE

40 IRE

REFERENCE COLOR BURST

FREQUENCY = F

(9 CYCLES)

= 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003s

27.382s 33.764s

FCC Code of Federal Regulations (CFR) 47 section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.

The ADV7314 uses a single buffering method. This means that
the closed captioning buffer is only one byte deep, therefore
there will be no frame delay in outputting the closed captioning
data unlike other two byte deep buffering systems. The data
must be loaded one line before (Line 20 or Line 283) it is out­put on Line 21 and Line 284. A typical implementation of this
method is to use VSYNC to interrupt a microprocessor, which
in turn will load the new data (two bytes) every field. If no new
data is required for transmission, 0s must be inserted in both
data registers, which is called nulling. It is also important to load
control codes, all of that are double bytes on Line 21 or a televi­sion will not recognize them. If there is a message like Hello
World that has an odd number of characters, it is important
to pad it out to even in order to get end-of-caption 2-byte
control code to land in the same field.

TWO 7-BIT + PARITY
ASCII CHARACTERS

(DATA)

S
T

D0–D6 D0–D6

A
R
T

P
A
R

I
T
Y

P
A
R

I

T

Y

BYTE 1BYTE 0

REV. 0

Figure 66. Closed Captioning Waveform, NTSC

–63–

ADV7314

APPENDIX 4—TEST PATTERNS

The ADV7314 can generate SD and HD test patterns.

T

2

CH2 200mV M 10.0sA CH2 1.20V

T

30.6000s

Figure 67. NTSC Color Bars

T

2

CH2 100mV M 10.0s CH2 EVEN

T

1.82600ms

Figure 70. PAL Black Bar (–21 mV, 0 mV, 3.5 mV,
7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)

T

T

2

CH2 200mV M 10.0sA CH2 1.21V

T

30.6000s

Figure 68. PAL Color Bars

T

2

CH2 100mV M 10.0s CH2 EVEN

T

1.82600ms

Figure 69. NTSC Black Bar (–21 mV, 0 mV, 3.5 mV,
7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)

2

CH2 200mV M 4.0s CH2 EVEN

Figure 71. 525p Hatch Pattern

T

2

CH2 200mV M 4.0s CH2 EVEN

Figure 72. 625p Hatch Pattern

T

T

1.82944ms

1.84208ms

REV. 0–64–

ADV7314

T

2

CH2 200mV M 4.0s CH2 EVEN

T

1.82872ms

Figure 73. 525p Field Pattern

T

T

2

CH2 100mV M 4.0s CH2 EVEN

Figure 75. 625p Field Pattern

T

T

1.82936ms

2

CH2 200mV M 4.0s CH2 EVEN

T

1.84176ms

Figure 74. 525p Black Bar (–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV)

The following register settings are used to generate an SD NTSC
CVBS output on DAC A.

Register

Subaddress Setting

00h 80h
40h 10h
42h 40h
44h 40h
4Ah 08h

*All other registers are set to default/normal settings.

For PAL CVBS output on DAC A, the same settings are used
except that Subaddress 40h is changed to 11h.

The following register settings are used to generate an SD NTSC
black bar pattern output on DAC A.

Register

Subaddress Setting

00h 80h
02h 04h
40h 10h
42h 40h
44h 40h
4Ah 08h

*All other registers are set to default/normal settings.

2

CH2 100mV M 4.0s CH2 EVEN

T

1.84176ms

Figure 76. 625p Black Bar (–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV)

For PAL black bar pattern output on DAC A, the same settings
are used except that subaddress = 40h and register setting = 11h.

The following register settings are used to generate a 525p hatch
pattern on DAC D.

Register

Subaddress Setting

00h 80h
01h 10h
10h 40h
11h 05h
16h A0h
17h 80h
18h 80h

*All other registers are set to default/normal settings.

For 625p hatch pattern on DAC D, the same register settings
are used except that subaddress = 10h and register setting = 50h.

For a 525p black bar pattern output on DAC D, the same settings
are used as for a 525p hatch pattern except that subaddress = 02h
and register setting = 24h.

For 625p black bar pattern output on DAC D, the same settings
are used as for a 625p hatch pattern except that subaddress = 02h
and register setting = 24h; and subaddress = 10h and register
setting = 50h.

REV. 0

–65–

ADV7314

APPENDIX 5—SD TIMING MODES
[Subaddress 4Ah]

Mode 0 (CCIR-656)—Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7314 is controlled by the SAV (start active video) and
EAV (end active video) time codes in the pixel data. All timing
information is transmitted using a 4-byte synchronization pat­tern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace. S_VSYNC,
S_HSYNC, and S_BLANK (if not used) pins should be tied
high during this mode. Blank output is available.

ANALOG

VIDEO

INPUT PIXELS

NTSC /PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

EAV CODE

C

FF0000X

Y

Y

r

4 CLOCK

4 CLOCK

END OF ACTIVE

VIDEO LINE

8

10801

0

Y

0

FF00FFABABA

ANCILLARY DATA

268 CLOCK

280 CLOCK

B

(HANC)

Figure 77. SD Slave Mode 0

801

0

SAV CODE

8

10FF0

0

0

XYC

Y

0

0

b

4 CLOCK

4 CLOCK

START OF ACTIVE

VIDEO LINE

C

C

Y

Y

b

r

1440 CLOCK

1440 CLOCK

C

C

Y

b

r

REV. 0–66–

Mode 0 (CCIR-656)—Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7314 generates H, V, and F signals required for the
SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. The H bit is output on
S_HSYNC, the V bit is output on S_BLANK, and the F bit is
output on S_VSYNC pin.

ADV7314

DISPLAY

522 523 524 525 1 2 3 4

H

V

F

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

H

V

F

EVEN FIELD

ODD FIELD

ODD FIELD

EVEN FIELD

VERTICAL BLANK

67

5

VERTICAL BLANK

9

8

Figure 78. SD Master Mode 0 (NTSC)

DISPLAY

10 11 20 21 22

283

284

285

DISPLAY

DISPLAY

622 623 624 625 1 2 3 4

H

V

F

DISPLAY

309 310 311 312 314 315 316 317

H

V

F

EVEN FIELD

ODD FIELD

ODD FIELD

313

EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 79. SD Master Mode 0 (PAL)

5

67

318

319 320

DISPLAY

22 23

21

DISPLAY

335 336

334

REV. 0

–67–

ADV7314

H

B

ANALOG

VIDEO

H

V

F

Figure 80. SD Master Mode 0, Data Transitions

Mode 1—Slave Option
(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode, the ADV7314 accepts horizontal SYNC and
odd/even field signals. A transition of the field input when HSYNC
is low indicates a new frame, i.e., vertical retrace. The BLANK
signal is optional. When the BLANK input is disabled, the
ADV7314 automatically blanks all normally blank lines as per
CCIR-624. HSYNC is input on HSYNC, BLANK on S_BLANK,
and FIELD on S_VSYNC.

284

DISPLAY

DISPLAY

285

DISPLAY

522 523 524 525

SYNC

LANK

FIELD

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

HSYNC

BLANK

FIELD

1234

EVEN FIELD

ODD FIELD EVEN FIELD

ODD FIELD

VERTICAL BLANK

678

5

VERTICAL BLANK

9

10 11

20 21 22

283

Figure 81. SD Slave Mode 1 (NTSC)

REV. 0–68–

Mode 1—Master Option

H

B

H

B

H

B

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7314 can generate horizontal sync and odd/
even field signals. A transition of the field input when HSYNC is
low indicates a new frame i.e., vertical retrace. The BLANK
signal is optional. When the BLANK input is disabled, the
ADV7314 automatically blanks all normally blank lines as per
CCIR-624. Pixel data is latched on the rising clock edge following
the timing signal transitions. HSYNC is output on the S_HSYNC,
BLANK on S_BLANK, and FIELD on S_VSYNC.

ADV7314

SYNC

LANK

FIELD

SYNC

LANK

FIELD

DISPLAY

622 623 624 625 1234

EVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD

ODD FIELD

EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 82. SD Slave Mode 1 (PAL)

317

5

67

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

SYNC

FIELD

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

LANK

PIXEL

REV. 0

DATA

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 83. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave

–69–

Cb Y

Cr Y

ADV7314

H

B

H

B

H

B

H

B

Mode 2—Slave Option
(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode, the ADV7314 accepts horizontal and vertical sync
signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an odd field. A VSYNC low transi­tion when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is
disabled the ADV7314 automatically blanks all normally blank
lines as per CCIR-624. HSYNC is input S_HSYNC, BLANK
on S_BLANK, and VSYNC on S_VSYNC.

SYNC

LANK

VSYNC

SYNC

LANK

VSYNC

DISPLAY

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

EVEN FIELD

ODD FIELD

VERTICAL BLANK

678

5

ODD FIELD

VERTICAL BLANK

EVEN FIELD

9

10 11

Figure 84. SD Slave Mode 2 (NTSC)

DISPLAY

VERTICAL BLANK

20 21 22

DISPLAY

283

284

DISPLAY

DISPLAY

285

622 623 624 625 1234

SYNC

LANK

VSYNC

SYNC

LANK

VSYNC

DISPLAY

309 310 311 312 313 314 315 316

EVEN FIELD

ODD FIELD

ODD FIELD

VERTICAL BLANK

EVEN FIELD

5

317

67

318 319

320

21 22 23

DISPLAY

334 335 336

Figure 85. SD Slave Mode 2 (PAL)

REV. 0–70–

H

B

H

B

Mode 2—Master Option
(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7314 can generate horizontal and vertical
sync signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low
transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7314 automatically blanks all normally blank
lines as per CCIR-624. HSYNC is output on S_HSYNC, BLANK
on S_BLANK, and VSYNC on S_VSYNC.

SYNC

VSYNC

PAL = 12  CLOCK/2

LANK

NTSC = 16  CLOCK/2

ADV7314

PIXEL
DATA

SYNC

VSYNC

LANK

PIXEL

DATA

Cb Y Cr

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 86. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave

PAL = 864  CLOCK/2

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

NTSC = 858  CLOCK/2

Cb Y Cr Y Cb

Figure 87. SD Timing Mode 2 Odd-to-Even Field Transition Master/Slave

Y

REV. 0

–71–

ADV7314

H

B

H

B

H

B

H

B

Mode 3—Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV7314 accepts or generates horizontal
sync and odd/even field signals. A transition of the field input
when HSYNC is high indicates a new frame i.e., vertical re­trace. The BLANK signal is optional. When the BLANK input
is disabled, the ADV7314 automatically blanks all normally
blank lines as per CCIR-624. HSYNC is output in master mode
and input in slave mode on S_HSYNC, BLANK on S_BLANK,
and VSYNC on S_VSYNC.

DISPLAY

VERTICAL BLANK

DISPLAY

SYNC

LANK

FIELD

SYNC

LANK

FIELD

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

678

5

VERTICAL BLANK

9

10 11

20 21 22

283

284

Figure 88. SD Timing Mode 3 (NTSC)

DISPLAY

622 623 624 625 1234

SYNC

VERTICAL BLANK

5

67

21 22 23

DISPLAY

285

LANK

FIELD

SYNC

LANK

FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELDEVEN FIELD

VERTICAL BLANK

318 319

317

ODD FIELDEVEN FIELD

320

334 335 336

DISPLAY

Figure 89. SD Timing Mode 3 (PAL)

REV. 0–72–

ADV7314

P

P

P

P

APPENDIX 6—HD TIMING

FIELD 1

1124 1125

_VSYNC

_HSYNC

FIELD 2

561 562

VERTICAL BLANKING INTERVAL

12

VERTICAL BLANKING INTERVAL

563 564

3

565

4

566

5

67

567 568

569

8

570

20

583

DISPLAY

21 22

DISPLAY

584

585

560

1123

_VSYNC

_HSYNC

Figure 90. 1080i

HSYNC

and

VSYNC

Input Timing

REV. 0

–73–

ADV7314

APPENDIX 7—VIDEO OUTPUT LEVELS
HD YPrPb Output Levels

INPUT CODE

EIA-770.2, STANDARD FOR Y

940

64

EIA-770.2, STANDARD FOR Pr/Pb

960

512

64

OUTPUT VOLTAGE

700mV

300mV

OUTPUT VOLTAGE

700mV

Figure 91. EIA 770.2 Standard Output Signals
(525p/625p)

INPUT CODE

EIA-770.1, STANDARD FOR Y

940

OUTPUT VOLTAGE

782mV

INPUT CODE

EIA-770.3, STANDARD FOR Y

940

64

EIA-770.3, STANDARD FOR Pr/Pb

960

512

64

OUTPUT VOLTAGE

700mV

300mV

OUTPUT VOLTAGE

600mV

700mV

Figure 93. EIA 770.3 Standard Output Signals
(1080i, 720p)

INPUT CODE

1023

Y–OUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

714mV

64

286mV

EIA-770.1, STANDARD FOR Pr/Pb

960

512

64

OUTPUT VOLTAGE

700mV

Figure 92. EIA 770.1 Standard Output Signals
(525p/625p)

700mV

64

300mV

INPUT CODE

1023

64

Pr/Pb–OUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

700mV

300mV

Figure 94. Output Levels for Full Input Selection

REV. 0–74–

RGB Output Levels

ADV7314

700mV

300mV

700mV

300mV

700mV

300mV

550mV

550mV

550mV

Figure 95. HD RGB Output Levels

700mV 550mV

700mV

300mV

700mV

300mV

700mV

300mV

550mV

550mV

550mV

Figure 97. SD RGB Output Levels—RGB Sync Disabled

700mV 550mV

300mV

0mV

700mV

300mV

0mV

700mV

300mV

0mV

550mV

550mV

Figure 96. HD RGB Output Levels—RGB Sync Enabled

300mV

0mV

700mV

300mV

0mV

700mV

300mV

0mV

550mV

550mV

Figure 98. SD RGB Output Levels—RGB Sync Enabled

REV. 0

–75–

ADV7314

YPrPb Output Levels

WHITE

160mV

YELLOW

CYAN

220mV

GREEN

280mV

MAGENTA

RED

332mV

110mV

BLUE

BLACK

1000mV

WHITE

1260mV

YELLOW

CYAN

GREEN

200mV

MAGENTA

RED

2150mV

900mV

BLUE

BLACK

60mV

Figure 99. U Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

220mV

160mV

60mV

Figure 100. U Levels—PAL

WHITE

YELLOW

CYAN

GREEN

MAGENTA

280mV

200mV

RED

332mV

110mV

MAGENTA

RED

2150mV

BLUE

BLUE

BLACK

BLACK

140mV

Figure 102. U Levels—PAL

WHITE

YELLOW

CYAN

GREEN

MAGENTA

300mV

Figure 103. Y Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

RED

BLUE

BLUE

BLACK

BLACK

1260mV

1000mV

140mV

Figure 101. U Levels—NTSC

300mV

900mV

Figure 104. Y Levels—PAL

REV. 0–76–

ADV7314

VOLTS

0.5

APL = 44.5%
525 LINE NTSC
SLOW CLAMP TO 0.00V AT 6.72s

VOLTS

IRE:FLT

100

50

0

0

0.4

0

–50

10 20

IRE:FLT

50

F1
L76

30 40 50 60

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = A

FRAMES SELECTED 1 2

Figure 105. NTSC Color Bars 75%

0.2

0

–0.2

–0.4

0

NOISE REDUCTION: 15.05dB
APL NEEDS SYNC-SOURCE!
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

0

–50

F1
L76

10 20

30 40 50 60

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = B

Figure 106. NTSC Chroma

FRAMES SELECTED 1 2

REV. 0

–77–

ADV7314

VOLTS

–0.2

NOISE REDUCTION: 15.05dB
APL = 44.3%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

VOLTS

0.6

0.4

0.2

0

IRE:FLT

50

0

0

F2
L238

10 20

30 40 50 60

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = SOURCE

Figure 107. NTSC Luma

FRAMES SELECTED 1 2

0.6

0.4

0.2

0

–0.2

L608

10020

NOISE REDUCTION: 0.00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

MICROSECONDS

30 40 50 60

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1 2 3 4

Figure 108. PAL Color Bars 75%

REV. 0–78–

VOLTS

0.5

0

–0.5

ADV7314

L575

10 20

APL NEEDS SYNC SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

VOLTS

0.5

0

L575

10020

APL NEEDS SYNC SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

30 40 50 60

MICROSECONDS NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

Figure 109. PAL Chroma

30 40 50 60 70

MICROSECONDS NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

Figure 110. PAL Luma

FRAMES SELECTED 1

FRAMES SELECTED 1

REV. 0

–79–

ADV7314

APPENDIX 8—VIDEO STANDARDS

SMPTE 274M

ANALOG WAVEFORM

*1

4T

EAV CODE

F

F

INPUT PIXELS

SAMPLE NUMBER

FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FIELD RATE OF 30Hz: 40 SAMPLES
FOR A FIELD RATE OF 25Hz: 480 SAMPLES

000

V

F

0

H*

4 CLOCK 4 CLOCK

2112 2116 2156 2199

0

DATUM

H

DIGITAL HORIZONTAL BLANKING

272T

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

0

44 188 192 2111

4T 1920T

SAV CODE

F

CbC

000

F

V

0

F

H*

DIGITAL

ACTIVE LINE

Y

r

C

Y

r

SMPTE 293M

ANALOG WAVEFORM

INPUT PIXELS

SAMPLE NUMBER

Figure 111. EAV/SAV Input Data Timing Diagram—SMPTE 274M

EAV CODE

F

000

F

V

0

F

H*

4 CLOCK 4 CLOCK

719 723 736 799 853 0

FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8

0HDATUM

DIGITAL HORIZONTAL BLANKING

ANCILLARY DATA

(OPTIONAL)

SAV CODE

000

F
F

Figure 112. EAV/SAV Input Data Timing Diagram—SMPTE 293M

DIGITAL

ACTIVE LINE

F

CbC

V

0

H*

Y

r

857 719

C

Y

Y

r

REV. 0–80–

ADV7314

ACTIVE

VIDEO

522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 44

VERTICAL BLANK

Figure 113. SMPTE 293M (525p)

ACTIVE

VIDEO

622 623 624 625 1 2 5 6 7 8 9 12 1310 11 43 44 454

VERTICAL BLANK

Figure 114. ITU-R BT.1358 (625p)

VERTICAL BLANKING INTERVAL

747 748 749 750 1 2 5 6 7 8 26 2725744 7454

3

ACTIVE

VIDEO

DISPLAY

ACTIVE

VIDEO

FIELD 1

FIELD 2

Figure 115. SMPTE 296M (720p)

VERTICAL BLANKING INTERVAL

1124 1125 1 2 5 6 7 8

VERTICAL BLANKING INTERVAL

561 562 563 564 567 568 569 570

43

566565

Figure 116. SMPTE 274M (1080i)

DISPLAY

21

20 22 560

DISPLAY

584

583 585 1123

REV. 0

–81–

ADV7314

OUTLINE DIMENSIONS

64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64)

Dimensions shown in millimeters

1.45

1.40

1.35

0.15

0.05

10

6
2

SEATING
PLANE

ROTATED 90 CCW

VIEW A

0.10 MAX
COPLANARITY

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7

3.5
0

COMPLIANT TO JEDEC STANDARDS MS-026BCD

1.60
MAX

1

VIEW A

16

17

PIN 1

0.50

BSC

12.00 BSC
SQ

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

4964

48

10.00

BSC SQ

33

32

REV. 0–82–

–83–

C03749–0–8/03(0)

–84–