Datasheet ADV7310 Datasheet (Analog Devices)

Multiformat 216 MHz

Video Encoder with Six NSV

™

ADV7310/ADV7311

12-Bit DACs

FEATURES
High Definition Input Formats

8-/10-, 16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:

SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3ⴛ10-Bit 4:4:4 Input Format

HDTV RGB Supported:

RGB, RGBHV
Other High Definition Formats Using Async

Timing Mode

High Definition Output Formats

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)*
CGMS-A (525p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1*

CGMS/WSS
Closed Captioning

GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference

Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.

*ADV7310 Only

Six 12-Bit NSV Precision Video DACs
2-Wire Serial I

2C®

Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product

APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video Systems

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

Y9–Y0
C9–C0
S9–S0

HSYNC
VSYNC
BLANK

CLKIN_A
CLKIN_B

D
E
M
U
X

TIMING

GENERATOR

PLL

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

ADV7310/
ADV7311

12-BIT

DAC

12-BIT

O
V

DAC
E
R

12-BIT

S

DAC
A

M

12-BIT

P
L

DAC

I

N

12-BIT

G

DAC

12-BIT

DAC

I2C

INTERFACE

GENERAL DESCRIPTION

The ADV®7310/ADV7311 is a high speed, digital-to-analog
encoder on a single monolithic chip. It includes six high speed
NSV video D/A converters with TTL compatible inputs.

The ADV7310/ADV7311 has separate 8-/10-/16-/20-bit input
ports that accept data in high definition and/or standard definition
video format. For all standards, external horizontal, vertical,
and blanking signals or EAV/SAV timing codes control the
insertion of appropriate synchronization signals into the digi­tal data stream and therefore the output signal.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADV7310/ADV7311

P

P
P

S

S
S

DETAILED FEATURES
High Definition Programmable Features (720p 1080i)

2 Oversampling (148.5 MHz)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)

High Definition Programmable Features (525p/625p)

8 Oversampling (216 MHz Output)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)*
CGMS-A (525p)

Standard Definition Programmable Features

16 Oversampling (216 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)

Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable

Gain/Attenuation
PrPb SSAF™
Separate Pedestal Control on Component and
Composite/S-Video Output
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1*
CGMS/WSS
Closed Captioning

Standards Directly Supported

Frame Clk

Resolution Rate (Hz) Input (MHz) Standard

720  480 29.97 27 ITU-R BT.656
720  576 25 27 ITU-R BT.656
720  483 59.94 27 SMPTE 293M
720  480 59.94 27 BTA T-1004
720  576 50 27 ITU-R BT.1362
1280  720 60 74.25 SMPTE 296M
1920  1080 30 74.25 SMPTE 274M
1920  1080 25 74.25 SMPTE 274M*

Other standards are supported in Async Timing Mode.
*SMPTE 274M-1998: System no. 6

DETAILED FUNCTIONAL BLOCK DIAGRAM

HD PIXEL

INPUT

CLKIN_B

_HSYNC
_VSYNC
_BLANK

_HSYNC
_VSYNC
_BLANK

CLKIN_A

SD PIXEL

INPUT

TERMINOLOGY

SD Standard Definition Video, conforming to

ITU-R BT.601/ITU-R BT.656.

HD High Definition Video, i.e., Progressive Scan or HDTV.

DE­INTER­LEAVE

DE­INTER­LEAVE

Y

TEST

CR

PAT T ERN

CB

CB

TEST

CR

PATTERN

Y

TIMING

GENERATOR

TIMING

GENERATOR

SHARPNESS

AND

ADAPTIVE

FILTER

CONT

ROL

DNR

GAMMA

Y COLOR
CR COLOR
CB COLOR

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

INSERTION

4:2:2

TO

4:4:4

SYNC

U

UV SSAF

V

CHROMA

FILTERS

LUMA

AND

2 OVER-

SAMPLING

RGB

MATRIX

F

SC

MODULATION

CGMS

WSS

PS 8

HDTV 2

SD 16

DAC

DAC

DAC

DAC

DAC

DAC

HDTV High Definition Television Video, conforming to

SMPTE 274M or SMPTE 296M.

YCrCb SD, PS, or HD Component Digital Video.

YPrPb SD, PS, or HD Component Analog Video.

PS Progressive Scan Video, conforming to SMPTE 293M,

ITU-R BT.1358, BTAT-1004EDTV2, or BTA1362.

*ADV7310 Only

REV. A–2–

CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14

THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 14

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 16

REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 17

INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 30

Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 30

Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 30

Simultaneous Standard Definition and Progressive Scan

or HDTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 31

OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 33

TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SD Real-Time Control, Subcarrier Reset,

and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 38

Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . . 38

Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 40

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 41

COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 45

HD Y Level, HD Cr Level, HD Cb Level . . . . . . . . . . . . 45

HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 45

SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 45

SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

ADV7310/ADV7311

PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 47

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

HD SHARPNESS FILTER CONTROL AND ADAPTIVE

FILTER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . . 49

HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . 49

HD Sharpness Filter and Adaptive Filter Application

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . 52

Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . 53

DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . 54

SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . . 54

BOARD DESIGN AND LAYOUT CONSIDERATIONS . 55

DAC Termination and Layout Considerations . . . . . . . . 55

Video Output Buffer and Optional Output Filter . . . . . . . 55

PCB Board Layout Considerations . . . . . . . . . . . . . . . . . 57

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 57

Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 57

APPENDIX 1—COPY GENERATION MANAGEMENT

SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PS CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 59

SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 59

HD/PS CGMS [Address 12h, Bit 6] . . . . . . . . . . . . . . . . 59

Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 59

CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . . 61

APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . . 62

APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . . 63

APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . . 67

Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 69

Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 71

Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 72

APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . . 73

APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . . 74

HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 74

RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

YUV Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . . 80

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 82

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

REV. A

–3–

ADV7310/ADV7311–SPECIFICATIONS

= 2.375–3.6 V, V

V

DD_IO

= 1.235 V, R

REF

= 3040 , R

SET

= 300 . All specifications T

LOAD

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V;

MIN

to T

(0C to 70C), unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

1

Resolution 12 Bits
Integral Nonlinearity 1.5 LSB
Differential Nonlinearity

2

, +ve 0.25 LSB

Differential Nonlinearity2, –ve 1.5 LSB

DIGITAL OUTPUTS

Output Low Voltage, V
Output High Voltage, V

OL

OH

2.4[2.0]

3

Three-State Leakage Current ±1.0 µAV

0.4 [0.4]3VI

VI

= 3.2 mA

SINK

SOURCE

= 0.4 V, 2.4 V

IN

= 400 µA

Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V

IH

IL

Input Leakage Current 3 µAV
Input Capacitance, C

IN

2V

0.8 V

= 2.4 V

IN

2pF

ANALOG OUTPUTS

Full-Scale Output Current 4.1 4.33 4.6 mA
Output Current Range 4.1 4.33 4.6 mA

DAC-to-DAC Matching 1.0 %

Output Compliance Range, V
Output Capacitance, C

OC

OUT

0 1.0 1.4 V

7pF

VOLTAGE REFERENCE

Internal Reference Range, V
External Reference Range, V
V

Current

REF

4

REF

REF

1.15 1.235 1.3 V

1.15 1.235 1.3 V

±10 µA

POWER REQUIREMENTS

Normal Power Mode

5

I

DD

170 mA SD Only [16]
110 mA PS Only [8]

I

DD_IO

I

AA

6, 7

95 mA HDTV Only [2]
172 190

1.0 mA
39 45 mA

8

mA SD[16, 10-bit] + PS[8, 20-bit]

Sleep Mode

I

DD

I

AA

I

DD_IO

200 µA
10 µA
250 µA

POWER SUPPLY REJECTION RATIO 0.01 % / %

NOTES

1

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

2

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.

3

Value in brackets for V

4

External current required to overdrive internal V

5

IDD, the circuit current, is the continuous current required to drive the digital core.

6

IAA is the total current required to supply all DACs including the V

7

All DACs on.

8

Guaranteed maximum by characterization.

Specifications subject to change without notice.

= 2.375 V–2.75 V.

DD_IO

REF

.

circuitry and the PLL circuitry.

REF

REV. A–4–

ADV7310/ADV7311

DYNAMIC SPECIFICATIONS

3040 , R

= 300 . All specifications T

LOAD

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; V

to T

MIN

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.6 V, V

DD_IO

= 1.235 V, R

REF

SET

Parameter Min Typ Max Unit Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz
Chroma Bandwidth 5.8 MHz
SNR 65.6 dB Luma ramp unweighted

72 dB Flat field full bandwidth

HDTV MODE

Luma Bandwidth 30 MHz
Chroma Bandwidth 13.75 MHz

STANDARD DEFINITION MODE

Hue Accuracy 0.2

o

Color Saturation Accuracy 0.20 %
Chroma Nonlinear Gain 0.84 ±%Referenced to 40 IRE
Chroma Nonlinear Phase –0.2 ±

o

Chroma/Luma Intermodulation 0 ±%
Chroma/Luma Gain Inequality 96.7 ±%
Chroma/Luma Delay Inequality –1.0 ns
Luminance Nonlinearity 0.2 ±%
Chroma AM Noise 84 dB
Chroma PM Noise 75.3 dB
Differential Gain 0.25 % NTSC
Differential Phase 0.2

o

NTSC

SNR 63.5 dB Luma ramp

77.7 dB Flat field full bandwidth

=

Specifications subject to change without notice.

REV. A

–5–

ADV7310/ADV7311

TIMING SPECIFICATIONS

R

= 300 . All specifications T

LOAD

MIN

to T

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; V

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.6 V, V

DD_IO

= 1.235 V, R

REF

Parameter Min Typ Max Unit Test Conditions

MPU PORT

1

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs First clock generated after this period

0.6 µs relevant for repeated start condition
100 ns

300 ns
300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

2

7ns

Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT

f

CLK

f

CLK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
SD Output Access Time, t
SD Output Hold Time, t
HD Output Access Time, t
HD Output Hold Time, t

PIPELINE DELAY

9

10

1

11

1

12

13

14

13

14

4

3

27 MHz Progressive scan mode

81 MHz HDTV mode/async mode
40 % of one clk cycle
40 % of one clk cycle

2.0 ns

2.0 ns

15 ns

5.0 ns

14 ns

5.0 ns

63 clk cycles SD [2, 16]

76 clk cycles SD component mode [16]

35 clk cycles PS [1]

41 clk cycles PS [8]

36 clk cycles HD[2, 1]

NOTES

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

Data: C[9:0]; Y[9:0], S[9:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.

4

SD, PS = 27 MHz, HD = 74.25 MHz.

Specifications subject to change without notice.

= 3040 ,

SET

REV. A–6–

CLKIN_A

ADV7310/ADV7311

t

12

t

13

t

14

CONTROL

INPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

C9–C0

CONTROL

OUTPUTS

t

t

9

10

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

t11

Figure 1. HD Only 4:2:2 Input Mode [Input Mode 010]; PS Only 4:2:2 Input Mode [Input Mode 001]

CLKIN_A

t

12

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

t

t

9

10

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cb1 Cb2 Cb3 Cb4 Cb5

t

11

Cr 0 Cr1 Cr 2 Cr3 Cr 4 Cr5

t

13

t

14

CONTROL

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

C9–C0

S9–S0

OUTPUTS

Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001]

REV. A

–7–

ADV7310/ADV7311

CONTROL

INPUTS

CLKIN_A

P_HSYNC,
P_VSYNC,
P_BLANK

t

t

9

10

t

12

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

CONTROL

INPUTS

Y9–Y0

C9–C0

S9–S0

G0 G1 G2 G3 G4 G5

B0 B1 B2 B3 B4 B5

t

11

R0 R1 R2 R3 R4 R5

Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010]

CLKIN_B*

t

t

10

t

12

t

11

t

P_HSYNC,

P_VSYNC,

P_BLANK

Y9–Y

CONTROL

OUTPUTS

9

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

0

t

12

t

11

t

13

t

14

13

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

*CLKIN_B MUST BE USED IN THIS PS MODE.

Figure 4. PS 4:2:2 10-Bit Interleaved at 27 MHz

t

14

HSYNC/VSYNC

Input Mode [Input Mode 100]

REV. A–8–

CONTROL

INPUTS

CLKIN_A

P_VSYNC,
P_HSYN
P_BLANK

ADV7310/ADV7311

t10

t9

C,

Y9–Y0

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Figure 5. PS 4:2:2 1  10-Bit Interleaved at 54 MHz

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

t11

CLKIN_B*

Y9–Y

CONTROL

OUTPUTS

t12

t

t

9

3FF 00 00 XY Cb0 Y0 Cr0 Y1

0

t

12

t

11

*CLKIN_B USED IN THIS PS ONLY MODE.

10

t13

t14

HSYNC/VSYNC

t

12

t

11

t

13

t

14

Input Mode [Input Mode 111]

Figure 6. PS Only 4:2:2 1  10-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]

REV. A

CLKIN_A

t10

t9

CONTROL

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Y9–Y0

OUTPUTS

3FF 00 00 XY Cb0 Y0 Cr0 Y1

t11

t12

NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0  01 BIT-1

t13

t14

Figure 7. PS Only 4:2:2 1  10-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]

–9–

ADV7310/ADV7311

CLKIN_B

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

t9

t10

t12

CONTROL

INPUTS

Y9–Y0

C9–C0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

Y0 Y1

Cb0 Cr0 Cb2

t11

t9

t10

Cb0 Y0 Cr0

Y2

Y3 Y4 Y5

Cr2

t12

Y1

t11

Cb4 Cr4

Cb1 Y2

Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101: SD Oversampled]
[Input Mode 110: HD Oversampled]

CLKIN_B

t12

Y2

Y3 Y4 Y5

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

t10

t9

Y0 Y1

HD INPUT

SD INPUT

PS INPUT

CONTROL

INPUTS

C9–C0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

Cb0 Cr0 Cb2

t11

t9

t10

Cb0 Y0 Cr0

t11

Cr2

Y1

Cb4 Cr4

t12

Cb1 Y2

Figure 9. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode [Input Mode 011]

SD INPUT

REV. A–10–

CONTROL

INPUTS

CONTROL

INPUTS

CONTROL

INPUTS

ADV7310/ADV7311

CLKIN_B

t

t

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

9

Cb0 Y0 Cr0 Y1

t

12

t

11

t

9

Cb0 Y0 Cr0

Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100]

CLKIN_A

t

t

9

10

S_HSYNC,
S_VSYNC,
S_BLANK

10

PS INPUT

Crxxx Yxxx

t

12

t

11

t

t

10

t

12

12

Y1

t

11

Cb1 Y2

SD INPUT

IN SLAVE MODE

S9–S0/Y9–Y0*

CONTROL
OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000]

t

11

t

13

IN MASTER/SLAVE MODE

t

14

REV. A

–11–

ADV7310/ADV7311

P

CLKIN_A

CONTROL

INPUTS

S_HSYNC,
S_VSYNC,
S_BLANK

t

t

9

10

t

12

IN SLAVE MODE

S9–S0/Y9–Y0*

C9–C0

CONTROL

OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000]

_HSYNC

P_VSYNC

P_BLANK

Y9–Y0

C9–C0

Y0 Y2 Y3

Cb0 Cr0 Cb2 Cr2

t

11

a

Y1

t

13

t

14

IN MASTER/SLAVE MODE

Y0 Y1

Cb0 Cr0 Cr1 Cb1

Y2 Y3

b

a = 16 CLKCYCLES FOR 525p
a = 12 CLKCYCLES FOR 626p
a = 44 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
a = 70 CLKCYCLES FOR 720p
AS RECOMMENDED BY STANDARD

b(MIN) = 122 CLKCYCLES FOR 525p
b(MIN) = 132 CLKCYCLES FOR 625p
b(MIN) = 236 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
b(MIN) = 300 CLKCYCLES FOR 720p

Figure 13. HD 4:2:2 Input Timing Diagram

REV. A–12–

P

_HSYNC

P_VSYNC

P_BLANK

ADV7310/ADV7311

a

Y9–Y0

a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p

Figure 14. PS 4:2:2 1  10-Bit Interleaved Input Timing Diagram

S_HSYNC

S_VSYNC

PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES

S_BLANK

S9–S0/Y9–Y0*

*SELECTED BY ADDRESS 0x01 BIT 7

b

Figure 15. SD Timing Input for Timing Mode 1

Cb Y

Cb Y

PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES

Cr Y

Cr Y

t

3

SDA

t

6

SCLK

t

2

Figure 16. MPU Port Timing Diagram

REV. A

t

5

t

1

t

7

–13–

t

3

t

4

t

8

ADV7310/ADV7311

K

ABSOLUTE MAXIMUM RATINGS*

VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

V

DD

V

to IO_GND . . . . . . . . . . . . –0.3 V to V

DD_IO

Ambient Operating Temperature (T
Storage Temperature (T

) . . . . . . . . . . . . . . .–65°C to +150°C

S

A

) . . . . . . . . . 0°C to 70°C

DD_IO

to +0.3 V

Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJC = 11°C/W
θJA = 47°C/W

PIN CONFIGURATION

The ADV7310/ADV7311 is a Pb-free environmentally friendly
product. It is manufactured using the most up-to-date materials
and processes. The coating on the leads of each device is 100%
pure Sn electroplate. The device is suitable for Pb-free applica­tions, and is able to withstand surface-mount soldering at up to
255°C (±5°C).

In addition it is backward compatible with conventional SnPb
soldering processes. This means that the electroplated Sn coating
can be soldered with Sn/Pb solder pastes at conventional reflow
temperatures of 220°C to 235°C.

ORDERING GUIDE*

Package Package

Model Description Option

ADV7310KST Plastic Quad Flat Package ST-64
ADV7311KST Plastic Quad Flat Package ST-64
EVAL-ADV7310EB Evaluation Board
EVAL-ADV7311EB Evaluation Board

*Analog output short circuit to any power supply or common can be of an

indefinite duration.

DD

V

V

DD_IO

V

DGND

P_VSYNC

P_BLANK

P_HSYNC

S4S3S2S1S0

C5C6C7C8C9

GND_IO

CLKIN_BS9S8S7S6S5DGND

1

PIN 1

2

Y0

IDENTIFIER

3

Y1

4

Y2

5

Y3

6

Y4

7

Y5

8

Y6

9

Y7

10

DD

11

12

Y8

13

Y9

14

C0

15

C1

16

C2

C3

ADV7310/ADV7311

TOP VIEW

(Not to Scale)

C

2

C4

I

SDA

ALSB

SCLK

S_HSYNCS_VSYNC

49505152535455565758596061626364

48

S_BLAN

47

R

46

V

45

COMP1

44

DAC A

43

DAC B

42

DAC C

41

V

40

AGND

39

DAC D

38

DAC E

37

DAC F

36

COMP2

35

R

34

EXT_LF

33

RESET

32313029282726252423222120191817

CLKIN_A

RTC_SCR_TR

SET1

REF

AA

SET2

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7310/ADV7311 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A–14–

ADV7310/ADV7311

PIN FUNCTION DESCRIPTIONS

Mnemonic Input/Output Function

DGND G Digital Ground.

AGND G Analog Ground.

CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).

CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz

(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.

COMP1,2 O Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin to V

DAC A O CVBS/Green/Y/Y Analog Output.

DAC B O Chroma/Blue/U/Pb Analog Output.

DAC C O Luma/Red/V/Pr Analog Output.

DAC D O In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Y/Green [HD] Analog Output.

DAC E O In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pr/Red Analog Output.

DAC F O In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pb/Blue [HD] Analog Output.

P_HSYNC I Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_VSYNC IVideo Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_BLANK IVideo Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
S_BLANK I/O Video Blanking Control Signal for SD Only.
S_HSYNC I/O Video Horizontal Sync Control Signal for SD Only.
S_VSYNC I/O Video Vertical Sync Control Signal for SD Only.

Y9–Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan

data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2.

C9–C0 I Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data.

The LSB is set up on pin C0. For 8-bit data input, LSB is set up on C2.

S9–S0 I SD or Progressive Scan/HDTV Input Port for Cr[Red/V] data in 4:4:4 input mode. LSB is set up

on pin S0. For 8-bit data input, LSB is set up on S2.

RESET I This input resets the on-chip timing generator and sets the ADV7310/ADV7311 into default register

setting. RESET is an active low signal.

R

SET1,2

IA 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes

of the DAC outputs.

SCLK I I

SDA I/O I

ALSB I TTL Address Input. This signal sets up the LSB of the I

V

DD_IO

V

DD

V

AA

V

REF

PPower Supply for Digital Inputs and Outputs.

PDigital Power Supply.

PAnalog Power Supply.

I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

2

C Port Serial Interface Clock Input.

2

C Port Serial Data Input/Output.

2

C filter is activated, which reduces noise on the I2C interface.

the I

2

C address. When this pin is tied low,

EXT_LF I External Loop Filter for the Internal PLL.

RTC_SCR_TR I Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.

2

I

CI This input pin must be tied high (V

) for the ADV7310/ADV7311 to interface over the I2C port.

DD_IO

GND_IO Digital Input/Output Ground.

AA

.

REV. A

–15–

ADV7310/ADV7311

MPU PORT DESCRIPTION

The ADV7310/ADV7311 support a 2-wire serial (I2C compat­ible) microprocessor bus driving multiple peripherals. Two inputs,
serial data (SDA) and serial clock (SCL), carry information
between any device connected to the bus and the ADV7310/
ADV7311. Each slave device is recognized by a unique address.
The ADV7310/ADV7311 have four possible slave addresses for
both read and write operations. These are unique addresses for
each device and are illustrated in Figure 17. The LSB sets
either a read or write operation. Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation. A1 is
set by setting the ALSB pin of the ADV7310/ADV7311 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater
input bandwidth on the I
transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I

2

C lines, which allows high speed data

2

C lines, which means that pulses of
less than 50 ns will not pass into the I2C internal controller.
This mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 17. ADV7310 Slave Address = D4h

0 1 0 1 0 1 A1 X

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 18. ADV7311 Slave Address = 54h

To control the various devices on the bus, the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transi­tion on SDA while SCL remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted address.
The R/W bit determines the direction of the data.

A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.

The ADV7310/ADV7311 acts as a standard slave device on
the bus. The data on the SDA pin is 8 bits long, supporting the
7-bit addresses plus the R/W bit. It interprets the first byte as
the device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.

Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then they cause an
immediate jump to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7310/ADV7311 will not issue an acknowledge and will return
to the idle condition. If in auto-increment mode the user exceeds
the highest subaddress, the following action will be taken:

1. In read mode, the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read.
A no-acknowledge condition is when the SDA line is not
pulled low on the ninth pulse.

2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7310/ADV7311, and the part will return to the
idle condition.

Before writing to the subcarrier frequency registers, it is a require­ment that the ADV7310/ADV7311 has been reset at least once
after power-up.

The four subcarrier frequency registers must be updated, starting
with subcarrier frequency register 0 through subcarrier frequency
register 3. The subcarrier frequency will not update until the last
subcarrier frequency register byte has been received by the
ADV7310/ADV7311.

Figure 19 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 20 shows
bus write and read sequences.

SDATA

SCLOCK

S

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

9

1–7 8 9

1–7

89

P

Figure 19. Bus Data Transfer

REV. A–16–

WRITE

SEQUENCE

READ

SEQUENCE

ADV7310/ADV7311

S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P

LSB = 0

S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT
P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER

Figure 20. Read and Write Sequence

LSB = 1

A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the
ADV7310/ADV7311 except the subaddress registers, which are
write only registers. The subaddress register determines which
register the next read or write operation accesses. All communi­cations with the part through the bus start with an access to the
subaddress register. A read/write operation is then performed
from/to the target address, which increments to the next address
until a stop command is performed on the bus.

Register Programming

The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless other­wise stated.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write only register. After
the part has been accessed over the bus and a read/write opera­tion is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.

REV. A

–17–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

Power Mode

00h

01h

Register

Mode Select
Register

Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal
PLL cct are disabled. I
registers can be read from
and written to in Sleep
Mode.

PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the over-sampling to be
switched off.

DAC F: Power On/Off

DAC E: Power On/Off

DAC D: Power On/Off

DAC C: Power On/Off

DAC B: Power On/Off

DAC A: Power On/Off

BTA T-1004 or BT.1362
Compatibility

Clock Edge Only for PS interleaved input at

Reserved 0

Clock Align

Input Mode

Y/S Bus Swap 0 10-bit data on S bus

2

C

0 DAC F off

1 DAC F on

0 DAC E off

1 DAC E on

0 DAC D off

1 DAC D on

0 DAC D off

1 DAC C on

0 DAC B off

1 DAC B on

0 DAC A off

1 DAC A on

0

1Must be set if the phase

00 0SD input only 38h

00 1 PS input only

01 0 HDTV input only

01 1SD and PS [20-bit]

10 0SD and PS [10-bit]

10 1SD and HDTV [SD

11 0SD and HDTV [HDTV

11 1 PS only [at 54 MHz]

1 10-bit data on Y bus

0 Sleep Mode off FCh

1 Sleep Mode on

0 PLL on

1 PLL off

0Disabled

1 Enabled

0 Cb clocked on rising edge

1Y clocked on rising edge

delay between the two input
clocks is <9.25 ns or
>27.75 ns.

oversampled]

oversampled]

Register Reset Values
(Shaded)

Only for PS dual edge clk mode

27 MHz

Only if two input clocks are used

SD Mode 10-bit/20-bit Modes

REV. A–18–

ADV7310/ADV7311

1

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

02h Mode Register 0

03h RGB Matrix 0 xxLSB for GY 03h
04h

RGB Matrix 1 x x LSB for RV F0h

05h RGB Matrix 2 x x x x x x x x Bit 9–2 for GY 4Eh
06h RGB Matrix 3 x x x x x x x x Bit 9–2 for GU 0Eh

07h RGB Matrix 4 x x x x x x x x Bit 9–2 for GV 24h
08h RGB Matrix 5 x x x x x x x x Bit 9–2 for BU 92h

09h RGB Matrix 6 x x x x x x x x Bit 9–2 for RV 7Ch
0Ah DAC A, B, C

Output Level

0Bh DAC D, E, F

Output Level

0Ch Reserved 00h

0Dh Reserved 00h
0Eh Reserved 00h

0Fh Reserved 00h

NOTES

1

For more detail, refer to Appendix 7.

2

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

Reserved 00Zero must be written to

Test Pattern Black Bar

RGB Matrix

Sync on RGB

RGB/YUV Output

SD Sync

HD Sync 0 No Sync output

Positive Gain to DAC Output

2

Voltage

Negative Gain to DAC Output
Voltage

Positive Gain to DAC Output
Voltage

Negative Gain to DAC Output
Voltage

0No Sync output

1Output SD Syncs on

1Output HD Syncs on

xx LSB for GU

000000000% 00h

0000 0001+0.018%

0000 00100.036%

0011 1111+7.382%
0100 0000+7.5%

1100 0000–7.5%

1100 0001–7.382%

1000 0010–7.364%

1111 1111–0.018%
000000000% 00h

0000 0001+0.018%

0000 00100.036%

0011 1111+7.382%
0100 0000+7.5%

1100 0000–7.5%

1100 0001–7.382%

1000 0010–7.364%

1111 1111–0.018%

0No Sync

1 Sync on all RGB outputs
0RGB component outputs

1YUV component outputs

xx LSB for GV

0Disabled
1 Enabled 0x11h, Bit 2

0Disable Programmable

1 Enable Programmable RGB

xx LSB for BU

these bits

RGB matrix

matrix

HSYNC output, VSYNC
output, BLANK output

HSYNC output, VSYNC
output, BLANK output

………

… …….

………

… …….

Reset
Values

20h

must also be
enabled

REV. A

–19–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

HD Mode

10h

Register 1

HD Mode

11h HD Pixel Data Valid 0 Pixel data valid off 00h

Register 2

12h HD Mode

Register 3

HD Output Standard 0 0 EIA770.2 output 00h

HD Input Control Signals 0 0

01 EAV/SAV codes
10 Async Timing Mode

HD 625p 0 525p

HD 720p 0 1080i

HD BLANK Polarity 0

HD Macrovision for
525p/625p

HD Test Pattern Enable 0 HD test pattern off

HD Test Pattern Hatch/Field

HD VBI Open 0 Disabled

HD Undershoot Limiter 0 0 Disabled

HD Sharpness Filter 0 Disabled

HD Y Delay with Respect to
Falling Edge of HSYNC

HD Color Delay with Respect
to Falling Edge of HSYNC

HD CGMS 0 Disabled

HD CGMS CRC

0 Macrovision off

1 Macrovision on

1 Enabled

0 Disabled
1 Enabled

1 720p

1 BLANK active low

01 –11 IRE
10 –6 IRE

11 –1.5 IRE

0000 clk cycles
0011 clk cycle

0102 clk cycles
0113 clk cycles

1004 clk cycles

1 Enabled

11 Reserved

1 625p

0 Hatch

1 Field/frame

1 Enabled

01 EIA770.1 output

10 Output levels for full

11 Reserved

0 Reserved

1 HD test pattern on

0000 clk cycles

0011 clk cycles
0102 clk cycles

0113 clk cycles
1004 clk cycles

input range

HSYNC, VSYNC,
BLANK

BLANK active high

1 Pixel data valid on

Reset
Values

REV. A–20–

ADV7310/ADV7311

g

g

VSYNC

SR7–
SR0 Re

13h HD Cr/Cb Sequence 0 Cb after falling edge of

14h HD Mode

ister Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Settin

HD Mode
Register 4

Register 5

Reserved 00 must be written to this

HD Input Format 0 8-bit input

Sinc Filter on DAC D, E, F

Reserved 0 0 must be written to this

HD Chroma SSAF 0 Disabled

HD Chroma Input 0 4:4:4

HD Double Buffering 0 Disabled

HD Timing Reset xA low-high-low transition

1080i Frame Rate

Reserved 0 0 0 0 0 must be written to these

HD

Lines/Frame

/Field Input 0 0 = Field Input

1

1 Enabled

0 Update field/line counter

1 Enabled

14:2:2

1

1 10-bit input
0Disabled

1 Enabled

00 30 Hz/2200 total

01 25 Hz/2640 total

HSYNC

1Cr after falling edge of

HSYNC

bit

bit

resets the internal HD
timing counters

samples/lines

samples/lines

bits

1 = VSYNC Input

Reset
Values

00h

1Field/line counter free

HD Mode

15h Reserved 00 must be written to this

Register 6

NOTES

1

When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are
free running and wrap around when external sync signals indicate so.

2

Adaptive Filter mode is not available in PS only @ 54 MHz input mode.

HD RGB Input

HD Sync on PrPb

HD Color DAC Swap

HD Gamma Curve A/B

HD Gamma Curve Enable

HD Adaptive Filter Mode

HD Adaptive Filter Enable

0Disabled

1 Enabled
0Disabled

1 Enabled

0 DAC E = Pb;

1 DAC E = Pr;

0 Gamma Curve A
1 Gamma Curve B

0Disabled

2

2

0Disabled
1 Enabled

1 Enabled

0 Mode A
1 Mode B

running

bit

DAC F = Pr

DAC F = Pb

00h

REV. A

–21–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

16h HD Y Level* xxxxxxxxY level value A0h
17h HD Cr Level* xxxxxxxxCr level value 80h

18h HD Cb Level* xxxxxxxxCb level value 80h
19h Reserved 00h

1Ah Reserved 00h
1Bh Reserved 00h

1Ch Reserved 00h
1Dh Reserved 00h

1Eh Reserved 00h
1Fh Reserved 00h

20h HD Sharpness Filter HD Sharpness Filter Gain Value A 0 0 0 0 Gain A = 0 00h

Gain 0001Gain A = +1

HD Sharpness Filter Gain Value B 0 0 0 0 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

21h HD CGMS Data 0 HD CGMS Data Bits 0 0 0 0 C19 C18 C17 C16 CGMS 19–16 00h
22h HD CGMS Data 1 HD CGMS Data Bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS 15–8 00h

23h HD CGMS Data 2 HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7–0 00h
24h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A0 00h

25h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A1 00h

26h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A2 00h
27h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A3 00h

28h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A4 00h
29h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A5 00h

2Ah HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A6 00h
2Bh HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A7 00h

2Ch HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A8 00h
2Dh HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A9 00h

2Eh HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B0 00h
2Fh HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B1 00h

30h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B2 00h
31h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B3 00h

32h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B4 00h
33h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B5 00h

34h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B6 00h
35h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B7 00h

36h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B8 00h
37h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B9 00h

.. .. .. .. ……

0111Gain A = +7

1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

Register
Setting

NOTES
Programmable gamma correction is not available in PS only @ 54 MHz input mode.
*For use with internal test pattern only.

Reset
Values

REV. A–22–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

38h 0 000Gain A = 0 00h

HD Adaptive Filter
Gain 1

39h 0 000Gain A = 0 00h

HD Adaptive Filter
Gain 2

3Ah 0 000Gain A = 0 00h

HD Adaptive Filter
Gain 3

3Bh xxxxxxxxThreshold A 00h

HD Adaptive Filter
Threshold A

3Ch x x x x x x x x Threshold B 00h

HD Adaptive Filter
Threshold B

3Dh x x x x x x x x Threshold C 00h

HD Adaptive Filter
Threshold C

HD Adaptive Filter Gain 1 Value A

HD Adaptive Filter Gain 1 Value B

HD Adaptive Filter Gain 2 Value A

HD Adaptive Filter Gain 2 Value B

HD Adaptive Filter Gain 3 Value A

HD Adaptive Filter Gain 3 Value B

HD Adaptive Filter Threshold A Value

HD Adaptive Filter Threshold B Value

HD Adaptive Filter Threshold C Value

0 001Gain A = +1

.. .. .. .. ……

0 111Gain A = +7

1 000Gain A = –8

.. .. .. .. ……

1 111Gain A = –1
0000 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0 001Gain A = +1

.. .. .. .. ……

0 111Gain A = +7

1 000Gain A = –8

.. .. .. .. ……

1 111Gain A = –1
0000 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0 001Gain A = +1

.. .. .. .. ……

0 111Gain A = +7

1 000Gain A = –8

.. .. .. .. ……

1 111Gain A = –1
0000 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7

1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

Register
Setting

Reset
Values

REV. A

–23–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

3Eh Reserved 00h
3Fh Reserved 00h

40h SD Mode Register 0 00NTSC 00h

41h Reserved 00h
42h SD Mode Register 1 SD PrPb SSAF 0 Disabled 08h

43h SD Mode Register 2 SD Pedestal YPrPb Output 0 No pedestal on YUV 00h

SD Standard

SD Luma Filter

SD Chroma Filter

SD DAC Output 1 0

SD DAC Output 2 0

SD Pedestal 0 Disabled

SD Square Pixel 0 Disabled

SD VCR FF/RW Sync 0 Disabled

SD Pixel Data Valid 0 Disabled

SD SAV/EAV Step Edge
Control

SD Output Levels Y 0 Y = 700 mV/300 mV

SD Output Levels PrPb 0 0 700 mV p-p[PAL];

SD VBI Open 0 Disabled

SD CC Field Control 0 0 CC disabled

Reserved 1 Reserved

000 1.3 MHz
001 0.65 MHz

010 1.0 MHz
011 2.0 MHz

100 Reserved
101 Chroma CIF

110 Chroma QCIF
111 3.0 MHz

1 Enabled

0 Disabled
1 Enabled

01 CC on odd field only

10 CC on odd field only
11 CC on both fields

000 LPF NTSC
001 LPF PAL

010 Notch NTSC
011 Notch PAL

100 SSAF Luma
101 Luma CIF

110 Luma QCIF
111 Reserved

1 Enabled

1 Enabled

1 Enabled

01 700 mV p-p
10 1000 mV p-p

11 648 mV p-p

1 Enabled

01PAL B, D, G, H, I

10PAL M
11PAL N

1 Enabled

Refer to output configuration

1

1

1Y = 714 mV/286 mV

section

Refer to output configuration
section

1 7.5 IRE pedestal on YUV

1000 mV p-p[NTSC]

Reset
Values

REV. A–24–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

SD Mode

44h SD VSYNC-3H 0Disabled 00h

Register 3

SD RTC/TR/SCR 0 0 Genlock disabled

SD Active Video Length 0 720 pixels

SD Chroma 0 Chroma enabled

SD Burst 0 Enabled

SD Color Bars 0 Disabled

SD DAC Swap 0 DAC A = Luma, DAC B =

45h Reserved 00h
46h Reserved 00h

47h SD PrPb Scale 0Disabled 00h

SD Mode
Register 4

SD Y Scale 0Disabled

SD Hue Adjust 0 Disabled

SD Brightness 0 Disabled

SD Luma SSAF Gain 0 Disabled

Reserved 0 0 must be written to this bit

Reserved 0 0 must be written to this bit

48h Reserved 0 00h

SD Mode
Register 5

49h SD Undershoot Limiter 0 0 Disabled 00h

SD Mode
Register 6

Reserved 0 0 must be written to this bit

Reserved 00 must be written to this bit
SD Double Buffering 0 Disabled

SD Input Format 0 0 8-bit Input

SD Digital Noise Reduction 0 Disabled

SD Gamma Control 0 Disabled

SD Gamma Curve 0 Gamma Curve A

Reserved 00 must be written to this bit
SD Black Burst Output on DAC

Luma

SD Chroma Delay 0 0 Disabled

Reserved 0 0 must be written to this bit
Reserved 0 0 must be written to this bit

1 Enabled

1DAC A = Chroma, DAC B =

1 Enabled

1 Gamma Curve B

1 Chroma disabled

1Disabled

1 Enabled

01 16-bit Input

10 10-bit Input
11 20-bit Input

1 Enabled

01 4 clk cycles

10 8 clk cycles
11 Reserved

01 Subcarrier Reset
10 Timing Reset

11 RTC enabled

1 710 [NTSC]/702[PAL]

1 Enabled

1 Enabled

1 Enabled

0Disabled

1 Enabled

1

VSYNC
VSYNC

Chroma

Luma

1 Enabled

1 Enabled

01 – 11 IRE

10 – 6 IRE
11 – 1.5 IRE

= 2.5 lines [PAL]
= 3 lines [NTSC]

Reset
Values

REV. A

–25–

ADV7310/ADV7311

H

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

SD Timing

4Ah SD Slave/Master Mode 0 Slave Mode 08h

Register 0

SD Timing

4Bh

Register 1

4Ch

SD F

Register 0
4Dh SD F
4Eh

4Fh SD F
50h

51h SD Closed

52h SD Closed

53h SD Closed

54h SD Closed

55h SD Pedestal

56h SD Pedestal

57h SD Pedestal

58h SD Pedestal

SC

Register 1

SC

SD F

Register 2

SC

Register 3

SC

SD F

Phase

SC

Captioning

Captioning

Captioning

Captioning

Register 0

Register 1

Register 2

Register 3

SD Timing Mode 0 0 Mode 0

SD BLANK Input

SD Luma Delay 0 0 No delay

SD Min. Luma Value 0 – 40 IRE

SD Timing Reset x 0 0 00000A low-high-low transition will reset

SD HSYNC Width

SD HSYNC to VSYNC delay

SD HSYNC to VSYNC Rising
Edge Delay [Mode 1 Only]

VSYNC Width [Mode 2 Only]

HSYNC to Pixel Data Adjust

Extended Data on Even Fields x x x xxxxxExtended Data Bit 7–0 00h

Extended Data on Even Fields x x x xxxxxExtended Data Bit 15–8 00h

Data on Odd Fields x x x xxxxxData Bit 7–0 00h

Data on Odd Fields x x x xxxxxData Bit 15–8 00h

Pedestal on Odd Fields 17 16 15 14 13 12 11 10 00h

Pedestal on Odd Fields 25 24 23 22 21 20 19 18 00h

Pedestal on Even Fields 17 16 15 14 13 12 11 10 00h

Pedestal on Even Fields 25 24 23 22 21 20 19 18 00h

00 0 clk cycles

01 1 clk cycle
10 2 clk cycles

11 3 clk cycles
xxxxxxxxSubcarrier Frequency Bit 7–0 16h

xxxxxxxxSubcarrier Frequency Bit 15–8 7Ch
xxxxxxxxSubcarrier Frequency Bit 23–16 F0h

xxxxxxxxSubcarrier Frequency Bit 31–24 21h
xxxxxxxxSubcarrier Phase Bit 9–2 00h

01 2 clk cycles

10 4 clk cycles
11 6 clk cycles

1– 7.5 IRE

x0 Tc = Tb

x1 Tc = Tb + 32 us
00 1 clk cycle

01 4 clk cycles
10 16 clk cycles

11 128 clk cycles

01 Mode 1

10 Mode 2
11 Mode 3

0 Enabled
1 Disabled

00 Tb = 0 clk cycle

01 Tb = 4 clk cycles
10 Tb = 8 clk cycles

11 Tb = 18 clk cycles

1 Master Mode

00 Ta = 1 clk cycle 00h

01 Ta = 4 clk cycles
10 Ta = 16 clk cycles

11 Ta = 128 clk cycles

the internal SD timing counters

Setting any of these bits to 1 will
disable pedestal on the line number
indicated by the bit settings

Reset
Values

LINE 313 LINE 314LINE 1

SYNC

VSYNC

t

A

t

t

B

C

Figure 21. Timing Register 1 in PAL Mode

REV. A–26–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

59h SD CGMS/WSS 0 SD CGMS Data 19 18 17 16 CGMS data bits C19–C16 00h

5Ah SD CGMS/WSS 1 SD CGMS/WSS Data 13 12 11 10 9 8 CGMS data bits C13–C8 or WSS

5Bh SD CGMS/WSS 2 SD CGMS/WSS Data 7 6 5 4 3 2 1 0 CGMS/WSS data bits C7–C0 00h
5Ch SD LSB Register SD LSB for Y Scale Value x x SD Y Scale Bit 1–0

5Dh SD Y Scale Register SD Y Scale Value x x x x x x x x SD Y Scale Bit 7–2 00h

5Eh SD V Scale Register SD V Scale Value x x x x x x x x SD V Scale Bit 7–2 00h
5Fh SD U Scale Register SD U Scale Value x x x x x x x x SD U Scale Bit 7–2 00h

60h SD Hue Register SD Hue Adjust Value x x x x x x x x SD Hue Adjust Bit 7–0 00h

61h SD Brightness Value x x x x x x x SD Brightness Bit 6–0 00h

SD Brightness/WSS

62h SD Luma SSAF 0 0 0 0 0 0 0 0 –4 dB 00h

63h SD DNR 0 Coring Gain Border 0 0 0 0 No gain 00h

64h SD DNR 1 DNR Threshold 0 0 0 0 0 0 0 00h

SD CGMS CRC 0 Disabled

SD CGMS on Odd Fields 0 Disabled

SD CGMS on Even Fields 0 Disabled

SD WSS 0 Disabled

SD LSB for U Scale Value x x SD U Scale Bit 1–0
SD LSB for V Scale Value x x SD V Scale Bit 1–0

SD LSB for F

SD Blank WSS Data 0 Disabled Line 23

SD Luma SSAF
Gain/Attenuation

Coring Gain Data 0 0 0 0 No gain

Border Area 0 2 pixels

Block Size Control 0 8 pixels

Phase x x Subcarrier Phase Bits 1–0

SC

1 Enabled

1 Enabled

15 14 CGMS data bits C15–C14 00h

1 Enabled

000001100 dB
00001100+4 dB

0001 +1/16 [–1/8]
0010 +2/16 [–2/8]

0011 +3/16 [–3/8]
0100 +4/16 [–4/8]

0101 +5/16 [–5/8]
0110 +6/16 [–6/8]

0111 +7/16 [–7/8]
1000 +8/16 [–1]

14 pixels

1 16 pixels

1 Enabled

1 Enabled

data bits C13–C8

0 001+1/16 [–1/8]

0 010+2/16 [–2/8]
0 011+3/16 [–3/8]

0 100+4/16 [–4/8]
0 101+5/16 [–5/8]

0 110+6/16 [–6/8]
0 111+7/16 [–7/8]

1 000+8/16 [–1]

0000011

…………………
11111062

11111163

Reset
Values

00h

In DNR
mode, the
values in
brackets
apply.

REV. A

–27–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

65h SD DNR 2 DNR Input Select 0 0 1 Filter A 00h

DNR Mode 0 DNR mode

DNR Block Offset 0 0 0 0 0 pixel offset

66h SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A0 00h

67h SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A1 00h
68h SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A2 00h

69h SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A3 00h
6Ah SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A4 00h

6Bh SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A5 00h
6Ch SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A6 00h

6Dh SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A7 00h
6Eh SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A8 00h

6Fh SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A9 00h
70h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B0 00h

71h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B1 00h
72h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B2 00h

73h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B3 00h
74h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B4 00h

75h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B5 00h
76h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B6 00h

77h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B7 00h
78h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B8 00h

79h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B9 00h
7Ah SD Brightness

Detect

7Bh Field Count x xxRead only

Field Count
Register

7Ch 10-Bit Input 0 0 0 0 0 0 1 0 Must write this for 10-bit data

SD Brightness Value x x x x x x x x Read only

Reserved 0 0 must be written to this bit

Reserved 0 0 must be written to this bit
Reserved 0 0 must be written to this bit

Revision Code x x Read only

1 0 0 Filter D

1 DNR sharpness mode

00011 pixel offset

………… …
1110 14 pixel offset

1111 15 pixel offset

0 10Filter B

0 11Filter C

input (SD, PS, HD)

Reset
Values

00h

REV. A–28–

ADV7310/ADV7311

SR7­SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

7Dh Reserved
7Eh Reserved

7Fh Reserved
80h Macrovision MV Control Bits x x x x x x x x 00h

81h Macrovision MV Control Bits x x x x x x x x 00h
82h Macrovision MV Control Bits x x x x x x x x 00h

83h Macrovision MV Control Bits x x x x x x x x 00h
84h Macrovision MV Control Bits x x x x x x x x 00h

85h Macrovision MV Control Bits x x x x x x x x 00h
86h Macrovision MV Control Bits x x x x x x x x 00h

87h Macrovision MV Control Bits x x x x x x x x 00h
88h Macrovision MV Control Bits x x x x x x x x 00h

89h Macrovision MV Control Bits x x x x x x x x 00h
8Ah Macrovision MV Control Bits x x x x x x x x 00h

8Bh Macrovision MV Control Bits x x x x x x x x 00h
8Ch Macrovision MV Control Bits x x x x x x x x 00h

8Dh Macrovision MV Control Bits x x x x x x x x 00h
8Eh Macrovision MV Control Bits x x x x x x x x 00h

8Fh Macrovision MV Control Bits x x x x x x x x 00h
90h Macrovision MV Control Bits x x x x x x x x 00h

91h Macrovision MV Control Bit x 00h

00 000000 must be written to these bits

NOTE
Macrovision registers only on the ADV7310.

Reset
Values

REV. A

–29–

ADV7310/ADV7311

INPUT CONFIGURATION

When 10-bit input data is applied, the following bits must be
set to 1:

Address 0x7C, Bit 1 (Global 10-Bit Enable)

Address 0x13, Bit 2 (HD 10-Bit Enable)

Address 0x48, Bit 4 (SD 10-Bit Enable)

Note that the ADV7310 defaults to simultaneous standard
definition and progressive scan on power-up.
Address[01h] : Input Mode = 011

Standard Definition Only
Address[01h] : Input Mode = 000

The 8-/10-bit multiplexed input data is input on Pins S9–S0 (or
Y9–Y0, depending on Register Address 01h, Bit 7), with S0 being
the LSB in 10-bit input mode. Input standards supported are
ITU-R BT.601/656. In 16-bit input mode, the Y pixel data is
input on Pins S9–S2 and CrCb data on Pins C9–C2. The 27 MHz
clock input must be input on Pin CLKIN_A. Input sync signals
are optional and are input on the S_VSYNC, S_HSYNC, and
S_BLANK pins.

ADV7310/
ADV7311

S_VSYNC

3

10

S_HSYNC
S_BLANK

CLKIN_A

S[9:0] OR Y[9:0]*

MPEG2

DECODER

27MHz

YCrCb

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 22. SD Only Input Mode

Progressive Scan Only or HDTV Only
Address[01h] Input Mode 001 or 010, Respectively

YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y9–Y0 and the CrCb data on Pins C9–C0. In
4:4:4 input mode, Y data is input on Pins Y9–Y0, Cb data on
Pins C9–C0, and Cr data on Pins S9–S0. If the YCrCb data
does not conform to SMPTE 293M (525p), ITU-R BT.1358M
(625p), SMPTE 274M[1080i], SMPTE 296M[720p], or
BTA-T1004/1362, the async timing mode must be used. RGB
data can only be input in 4:4:4 format in PS input mode only or
HDTV input mode only when HD RGB input is enabled. G data
is input on Pins Y9–Y0, R data on S9–S0, and B data on C9–C0.
The clock signal must be input on Pin CLKIN_A.

MPEG2

DECODER

YCrCb

INTERLACED TO
PROGRESSIVE

27MHz

Cb

Cr

Y

10

10

10

3

ADV7310/
ADV7311

CLKIN_A

C[9:0]

S[9:0]

Y[9:0]

P_VSYNC
P_HSYNC
P_BLANK

Figure 23. Progressive Scan Input Mode

Simultaneous Standard Definition and
Progressive Scan or HDTV
Address[01h] : Input Mode 011(SD 10-Bit, PS 20-Bit) or
101(SD and HD, SD Oversampled), 110(SD and HD, HD
Oversampled), Respectively

YCrCb, PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode the HD Y data is input on
Pins Y9–Y0 and the HD CrCb data on C9–C0. If PS 4:2:2 data
is interleaved onto a single 10-bit bus, Y9–Y0 are used for the
input port. The input data is to be input at 27 MHz, with the
data being clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accord­ingly. If the YCrCb data does not conform to SMPTE 293M
(525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i],
SMPTE 296M[720p], or BTA-T1004, the async timing mode
must be used.

The 8- or 10-bit standard definition data must be compliant
with ITU-R BT.601/656 in 4:2:2 format. Standard definition
data is input on Pins S9–S0, with S0 being the LSB. Using
8-bit input format, the data is input on Pins S9–S2. The clock
input for SD must be input on CLKIN_A and the clock input
for HD must be input on CLKIN_B. Synchronization signals are
optional. SD syncs are input on Pins S_VSYNC, S_HSYNC,
and S_BLANK. HD syncs on Pins P_VSYNC, P_HSYNC,
and P_BLANK.

ADV7310/
ADV7311

S_VSYNC

3

MPEG2

DECODER

YCrCb

INTERLACED TO
PROGRESSIVE

27MHz

CrCb

Y

27MHz

S_HSYNC
S_BLANK

CLKIN_A

10

S[9:0]

10

C[9:0]

10

Y[9:0]

P_VSYNC

3

P_HSYNC
P_BLANK

CLKIN_B

Figure 24. Simultaneous PS and SD Input

REV. A–30–

ADV7310/ADV7311

ADV7310/
ADV7311

S_VSYNC

3

SDTV

DECODER

HDTV

DECODER

1080i

720p

27MHz

OR

74.25MHz

S_HSYNC
S_BLANK

CLKIN_A

10YCrCb

S[9:0]

10CrCb

C[9:0]

10Y

Y[9:0]

P_VSYNC

3

P_HSYNC
P_BLANK

CLKIN_B

Figure 25. Simultaneous HD and SD Input

If in simultaneous SD/HD input mode the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 01h Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.

CLKIN_A

CLKIN_B

t

 9.25ns OR

DELAY

t

  27.75ns

DELAY

Figure 26. Clock Phase with Two Input Clocks

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address[01h] : Input Mode 100 or 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-/10-bit bus and is
input on Pins Y9–Y0. When a 27 MHz clock is supplied, the data
is clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 0x01, Bit 1] must be set accordingly.

The following figures show the possible conditions: (a) Cb data
on the rising edge and (b) Y data on the rising edge.

CLKIN_B

Y9–Y0

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.

3FF 00 00 XY Y0 Y1Cr0

Cb0

Figure 27a. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)

CLKIN_B

Y9–Y0

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.

3FF 00 00 XY Cb0 Cr0Y1

Y0

Figure 27b. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)

CLKIN

PIXEL INPUT

DATA

WITH A 54 MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.

3FF 00 00 XY Cb0 Y0 Y1Cr0

Figure 27c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)

MPEG2

DECODER

27MHz OR 54MHz

YCrCb

INTERLACED

TO

PROGRESSIVE

YCrCb

10

3

ADV7310/
ADV7311

CLKIN_A

Y[9:0]

P_VSYNC
P_HSYNC
P_BLANK

Figure 28. 1  10-Bit PS at 27 MHz or 54 MHz

Table I provides an overview of all possible input configurations.

REV. A

–31–

ADV7310/ADV7311

Input Format Total Bits Input Video Input Pins Subaddress Register Setting

ITU-R BT.656 8 4:2:2 YCrCb S9–S2 [MSB = S9] 01h

PS Only 8 [27 MHz clock] 4:2:2 YCrCb Y9–Y2 [MSB = Y9] 01h

HDTV Only 16 4:2:2 Y Y9–Y2 [MSB = Y9] 01h 20h

HD RGB 24 4:4:4 G Y9–Y2 [MSB = Y9] 01h 10h or 20h

ITU-R BT.656 and PS

ITU-R BT.656 and PS

ITU-R BT.656 and PS or HDTV 8 4:2:2 YCrCb S9–S2 [MSB = S9] 01h 30h or 50h or 60h

ITU-R BT.656 and PS or HDTV 10 4:2:2 YCrCb S9–S0 [MSB = S9] 01h 30h or 50h or 60h

Table I. Input Configurations

10 4:2:2 YCrCb S9–S0 [MSB = S9] 01h

16 4:2:2 Y S9–S2 [MSB = S9] 01h 00h

CrCb Y9–Y2 [MSB = Y9] 48h 08h

20 4:2:2 Y S9–S0 [MSB = S9] 01h 00h

CrCb Y9–Y0 [MSB = Y9] 48h 18h

8 4:2:2 YCrCb Y9–Y2 [MSB = Y9] 01h 80h

10 4:2:2 YCrCb Y9–Y0 [MSB = Y9] 01h

10 [27 MHz clock] 4:2:2 YCrCb Y9–Y0 [MSB = Y9] 01h

8 [54 MHz clock] 4:2:2 YCrCb Y9–Y2 [MSB = Y9] 01h

10 [54 MHz clock] 4:2:2 YCrCb Y9–Y0 [MSB = Y9] 01h

16 4:2:2 Y Y9–Y2 [MSB = Y9] 01h 10h

CrCb C9–C2 [MSB = C9] 13h 40h

20 4:2:2 Y Y9–Y0 [MSB = Y9] 01h 10h

CrCb C9–C0 [MSB = C9] 13h 44h

24 4:4:4 Y Y9–Y2 [MSB = Y9] 01h 10h

Cb C9–C2 [MSB = C9] 13h 00h

Cr S9–S2 [MSB = S9]

30 4:4:4 Y Y9–Y0 [MSB = Y9] 01h 10h

Cb C9–C0 [MSB = C9] 13h 04h
Cr S9–S0 [MSB = S9]

CrCb C9–Y2 [MSB = C9] 13h 40h

20 4:2:2 Y Y9–Y0 [MSB = Y9] 01h 20h

CrCb C9–C0 [MSB = C9] 13h 44h

24 4:4:4 Y Y9–Y2 [MSB = Y9] 01h 20h

Cb C9–Y2 [MSB = C9] 13h 00h
Cr S9–S2 [MSB = S9]

30 4:4:4 Y Y9–Y0 [MSB = Y9] 01h 20h

Cb C9–C0 [MSB = C9] 13h 04h

Cr S9–S0 [MSB = S9]

B C9–C2 [MSB = C9] 13h 00h

R S9–S2 [MSB = S9] 15h 02h

30 4:4:4 G Y9–Y0 [MSB = Y9] 01h 10h or 20h

B C9–C0 [MSB = C9] 13h 04h
R S9–S0 [MSB = S9] 15h 02h

8 4:2:2 YCrCb S9–S2 [MSB = S9] 01h 40h
8 4:2:2 YCrCb Y9–Y2 [MSB = Y9] 13h

10 4:2:2 YCrCb S9–S0 [MSB = S9] 01h 40h

10 4:2:2 YCrCb Y9–Y0 [MSB = Y9] 13h

16 4:2:2 Y Y9–Y2 [MSB = Y9] 13h 40h

CrCb C9–C2 [MSB = C9] 48h 00h

20 4:2:2 Y Y9–Y0 [MSB = Y9] 13h 44h

CrCb C9–C0 [MSB = C9] 48h 10h

48h

48h

48h 00h

48h

13h

13h

13h

13h

48h

00h
00h

00h
10h

80h
10h

10h
40h

10h
44h

70h
40h

70h
44h

40h

44h
10h

REV. A–32–

ADV7310/ADV7311

OUTPUT CONFIGURATION

The tables below demonstrate what output signals are assigned to the DACs when the control bits are set accordingly.

Table II. Output Configuration in SD Only Mode

RGB/YUV Output
02h, Bit 5

000

001

010

011

100CVBS Luma Chroma Y U V

101YUVCVBS Luma Chroma

110YLuma Chroma CVBS U V

111CVBS U V Y Luma Chroma

Luma/Chroma Swap 44h, Bit 7

0

1 Table above with all Luma/Chroma instances swapped

SD DAC Output 1
42h, Bit 2

Table as above

Table III. Output Configuration in HD/PS Only Mode

SD DAC Output 2
42h, Bit 1 DAC A DAC B DAC C DAC D DAC E

CVBS Luma Chroma G

GB RCVBS

G Luma Chroma CVBS

CVBS B R G

B

Luma

B

Luma

DAC F

R

Chroma

R

Chroma

HD/PS
Input
Format

YCrCb 4:2:2 0 0 0 N/A N/A N/A G B R

YCrCb 4:2:2 0 0 1

YCrCb 4:2:2 0 1 0

YCrCb 4:2:2 0 1 1

YCrCb 4:4:4 0 0 0

YCrCb 4:4:4 0 0 1 N/A N/A N/A G R B

YCrCb 4:4:4 0 1 0 N/A N/A N/A Y Pb Pr

YCrCb 4:4:4 0 1 1 N/A N/A N/A Y Pr Pb

RGB 4:4:4 1 0 0

RGB 4:4:4 1 0 1 N/A N/A N/A G R B

RGB 4:4:4 1 1 0 N/A N/A N/A G B R

RGB 4:4:4 1 1 1 N/A N/A N/A G R B

HD/PS RGB
Input 15h,
Bit 1

RGB/YPrPb
Output 02h,
Bit 5

HD/PS Color
Swap 15h, Bit 3 DAC A DAC B DAC C DAC D DAC E

N/A N/A N/A G

N/A N/A N/A Y

N/A N/A N/A Y

N/A N/A N/A G

N/A N/A N/A G

R

Pb

Pr

B

B

Table IV. Output Configuration in Simultaneous SD and HD/PS Only Mode

Input Formats

ITU-R.BT656 and
HD YCrCb in 4:2:2

ITU-R.BT656 and
HD YCrCb in 4:2:2

ITU-R.BT656 and
HD YCrCb in 4:2:2

ITU-R.BT656 and
HD YCrCb in 4:2:2

RGB/YPrPb
Output 02h, Bit 5

00

01 CVBS Luma Chroma G R B

10

11 CVBS Luma Chroma Y Pr Pb

HD/PS Color
Swap 15h, Bit 3 DAC A DAC B DAC C DAC D DAC E

CVBS Luma Chroma G

CVBS Luma Chroma Y

B

Pb

DAC F

R

Pr

DAC F

B

Pr

Pb

R

R

REV. A

–33–

ADV7310/ADV7311

TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bit 3, 2]

For any input data that does not conform to the standards select­able in input mode, Subaddress 10h, asynchronous timing mode
can be used to interface to the ADV7310/ADV7311. Timing control
signals for HSYNC, VSYNC, and BLANK have to be programmed
by the user. Macrovision and programmable oversampling rates
are not available in async timing mode.

CLK

P_HSYNC

P_VSYNC

P_BLANK

SET ADDRESS 10h,

BIT 6 TO 1

HORIZONTAL SYNC

In async mode, the PLL must be turned off [Subaddress 00h,
Bit 1 = 1].

Figures 29a and 29b show examples of how to program the
ADV7310/ADV7311 to accept a different high definition standard
other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358.

The following truth table must be followed when programming the
control signals in async timing mode. For standards that do not
require a tri-sync level, P_BLANK must be tied low at all times.

PROGRAMMABLE
INPUT TIMING

ACTIVE VIDEO

ANALOG
OUTPUT

Figure 29a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility

CLK

P_HSYNC

P_VSYNC

P_BLANK

SET ADDRESS 10h,

BIT 6 TO 1

ANALOG OUTPUT

81 66 66 243 1920

edcba

HORIZONTAL SYNC

ACTIVE VIDEO

Figure 29b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal

0

1

edcba

REV. A–34–

ADV7310/ADV7311

Table V. Async Timing Mode Truth Table

Reference

P_HSYNC P_VSYNC P_BLANK* Reference in Figure 29

1 → 0 0 0 or 1 50% point of falling edge of trilevel horizontal sync signal a
00 → 1 0 or 1 25% point of rising edge of trilevel horizontal sync signal b
0 → 1 0 or 1 0 50% point of falling edge of trilevel horizontal sync signal c
10 or 1 0 → 1 50% start of active video d
10 or 1 1 → 0 50% end of active video e

*When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.

HD TIMING RESET

A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 14h, Bit 0] from 0 to 1. In this state the horizontal
and vertical counters will remain reset. When this bit is set back
to 0, the internal counters will commence counting again.

The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.

REV. A

–35–

ADV7310/ADV7311

SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2, 1]

Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 44h, Bit 1, 2], the ADV7310/ADV7311 can be used in
(a) timing reset mode, (b) subcarrier phase reset mode, or (c)
RTC mode.

a. A timing reset is achieved in a low-to-high transition on the

RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set
to low), the internal counters will commence counting again,
the field count will start on Field 1, and the subcarrier phase
will be reset.

The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.

b. In subcarrier phase reset, a low-to-high transition on the

RTC_SCR_TR pin (Pin 31) will reset the subcarrier phase to
zero on the field following the subcarrier phase reset when the
SD RTC/TR/SCR control bits at Address 44h are set to 01.

DISPLAY

307 310

NO TIMING RESET APPLIED

START OF FIELD 4 OR 8 FSC PHASE = FIELD 4 OR 8

313 320

This reset signal will have to be held high for a minimum of
one clock cycle.

Since the field counter is not reset, it is recommended that
the reset signal be applied in Field 7 [PAL] or Field 3 [NTSC].
The reset of the phase will then occur on the next field, i.e.,
Field 1, being lined up correctly with the internal counters.
The field count register at Address 7Bh can be used to iden­tify the number of the active field.

c. In RTC mode, the ADV7310/ADV7311 can be used to lock

to an external video source. The real-time control mode allows
the ADV7310/ADV7311 to automatically alter the subcarrier
frequency to compensate for line length variations. When the
part is connected to a device that outputs a digital data stream
in the RTC format, such as an ADV7183A video decoder
(see Figure 32), the part will automatically change to the
compensated subcarrier frequency on a line by line basis. This
digital data stream is 67 bits wide and the subcarrier is con­tained in Bits 0 to 21. Each bit is two clock cycles long. 00h
should be written into all four subcarrier frequency registers
when this mode is used.

DISPLAY

START OF FIELD 1

307 1 2 3 4 5 6 7 21

TIMING RESET APPLIED

F

PHASE = FIELD 1

SC

Figure 30. Timing Reset Timing Diagram

DISPLAY

307 310 313 320

NO FSC RESET APPLIED

DISPLAY

307 310 313 320

FSC RESET APPLIED

START OF FIELD 4 OR 8

START OF FIELD 4 OR 8

Figure 31. Subcarrier Reset Timing Diagram

TIMING RESET PULSE

PHASE = FIELD 4 OR 8

F

SC

PHASE = FIELD 1

F

SC

F

RESET PULSE

SC

REV. A–36–

ADV7310/ADV7311

Reset Sequence

A reset is activated with a high-to-low transition on the RESET
pin [Pin 33] according to the timing specifications. The ADV7310/
ADV7311 will revert to the default output configuration.

Figure 32 illustrates the RESET sequence timing.

SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]

In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non­standard input video, i.e., in fast forward or rewind modes.

CLKIN_A

LCC1

COMPOSITE

VIDEO

H/L TRANSITION

COUNT START

RTC

TIME SLOT 01

NOTES

1

i.e., VCR OR CABLE

2

F

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7310/ADV7311 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0

SC

PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7310/ADV7311.

3

SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE

4

RESET ADV7310/ADV7311 DDS

5

SELECTED BY REGISTER ADDRESS 0x01 BIT 7

1

128

ADV7183A

VIDEO

DECODER

SUBCARRIER

LOW

13 0

14 BITS

PHASE

GLL

P19–P10

RESERVED

142119

4 BITS

RTC_SCR_TR

Y9-Y0/S9–S0

Figure 32. RTC Timing and Connections

In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct num­ber of lines/fields are reached; in rewind mode, this sync signal
usually occurs after the total number of lines/fields are reached.
Conventionally this means that the output video will have cor­rupted field signals, one generated by the incoming video and
one generated when the internal lines/field counters reach the
end of a field.

When the VCR FF/RW sync control is enabled [Subaddress 42h
Bit 5] the lines/field counters are updated according to the
incoming VSYNC signal and the analog output matches the
incoming VSYNC signal.

This control is available in all slave timing modes except Slave
Mode 0.

ADV7310/

ADV7311

DAC A

DAC B

DAC C

DAC D

5

DAC E

DAC F

FSC PLL INCREMENT

VALID

INVALID

SAMPLE

SAMPLE

SEQUENCE

BIT

2

8/LINE

LOCKED

CLOCK

0

3

6768

5 BITS

RESERVED

RESET

4

BIT

RESERVED

REV. A

RESET

DACs

A, B, C

DIGITAL TIMING

PIXEL DATA

VALID

XXXXXX

XXXXXX

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

Figure 33.

RESET

Timing Sequence

–37–

VALID VIDEO

TIMING ACTIVE

ADV7310/ADV7311

H

B

Vertical Blanking Interval

The ADV7310/ADV7311 accept input data that contains VBI
data [CGMS, WSS, VITS, and so on] in SD and HD modes.

For SMPTE 293M [525p] standards, VBI data can be inserted
on Lines 13 to 42 of each frame, or on Lines 6 to 43 for the
ITU-R BT.1358 [625p] standard.

For SD NTSC this data can be present on Lines 10 to 20, and
in PAL on Lines 7 to 22.

If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.

In Slave Mode 0, if VBI is enabled, the blanking bit in the
EAV/SAV code is overwritten, and it is possible to use VBI in
this timing mode as well.

In Slave Mode 1 or 2, the BLANK control bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7310/ADV7311. Otherwise, the ADV7310/ADV7311
automatically blanks the VBI to standard.

If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.

Subcarrier Frequency Registers
[Subaddress 4Ch–4Fh]

Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the equation

Subcarrier Frequency Register

Number of subcarrier frequency values in one video line

Number of 27 MHz clk cyclesin onevideo line

*Rounded to the nearest integer

=

23

*

 2

For example, in NTSC mode,

227.5

Subcarrier FrequencyValue =






1716



23

2 569408542

×=




Subcarrier Register Value = 21F07C1Eh

SD F

Register 0: 1Eh

SC

Register 1: 7Ch

SD F

SC

SD F

Register 2: F0h

SC

Register 3: 21h

SD F

SC

Refer to the MPU Port Description section for more details on
how to access the subcarrier frequency registers.

Square Pixel Timing
[Register 42h, Bit 4]

In square pixel mode, the following timing diagrams apply.

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

EAV CODE

C

FF0000X

Y

Y

r

4 CLOCK

4 CLOCK

END OF ACTIVE

VIDEO LINE

8

10801

0

Y

0

FF00FFABABA

ANCILLARY DATA

272 CLOCK

344 CLOCK

B

(HANC)

801

0

SAV CODE

8

10FF0

0

0

XYC

Y

0

0

b

4 CLOCK

4 CLOCK

START OF ACTIVE

VIDEO LINE

C

C

Y

Y

b

r

1280 CLOCK

1536 CLOCK

C

C

Y

b

r

Figure 34. EAV/SAV Embedded Timing

SYNC

FIELD

PAL = 44 CLOCK CYCLES

LANK

PIXEL

DATA

NTSC = 44 CLOCK CYCLES

Cb Y

Cr Y

PAL = 136 CLOCK CYCLES

NTSC = 208 CLOCK CYCLES

Figure 35. Active Pixel Timing

REV. A–38–

ADV7310/ADV7311

)

)

FILTER SECTION

Table VI shows an overview of the programmable filters available
on the ADV7310/ADV7311.

Table VI. Selectable Filters

Filter Subaddress

SD Luma LPF NTSC 40h
SD Luma LPF PAL 40h
SD Luma Notch NTSC 40h
SD Luma Notch PAL 40h
SD Luma SSAF 40h
SD Luma CIF 40h
SD Luma QCIF 40h
SD Chroma 0.65 MHz 40h
SD Chroma 1.0 MHz 40h
SD Chroma 1.3 MHz 40h
SD Chroma 2.0 MHz 40h
SD Chroma 3.0 MHz 40h
SD Chroma CIF 40h
SD Chroma QCIF 40h
SD UV SSAF 42h
HD Chroma Input 13h
HD Sinc Filter 13h
HD Chroma SSAF 13h

HD Sinc Filter

0.5

0.4

0.3

0.2

0.1

0

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

Figure 36. HD Sinc Filter Enabled

0.5

0.4

0.3

0.2

0.1

0

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

Figure 37. HD Sinc Filter Disabled

10 15 20 25

FREQUENCY (MHz

10 15 20 25

FREQUENCY (MHz

3050

3050

REV. A

–39–

ADV7310/ADV7311

SD Internal Filter Response
[Subaddress 40h; Subaddress 42, Bit 0]

The Y filter supports several different frequency responses including
two low-pass responses, two notch responses, an extended (SSAF)
response with or without gain boost attenuation, a CIF response,
and a QCIF response. The UV filter supports several different
frequency responses including six low-pass responses, a CIF
response, and a QCIF response, as can be seen in the figures on
the following pages.

If SD SSAF gain is enabled, there is the option of 12 responses
in the range from –4 dB to +4 dB [Subaddress 47, Bit 4]. The
desired response can be chosen by the user by programming the
correct value via the I2C [Subaddress 62h]. The variation of fre­quency responses can be seen in the figures on the following pages.

In addition to the chroma filters listed in Table VII, the
ADV7310/ADV7311 contains an SSAF filter specifically designed
for and applicable to the color difference component outputs,
U and V. This filter has a cutoff frequency of about 2.7 MHz
and –40 dB at 3.8 MHz, as can be seen in Figure 38. This filter
can be controlled with Address 42h, Bit 0.

If this filter is disabled, the selectable chroma filters shown in
Table VII can be used for the CVBS or Luma/Chroma signal.

Table VII. Internal Filter Specifications

Pass-Band 3 dB

Filter Ripple1 (dB) Bandwidth2 (MHz)

Luma LPF NTSC 0.16 4.24
Luma LPF PAL 0.1 4.81
Luma Notch NTSC 0.09 2.3/4.9/6.6
Luma Notch PAL 0.1 3.1/5.6/6.4
Luma SSAF 0.04 6.45
Luma CIF 0.127 3.02
Luma QCIF Monotonic 1.5
Chroma 0.65 MHz Monotonic 0.65
Chroma 1.0 MHz Monotonic 1
Chroma 1.3 MHz 0.09 1.395
Chroma 2.0 MHz 0.048 2.2
Chroma 3.0 MHz Monotonic 3.2
Chroma CIF Monotonic 0.65
Chroma QCIF Monotonic 0.5

NOTES

1

Pass-band ripple is the maximum fluctuation from the 0 dB response in the

pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz)
frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to infinity for
a notch filter, where fc, f1, and f2 are the –3 dB points.

2

3 dB bandwidth refers to the –3 dB cutoff frequency.

EXTENDED UV FILTER MODE

0

–10

–20

–30

GAIN (dB)

–40

–50

–60

6543210

FREQUENCY (MHz)

Figure 38. UV SSAF Filter

REV. A–40–

Typical Performance Characteristics–ADV7310/ADV7311

PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 1. PS—UV 8× Oversampling Filter (Linear)

PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

1.0

0.5

0

–0.5

–1.0

GAIN (dB)

–1.5

–2.0

–2.5

–3.0

Y PASS BAND IN PS OVERSAMPLING MODE

122468100

FREQUENCY (MHz)

TPC 4. PS—Y 8× Oversampling Filter (Pass Band)

Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 2. PS—UV 8× Oversampling Filter (SSAF)

Y RESPONSE IN PS OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 3. PS—Y (8× Oversampling Filter)

–80

FREQUENCY (MHz)

TPC 5. HDTV—UV (2× Oversampling Filter)

Y RESPONSE IN HDTV OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

TPC 6. HDTV—Y (2× Oversampling Filter)

14020 40 60 80 100 1200

14020 40 60 80 100 1200

REV. A

–41–

ADV7310/ADV7311

)

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz

TPC 7. Luma NTSC Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

TPC 8. Luma PAL Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

121086420

–70

FREQUENCY (MHz)

121086420

TPC 10. Luma PAL Notch Filter

Y RESPONSE IN SD OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

121086420

–80

020406080100 120 140 160 180 200

FREQUENCY (MHz)

TPC 11. Y—16× Oversampling Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

TPC 9. Luma NTSC Notch Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

121086420

–70

FREQUENCY (MHz)

121086420

TPC 12. Luma SSAF Filter up to 12 MHz

REV. A–42–

ADV7310/ADV7311

)

)

4

2

0

–2

–4

–6

MAGNITUDE (dB)

–8

–10

–12

01234 7

FREQUENCY (MHz)

5

6

TPC 13. Luma SSAF Filter—Programmable Responses

5

4

3

2

MAGNITUDE (dB)

1

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 16. Luma CIF Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

0

–1

01234 7

FREQUENCY (MHz

5

6

TPC 14. Luma SSAF Filter—Programmable Gain

1

0

–1

–2

MAGNITUDE (dB)

–3

–4

–5

01234 7

FREQUENCY (MHz

5

6

TPC 15. Luma SSAF Filter—Programmable Attenuation

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 17. Luma QCIF Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 18. Chroma 3.0 MHz Low-Pass Filter

REV. A

–43–

ADV7310/ADV7311

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 19. Chroma 2.0 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 22. Chroma 0.65 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 20. Chroma 1.3 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 21. Chroma 1.0 MHz Low-Pass Filter

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 23. Chroma CIF Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

10

TPC 24. Chroma QCIF Low-Pass Filter

REV. A–44–

ADV7310/ADV7311

COLOR CONTROLS AND RGB MATRIX
HD Y Level, HD Cr Level, HD Cb Level
[Subaddress 16h–18h]

Three 8-bit registers at Address 16h, 17h, 18h are used to program
the output color of the internal HD test pattern generator, be it
the lines of the cross hatch pattern or the uniform field test
pattern. They are not functional as color controls on external
pixel data input. For this purpose the RGB matrix is used.

The standard used for the values for Y and the color difference
signals to obtain white, black, and the saturated primary and
complementary colors conforms to the ITU-R BT.601-4 standard.

Table VIII shows sample color values to be programmed into
the color registers when Output Standard Selection is set to EIA 770.2.

Table VIII. Sample Color Values for EIA 770.2 Output
Standard Selection

Sample Y Cr Cb
Color Value Value Value

White 235 (EB) 128 (80) 128 (80)
Black 16 (10) 128 (80) 128 (80)
Red 81 (51) 240 (F0) 90 (5A)
Green 145 (91) 34 (22) 54 (36)
Blue 41 (29) 110 (6E) 240 (F0)
Yellow 210 (D2) 146 (92) 16 (10)
Cyan 170 (AA) 16 (10) 166 (A6)
Magenta 106 (6A) 222 (DE) 202 (CA)

HD RGB Matrix
[Subaddress 03h–09h]

When the programmable RGB matrix is disabled [Address 02h,
Bit 3], the internal RGB matrix takes care of all YCrCb to YUV
or RGB scaling according to the input standard programmed
into the device.

When the programmable RGB matrix is enabled, the color compo­nents are converted according to the 1080i standard [SMPTE 274M]:

Y' R' G' B'

=++

0 2126 0 7152 0 0722

...

CB' B' Y'

=− −

05 100722

[. /( . )]( )

CR' R' Y'

=− −

05 102126

[. /( . )]( )

This is reflected in the preprogrammed values for GY = 138Bh,
GU = 93h, GV = 3B, BU = 248h, and RV = 1F0.

If another input standard is used, the scale values for GY, GU,
GV, BU, and RV have to be adjusted according to this input
standard. The user must consider the fact that the color compo­nent conversion might use different scale values. For example,
SMPTE 293M uses the following conversion:

Y' R' G' B'

=++

0 299 0 587 0 114

...

CB' B' Y'

=− −

05 1 0114

[. /( . )]( )

CR' R' Y'

=− −

05 1 0299

[. /( . )]( )

The programmable RGB matrix can be used to control the HD
output levels in cases where the video output does not conform
to standard due to altering the DAC output stages such as ter­mination resistors. The programmable RGB matrix is used for
external HD data and is not functional when the HD test pattern
is enabled.

REV. A

–45–

Programming the RGB Matrix

The RGB matrix should be enabled [Address 02h, Bit 3], the
output should be set to RGB [Address 02h, Bit 5], sync on PrPb
should be disabled [Address 15h, Bit 2], and sync on RGB is
optional [Address 02h, Bit 4].

GY at address 03h and 05h control the output levels on the green
signal, BU at 04h and 08h the blue signal output levels and RV
at 04h and 09h the red output levels. To control YPrPb output
levels, YUV output should be enabled [Address 02h, Bit 5]. In
this case GY [Address 05h; Address 03, Bit 0-1] is used for the
Y output, RV [Address 09; Address 04, Bit 0-1] is used for the
Pr output, and BU [Address 08h; Address 04h, Bit 2-3] is used
for the Pb output.

If RGB output is selected the RGB matrix scaler uses the
following equations:

GGYYGUPb GV Pr

=×+×+×

BGYY BU Pb

=×+×

RGYY RV Pr

=×+×

If YPrPb output is selected the following equations are used:

YGYY

=×

UBUPb

=×

VRVPr

=×

On power-up, the RGB matrix is programmed with the default
values below.

Table IX. RGB Matrix Default Values

Address Default

03h 03h
04h F0h
05h 4Eh
06h 0Eh
07h 24h
08h 92h
09h 7Ch

When the programmable RGB matrix is not enabled, the
ADV7310/ADV7311 automatically scales YCrCb inputs to
all standards supported by this part.

SD Luma and Color Control
[Subaddress 5Ch, 5Dh, 5Eh, 5Fh]

SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit
wide control registers to scale the Y, U, and V output levels.

Each of these registers represents the value required to scale the
U or V level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of
its initial level. The value of these 10 bits is calculated using the
following equation:

Y, U, or V ScalarValue Scale Factor=×512

For example:

Scale Factor = 1.18

Y, U, or V Scale Value

Y, U, or V Scale Value (rounded to the nearest integer)

Y, U, or V Scale Value b

Address 5Ch, SD LSB Register = 15h
Address 5Dh, SD Y Scale Register = A6h
Address 5Eh, SD V Scale Register = A6h
Address 5Fh, SD U Scale Register = A6h

=×=

1.18 512 665.6

=

665

=

1010 0110 01

ADV7310/ADV7311

SD Hue Adjust Value
[Subaddress 60h]

The hue adjust value is used to adjust the hue on the composite
and chroma outputs.

These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during
the color burst. The ADV7310/ADV7311 provides a range of

o

22.5

increments of 0.17578125o. For normal operation (zero
adjustment), this register is set to 80h. FFh and 00h represent the
upper and lower limits (respectively) of adjustment attainable.

(Hue Adjust) [

o

] = 0.17578125o × (HCRd – 128), for positive

hue adjust value.

For example, to adjust the hue by +4

o

, write 97h to the Hue

Adjust Value register:

4





0 17578125

.

*rounded to the nearest integer



128 105 97

+= =dh




*

To adjust the hue by –4o, write 69h to the Hue Adjust Value
register:

−

4





0 17578125

.

*rounded to the nearest integer

SD Brightness Control
[Subaddress 61h]



128 105 69

+= =




*dh

The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0IRE to 22.5IRE. For NTSC without pedestal and
PAL, the setup can vary from –7.5IRE to +15IRE.

The brightness control register is an 8-bit register. Seven bits of
this 8-bit register are used to control the brightness level. This
brightness level can be a positive or negative value.

For example:
Standard: NTSC with Pedestal.
To add +20IRE brightness level, write 28h to Address 61h,
SD brightness.

Standard: PAL.
To add –7IRE brightness level, write 72h to Address 61h,
SD brightness.

IREValue

[]

7 2.015631 14.109417 0001110

×

[]

0001110 1110010 72

[]=[]

2.015631

×

=

[]

=

=

b

into twos complement b h

Table X. Brightness Control Values*

=

Setup Setup
Level In Level In Setup
NTSC with NTSC No Level In SD
Pedestal Pedestal PAL Brightness

22.5 IRE 15 IRE 15 IRE 1Eh
15 IRE 7.5 IRE 7.5 IRE 0Fh

7.5 IRE 0 IRE 0 IRE 00h
0 IRE –7.5 IRE –7.5 IRE 71h

*Values in the range from 3Fh to 44h might result in an invalid output signal.

SD Brightness Detect
[Subaddress 7Ah]

The ADV7310/ADV7311 allow monitoring of the brightness
level of the incoming video data. Brightness detect is a read-only
register.

Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]

Double buffered registers are updated once per field on the
falling edge of the VSYNC signal. Double buffering improves
the overall performance since modifications to register settings
will not be made during active video, but take effect on the start
of the active video.

Double buffering can be activated on the following HD registers:
HD Gamma A and Gamma B curves and HD CGMS registers.

Double buffering can be activated on the following SD registers:
SD Gamma A and Gamma B curves, SD Y Scale, SD U Scale,
SD V Scale, SD Brightness, SD Closed Captioning, and
SD Macrovision Bits 5–0.

SD BrightnessValue

[]

IREValue

[]

20 2.015631 40.31262 28

×

[]

2.015631

×

h

=

h

=

hh

=

[]

NTSC WITHOUT PEDESTAL

100 IRE

0 IRE

=

h

NO SETUP

VALUE ADDED

Figure 39. Examples of Brightness Control Values

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

+7.5 IRE

–7.5 IRE

REV. A–46–

ADV7310/ADV7311

PROGRAMMABLE DAC GAIN CONTROL

DACs A, B, and C are controlled by REG 0A.
DACs D, E, and F are controlled by REG 0B.

2

C control registers will adjust the output signal gain up or

The I
down from its absolute level.

CASE A

GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0Ah, 0Bh

700mV

300mV

CASE B

700mV

300mV

NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0Ah, 0Bh

Figure 40. Programmable DAC Gain—Positive and
Negative Gain

In case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the signal
is increased from the reference signal.

In case B, the video output signal is reduced. The absolute level
of the sync tip and blanking level both decrease with respect to
the reference video output signal. The overall gain of the signal
is reduced from the reference signal.

The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of
the DAC is 4.33 mA, the DAC tune feature can change this
output current from 4.008 mA (–7.5%) to 4.658 mA (+7.5%).

The reset value of the vid_out_ctrl registers is 00h → nominal
DAC output current. The following table is an example of how
the output current of the DACs varies for a nominal 4.33 mA
output current.

Table XI.

DAC
Current

Reg 0Ah or 0Bh (mA) % Gain

0100 0000 (40h) 4.658 7.5000%
0011 1111 (3Fh) 4.653 7.3820%
0011 1110 (3Eh) 4.648 7.3640%

... ... ...

... ... ...

0000 0010 (02h) 4.43 0.0360%
0000 0001 (01h) 4.38 0.0180%
0000 0000 (00h) 4.33 0.0000% (I

2

C Reset Value,

Nominal)
1111 1111 (FFh) 4.25 –0.0180%
1111 1110 (FEh) 4.23 –0.0360%

... ... ...

... ... ...

1100 0010 (C2h) 4.018 –7.3640%
1100 0001 (C1h) 4.013 –7.3820%
1100 0000 (C0h) 4.008 –7.5000%

REV. A

–47–

ADV7310/ADV7311

Gamma Correction
[Subaddress 24h–37h for HD, Subaddress 66h–79h for SD]

Gamma correction is available for SD and HD video. For each
standard, there are twenty 8-bit wide registers. They are used to
program the gamma correction curves A and B. HD gamma
curve A is programmed at Addresses 24h to 2Dh, HD gamma
curve B at 2Eh to 7h. SD gamma curve A is programmed at
Addresses 66h to 6Fh, and SD gamma curve B at Addresses
70h to 79h.

Generally gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wherever
nonlinear processing is used.

Gamma correction uses the function

Signal Signal

=

()

OUT IN

γ

where  = gamma power factor.

Gamma correction is performed on the luma data only. The user
may choose either of two different curves, curve A or curve B.
At any one time, only one of these curves can be used.

The response of the curve is programmed at 10 predefined loca­tions. In changing the values at these locations, the gamma curve
can be modified. Between these points, linear interpolation is
used to generate intermediate values. Considering the curve to
have a total length of 256 points, the 10 locations are at 24, 32,
48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240,
and 255 are fixed and cannot be changed.

For the length of 16 to 240, the gamma correction curve has to
be calculated as follows:

γ

yx=

where:

y = gamma corrected output
x = linear input signal



= gamma power factor

To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:



y

x

=



n

240 16

()





n

−( 16)

−



240 16 16

×−

()






+

where:

x

= Value for x along x axis at points

(n – 16)

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224

y

= Value for y along the y axis, which has to be written into

n

the gamma correction register

For example:

y

= [(8 / 224)

24

= [(16 / 224)

y

32

y

= [(32 / 224)

48

= [(48 / 224)

y

64

= [(64 / 224)

y

80

= [(80 / 224)

y

96

y

= [(112 / 224)

128

= [(144 / 224)

y

160

= [(176 / 224)

y

192

y

= [(208 / 224)

*rounded to the nearest integer

224

0.5

× 224] + 16 = 58*

0.5

× 224] + 16 = 76*

0.5

× 224] + 16 = 101*

0.5

× 224] + 16 =120*

0.5

× 224] + 16 =136*

0.5

× 224] + 16 = 150*

0.5

× 224] + 16 = 174*

0.5

× 224] + 16 = 195*

0.5

× 224] + 16 = 214*

0.5

× 224] + 16 = 232*

The gamma curves in Figures 46 and 47 are examples only; any
user defined curve is acceptable in the range of 16 to 240.

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

300

250

200

150

100

GAMMA CORRECTED AMPLITUDE

50

0

0

SIGNAL INPUT

50 100 150 200 250

SIGNAL OUTPUT

0.5

LOCATION

Figure 41. Signal Input (Ramp) and Signal Output
for Gamma 0.5

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

300

250

200

150

100

GAMMA CORRECTED AMPLITUDE

50

0

0

VARIOUS GAMMA VALUES

0.3

0.5

1.5

SIGNAL INPUT

50 100 150 200 250

1.8

LOCATION

Figure 42. Signal Input (Ramp) and Selectable
Output Curves

REV. A–48–

ADV7310/ADV7311

HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL

[Subaddress 20h, 38h–3Dh]

There are three filter modes available on the ADV7310/ADV7311:
sharpness filter mode and two adaptive filter modes.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges
shown in the figures below, the following register settings must
be used: HD sharpness filter must be enabled and HD adaptive
filter enable must be set to disabled.

To select one of the 256 individual responses, the according
gain values for each filter, which range from –8 to +7, must
be programmed into the HD sharpness filter gain register at
Address 20h.

HD Adaptive Filter Mode

The HD adaptive filter threshold A, B, C registers, the HD
adaptive filter gain 1, 2, 3 registers, and the HD sharpness gain
register are used in adaptive filter mode. To activate the adaptive
filter control, the HD sharpness filter must be enabled and HD
adaptive filter enable must be enabled.

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

FREQUENCY (MHz)

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5

FILTER B RESPONSE (Gain Kb)

INPUT

SIGNAL:

STEP

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5

FILTER A RESPONSE (Gain Ka)

Figure 43. Sharpness and Adaptive Filter Control Block

The derivative of the incoming signal is compared to the three pro­grammable threshold values: HD adaptive filter threshold A, B, C.
The recommended threshold range is from 16 to 235 although
any value in the range of 0 to 255 can be used.

The edges can then be attenuated with the settings in HD adap­tive filter gain 1, 2, 3 registers and HD sharpness filter gain
register.

According to the settings of the HD adaptive filter mode control,
there are two adaptive filter modes available:

1. Mode A is used when adaptive filter mode is set to 0. In this

case, Filter B (LPF) will be used in the adaptive filter block.
Also, only the programmed values for Gain B in the HD sharp­ness filter gain, HD adaptive filter gain 1, 2, 3 are applied when
needed. The Gain A values are fixed and cannot be changed.

2. Mode B is used when adaptive filter mode is set to 1. In this

mode, a cascade of Filter A and Filter B is used. Both set­tings for Gain A and Gain B in the HD sharpness filter gain,
HD adaptive filter gain 1, 2, 3 become active when needed.

1.6

1.5

1.4

1.3

1.2

1.1

MAGNITUDE RESPONSE (Linear Scale)

1.0

FREQUENCY (MHz)

024681012

FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7

FREQUENCY (MHz)

REV. A

–49–

ADV7310/ADV7311

HD Sharpness Filter and Adaptive Filter Application Examples

HD Sharpness Filter Application

The HD sharpness filter can be used to enhance or attenuate
the Y video output signal. The following register settings were
used to achieve the results shown in the figures below. Input
data was generated by an external signal source.

Table XII.

Address Register Setting Reference*

00h FCh
01h 10h
02h 20h
10h 00h
11h 81h
20h 00h a
20h 08h b
20h 04h c
20h 40h d
20h 80h e
20h 22h f

*See Figure 44.

The effect of the sharpness filter can also be seen when using
the internally generated cross hatch pattern.

Table XIII.

Address Register Setting

00h FCh
01h 10h
02h 20h
10h 00h
11h 85h
20h 99h

d

e

f

R2

R4

1

CH1 500mV M 4.00s CH1

REF A 500mV 4.00s 1 9.99978ms

ALL FIELDS

a

1

b

R1

c

R2

CH1 500mV M 4.00s CH1

REF A 500mV 4.00s 1 9.99978ms

ALL FIELDS

Figure 44. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value

REV. A–50–

ADV7310/ADV7311

Adaptive Filter Control Application

Figures 45 and 46 show typical signals to be processed by the
adaptive filter control block.

: 692mV
@: 446mV

: 332ns
@: 12.8ms

Figure 45. Input Signal to Adaptive Filter Control

: 692mV
@: 446mV

: 332ns
@: 12.8ms

Figure 46. Output Signal after Adaptive Filter Control

The following register settings were used to obtain the results
shown in Figure 46, i.e., to remove the ringing on the Y signal.

Input data was generated by an external signal source.

When changing the adaptive filter mode to Mode B [Address 15h,
Bit 6], the following output can be obtained:

: 674mV
@: 446mV

: 332ns
@: 12.8ms

Figure 47. Output Signal from Adaptive Filter Control

The adaptive filter control can also be demonstrated using the
internally generated cross hatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].

Table XV.

Address Register Setting

00h FCh
01h 38h
02h 20h
10h 00h
11h 85h
15h 80h
20h 00h
38h ACh
39h 9Ah
3Ah 88h
3Bh 28h
3Ch 3Fh
3Dh 64h

REV. A

Table XIV.

Address Register Setting

00h FCh
01h 38h
02h 20h
10h 00h
11h 81h
15h 80h
20h 00h
38h ACh
39h 9Ah
3Ah 88h
3Bh 28h
3Ch 3Fh
3Dh 64h

All other registers are set as normal/default.

–51–

ADV7310/ADV7311

SD Digital Noise Reduction
[Subaddress 63h, 64h, 65h]

DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
[DNR input select]. The absolute value of the filter output is
compared to a programmable threshold value ['DNR threshold
control]. There are two DNR modes available: DNR mode and
DNR sharpness mode.

In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount [coring gain border, coring gain data] of this noise
signal will be subtracted from the original signal. In DNR sharp­ness mode, if the absolute value of the filter output is less than
the programmed threshold, it is assumed to be noise, as before.
Otherwise, if the level exceeds the threshold, now being identi­fied as a valid signal, a fraction of the signal [coring gain border,
coring gain data] will be added to the original signal in order to
boost high frequency components and sharpen the video image.

In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels ×
16 pixels for MPEG1 systems [block size control]. DNR can be
applied to the resulting block transition areas that are known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels [bor­der area].

It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the [DNR
block offset].

The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.

Y DATA

INPUT

Y DATA

INPUT

DNR MODE

NOISE
SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR
SHARPNESS
MODE

NOISE
SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA
BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

< THRESHOLD?

FILTER OUTPUT

> THRESHOLD

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

> THRESHOLD?

FILTER OUTPUT

< THRESHOLD

Figure 48. DNR Block Diagram

SUBTRACT SIGNAL
IN THRESHOLD
RANGE FROM
ORIGINAL SIGNAL

–

+

DNR OUT

ADD SIGNAL
ABOVE THRESHOLD
RANGE FROM
ORIGINAL SIGNAL

+

+

DNR OUT

REV. A–52–

ADV7310/ADV7311

Coring Gain Border
[Address 63h, Bits 3–0]

These four bits are assigned to the gain factor applied to
border areas.

In DNR mode, the range of gain values is 0 to 1 in increments
of 1/8. This factor is applied to the DNR filter output, which
lies below the set threshold range. The result is then subtracted
from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range.

The result is added to the original signal.

Coring Gain Data
[Address 63h, Bits 7–4]

These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.

In DNR mode, the range of gain values is 0 to 1 in increments
of 1/8. This factor is applied to the DNR filter output, which
lies below the set threshold range. The result is then subtracted
from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range.

The result is added to the original signal.

APPLY BORDER
CORING GAIN

OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING

DNR27 – DNR24 = 01h

APPLY DATA
CORING GAIN

OXXXXXXOOXXXXXXO

OXXXXXXOOXXXXXXO

OXXXXXXOOXXXXXXO

Figure 49. DNR Offset Control

DNR Threshold
[Address 64h, Bits 5–0]

These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.

Border Area
[Address 64h, Bit 6]

When this bit is set to a Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to a Logic 0,
the border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.

720485 PIXELS

(NTSC)

2-PIXEL

BORDER

DATA

Block Size Control
[Address 64h, Bit 7]

This bit is used to select the size of the data blocks to be pro­cessed. Setting the block size control function to a Logic 1 defines
a 16 pixel × 16 pixel data block, and a Logic 0 defines an 8 pixel ×
8 pixel data block, where one pixel refers to two clock cycles
at 27 MHz.

DNR Input Select Control
[Address 65h, Bit 2–0]

Three bits are assigned to select the filter, which is applied to
the incoming Y data. The signal that lies in the pass band of
the selected filter is the signal that will be DNR processed.
Figure 51 shows the filter responses selectable with this control.

1.0
FILTER D

0.8

FILTER C

0.6

MAGNITUDE

0.4

0.2

0

012 3456

FILTER B

FILTER A

FREQUENCY (Hz)

Figure 51. DNR Input Select

DNR Mode Control
[Address 65h, Bit 4]

This bit controls the DNR mode selected. A Logic 0 selects
DNR mode; a Logic 1 selects DNR sharpness mode.

DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.

When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using Extended SSAF filter).

Block Offset Control
[Address 65h, Bits 7–4]

Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain posi­tions fixed. The block offset shifts the data in steps of one pixel
such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.

REV. A

88 PIXEL BLOCK 88 PIXEL BLOCK

Figure 50. DNR Border Area

–53–

ADV7310/ADV7311

SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]

When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the luma channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are ×1/8, ×1/2, and × 7/8.
All other active video passes through unprocessed.

LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED

100 IRE

0 IRE

Figure 52. Example of Active Video Edge Functionality

VOLTS

IRE:FLT

100

0.5

SAV/EAV Step Edge Control

The ADV7310/ADV7311 has the capability of controlling fast
rising and falling signals at the start and end of active video to
minimize ringing.

An algorithm monitors SAV and EAV and governs when the
edges are too fast. The result will be reduced ringing at the start
and end of active video for fast transitions.

Subaddress 0x42, Bit 7 = 1 enables this feature.

LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED

100 IRE

87.5 IRE

50 IRE

12.5 IRE
0 IRE

50

0

024

0

–50

Figure 53. Address 0x42, Bit 7 = 0

VOLTS

0.5

IRE:FLT

100

50

0

0

F2
L135

681012

F2

–50

02–2 4 6 8 10 12

L135

Figure 54. Address 0x42, Bit 7 = 1

REV. A–54–

ADV7310/ADV7311

BOARD DESIGN AND LAYOUT CONSIDERATIONS
DAC Termination and Layout Considerations

The ADV7310/ADV7311 contain an on-board voltage reference.
The ADV7310/ADV7311 can be used with an external V

REF

(AD1580).

The R

resistors are connected between the R

SET

pins and

SET

AGND and are used to control the full-scale output current and
therefore the DAC voltage output levels. For full-scale output,

must have a value of 3040 Ω. The R

R

SET

be changed. R

has a value of 300 Ω for full-scale output.

LOAD

values should not

SET

Video Output Buffer and Optional Output Filter

Output buffering on all six DACs is necessary in order to drive
output devices, such as SD or HD monitors. Analog Devices
produces a range of suitable op amps for this application, for
example the AD8061. More information on line driver buffering
circuits is given in the relevant op amps’ data sheets.

An optional analog reconstruction low-pass filter (LPF) may be
required as an anti-imaging filter if the ADV7310/ADV7311 is
connected to a device that requires this filtering.

The filter specifications vary with the application.

Table XVI. External Filter Requirements

Cutoff
Frequency Attenuation

Application Oversampling (MHz) –50 dB @ (MHz)

SD 2× >6.5 20.5
SD 16× >6.5 209.5
PS 1× >12.5 14.5
PS 8× >12.5 203.5
HDTV 1× >30 44.25
HDTV 2× >30 118.5

DAC

OUTPUT

10H

22pF600

600

3

4

560

1

560

Figure 55. Example of Output Filter for SD,

×

Oversampling

16

0

–10

–20

–30

–40

GAIN (dB)

–50

GROUP DELAY (sec)

–60

–70

–80

1M 10M 100M

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

PHASE (Deg)

FREQUENCY (Hz)

Figure 56. Filter Plot for Output Filter for SD,
16× Oversampling

75

BNC
OUTPUT

0

–30

–60

–90

–120

–150

–180

–210

–240

1G

24n

21n

18n

15n

12n

9n

6n

3n

0

REV. A

–55–

ADV7310/ADV7311

DAC

OUTPUT

4.7H

6.8pF 600

6.8pF600

3

4

560

560

75

1

BNC
OUTPUT

Figure 57. Example of Output Filter for PS,

×

Oversampling

8

DAC
OUTPUT

300

3

4

75

1

220nH470nH

82pF33pF

75

3

4

500

500

1

BNC

OUTPUT

Figure 58. Example of Output Filter for HDTV,
2× Oversampling

Table XVII. Possible Output Rates From the ADV7310/ADV7311

Input Mode PLL Output
Address 01h, Bit 6–4 Address 00h, Bit 1 Rate (MHz)

SD Only Off 27 (2×)

On 216 (16×)

PS Only Off 27 (1×)

On 216 (8×)

HDTV Only Off 74.25 (1×)

On 148.5 (2×)

0

–10

–20

–30

GROUP DELAY (Sec)

–40

–50

GAIN (dB)

–60

–70

–80

–90

1M 10M 100M 1G

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

PHASE (Deg)

FREQUENCY (Hz)

Figure 59. Filter Plot for Output Filter for PS,
8

×

Oversampling

0

–10

–20

GROUP DELAY (sec)

–30

GAIN (dB)

–40

PHASE (Deg)

–50

–60

1M 10M 100M 1G

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

FREQUENCY (Hz)

480

400

320

240

160

80

0

–80

–160

–240

480

360

240

120

0

–120

–240

18n

16n

14n

12n

10n

8n

6n

4n

2n

0

18n

15n

12n

9n

6n

3n

0

Figure 60. Filter Plot for Output Filter for HDTV,
2× Oversampling

REV. A–56–

ADV7310/ADV7311

PCB Board Layout Considerations

The ADV7310/ADV7311 are optimally designed for lowest noise
performance, both radiated and conducted noise. To complement
the excellent noise performance of the ADV7310/ADV7311, it
is imperative that great care be given to the PC board layout.

The layout should be optimized for lowest noise on the ADV7310/
ADV7311 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
The lead length between groups of V
DGND, and V

and GND_IO pins should be kept as short

DD_IO

and AGND, VDD and

AA

as possible to minimized inductive ringing.

It is recommended that a 4-layer printed circuit board is used,
with power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Com­ponent placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.

There should be a separate analog ground plane and a separate
digital ground plane.

Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, V

circuitry. The digital

REF

power plane should contain all logic circuitry.

The analog and digital power planes should be individually
connected to the common power plane at a single point through
a suitable filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termina­tion resistors should be placed as close as possible to the DAC
outputs and should overlay the PCB’s ground plane. As well as
minimizing reflections, short analog output traces will reduce
noise pickup due to neighboring digital circuitry.

To avoid crosstalk between the DAC outputs, it is recommended
that as much space as possible be left between the tracks of the
individual DAC output pins. The addition of ground tracks
between outputs is also recommended.

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.

Optimum performance is achieved by the use of 10 nF and

0.1 µF ceramic capacitors. Each group of V

, VDD, or V

AA

DD_IO

pins should be individually decoupled to ground. This should
be done by placing the capacitors as close as possible to the
device with the capacitor leads as short as possible, thus mini­mizing lead inductance.

A 1 µF tantalum capacitor is recommended across the V

AA

supply in addition to 10 nF ceramic.

See the circuit layout in Figure 61.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.

Due to the high clock rates used, long clock lines to the
ADV7310/ADV7311 should be avoided to minimize noise
pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not the
analog power plane.

Analog Signal Interconnect

The ADV7310/ADV7311 should be located as close as possible
to the output connectors, thus minimizing noise pickup and
reflections due to impedance mismatch.

For optimum performance, the analog outputs should each
be source and load terminated, as shown in Figure 61. The
termination resistors should be as close as possible to the
ADV7310/ADV7311 to minimize reflections.

For optimum performance, it is recommended that all decoupling
and external components relating to the ADV7310/ADV7311
be located on the same side of the PCB and as close as possible
to the ADV7310/ADV7311.

Any unused inputs should be tied to ground.

REV. A

–57–

ADV7310/ADV7311

5k

UNUSED

INPUTS
SHOULD BE
GROUNDED

V

AA

4.7k

+

4.7F

V

AA

680

820pF

V

V

AA

0.1F

DD_IO

COMP1, 245V

19

I2C

S0–S9

50

S_HSYNC

49

S_VSYNC

48

S_BLANK

C0–C9

Y0–Y9

63

CLKIN_B

23

P_HSYNC

24

P_VSYNC

25

P_BLANK

33

RESET

32

CLKIN_A

34

EXT_LF

3.9nF

GND_ IO64AGND40DGND

V

AA

0.1F

36

ADV7310/

ADV7311

POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP

10nF 1F

10nF 0.1F

10, 56

41

AA

VDDV

1

DD_IO

V

REF

DAC A

10nF 0.1F

46

44

300

43

DAC B

300

42

DAC C

300

39

DAC D

300

38

DAC E

300

37

DAC F

300

SCLK

SDA

ALSB

R

SET2

R

SET1

22

21

20

35

47

100

100

3040

3040

11, 57

V

V

V

AA

DD

DD_IO

V

AA

+

1.1k

RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE

2

C BUS

I

V

DD_IO

100nF

5k

V

V

DD_IO

DD_IO

5k

5k

SELECTION HERE
DETERMINES
DEVICE ADDRESS

Figure 61. ADV7310/ADV7311 Circuit Layout

REV. A–58–

ADV7310/ADV7311

APPENDIX 1—COPY GENERATION
MANAGEMENT SYSTEM
PS CGMS Data Registers 2–0
[Subaddress 21h, 22h, 23h]

PS CGMS is available in 525p mode conforming to CGMS-A
EIA-J CPR1204-1, transfer method of video ID information using
vertical blanking interval (525p system), March 1998, and
IEC61880, 1998, Video systems (525/60)—video and accom­panied data using the vertical blanking interval—analog interface.

When PS CGMS is enabled [Subaddress 12h, Bit 6 = 1], CGMS
data is inserted on line 41. The PS CGMS data registers are at
Addresses 21h, 22h, and 23h.

SD CGMS Data Registers 2–0
[Subaddress 59h, 5Ah, 5Bh]

The ADV7310/ADV7311 supports Copy Generation Manage­ment System (CGMS), conforming to the standard. CGMS
data is transmitted on Line 20 of the odd fields and Line 283 of
even fields. Bits C/W05 and C/W06 control whether or not
CGMS data is output on odd and even fields. CGMS data can
be transmitted only when the ADV7310/ADV7311 is configured
in NTSC mode. The CGMS data is 20 bits long, and the func­tion of each of these bits is as shown in the following table. The
CGMS data is preceded by a reference pulse of the same ampli­tude and duration as a CGMS bit; see Figure 63.

HD/PS CGMS [Address 12h, Bit 6]

The ADV7310/ADV7311 supports Copy Generation Management
System (CGMS) in HDTV mode (720p and 1080i) in accor­dance with EIAJ CPR-1204-2.

The HD CGMS data registers are to be found at address 021h,
22h, 23h.

Function of CGMS Bits

Word 0–6 bits; Word 1–4 bits; Word 2–6 bits; CRC 6 bits CRC
polynomial = x

720p System

6

+ x + 1 (preset to 111111)

CGMS data is applied to Line 24 of the luminance vertical
blanking interval.

1080i System

CGMS data is applied to Line 19 and on Line 582 of the lumi­nance vertical blanking interval.

CGMS Functionality

If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC
[Subaddress 12h, Bit 7] is set to a Logic 1, the last six bits,
C19–C14, which comprise the 6-bit CRC check sequence, are
calculated automatically on the ADV7310/ADV7311 based on
the lower 14 bits (C0–C13) of the data in the data registers and
output with the remaining 14 bits to form the complete 20 bits
of the CGMS data. The calculation of the CRC sequence is
based on the polynomial x

6

+ x + 1 with a preset value of 111111.
If SD CGMS CRC [Address 59h, Bit 4] and PS/HD CGMS
CRC [Address 12h, Bit 7] is set to a Logic 0, all 20 bits (C0–C19)
are output directly from the CGMS registers (no CRC is calcu­lated, must be calculated by the user).

Table XVIII.

Bit Function

WORD0 1 0
B1 Aspect ratio 16:9 4:3
B2 Display format Letterbox Normal
B3 Undefined

WORD0
B4, B5, B6 Identification information about video

and other signals (e.g., audio)

WORD1
B7, B8, B9, B10 Identification signal incidental to Word 0

WORD2
B11, B12, B13, B14 Identification signal and information

incidental to Word 0

REV. A

–59–

ADV7310/ADV7311

+700mV

70% 10%

0mV

–300mV

5.8s 0.15s
6T

REF

BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

21.2s 0.22s
22T

Figure 62. Progressive Scan CGMS Waveform

CRC SEQUENCE

T = 1/(fH  33) = 963ns

f

= HORIZONTAL SCAN FREQUENCY

H

T 30ns

+700mV

70% 10%

0mV

–300mV

+100 IRE

+70 IRE

0 IRE

–40 IRE

11.2s

4T

3.128s 90ns

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

49.1s 0.5s

2.235s 20ns

Figure 63. Standard Definition CGMS Waveform Diagram

CRC SEQUENCE

REF

BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

T 30ns

17.2s 160ns
22 T

1H

T = 1/(f

 1650/58) = 781.93ns

H

= HORIZONTAL SCAN FREQUENCY

f

H

Figure 64. HDTV 720p CGMS Waveform

CRC SEQUENCE

+700mV

70% 10%

0mV

–300mV

4T

4.15s 60ns

CRC SEQUENCE

REF

BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

T 30ns

22.84s 210ns
22 T

1H

T = 1/(f

 2200/77) = 1.038s

H

= HORIZONTAL SCAN FREQUENCY

f

H

Figure 65. HDTV 1080i CGMS Waveform

REV. A–60–

ADV7310/ADV7311

APPENDIX 2—SD WIDE SCREEN SIGNALING
[Subaddress 59h, 5Ah, 5Bh]

The ADV7310/ADV7311 support wide screen signaling (WSS)
conforming to the standard. WSS data is transmitted on Line 23.
WSS data can be transmitted only when the device is configured
in PAL mode. The WSS data is 14 bits long, and the function
of each of these bits is shown in Table XIX. The WSS data is

Table XIX. Function of WSS Bits

Bit Description

Bit 0–Bit 2 Aspect Ratio/Format/Position

Bit 3 Odd Parity Check of Bit 0 to Bit 2

B0, B1, B2, B3 Aspect Ratio Format Position
00014:3 Full Format N/A
100014:9 Letterbox Center
010014:9 Letterbox Top
110116:9 Letterbox Center
001016:9 Letterbox Top
1011>16:9 Letterbox Center
011114:9 Full Format Center
111016:9 N/A N/A
111016:9

B4
0Camera Mode
1Film Mode

preceded by a run-in sequence and a start code; see Figure 66.
If SD WSS [Address 59h, Bit 7] is set to a Logic 1, it enables the
WSS data to be transmitted on Line 23. The latter portion of
Line 23 (42.5 µs from the falling edge of HSYNC) is available for
the insertion of video.

It is possible to blank the WSS portion of Line 23 with
Subaddress 61h, Bit 7.

Bit Description

B5
0 Standard Coding
1Motion Adaptive Color Plus

B6
0No Helper
1Modulated Helper

B7 Reserved

B9 B10
0 0 No Open Subtitles
1 0 Subtitles in Active Image Area
0 1 Subtitles out of Active Image Area
1 1 Reserved

B11
0No Surround Sound Information
1 Surround Sound Mode

B12 Reserved

B13 Reserved

500mV

11.0s

RUN-IN

SEQUENCE

START

CODE

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10

38.4s

42.5s

Figure 66. WSS Waveform Diagram

W11 W12 W13

ACTIVE

VIDEO

REV. A

–61–

ADV7310/ADV7311

APPENDIX 3—SD CLOSED CAPTIONING
[Subaddress 51h–54h]

The ADV7310/ADV7311 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the blanked
active line time of Line 21 of the odd fields and Line 284 of the
even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic 1 start bit. Sixteen bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits, and
one odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Address 53h–54h].

The ADV7310/ADV7311 also support the extended closed
captioning operation, which is active during even fields and is
encoded on Scan Line 284. The data for this operation is stored
in the SD closed captioning registers [Address 51h–52h].

All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7310/

10.5  0.25s 12.91s

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

50 IRE

40 IRE

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F

AMPLITUDE = 40 IRE

SC

10.003s

= 3.579545MHz

27.382s 33.764s

ADV7311. All pixels inputs are ignored during Lines 21 and
284 if closed captioning is enabled.

FCC Code of Federal Regulations (CFR) 47 section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.

The ADV7310/ADV7311 use a single buffering method. This
means that the closed captioning buffer is only 1-byte deep;
therefore there will be no frame delay in outputting the closed
captioning data unlike other 2-byte deep buffering systems. The
data must be loaded one line before (Line 20 or Line 283) it is
output on Line 21 and Line 284. A typical implementation of this
method is to use VSYNC to interrupt a microprocessor, which
in turn will load the new data (two bytes) in every field. If no
new data is required for transmission, 0s must be inserted in
both data registers; this is called nulling. It is also important to
load control codes, all of which are double bytes on Line 21, or
a TV will not recognize them. If there is a message like “Hello
World” that has an odd number of characters, it is important to
pad it out to even in order to get “end of caption” 2-byte control
code to land in the same field.

TWO 7-BIT + PARITY
ASCII CHARACTERS

(DATA)

S
T

D0–D6 D0–D6

A
R
T

P
A
R

I
T
Y

P
A
R

I
T
Y

BYTE 1BYTE 0

Figure 67. Closed Captioning Waveform, NTSC

REV. A–62–

APPENDIX 4—TEST PATTERNS

The ADV7310/ADV7311 can generate SD and HD test patterns.

ADV7310/ADV7311

T

2

CH2 200mV M 10.0␮sA CH2 1.20V

T

30.6000␮s

Figure 68. NTSC Color Bars

T

2

CH2 100mV M 10.0␮s CH2 EVEN

T

1.82600ms

Figure 71. PAL Black Bar [–21 mV, 0 mV, 3.5 mV, 7
mV, 10.5 mV, 14 mV, 18 mV, 23 mV]

T

T

2

CH2 200mV M 10.0␮sA CH2 1.21V

T

30.6000␮s

Figure 69. PAL Color Bars

T

2

CH2 100mV M 10.0␮s CH2 EVEN

T

1.82380ms

Figure 70. NTSC Black Bar [–21 mV, 0 mV,

3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV]

2

CH2 200mV M 4.0␮s CH2 EVEN

Figure 72. 525p Hatch Pattern

T

2

CH2 200mV M 4.0␮s CH2 EVEN

Figure 73. 625p Hatch Pattern

T

T

1.82944ms

1.84208ms

REV. A

–63–

ADV7310/ADV7311

T

2

CH2 200mV M 4.0s CH2 EVEN

T

1.82872ms

Figure 74. 525p Field Pattern

T

2

CH2 100mV M 4.0s CH2 EVEN

T

1.82936ms

Figure 76. 525p Black Bar [–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV]

T

T

2

CH2 200mV M 4.0s CH2 EVEN

T

1.84176ms

Figure 75. 625p Field Pattern

2

CH2 100mV M 4.0s CH2 EVEN

T

1.84176ms

Figure 77. 625p Black Bar [–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV]

REV. A–64–

ADV7310/ADV7311

The following register settings are used to generate an SD NTSC
CVBS output on DAC A:

Register

Subaddress Setting

00h 80h
40h 10h
42h 40h
44h 40h
4Ah 08h

All other registers are set as normal/default.

For PAL CVBS output on DAC A, the same settings are used
except that subaddress = 40h and register setting = 11h.

The following register settings are used to generate an SD NTSC
black bar pattern output on DAC A:

Register

Subaddress Setting

00h 80h
02h 04h
40h 10h
42h 40h
44h 40h
4Ah 08h

All other registers are set as normal/default.

For PAL black bar pattern output on DAC A, the same settings
are used except that subaddress = 40h and register setting = 11h.

The following register settings are used to generate a 525p hatch
pattern on DAC D:

Register

Subaddress Setting

00h 10h
01h 10h
10h 40h
11h 05h
16h A0h
17h 80h
18h 80h

All other registers are set as normal/default.

For 625p hatch pattern on DAC D, the same register settings
are used except that subaddress = 10h and register setting = 50h.

For a 525p black bar pattern output on DAC D, the same settings
are used as above except that subaddress = 02h and register
setting = 24h.

For 625p black bar pattern output on DAC D, the same settings
are used as above except that subaddress = 02h and register
setting = 24h; and subaddress = 10h and register setting = 50h.

REV. A

–65–

ADV7310/ADV7311

APPENDIX 5—SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656)—Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7310/ADV7311 is controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchroniza­tion pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. S_VSYNC,
S_HSYNC, and S_BLANK (if not used) pins should be tied
high during this mode. Blank output is available.

ANALOG

VIDEO

INPUT PIXELS

NTSC /PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

EAV CODE

C

FF0000X

Y

Y

r

4 CLOCK

4 CLOCK

END OF ACTIVE

VIDEO LINE

8

10801

0

Y

0

FF00FFABABA

ANCILLARY DATA

268 CLOCK

280 CLOCK

B

(HANC)

Figure 78. SD Slave Mode 0

801

0

SAV CODE

8

10FF0

0

0

XYC

Y

0

0

b

4 CLOCK

4 CLOCK

START OF ACTIVE

VIDEO LINE

C

C

Y

Y

b

r

1440 CLOCK

1440 CLOCK

C

C

Y

b

r

REV. A–66–

Mode 0 (CCIR-656)—Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7310/ADV7311 generates H, V, and F signals required
for the SAV (start active video) and EAV (end active video)
time codes in the CCIR656 standard. The H bit is output on
the S_HSYNC, the V bit is output on S_BLANK, and the F bit
is output on S_VSYNC.

ADV7310/ADV7311

DISPLAY

522 523 524 525 1 2 3 4

H

V

F

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

H

V

F

EVEN FIELD

ODD FIELD

ODD FIELD

EVEN FIELD

VERTICAL BLANK

67

5

VERTICAL BLANK

9

8

Figure 79. SD Master Mode 0, NTSC

DISPLAY

10 11 20 21 22

283

284

285

DISPLAY

REV. A

DISPLAY

622 623 624 625 1 2 3 4

H

V

F

DISPLAY

309 310 311 312 314 315 316 317

H

V

F

EVEN FIELD

ODD FIELD

ODD FIELD

313

EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 80. SD Master Mode 0, PAL

–67–

5

67

318

319 320

DISPLAY

22 23

21

DISPLAY

335 336

334

ADV7310/ADV7311

H

B

ANALOG

VIDEO

H

F

V

Figure 81. SD Master Mode 0, Data Transitions

Mode 1—Slave Option
(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode, the ADV7310/ADV7311 accept horizontal sync
and odd/even field signals. A transition of the field input when

HSYNC is low indicates a new frame, i.e., vertical retrace. The
BLANK signal is optional. When the BLANK input is disabled,

the ADV7310/ADV7311 automatically blank all normally blank
lines as per CCIR-624. HSYNC is input on S_HSYNC, BLANK
on S_BLANK, and FIELD on S_VSYNC.

284

DISPLAY

DISPLAY

285

DISPLAY

522 523 524 525

SYNC

LANK

FIELD

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

HSYNC

BLANK

FIELD

1234

EVEN FIELD

ODD FIELD EVEN FIELD

ODD FIELD

VERTICAL BLANK

678

5

VERTICAL BLANK

9

10 11

20 21 22

283

Figure 82. SD Slave Mode 1 (NTSC)

REV. A–68–

Mode 1—Master Option

H

B

H

B

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7310/ADV7311 can generate horizontal
sync and odd/even field signals. A transition of the field input
when HSYNC is low indicates a new frame, i.e., vertical retrace.
The blank signal is optional. When the BLANK input is disabled,
the ADV7310/ADV7311 automatically blank all normally blank
lines as per CCIR-624. Pixel data is latched on the rising clock
edge following the timing signal transitions. HSYNC is output
on the S_HSYNC, BLANK on S_BLANK, and FIELD on
S_VSYNC.

ADV7310/ADV7311

HSYNC

BLANK

FIELD

SYNC

LANK

FIELD

DISPLAY

622 623 624 625 1234

EVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD

ODD FIELD

EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 83. SD Slave Mode 1 (PAL)

317

5

67

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

SYNC

FIELD

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

LANK

PIXEL

DATA

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Cb Y

Cr Y

Figure 84. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave

REV. A

–69–

ADV7310/ADV7311

H

B

H

B

Mode 2— Slave Option
(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode, the ADV7310/ADV7311 accepts horizontal and
vertical sync signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC
low transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7310/ADV7311 automatically blank all normally
blank lines as per CCIR-624. HSYNC is input S_HSYNC,
BLANK on S_BLANK, and VSYNC on S_VSYNC.

SYNC

LANK

VSYNC

HSYNC

BLANK

VSYNC

DISPLAY

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

EVEN FIELD

ODD FIELD

VERTICAL BLANK

678

5

ODD FIELD

VERTICAL BLANK

EVEN FIELD

9

10 11

Figure 85. SD Slave Mode 2 (NTSC)

DISPLAY

VERTICAL BLANK

20 21 22

DISPLAY

283

284

DISPLAY

DISPLAY

285

622 623 624 625 1234

HSYNC

BLANK

VSYNC

SYNC

LANK

VSYNC

DISPLAY

309 310 311 312 313 314 315 316

EVEN FIELD

ODD FIELD

ODD FIELD

VERTICAL BLANK

EVEN FIELD

Figure 86. SD Slave Mode 2 (PAL)

5

317

67

318 319

320

21 22 23

DISPLAY

334 335 336

REV. A–70–

Mode 2—Master Option

B

B

(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7310/ADV7311 can generate horizontal
and vertical sync signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field.
A VSYNC low transition when HSYNC is high indicates the
start of an even field. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7310/ADV7311 automati­cally blank all normally blank lines as per CCIR-624. HSYNC
is output on S_HSYNC , BLANK on S_BLANK, and VSYNC
on S_VSYNC.

HSYNC

VSYNC

PAL = 12  CLOCK/2

LANK

NTSC = 16  CLOCK/2

ADV7310/ADV7311

PIXEL
DATA

HSYNC

VSYNC

LANK

PIXEL

DATA

Cb Y Cr

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 87. SD Timing Mode 2 Even to Odd Field Transition Master/Slave

PAL = 864  CLOCK/2

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

NTSC = 858  CLOCK/2

Cb Y Cr Y Cb

Figure 88. SD Timing Mode 2 Odd to Even Field Transition Master/Slave

Y

REV. A

–71–

ADV7310/ADV7311

B

B

B

B

Mode 3—Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV7310/ADV7311 accept or generate horizon­tal sync and odd/even field signals. A transition of the field input
when HSYNC is high indicates a new frame, i.e., vertical retrace.
The BLANK signal is optional. When the BLANK input is dis­abled, the ADV7310/ADV7311 automatically blank all normally
blank lines as per CCIR-624. HSYNC is output in master mode
and input in slave mode on S_VSYNC, BLANK on S_BLANK,
and VSYNC on S_VSYNC.

HSYNC

LANK

FIELD

HSYNC

LANK

FIELD

284

DISPLAY

285

DISPLAY

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

VERTICAL BLANK

678

5

VERTICAL BLANK

9

10 11

20 21 22

283

Figure 89. SD Timing Mode 3 (NTSC)

DISPLAY

VERTICAL BLANK

DISPLAY

622 623 624 625 1234

HSYNC

LANK

FIELD

DISPLAY

309 310 311 312 313 314 315 316

HSYNC

LANK

FIELD

ODD FIELDEVEN FIELD

VERTICAL BLANK

ODD FIELDEVEN FIELD

5

317

67

318 319

320

21 22 23

DISPLAY

334 335 336

Figure 90. SD Timing Mode 3 (PAL)

REV. A–72–

APPENDIX 6—HD TIMING

P

P

ADV7310/ADV7311

DISPLAY

FIELD 1

P_VSYNC

_HSYNC

FIELD 2

P_VSYNC

_HSYNC

VERTICAL BLANKING INTERVAL

1124 1125 1 2 5 6 7 8

VERTICAL BLANKING INTERVAL

561 562 563 564 567 568 569 570

Figure 91. 1080i

43

566565

HSYNC

and

VSYNC

Input Timing

20 22 560

21

DISPLAY

584

583 585 1123

REV. A

–73–

ADV7310/ADV7311

APPENDIX 7—VIDEO OUTPUT LEVELS
HD YPrPb Output Levels

INPUT CODE

EIA-770.2, STANDARD FOR Y

940

64

EIA-770.2, STANDARD FOR Pr/Pb

960

512

64

OUTPUT VOLTAGE

700mV

300mV

OUTPUT VOLTAGE

700mV

Figure 92. EIA 770.2 Standard Output Signals
(525p/625p)

INPUT CODE

EIA-770.1, STANDARD FOR Y

940

OUTPUT VOLTAGE

782mV

INPUT CODE

EIA-770.3, STANDARD FOR Y

940

64

EIA-770.3, STANDARD FOR Pr/Pb

960

512

64

OUTPUT VOLTAGE

700mV

300mV

OUTPUT VOLTAGE

600mV

700mV

Figure 94. EIA 770.3 Standard Output Signals
(1080i, 720p)

INPUT CODE

1023

Y–OUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

714mV

64

286mV

EIA-770.1, STANDARD FOR Pr/Pb

960

512

64

OUTPUT VOLTAGE

700mV

Figure 93. EIA 770.1 Standard Output Signals
(525p/625p)

700mV

64

300mV

INPUT CODE

1023

64

Pr/Pb–OUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

700mV

300mV

Figure 95. Output Levels for Full Input Selection

REV. A–74–

RGB Output Levels

ADV7310/ADV7311

700mV

300mV

700mV

300mV

700mV

300mV

550mV

550mV

550mV

Figure 96. HD RGB Output Levels

700mV 550mV

700mV

300mV

700mV

300mV

700mV

300mV

550mV

550mV

550mV

Figure 98. SD RGB Output Levels—RGB Sync Disabled

700mV 550mV

300mV

0mV

700mV

300mV

0mV

700mV

300mV

0mV

550mV

550mV

Figure 97. HD RGB Output Levels—RGB Sync Enabled

300mV

0mV

700mV

300mV

0mV

700mV

300mV

0mV

550mV

550mV

Figure 99. SD RGB Output Levels—RGB Sync Enabled

REV. A

–75–

ADV7310/ADV7311

YUV Output Levels

WHiTE

YELLOW

CYAN

GREEN

280mV

MAGENTA

RED

332mV

BLUE

BLACK

WHITE

YELLOW

CYAN

GREEN

200mV

MAGENTA

RED

2150mV

BLUE

BLACK

220mV

160mV

60mV

Figure 100. U Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

280mV

220mV

160mV

60mV

110mV

MAGENTA

RED

332mV

110mV

BLUE

BLACK

1260mV

1000mV

140mV

Figure 103. U Levels—PAL

WHITE

YELLOW

CYAN

GREEN

300mV

MAGENTA

RED

900mV

BLUE

BLACK

Figure 101. U Levels—PAL

WHITE

YELLOW

CYAN

GREEN

200mV

1260mV

1000mV

140mV

Figure 102. U Levels—NTSC

MAGENTA

RED

2150mV

900mV

BLUE

BLACK

Figure 104. Y Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

MAGENTA

300mV

Figure 105. Y Levels—PAL

RED

BLUE

BLACK

REV. A–76–

ADV7310/ADV7311

VOLTS

0.5

APL = 44.5%
525 LINE NTSC
SLOW CLAMP TO 0.00V AT 6.72s

VOLTS

IRE:FLT

100

50

0

0

0.4

0

–50

10 20

IRE:FLT

50

F1
L76

30 40 50 60

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = A

FRAMES SELECTED 1 2

Figure 106. NTSC Color Bars 75%

0.2

0

–0.2

–0.4

0

NOISE REDUCTION: 15.05dB
APL NEEDS SYNC-SOURCE.
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

0

–50

F1
L76

10 20

30 40 50 60

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = B

Figure 107. NTSC Chroma

FRAMES SELECTED 1 2

REV. A

–77–

ADV7310/ADV7311

VOLTS

0.6

0.4

0.2

–0.2

NOISE REDUCTION: 15.05dB
APL = 44.3%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

VOLTS

0

IRE:FLT

50

0

0

F2
L238

10 20

30 40 50 60

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = SOURCE

Figure 108. NTSC Luma

FRAMES SELECTED 1 2

0.6

0.4

0.2

0

–0.2

L608

10020

NOISE REDUCTION: 0.00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

MICROSECONDS

30 40 50 60

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1 2 3 4

Figure 109. PAL Color Bars 75%

REV. A–78–

VOLTS

0.5

0

–0.5

ADV7310/ADV7311

L575

10 20

APL NEEDS SYNC-SOURCE.
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

VOLTS

0.5

0

L575

10020

APL NEEDS SYNC-SOURCE.
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s

30 40 50 60

MICROSECONDS NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

Figure 110. PAL Chroma

30 40 50 60 70

MICROSECONDS NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

Figure 111. PAL Luma

FRAMES SELECTED 1

FRAMES SELECTED 1

REV. A

–79–

ADV7310/ADV7311

APPENDIX 8—VIDEO STANDARDS

SMPTE 274M

ANALOG WAVEFORM

4T

EAV CODE

INPUT PIXELS

SAMPLE NUMBER

F
F

2112 2116 2156 2199

FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FIELD RATE OF 30Hz: 40 SAMPLES
FOR A FIELD RATE OF 25Hz: 480 SAMPLES

F

000

V

0

H*

4 CLOCK 4 CLOCK

0

DATUM

H

DIGITAL HORIZONTAL BLANKING

*1

272T

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

0

44 188 192 2111

4T 1920T

SAV CODE

F

CbC

000

F

V

0

F

H*

DIGITAL

ACTIVE LINE

Y

r

C

Y

r

SMPTE 293M

ANALOG WAVEFORM

INPUT PIXELS

SAMPLE NUMBER

Figure 112. EAV/SAV Input Data Timing Diagram—SMPTE 274M

EAV CODE

F
F

719 723 736 799 853 0

FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8

F

000

V

0

H*

4 CLOCK 4 CLOCK

0HDATUM

DIGITAL HORIZONTAL BLANKING

ANCILLARY DATA

(OPTIONAL)

SAV CODE

F

000

F

Figure 113. EAV/SAV Input Data Timing Diagram—SMPTE 293M

DIGITAL

ACTIVE LINE

F

CbC

V

0

H*

Y

r

857 719

C

Y

Y

r

REV. A–80–

ADV7310/ADV7311

ACTIVE

VIDEO

522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 44

VERTICAL BLANK

Figure 114. SMPTE 293M (525p)

ACTIVE

VIDEO

622 623 624 625 1 2 5 6 7 8 9 12 1310 11 43 44 454

VERTICAL BLANK

Figure 115. ITU-R BT.1358 (625p)

VERTICAL BLANKING INTERVAL

747 748 749 750 1 2 5 6 7 8 26 2725744 7454

3

ACTIVE

VIDEO

DISPLAY

ACTIVE

VIDEO

FIELD 1

FIELD 2

Figure 116. SMPTE 296M (720p)

VERTICAL BLANKING INTERVAL

1124 1125 1 2 5 6 7 8

VERTICAL BLANKING INTERVAL

561 562 563 564 567 568 569 570

43

566565

Figure 117. SMPTE 274M (1080i)

DISPLAY

21

20 22 560

DISPLAY

584

583 585 1123

REV. A

–81–

ADV7310/ADV7311

OUTLINE DIMENSIONS

64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64)

Dimensions shown in millimeters

1.45

1.40

1.35

0.15

0.05

10

6
2

SEATING
PLANE

ROTATED 90 CCW

VIEW A

0.08 MAX
COPLANARITY

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7

3.5
0

COMPLIANT TO JEDEC STANDARDS MS-026BCD

1.60
MAX

1

VIEW A

16

17

PIN 1

0.50

BSC

12.00 BSC
SQ

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

4964

48

10.00

BSC SQ

33

32

REV. A–82–

ADV7310/ADV7311

Revision History

Location Page

8/03—Data Sheet changed from REV. 0 to REV. A.

Addition to Standards Directly Supported Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to Figure 13 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Change to Table XI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Updated Figure 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Updated Figures 59 and 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Change to Figure 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Deletion of line from notes in Figure 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

REV. A

–83–

C03748–0–8/03(A)

–84–