Datasheet ADV7197KST Datasheet (Analog Devices)

Multiformat HDTV Encoder with

a

FEATURES
INPUT FORMATS

YCrCb in 2  10-Bit (4:2:2) or 3  10-Bit (4:4:4) Format
Compliant to SMPTE274M (1080i), SMPTE296M
(720p) and Any Other High-Definition Standard Using
Async Timing Mode
RGB in 3  10-Bit 4:4:4 Format

OUTPUT FORMATS

YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit + Sync (DAC A)
11-Bit DACs (DAC B, C)

PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay ()
Individual DAC On/Off Control
VBI Open Control

2

C Filter

I
2-Wire Serial MPU Interface
Single Supply 5 V/3.3 V Operation
52-Lead MQFP Package

Y0–Y9

Cr0–Cr9

Cb0–Cb9

CLKIN

HORIZONTAL

SYNC

VERTICAL

SYNC

BLANKING

RESET

Three 11-Bit DACs

ADV7197

FUNCTIONAL BLOCK DIAGRAM

11-BIT

+ SYNC

DAC

TEST

PATTERN

GENERATOR

AND

DELAY

CHROMA

4:2:2 TO 4:4:4

CHROMA

4:2:2 TO 4:4:4

TIMING

GENERATOR

(SSAF)

(SSAF)

SYNC

GENERATOR

I2C MPU

PORT

11-BIT

DAC

11-BIT

DAC

DAC CONTROL

BLOCK

ADV7197

DAC A ( Y)

DAC B

DAC C

V

REF

R

SET

COMP

APPLICATIONS
HDTV Display Devices
HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction

GENERAL DESCRIPTION

The ADV7197 is a triple, high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.

The ADV7197 has three separate 10-bit-wide input ports that
accept data in 4:4:4 10-bit YCrCb or RGB, or 4:2:2 10-bit
YCrCb. This data is accepted in HDTV format at 74.25 MHz
or 74.1758 MHz. For any other high definition standard but
SMPTE274M or SMPTE296M, the Async Timing Mode can
be used to input data to the ADV7197. For all standards,

*ADV is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

external horizontal, vertical, and blanking signals or EAV/SAV
codes control the insertion of appropriate synchronization signals
into the digital data stream and therefore the output signals.

The ADV7197 outputs analog YPrPb HDTV complying to
EIA-770.3, or RGB complying to RS-170/RS-343A.

The ADV7197 requires a single 5 V/3.3 V power supply, an
optional external 1.235 V reference, and a 74.25 MHz (or

74.1758 MHz) clock.

The ADV7197 is packaged in a 52-lead MQFP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

ADV7197–SPECIFICATIONS

(VAA = 4.75 V to 5.25 V, V

1

5 V SPECIFICATIONS

70C] unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution 11 Bits
Integral Nonlinearity 1.5 LSB
Differential Nonlinearity 0.9 2.0 LSB Guaranteed Monotonic

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OH

OL

Three-State Leakage Current 10 µAV
Three-State Output Capacitance 4 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V

IH

IL

Input Leakage Current 0 1 µAV
Input Capacitance, C

IN

ANALOG OUTPUTS

Full-Scale Output Current 3.92 4.25 4.56 mA DAC A

Output Current Range 3.92 4.25 4.56 mA DAC A

DAC-to-DAC Matching 1.4 % DAC A, B, C
Output Compliance Range, V
Output Impedance, R

OUT

Output Capacitance, C

OC

OUT

VOLTAGE REFERENCE (External and Internal)

Reference Range, V

POWER REQUIREMENTS

2

I

DD

3, 4

I

AA

REF

Power Supply Rejection Ratio 0.01 %/%

NOTES

1

Guaranteed by characterization.

2

IDD or the circuit current is the continuous current required to drive the digital core.

3

IAA is the total current required to supply all DACs including V

4

All DACs on.

Specifications subject to change without notice.

REF

= 1.235 V, R

REF

2.4 V I

= 2470 , R

SET

LOAD

0.4 V I

= 300 . All specifications T

= 400 µA

SOURCE

= 3.2 mA

SINK

= 0.4 V

IN

2.0 V

0.8 V
= 0.4 V or 2.4 V

IN

4pF

2.54 2.83 3.11 mA DAC B, C

2.39 2.66 2.93 mA DAC B, C

1.4 V
100 kΩ
7pF

1.112 1.235 1.359 V

96 102 mA With f

CLK

11 15 mA

circuitry.

to T

MIN

= 74.25 MHz

MAX

[0C to

–2–

REV. 0

ADV7197

3.3 V SPECIFICATIONS

(VAA = 3.15 V to 3.45 V, V

1

to 70C] unless otherwise noted.)

= 1.235 V, R

REF

= 2470 , R

SET

= 300 . All specifications T

LOAD

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution 11 Bits
Integral Nonlinearity 1.5 LSB
Differential Nonlinearity 0.9 2.0 LSB

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OH

OL

Three-State Leakage Current 10 µAV

2.4 V I

0.4 V I

SOURCE

= 3.2 mA

SINK

= 0.4 V

IN

= 400 µA

Three-State Output Capacitance 4 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V

IH

IL

Input Leakage Current 0 1 µAV
Input Capacitance, C

IN

2V

0.8 0.65 V
= 0.4 V or = 2.4 V

IN

4pF

ANALOG OUTPUTS

Full-Scale Output Current 3.92 4.25 4.56 mA DAC A

2.54 2.83 3.11 mA DAC B, C

Output Current Range 3.92 4.25 4.56 mA DAC A

2.39 2.66 2.93 mA DAC B, C
DAC-to-DAC Matching 1.4 % DAC A, B, C
Output Compliance Range, V
Output Impedance, R

OUT

Output Capacitance, C

OC

OUT

0 1.4 V

100 kΩ
7pF

VOLTAGE REFERENCE (External)

Reference Range, V

POWER REQUIREMENTS

2

I

DD

3, 4

I

AA

REF

1.112 1.235 1.359 V

46 mA With f
11 15 mA

= 74.25 MHz

CLK

Power Supply Rejection Ratio 0.01 %/%

NOTES

1

Guaranteed by characterization.

2

IDD or the circuit current is the continuous current required to drive the digital core.

3

IAA is the total current required to supply all DACs including V

4

All DACs on.

Specifications subject to change without notice.

circuitry.

REF

MIN

to T

MAX

[0C

REV. 0

–3–

ADV7197–SPECIFICATIONS

(VAA = 4.75 V to 5.25 V, V
to T

5 V DYNAMIC–SPECIFICATIONS

[0C to 70C] unless otherwise noted.)

MAX

Parameter Min Typ Max Unit

Luma Bandwidth 13.5 MHz
Chroma Bandwidth 6.75 MHz
Signal-to-Noise Ratio 64 dB Luma Ramp Unweighted
Chroma/Luma Delay Inequality 0 ns

Specifications subject to change without notice.

= 1.235 V, R

REF

= 2470 , R

SET

= 300 . All specifications T

LOAD

MIN

3.3 V DYNAMIC–SPECIFICATIONS

(VAA = 3.15 V to 3.45 V, V
T

to T

MIN

[0C to 70C] unless otherwise noted.)

MAX

= 1.235 V, R

REF

= 2470 , R

SET

= 300 . All specifications

LOAD

Parameter Min Typ Max Unit

Luma Bandwidth 13.5 MHz
Chroma Bandwidth 6.75 MHz
Signal-to-Noise Ratio 64 dB Luma Ramp Unweighted
Chroma/Luma Delay Inequality 0 ns

Specifications subject to change without notice.

(VAA = 4.75 V to 5.25 V, V

5 V TIMING–SPECIFICATIONS

P

arameter Min Typ Max Unit Conditions

MPU PORT

1

to T

[0C to 70C] unless otherwise noted.)

MAX

= 1.235 V, R

REF

= 2470 , R

SET

= 300 . All specifications T

LOAD

MIN

SCLOCK Frequency 10 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs After This Period the 1st Clock Is Generated

0.6 µs Relevant for Repeated Start Condition
100 ns

300 ns
300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

2

10 ns

Analog Output Skew 0.5 ns

CLOCK CONTROL AND PIXEL PORT

f

CLK

t

CLK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t

9

10

11

12

11

12

3

74.25 MHz HDTV Mode

81 MHz Async Timing Mode
5 1.5 ns
5 2.0 ns

2.0 ns

4.5 ns
7ns

4.0 ns

Pipeline Delay 16 Clock Cycles For 4:4:4 Pixel Input Format

NOTES

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV

Specifications subject to change without notice.

–4–

REV. 0

ADV7197

(VAA = 3.15 V to 3.45 V, V
T

to T

3.3 V TIMING–SPECIFICATIONS

P

arameter Min Typ Max Unit Conditions

MPU PORT

1

MIN

[0C to 70C] unless otherwise noted.)

MAX

= 1.235 V, R

REF

= 2470 , R

SET

= 300 . All specifications

LOAD

SCLOCK Frequency 10 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs After This Period the 1st Clock Is Generated

0.6 µs Relevant for Repeated Start Condition
100 ns

300 ns
300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

2

Analog Output Delay 10 ns
Analog Output Skew 0.5 ns

CLOCK CONTROL AND PIXEL PORT

f

CLK

t

CLK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t

9

10

11

12

11

12

3

74.25 MHz HDTV Mode
81 MHz Async Timing Mode

51.5 ns

52.0 ns

2.0 ns

4.5 ns
7ns

4.0 ns

Pipeline Delay 16 Clock Cycles For 4:4:4 Pixel Input Format

NOTES

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV

Specifications subject to change without notice.

REV. 0

CLOCK

PIXEL INPUT

DATA

t

t

9

10

Y0

Cb0

t

t

11

Y1

Cr0

12

Y2

Cb1 Cr1

...

...

...

Figure 1. 4:2:2 Input Data Format Timing Diagram

–5–

Yxxx

Cbxxx

Yxxx

Crxxx

– CLOCK HIGH TIME

t

9

– CLOCK LOW TIME

t

10

– DATA SETUP TIME

t

11

– DATA HOLD TIME

t

12

ADV7197

CLOCK

t

t

9

10

PIXEL INPUT

DATA

CLOCK

PIXEL INPUT

DATA

Y0

Cb0

Cr0 Cr1 Cr2 Cr3 ... Crxxx

t

t

11

Y1

Cb1

12

Y2

Cb2 Cb3

... ...

Yxxx

...

Cbxxx

Yxxx

Cbxxx

Crxxx

t

– CLOCK HIGH TIME

9

t

– CLOCK LOW TIME

10

t

– DATA SETUP TIME

11

t

– DATA HOLD TIME

12

Figure 2. 4:4:4 YCrCb Input Data Format Timing Diagram

t

t

9

10

R0

G0

B0 B1 B2 B3 ... Bxxx

t

t

11

R1

G1

12

R2

G2 G3

... ...

Rxxx

...

Gxxx

Rxxx

Gxxx

Bxxx

t

– CLOCK HIGH TIME

9

t

– CLOCK LOW TIME

10

t

– DATA SETUP TIME

11

t

– DATA HOLD TIME

12

Figure 3. 4:4:4 RGB Input Data Format Timing Diagram

–6–

REV. 0

HSYNC

VSYNC

DV

ADV7197

A

PIXEL

DATA

A

= 44 CLK CYCLES FOR 1080i

MIN

= 70 CLK CYCLES FOR 720P

A

MIN

= 236 CLK CYCLES FOR 1080i

B

MIN

= 300 CLK CYCLES FOR 720P

B

MIN

t

3

SDA

SCL

B

Figure 4. Input Timing Diagram

t

t

6

t

2

5

t

1

t

7

Figure 5. MPU Port Timing Diagram

YYYY

Cr Cr Cr Cr

Cb Cb Cb Cb

t

3

t

4

t

8

REV. 0

–7–

ADV7197

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Pin . . . . GND – 0.5 V to V

Ambient Operating Temperature (T
Storage Temperature (T
Junction Temperature (T

) . . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . . 150°C

J

) . . . . . –40°C to +85°C

A

+ 0.5 V

AA

Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . 225°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Analog Output Short Circuit to any Power Supply or Common can be of an

indefinite duration.

Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220°C

to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

I

OUT

AA

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7197KST 0°C to 70°C Plastic Quad Flatpack (MQFP) S-52

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7197 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

V

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

Y[9]

V

GND

PIN CONFIGURATION

GND

Cb/Cr[0]

Cb/Cr[1]

Cb/Cr[2]

Cb/Cr[3]

Cr[2]

Cr[3]

Cb/Cr[4]

ADV7197

TOP VIEW

(Not to Scale)

Cr[4]

Cr[5]

52 51 50 49 48 43 42 41 4047 46 45 44

1

DD

DD

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

Cr[0]

Cr[1]

Cb/Cr[5]

Cb/Cr[6]

Cr[6]

Cr[7]

Cb/Cr[7]

Cb/Cr[8]

Cr[8]

Cr[9]

Cb/Cr[9]

ALSB

AA

V

CLKIN

RESET

39

V

38

R

37

COMP

36

DAC B

35

V

34

DAC A

33

AGND

32

DAC C

31

SDA

30

SCL

29

HSYNC/SYNC

28

VSYNC/TSYNC

27

DV

AGND

REF

SET

AA

–8–

REV. 0

ADV7197

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Input/Output Function

1, 12 V

DD

2–11 Y0–Y9 I 10-Bit HDTV Input Port for Y Data. G data input in RGB mode.
13, 52 GND G Digital Ground
14–23 Cr0–Cr9 I 10-Bit HDTV Input Port for Color Data in 4:4:4 Input Mode. In 4:2:2 mode this

24, 35 V

AA

25 CLKIN I Pixel Clock Input. Requires a 74.25 MHz (74.1758 MHz) reference clock.
26, 33 AGND G Analog Ground
27 DV I Video Blanking Control Signal Input.
28 VSYNC/ I VSYNC, vertical sync control signal input or TSYNC input control signal in

TSYNC Async Timing Mode.

29 HSYNC/

SYNC I HSYNC, horizontal

30 SCL I MPU Port Serial Interface Clock Input.
31 SDA I/O MPU Port Serial Data Input/Output.
32 DAC C O Color component analog output of input data on Cb/Cr9–0 input pins.
34 DAC A O Y Analog Output.
36 DAC B O Color component analog output of input data on Cr9–Cr0 input pins.
37 COMP O Compensation Pin for DACs. Connect 0.1 µF Capacitor from COMP pin to V
38 R

39 V

SET

REF

40 RESET I This input resets the on-chip timing generator and sets the ADV7197 into Default

41 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address. When this

42–51 Cb/Cr9–0 I 10-Bit HDTV Input Port for Color Data. In 4:2:2 mode the multiplexed CrCb

P Digital Power Supply.

input port is not used. R data input in RGB mode.

P Analog Power Supply.

sync control signal input or SYNC input control signal in

Async Timing Mode.

AA

I A 2470 Ω resistor (for input ranges 64–940 and 64–960, output standards

EIA-770.3) must be connected from this pin to ground and is used to control the
amplitudes of the DAC outputs. For input ranges 0–1023 (output standards
RS-170, RS-343A) the R

value must be 2820 Ω.

SET

I/O Optional External Voltage Reference Input for DACs or Voltage Reference

Output (1.235 V).

Register setting. Reset is an active low signal.

pin is tied high, the I
When this pin is tied low, the input bandwidth on the I

2

C filter is activated which reduces noise on the I2C interface.

2

C interface is increased.

data must be input on these pins. B data input in RGB mode.

.

REV. 0

–9–

ADV7197

0

X

1

0

1

01

A1

READ/ WRITE

CONTROL

0 WRITE
1READ

ADDRESS
CONTROL

SET UP BY

ALSB

FUNCTIONAL DESCRIPTION
Digital Inputs

The digital inputs of the ADV7197 are TTL-compatible. 30-bit
YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel
data in 4:2:2 format is latched into the device on the rising edge
of each clock cycle at 74.25 MHz or 74.1758 in HDTV mode.
It is recommended to input data in 4:2:2 mode to make use of
the Chroma SSAFs on the ADV7197. As can be seen in the
figures below, these filters have 0 dB passband response and
prevent signal components being folded back into the frequency
band. In 4:4:4 input mode, the video data is already interpo­lated by an external input device and the chroma SSAFs of the
ADV7197 are bypassed.

ATTEN 10dB VAVG 1 MKR 0dB
RL –10.0dBm 10dB/ 3.18MHz

START 100kHz STOP 20.00MHz

RBW 10kHz VBW 300Hz SWP 17.0SEC

Figure 6. SSAF Response to a 2.5 MHz Chroma Sweep
Using 4:2:2 Input Mode

ATTEN 10dB VAVG 4 MKR –3.00dB
RL –10.0dBm 10dB/ 3.12MHz

(EIA-770.3), R
form to RS-170/RS-343A standards R

has a value of 300 Ω. For the outputs to con-

LOAD

must have a value

SET

of 2820 Ω.

Internal Test Pattern Generator

The ADV7197 can generate a Cross-Hatch pattern (white lines
against a black background). Additionally, the ADV7197 can
output a uniform color pattern. The color of the lines or uni­form field/frame can be programmed by the user.

Y/CrCb Delay

The Y output and the color component outputs can be delayed
wrt the falling edge of the horizontal sync signal by up to four
clock cycles.

I2C Filter

A selectable internal I2C filter allows significant noise reduction
on the I
width on the I
are not passed to the I
greater input bandwidth on the I

2

C interface. For setting ALSB high, the input band-

2

C lines is reduced and pulses of less than 50 ns

2

C controller. Setting ALSB low allows

2

C lines.

MPU PORT DESCRIPTION

The ADV7197 support a 2-wire serial (I2C-compatible) micro­processor bus driving multiple peripherals. Two inputs Serial
Data (SDA) and Serial Clock (SCL) carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7197 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 8. The LSB
sets either a read or write operation. Logic Level “1” corresponds
to a read operation while Logic Level “0” corresponds to a write
operation. A1 is set by setting the ALSB pin of the ADV7197 to
Logic Level “0” or Logic Level “1.” When ALSB is set to “0,”
there is greater input bandwidth on the I
high-speed data transfers on this bus. When ALSB is set to “1,”
there is reduced input bandwidth on the I
that pulses of less than 50 ns will not pass into the I

2

C lines, which allows

2

C lines, which means

2

C internal

controller. This mode is recommended for noisy systems.

START 100kHz STOP 20.00MHz
RBW 10kHz VBW 300Hz SWP 17.0SEC

Figure 7. Conventional Filter Response to a 2.5 MHz Chroma
Sweep Using 4:4:4 Input Mode

Control Signals

The ADV7197 accepts sync control signals accompanied by
valid 4:2:2 or 4:4:4 data. These external horizontal, vertical and
blanking pulses (or EAV/SAV codes) control the insertion of
appropriate sync information into the output signals.

Analog Outputs

The analog Y signal is output on the 11-bit + Sync DAC A,
the color component analog signals on the 11-bit DACs B, C
conforming to EIA-770.3 standards R

has a value of 2470 Ω

SET

Figure 8. Slave Address

To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transi­tion on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/W
bit). The bits are transferred from MSB down to LSB. The periph­eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known
as an Acknowledge Bit. All other devices withdraw from the bus
at this point and maintain an idle condition. The idle condition
is where the device monitors the SDA and SCL lines waiting for
the Start condition and the correct transmitted address. The R/W
bit determines the direction of the data.

–10–

REV. 0

ADV7197

A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.

The ADV7197 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses
plus the R/W bit. It interprets the first byte as the device address
and the second byte as the starting subaddress. The subaddresses
auto-increment, allowing data to be written to or read from the
starting subaddress. A data transfer is always terminated by a
Stop condition. The user can also access any unique subad­dress register on a one-by-one basis without having to update
all the registers.

Stop and Start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period the
user should issue only one Start condition, one Stop condition
or a single Stop condition followed by a single Start condition. If
an invalid subaddress is issued by the user, the ADV7197 will
not issue an acknowledge and will return to the idle condition. If
in auto-increment mode, the user exceeds the highest subaddress,
the following action will be taken:

1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no­acknowledge condition is where the SDA line is not pulled
low on the ninth pulse.

2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7197 and the part will return to the idle
condition.

SDATA

SCLOCK

S

1–7

8

9

START ADDR R /W ACK

1–71–7

89 8

SUBADDRESS

ACK DATA

ACK

P

9

STOP

Figure 9. Bus Data Transfer

Figure 9 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.

Figure 10 shows bus write and read sequences.

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the
ADV7197 except the Subaddress Registers, which are write-only
registers. The Subaddress Register determines which register is
accessed by the next read or write operation.

All communications with the part through the bus begin with an
access to the Subaddress Register. A read/write operation is
performed from/to the target address which then increments to
the next address until a Stop command on the bus is performed.

REGISTER PROGRAMMING

The following section describes the functionality of each regis­ter. All registers can be read from as well as written to unless
otherwise stated.

Subaddress Register (SR7–SR0)

The Communications Register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation
takes place.

Figure 11 shows the various operations under the control of the
Subaddress Register. “0” should always be written to SR7.

Register Select (SR6–SR0)

These bits are set up to point to the required starting address.

REV. 0

WRITE

SEQUENCE

READ

SEQUENCE

DATA A(S)S SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 0

S SLAVE ADDR A(S) SUB ADDR

S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) = NO-ACKNOWLEDGE BY SLAVE
P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A(M) = NO-ACKNOWLEDGE BY MASTER

S SLAVE ADDR

A(S)

LSB = 1

A(S) DATA

DATA

A(S) P

A(M)

Figure 10. Write and Read Sequence

SR3

SR2

SR1

SR7

ZERO SHOULD

BE WRITTEN

HERE

SR4

ADV7197 SUBADDRESS REGISTER

ADDRESS SR6 SR5 SR4 SR3 SR2 SR1 SR0

00h 0000000 MODE REGISTER 0
01h 0000001 MODE REGISTER 1
02h 0000010 MODE REGISTER 2
03h 0000011 MODE REGISTER 3
04h 0000100 MODE REGISTER 4
05h 0000101 MODE REGISTER 5
06h 0000110 COLOR Y
07h 0000111 COLOR CR
08h 0001000 COLOR CB

Figure 11. Subaddress Registers

–11–

DATA P

SR0SR7 SR6 SR5

A(M )

ADV7197

H

MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)

Figure 14 shows the various operations under the control of
Mode Register 0.

MR0 BIT DESCRIPTION
Output Standard Selection (MR00–MR01)

These bits are used to select the output levels from the ADV7197.

If EIA 770.3 (MR01–00 = “00”) is selected, the output levels will
be: 0 mV for blanking level, 700 mV for peak white (Y channel),
± 350 mV for Pr, Pb outputs and –300 mV for tri-level sync.

If Full Input Range (MR01–00 = “10”) is selected, the output
levels will be 700 mV for peak white for the Y channel, ±350 mV
for Pr, Pb outputs, and –300 mV for Sync. This mode is used
for RS-170, RS-343A standard output compatibility.

Sync insertion on the Pr, Pb channels is optional. For output
levels refer to the Appendix.

Input Control Signals (MR02–MR03)

These control bits are used to select whether data is input with
external horizontal, vertical, and blanking sync signals or if the

CLK

SYNC

TSYNC

DV SET

MR06 = ‘1’

data is input with embedded EAV/SAV codes. An Asynchro­nous timing mode is also available using TSYNC, SYNC and
DV as input control signals.

These timing control signals have to be programmed by the user
and are used for any other high definition standard input but
SMPTE274M and SMPTE296M.

Figure 12 shows an example of how to program the ADV7197
to accept a different high definition standard but SMPTE274M
or SMPTE296M.

Reserved (MR04)

A “0” must be written to this bit.

Input Standard (MR05)

Select between 1080i or 720p input.

DV Polarity (MR06)

This control bit allows to select the polarity of the DV input
control signal to be either active high or active low. This is in
order to facilitate interfacing from input devices which use an
active high blanking signal output.

Reserved (MR07)

A “0” must be written to this bit.

PROGRAMMABLE
INPUT TIMING

HORIZONTAL SYNC

81 66

AB C

66 243 1920

DE

ACTIVE VIDEO

ANALOG
OUTPUT

Figure 12. Async Timing Mode—Programming Input Control Signals for SMPTE295M Compatibility

SYNC

VSYNC

DV

DISPLAY

VERTICAL BLANKING INTERVAL

747 748 749 750 1 2 3 4

7

5

6

8

25

26 27

DISPLAY

744 745

Figure 13. DV Input Control Signal in Relation to Video Output Signal for SMPTE296M (720p)

–12–

REV. 0

ADV7197

MR07

MR07

ZERO MUST

BE WRITTEN

TO THIS BIT

MR06

0 ACTIVE HIGH
1 ACTIVE LOW

INPUT STANDARD

MR05

0 1080I
1 720P

DV POLARITY

MR04MR05MR06 MR03 MR00

MR04

ZERO MUST
BE WRITTEN

TO THIS BIT

Figure 14. Mode Register 0

Table I must be followed when programming the control signals
in Async Timing Mode.

Table I. Truth Table

SYNC TSYNC DV

1 –> 0 0 0 or 1 50% Point of Falling Edge of

Tri-Level Horizontal Sync
Signal, a

0 0 –> 1 0 or 1 25% Point of Rising Edge of

Tri-Level Horizontal Sync
Signal, b

0 –> 1 0 or 1 0 50% Point of Falling Edge of

Tri-Level Horizontal Sync

Signal, c
1 0 or 1 0 –> 1 50% Start of Active Video, d
1 0 or 1 1 –> 0 50% End of Active Video, e

MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)

Figure 15 shows the various operations under the control of
Mode Register 1.

MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)

When this bit is set to “0,” the pixel data input to the ADV7197
is blanked such that a black screen is output from the DACs.

MR02

INPUT CONTROL SIGNALS

MR03 MR02
00 HSYNC\VSYNC/DV

0 1 EAV/SAV
1 0 TSYNC/SYNC/DV
1 1 RESERVED

OUTPUT STANDARD SELECTION

MR01 MR00

0 0 EIA-770.3
0 1 RESERVED
1 0 FULL I/P RANGE
1 1 RESERVED

MR01

When this bit is set to “1,” pixel data is accepted at the input
pins and the ADV7197 outputs to the standard set in “Output
Standard Selection” (MR01–MR00). This bit also must be set
to “1” to enable output of the test pattern signals.

Input Format (MR11)

It is possible to input data in 4:2:2 format or in 4:4:4 format.

Test Pattern Enable (MR12)

Enables or disables the internal test pattern generator.

Test Pattern Hatch/Frame (MR13)

If this bit is set to “0,” a cross hatch test pattern is output from
the ADV7197. The cross hatch test pattern can be used to test
monitor convergence.

If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7197.

The color of the lines or the frame/field is by default white but
can be programmed to be any color using the Color Y, Color
Cr, Color Cb Registers.

VBI Open (MR14)

This bit enables or disables the facility of VBI data insertion
during the Vertical Blanking Interval.

For this purpose Lines 7–20 in 1080i and Lines 6–25 in 720p
can be used for VBI data insertion.

Reserved (MR15–MR17)

A “0” must be written to these bits.

REV. 0

MR17

MR17–MR15

ZERO MUST
BE WRITTEN

TO THESE BITS

MR12MR14MR15MR16 MR13 MR10

VBI OPEN

MR14

0 DISABLED
1 ENABLED

TEST PATTERN
HATCH/FRAME

MR13

0HATCH
1 FIELD/FRAME

TEST PATTERN

ENABLE

MR12

0 DISABLED
1 ENABLED

Figure 15. Mode Register 1

–13–

MR11

PIXEL DATA

MR10

0 DISABLED
1 ENABLED

INPUT FORMAT

MR11

0 4:4:4 YCrCb
1 4:2:2 YCrCb

ENABLE

ADV7197

MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)

Figure 17 shows the various operations under the control of
Mode Register 2.

MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)

With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 16 demonstrates this facility.

Color Delay (MR23–MR25)

With theses bits it is possible to delay the color signals with
respect to the falling edge of the horizontal sync signal by up to
four pixel clock cycles. Figure 16 demonstrates this facility.

Reserved (MR26–MR27)

A “0” must be written to these bits.

Y DELAY

NO DELAY

MAX DELAY

NO DELAY

Y OUTPUT

MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)

Figure 18 shows the various operations under the control of
Mode Register 3.

MR3 BIT DESCRIPTION
Reserved (MR31–MR32)

A “0” must be written to these bits.

DAC A Control (MR33)

Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.

DAC B Control (MR34)

Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.

DAC C Control (MR35)

Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.

Reserved (MR36–MR37)

A “0” must be written to these bits.

PrPb DELAY

MAX DELAY

Figure 16. Y and Color Delay

MR27

MR27–MR26

ZERO MUST

BE WRITTEN

TO THESE BITS

MR37

MR37–MR36

ZERO MUST BE

WRITTEN TO
THESE BITS

MR35

0 POWER-DOWN
1 NORMAL

PrPb OUTPUTS

COLOR DELAY

MR25 MR24 MR23

0 0 0 0 PCLK
0 0 1 1 PCLK
0 1 0 2 PCLK
0 1 1 3 PCLK
1 0 0 4 PCLK

Figure 17. Mode Register 2

MR35

MR34

0 POWER-DOWN
1 NORMAL

DAC C CONTROL

DAC B CONTROL

MR33

DAC A CONTROL

MR33

0 POWER-DOWN
1 NORMAL

MR22MR24MR25 MR23 MR20MR26

MR32MR34MR36

MR32–MR30

ZERO MUST BE

WRITTEN TO

THESE BITS

MR21

MR22 MR21 MR20

0 0 0 0 PCLK
0 0 1 1 PCLK
0 1 0 2 PCLK
0 1 1 3 PCLK
1 0 0 4 PCLK

Y DELAY

MR31

MR30

Figure 18. Mode Register 3

–14–

REV. 0

ADV7197

MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)

Figure 19 shows the various operations under the control of
Mode Register 4.

MR4 BIT DESCRIPTION
Timing Reset (MR40)

Toggling MR40 from low to high and low again resets the inter­nal horizontal and vertical timing counters.

MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4-SR0) = 05H)

Figure 20 shows the various operations under the control of
Mode Register 5.

MR5 BIT DESCRIPTION
Reserved (MR50)

This bit is reserved for the revision code.

RGB Mode (MR51)

When RGB mode is enabled (MR51 = “1”) the ADV7197
accepts unsigned binary RGB data at its input port. This control
is also available in Async Timing Mode.

Sync on PrPb (MR52)

By default the color component output signals Pr, Pb do not
contain any horizontal sync pulses. They can be inserted when
MR52 = “1.”

This control is not available in RGB mode.

Color Output Swap (MR53)

By default DAC B is configured as the Pr output and DAC C
as the Pb output. In setting this bit to “1” the DAC outputs
can be swapped around so that DAC B outputs Pb and DAC C
outputs Pr. The table below demonstrates this in more detail.
This control is also available in RGB mode.

Reserved (MR54–MR57)

A “0” must be written to these bits.

Table II. Relationship Between Color Input Pixel Port, MR53
and DAC B, DAC C Outputs

In 4:4:4 Input Mode

Color Data Analog Output
Input on Pins MR53 Signal

Cr9–0 0 DAC B
Cb/Cr9–0 0 DAC C
Cr9–0 1 DAC C
Cb/Cr9–0 1 DAC B

In 4:2:2 Input Mode

Color Data Analog Output
Input on Pins MR53 Signal

Cr9–0 0 or 1 Not Operational
Cb/Cr9–0 0 DAC C (Pb)
Cb/Cr9–0 1 DAC C (Pr)

MR47

MR57

MR45 MR43

THESE REGISTERS

MR57–MR54

ZERO MUST BE

WRITTEN TO

THESE BITS

MR42MR44MR46

MR47–MR41

ZERO MUST BE

WRITTEN TO

Figure 19. Mode Register 4

MR52MR56 MR55 MR53 MR50MR54

SYNC ON PrPb

MR52

0 DISABLE
1 ENABLE

COLOR OUTPUT

SWAP

MR53

0 DAC B = Pr
1 DAC C = Pr

Figure 20. Mode Register 5

TIMING RESET

MR40

RESERVED FOR
REVISION CODE

RGB MODE

MR40

MR50

MR41

MR51

MR51

0 DISABLE
1 ENABLE

REV. 0

–15–

ADV7197

COLOR Y
CY (CY7–CY0)
(Address (SR4–SR0) = 06H)

CY6 CY5 CY4 CY3 CY2 CY1 CY0

CY7

CY7–CY0

COLOR Y VALUE

Figure 21. Color Y Register

COLOR CR
CCR (CCR7–CCR0)
(Address (SR4–SR0) = 07H)

CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0

CCR7

CCR7–CCR0

COLOR CR VALUE

Figure 22. Color Cr Register

COLOR CB
CCB (CCB7–CCB0)
(Address (SR4–SR0) = 08H)

CCB6 CCB5 CCB4 CCB3 CCB2 CCB1 CCB0

CCB7

CCB7 –CCB0

COLOR CB VALUE

Figure 23. Color Cb Register

These three 8-bit-wide registers are used to program the output
color of the internal test pattern generator, be it the lines of the
cross hatch pattern or the uniform field test pattern.

The standard used for the values for Y and the color difference
signals to obtain white, black and the saturated primary and comple­mentary colors conforms to the ITU-R BT 601-4 standard.

The Table III shows sample color values to be programmed into
the color registers.

Table III. Sample Color Values

Sample Color Y Color Cr Color Cb
Color Value Value Value

White 235 (EB) 128 (80) 128 (80)
Black 16 (10) 128 (80) 128 (80)
Red 81 (51) 240 (F0) 90 (5A)
Green 145 (91) 34 (22) 54 (36)
Blue 41 (29) 110 (6E) 240 (F0)
Yellow 210 (D2) 146 (92) 16 (10)
Cyan 170 (AA) 16 (10) 166 (A6)
Magenta 106 (6A) 222 (DE) 202 (CA)

DAC TERMINATION AND LAYOUT CONSIDERATIONS
Voltage Reference

The ADV7197 contains an on-board voltage reference. The

pin is normally terminated to VAA through a 0.1 µF capacitor

V

REF

when the internal V
can be used with an external V

Resistor R

is connected between the R

SET

is used. Alternatively, the ADV7197

REF

(AD589).

REF

pin and analog

SET

ground and is used to control the full scale output current and
therefore the DAC voltage output levels. For full-scale output

must have a value of 2470 Ω. R

R

SET

When an input range of 0–1023 is selected the value of R

has a value of 300 Ω.

LOAD

SET

must be 2820 Ω.

The ADV7197 has three analog outputs, corresponding to Y,
Pr, Pb video signals. The DACs must be used with external
buffer circuits in order to provide sufficient current to drive an
output device. A suitable op amp would be the AD8057.

PC BOARD LAYOUT CONSIDERATIONS

The ADV7197 is optimally designed for lowest noise perfor­mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7197, it is imperative
that great care be given to the PC board layout.

The layout should be optimized for lowest noise on the ADV7197
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V

and AGND and VDD and DGND pins

AA

should be kept as short as possible to minimized inductive ringing.

It is recommended that a four-layer printed circuit board is
used. With power and ground planes separating the layer of the
signal carrying traces of the components and solder side layer.
Placement of components should consider to separate noisy
circuits, such as crystal clocks, high-speed logic circuitry and
analog circuitry.

There should be a separate analog ground plane (AGND) and
a separate digital ground plane (GND).

Power planes should encompass a digital power plane (V
analog power plane (V
the DACs and all associated circuitry, and the V

). The analog power plane should contain

AA

REF

) and a

DD

circuitry.

The digital power plane should contain all logic circuitry. The
analog and digital power planes should be individually connected
to the common power plane at one single point through a suit­able filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches. The DAC termi­nation resistors should be placed as close as possible to the DAC
outputs and should overlay the PCB’s ground plane. As well as
minimizing reflections, short analog output traces will reduce
noise pickup due to neighboring digital circuitry.

–16–

REV. 0

ADV7197

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.

Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of group of V

or VDD pins should be indi-

AA

vidually decoupled to ground. This should be done by placing
the capacitors as close as possible to the device with the capaci­tor leads as short as possible, thus minimizing lead inductance.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.

POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP

V

AA

0.1F
24, 35 1, 12

V

V

COMP

Cb/Cr0–Cb/Cr9

Cr0–Cr9

AA

DAC A

ADV7197

Due to the high clock rates used, long clock lines to the ADV7197
should be avoided to minimize noise pickup. Any active pull-up
termination resistors for the digital inputs should be connected
to the digital power plane and not the analog power plane.

Analog Signal Interconnect

The ADV7197 should be located as close as possible to the
output connectors thus minimizing noise pickup and reflections
due to impedance mismatch.

For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω. This termi­nation resistance should be as close as possible to the ADV7197
to minimize reflections.

Any unused inputs should be tied to ground.

V

0.1F

Y OUTPUT

AA

V

DD

10nF

DD

0.1F

10nF

300

UNUSED
INPUTS
SHOULD BE
GROUNDED

V

DD

4.7k

4.7F

6.3V

27MHz, 74.25MHz OR

74.1758MHz CLOCK

V

AA

4.7k

26, 33

DAC B

DAC C

SCL

SDA

V

R

GND

13, 52

REF

SET

Y0–Y9

HSYNC/SYNC

VSYNC/TSYNC

DV

RESET

CLKIN

ALSB

AGND

Figure 24. Circuit Layout

300

300

2.47k OR 2.82k

Pr(V) OUTPUT

Pb(U) OUTPUT

100

100

V

V

DD

5k

DD

5k

MPU BUS

REV. 0

–17–

ADV7197

Video Output Buffer and Optional Output Filter

Output buffering is necessary in order to drive output devices,

such as HDTV monitors.

Analog Devices produces a range of suitable op amps for this
application. A suitable op amp would be the AD8057. More
information on line driver buffering circuits is given in the rel­evant op amp data sheets.

An optional analog reconstruction LPF might be required as an
antialias filter if the ADV7197 is connected to a device that
requires this filtering.

The Eval ADV7196/ADV7197EB evaluation board uses the
ML6426 Microlinear IC, which provides buffering and low-pass
filtering for HDTV applications.

The Eval ADV7196/ADV7197EB Rev. B and Rev. C evaluation
boards use the AD8057 as a buffer and a 6th order LPF.

The Application Note, AN-TBD, describes in detail these two
designs and should be consulted when designing external filter
and buffers for Analog Devices Video Encoders.

+5V

LPF

AD8057

To calculate the output full-scale current and voltage, the fol­lowing equations should be used:

V

= I

OUT

REF

× R

LOAD

× K)/R

SET

I

OUT

OUT

= (V

where:

K = 5.66 (for input ranges 64–940, 64–960, output standards
EIA770.3)

K = 6.46 (for input ranges 0–1023, output standards
RS170/343A

V

= 1.235 V.

REF

0.1F

10F

75 COAX

75

75

ADV7197

DAC A

DAC B

DAC C

0.1F

–5V

LPF

AD8057

75

5V

+5V

LPF

AD8057

75

–5V

10F

0.1F5V10F

75 COAX

0.1F

10F

0.1F

10F

75 COAX

0.1F

10F

Figure 25. Output Buffer and Optional Filter

HDTV MONITOR

75

75

–18–

REV. 0

ADV7197

OUTPUT VOLTAGEINPUT CODE EIA-770.3, STANDARD FOR Y

940

960

512

ACTIVE

VIDEO

64

ACTIVE

VIDEO

64

700mV

300mV

0mV

–300mV

OUTPUT VOLTAGEEIA-770.3, STANDARD FOR Pr/Pb

350mV

300mV

0mV

–300mV

–350mV

Figure 26. EIA 770.3 Standard Output Signals (1080i, 720p)

REGISTER SETTINGS
Register Settings on Power-Up

1023

ACTIVE

VIDEO

64

INPUT CODE

PrPb-OUTPUT LEVELS FOR FULL I/P SELECTIONS

1023

64

ACTIVE

VIDEO

Figure 27. Output Levels for Full I/P Selection

REGISTER SETTINGS
Internal Colorbars (Field), HDTV Mode

OUTPUT VOLTAGEINPUT CODE Y-OUTPUT LEVELS FOR FULL I/P SELECTIONS

700mV

0mV

–300mV

OUTPUT VOLTAGE

700mV

0mV

–300mV

Address Register Setting

00hex Mode Register 0 00hex
01hex Mode Register 1 00hex
02hex Mode Register 2 00hex
03hex Mode Register 3 39hex
04hex Mode Register 4 00hex
05hex Mode Register 5 00hex
06hex Color Y A0hex
07hex Color Cr 80hex
08hex Color Cb 80hex

0HDATUM

SMPTE274M

ANALOG WAVEFORM

INPUT PIXELS

SAMPLE NUMBER

4T

EAV CODE

FF0

00F

0

V
H*

4 CLOCK

2112 2116

DIGITAL HORIZONTAL BLANKING

ANCILLARY DATA (OPTIONAL)

OR BLANKING CODE

2199

2156 0 44 188 192 2111

Figure 28. EAV/SAV Input Data Timing Diagram—SMPTE274M (1080i)

Address Register Setting

00hex Mode Register 0 00hex
01hex Mode Register 1 0Dhex
02hex Mode Register 2 00hex
03hex Mode Register 3 39hex
04hex Mode Register 4 00hex
05hex Mode Register 5 00hex
06hex Color Y xxhex
07hex Color Cr xxhex
08hex Color Cb xxhex

272T

4T

SAV CODE

FF0

0

0

0

4 CLOCK

FVH* = FVH AND PARITY BITS
SAV/EAV: LINES 1–562: F = 0
SAV/EAV: LINES 563–1125: F = 1
SAV/EAV: LINES 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINES 21–560; 584–1123: V = 0

C

F

b

V
H*

1920T

DIGITAL

ACTIVE LINE

C

Y

r

C

Y

r

REV. 0

–19–

ADV7197

DISPLAY

VERTICAL BLANKING INTERVAL

747 748 749 750 1 2 3 4

Figure 29. SMPTE296M (720p)

FIELD 1

VERTICAL BLANKING INTERVAL

1124 1125 1 2 3 4 5 6

FIELD 2

VERTICAL BLANKING INTERVAL

561 562 563 564 565 566 567 568

Figure 30. SMPTE274M (1080i)

7

5

6

8

25

26 27

744 745

DISPLAY

C02155–1.5–4/01(0)

20

583

584

21

22

DISPLAY

585

560

1123

569

7

8

570

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

52-Lead Plastic Quad Flatpack (MQFP)

(S-52)

13

1

14

0.0256

0.557 (14.15)

0.537 (13.65)

0.398 (10.11)

0.390 (9.91)

PIN 1

TOP VIEW

(PINS DOWN)

(0.65)

BSC

4052

26

0.014 (0.35)

0.010 (0.25)

39

27

0.037 (0.95)

0.026 (0.65)

SEATING

PLANE

0.012 (0.30)

0.006 (0.15)

0.008 (0.20)

0.006 (0.15)

0.094 (2.39)

0.084 (2.13)

0.082 (2.09)

0.078 (1.97)

0.390 (9.91)

0.398 (10.11)

0.557 (14.15)

0.537 (13.65)

PRINTED IN U.S.A.

–20–

REV. 0