Datasheet ADV7190 Datasheet (Analog Devices)

Page 1

Video Encoders with Six 10-Bit DACs and

FEATURES Six High Quality 10-Bit Video DACs Multistandard Video Input Multistandard Video Output 4 Oversampling with Internal 54 MHz PLL Programmable Video Control Includes:

Digital Noise Reduction Gamma Correction LUMA Delay

CHROMA Delay Multiple Luma and Chroma Filters Luma SSAF™ (Super Subalias Filter) Average Brightness Detection Field Counter Macrovision Rev 7.1 (ADV7190 Only) CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface Supply Voltage 5 V and 3.3 V Operation 64-Lead LQFP Package

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

54 MHz Oversampling

ADV7190/ADV7191

APPLICATIONS DVD Playback Systems, PC Video/Multimedia Playback Systems

GENERAL DESCRIPTION

The ADV7190/ADV7191 is part of the new generation of video encoders from Analog Devices. The device builds on the performance of previous video encoders and provides new features such as Digital Noise Reduction, Gamma Correction, 4¥ Oversam- pling and 54 MHz operation, Average Brightness Detection, Chroma Delay, an additional Chroma Filter, and so on.

The ADV7190/ADV7191 supports NTSC-M, NTSC-N (Japan), PAL N, PAL M, PAL-B/D/G/H/I, and PAL-60 standards. Input standards supported include ITU-R.BT656/601 4:2:2 YCrCb in 8- or 16-bit format.

The ADV7190/ADV7191 can output Composite Video (CVBS), S-Video (Y/C), Component YUV component output is also compatible with Betacam, MII and SMPTE/EBU N10 levels, SMPTE 170M NTSC, and ITUR.BT 470 PAL.

For more information about the ADV7190/ADV7191’s features, refer to Detailed Description.

, or RGB. The analog

Continued on page 11

DIGITAL

INPUT

27MHz

CLOCK

ITU–R.BT

656/601

8-BIT YCrCb

IN 4:2:2 FORMAT

*This device is protected by U.S. Patent Numbers 4631603, 4577216, and 4819098, and other intellectual property rights.

Throughout the document, YUV refers to digital or analog component video. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales ofﬁce for latest available Macrovision version. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). SSAF is a trademark of Analog Devices Inc. I2C is a registered trademark of Philips Corporation.

VIDEO INPUT PROCESSING

PLL

AND

54MHz

DEMUX

AND

YCrCb–

TO–

YUV

MATRIX

VIDEO SIGNAL PROCESSING

COLOR CONTROL DNR GAMMA CORRECTION

VBI TELETEXT CLOSED CAPTION CGMS/WSS MACROVISION

CHROMA LPF

SSAF LPF

LUMA LPF

I2C INTERFACE

VIDEO OUTPUT PROCESSING

2

OVERSAMPLING

4

OVERSAMPLING

ADV7190/ADV7191

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

ANALOG OUTPUT

COMPOSITE VIDEO Y [S-VIDEO] C [S-VIDEO] RGB YUV

TVSCREEN

REV.B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

Page 2

ADV7190/ADV7191

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS

5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 V DYNAMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.3 V DYNAMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 V TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . 6

3.3 V TIMING CHARACTERISTICS . . . . . . . . . . . . . . .. 7

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9

PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10

DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11

DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12

INTERNAL FILTER RESPONSE.. . . . . . . . . . . . . . . . . . . 13

FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17

Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chroma/Luma Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clamp Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CSO, HSO, and VSO Outputs . . . . . . . . . . . . . . . . . . . . . 17

Color Bar Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Color Burst Signal Control . . . . . . . . . . . . . . . . . . . . . . . 17

Color Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chrominance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Gamma Correction Control . . . . . . . . . . . . . . . . . . . . . . . 18

NTSC Pedestal Control . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Real-Time Control, Subcarrier Reset,

and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SCH Phase Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Square Pixel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Vertical Blanking Data Insertion And BLANK Input . . . . 19

YUV Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4¥ Oversampling and Internal PLL . . . . . . . . . . . . . . . . . 19

VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 19

RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 27

MODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

TIMING REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SUBCARRIER FREQUENCY AND

PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 36

NTSC PEDESTAL REGISTERS . . . . . . . . . . . . . . . . . . . . 37

TELETEXT REQUEST CONTROL REGISTER . . . . . . 37

CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 37

CONTRAST CONTROL REGISTER . . . . . . . . . . . . . . . . 38

COLOR CONTROL REGISTERS . . . . . . . . . . . . . . . . . . 38

HUE ADJUST CONTROL REGISTER . . . . . . . . . . . . . . 39

BRIGHTNESS CONTROL REGISTERS . . . . . . . . . . . . . 39

SHARPNESS CONTROL REGISTER . . . . . . . . . . . . . . . 40

DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 42

BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 43

OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX 1

BOARD DESIGN AND LAYOUT

CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44

APPENDIX 2

CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . 46

APPENDIX 3

COPY GENERATION MANAGEMENT

SYSTEM (CGMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

APPENDIX 4

WISE SCREEN SIGNALING (WSS) . . . . . . . . . . . . . . . 48

APPENDIX 5

TELETEXT INSERTION . . . . . . . . . . . . . . . . . . . . . . . 49

APPENDIX 6

OPTIONAL OUTPUT FILTER . . . . . . . . . . . . . . . . . . 50

APPENDIX 7

DAC BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

APPENDIX 8

RECOMMENDED REGISTER VALUES . . . . . . . . . . . 52

APPENDIX 9

NTSC WAVEFORMS (WITH PEDESTAL) . . . . . . . . . 56

NTSC WAVEFORMS (WITHOUT PEDESTAL) . . . . . 57

PAL WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

UV WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . 60

VIDEO MEASUREMENT PLOTS . . . . . . . . . . . . . . . . 64

APPENDIX 10

VECTOR PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

–2–

REV. B

Page 3

ADV7190/ADV7191

SPECIFICATIONS

(VAA = 5 V, V

5 V SPECIFICATIONS

unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INH

INL

Input Leakage Current 1 mA

DIGITAL OUTPUTS

Output High Voltage, V Output Low Voltage, V

Three-State Leakage Current 10 mA Three-State Output Capacitance 6 10 pF

ANALOG OUTPUTS

Output Current (Max) 4.125 4.33 4.625 mA RL = 300 W, R Output Current (Min) 2.16 mA R DAC-to-DAC Matching Output Compliance, V Output Impedance, R Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

OUT

REF

POWER REQUIREMENTS

Normal Power Mode

DAC

(2¥ Oversampling)

CCT

(4¥ Oversampling)

CCT

PLL

6, 7

Sleep Mode

DAC

CCT

NOTES

All measurements are made in 4¥ Oversampling Mode unless otherwise speciﬁed.

Temperature range T

Guaranteed by characterization.

Measurement made in 2¥ oversampling mode.

is the total current required to supply all DACs including the V

DAC

All six DACs ON.

, or the circuit current, is the continuous current required to drive the digital core without I

CCT

Speciﬁcations subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

= 1.235 V, R

REF

= 1200 , unless otherwise noted. All speciﬁcations T

SET1,2

± 1.0 LSB ± 1.0 LSB Guaranteed Monotonic

0.8 V

0 ± 1 mAV

= 0.4 V or 2.4 V

610 pF

2.4 V I

0.8 0.4 V I

= 400 mA

SOURCE

= 3.2 mA

SINK

= 600 W, R

SET1,2

0.4 2.5 %

0 1.4 V

100 kW 6pFI

OUT

= 0 mA

1.112 1.235 1.359 V

4.75 5.0 5.25 V

29 35 mA 80 120 mA 120 170 mA 610 mA

0.01 mA 85 mA

circuitry.

REF

PLL

to T

MIN

= 1200 W = 2400 W

MAX

REV. B

–3–

Page 4

ADV7190/ADV7191–SPECIFICATIONS

(

3.3 V SPECIFICATIONS

VAA = 3.3 V, V

unless otherwise noted.)

= 1.235 V, R

REF

= 1200 , unless otherwise noted. All speciﬁcations T

SET1,2

MIN

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity ± 1.0 LSB Differential Nonlinearity ± 1.0 LSB Guaranteed Monotonic

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

0.8 V ± 1 mAV

= 0.4 V or 2.4 V

610pF

Input Leakage Current 1 mA

DIGITAL OUTPUTS

Output High Voltage, V Output Low Voltage, V

2.4 V I

0.4 V I

SOURCE

= 3.2 mA

SINK

= 400 mA

Three-State Leakage Current 10 mA Three-State Output Capacitance 6 10 pF

ANALOG OUTPUTS

Output Current (Max) 4.25 4.33 4.625 mA R Output Current (Min) 2.16 mA R

= 1200 W, RL = 300 W

SET1,2

= 600 W, R

SET1,2

DAC-to-DAC Matching 0.4 % Output Compliance, V Output Impedance, R

OUT

Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

REF

OUT

100 kW 630pFI

1.235 V I

1.4 V

= 0 mA

OUT

VREFOUT

= 20 mA

POWER REQUIREMENTS

V

Normal Power Mode

DAC

(2¥ Oversampling)

CCT

(4¥ Oversampling)

CCT

PLL

5, 6

3.15 3.3 3.45 V

29 mA 42 54 mA 68 86 mA 6mA

Sleep Mode

DAC

CCT

NOTES

All measurements are made in 4¥ Oversampling Mode unless otherwise speciﬁed and are guaranteed by characterization. In 2 ¥ Oversampling Mode, the power requirement for the ADV7190/ADV7191 are typically 3.0 V.

Temperature range T

Measurement made in 2¥ oversampling mode.

is the total current required to supply all DACs including the V

DAC

All six DACs ON.

, or the circuit current, is the continuous current required to drive the digital core without I

CCT

Speciﬁcations subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

0.01 mA

85 mA

circuitry.

REF

PLL

to T

MAX

= 2400 W

–4–

REV. B

Page 5

ADV7190/ADV7191

(VAA = 5 V  250 mV, V

5 V DYNAMIC–SPECIFICATIONS

speciﬁcations T

MIN

Parameter Min Typ Max Unit Test Conditions

Differential Gain Differential Phase SNR (Pedestal)

SNR (Ramp)

61.7 (61.7) dB rms RMS

0.1 (0.4) 0.3 (0.5) %

0.4 (0.15) 0.5 (0.3) Degrees

78.5 (78) dB rms RMS 78 (78) dB p-p Peak Periodic

62 (63) dB p-p Peak Periodic Hue Accuracy 0.5 Degrees Color Saturation Accuracy 0.7 % Chroma Nonlinear Gain 0.7 0.9 ± %Referenced to 40 IRE Chroma Nonlinear Phase 0.5 ±Degrees Chroma/Luma Intermod 0.1 ± % Chroma/Luma Gain Ineq 1.7 ± % Chroma/Luma Delay Ineq 2.2 ns Luminance Nonlinearity 0.6 0.7 ± % Chroma AM Noise 82 dB Chroma PM Noise 72 dB

NOTES

All measurements are made in 4¥ Oversampling Mode unless otherwise speciﬁed.

Temperature range T

Values in parentheses apply to 2¥ Oversampling Mode.

Speciﬁcations subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

= 1.235 V, R

REF

to T

, unless otherwise noted.)

MAX

= 1200 , unless otherwise noted. All

SET1,2

3.3 V DYNAMIC–SPECIFICATIONS

(VAA = 3.3 V  150 mV, V

speciﬁcations T

MIN

to T

= 1.235 V, R

REF

, unless otherwise noted.)

MAX

SET1,2

= 1200 , unless otherwise noted. All

Parameter Min Typ Max Unit Test Conditions

Differential Gain Differential Phase SNR (Pedestal)

SNR (Ramp)

62.3 (62) dB rms RMS

0.2 (0.5) %

0.5 (0.2) Degrees

78.5 (78) dB rms RMS 78 (78) dB p-p Peak Periodic

61 (62.5) dB p-p Peak Periodic Hue Accuracy 0.5 Degrees Color Saturation Accuracy 0.8 % Chroma Nonlinear Gain 0.6 ±%Referenced to 40 IRE Chroma Nonlinear Phase 0.5 ±Degrees Chroma/Luma Intermod 0.1 ± % Luminance Nonlinearity 0.6 ±% Chroma AM Noise 83 dB Chroma PM Noise 71 dB

NOTES

All measurements are made in 4¥ Oversampling Mode unless otherwise speciﬁed.

Temperature range T

Values in parentheses apply to 2¥ Oversample Mode.

Speciﬁcations subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

REV. B

–5–

Page 6

ADV7190/ADV7191

5 V TIMING CHARACTERISTICS

(VAA = 5 V  250 mV, V T

MIN

to T

, unless otherwise noted.)

MAX

= 1.235 V, R

REF

= 1200 , unless otherwise noted. All speciﬁcations

SET1,2

Parameter Min Typ Max Unit Test Conditions

MPU PORT

SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth, t SCLOCK Low Pulsewidth, t Hold Time (Start Condition), t Setup Time (Start Condition), t Data Setup Time, t

SDATA, SCLOCK Rise Time, t SDATA, SCLOCK Fall Time, t Setup Time (Stop Condition), t

ANALOG OUTPUTS

0.6 ms

1.3 ms

0.6 ms

After This Period, the First Clock is Generated

0.6 msRelevant for Repeated Start Condition 100 ns

300 ns 300 ns

0.6 ms

Analog Output Delay 8 ns DAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXEL PORT

CLOCK

Clock High Time, t Clock Low Time, t Data Setup Time, t Data Hold Time, t Control Setup Time, t Control Hold Time, t Digital Output Access Time, t Digital Output Hold Time, t Pipeline Delay, t

(2¥ Oversampling) 57 Clock Cycles

27 MHz 8ns 8ns 6ns 5ns 6ns 4ns

13 ns

12 ns

Pipeline Delay, t15 (4¥ Oversampling) 67 Clock Cycles

TELETEXT PORT

Digital Output Access Time, t Data Setup Time, t Data Hold Time, t

11 ns

3ns

6ns

RESET CONTROL

RESET Low Time 3 20 ns

PLL

PLL Output Frequency 54 MHz

NOTES

Temperature range T

Guaranteed by characterization.

Pixel Port consists of: Data: P15–P0 Pixel Inputs, Control: HSYNC, VSYNC, BLANK, Clock: CLKIN Input.

Teletext Port consists of: Digital Output: TTXREQ, Data: TTX.

Speciﬁcations subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

–6–

REV. B

Page 7

ADV7190/ADV7191

3.3 V TIMING CHARACTERISTICS

(VAA = 3.3 V  150 mV, V speciﬁcations T

MIN

to T

= 1.235 V, R

REF

, unless otherwise noted2.)

MAX

SET1,2

= 1200 , unless otherwise noted. All

Parameter Min Typ Max Unit Test Conditions

MPU PORT

SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth, t SCLOCK Low Pulsewidth, t Hold Time (Start Condition), t Setup Time (Start Condition), t Data Setup Time, t

SDATA, SCLOCK Rise Time, t SDATA, SCLOCK Fall Time, t Setup Time (Stop Condition), t

0.6 ms

1.3 ms

0.6 msAfter This Period, the First Clock is Generated

0.6 msRelevant for Repeated Start Condition 100 ns

300 ns 300 ns

0.6 2 ms

ANALOG OUTPUTS

Analog Output Delay 8 ns DAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXEL PORT

CLOCK

Clock High Time, t Clock Low Time, t Data Setup Time, t Data Hold Time, t Control Setup Time, t Control Hold Time, t Digital Output Access Time, t Digital Output Hold Time, t Pipeline Delay, t

(2¥ Oversampling) 57 Clock Cycles

27 MHz 8ns 8ns 6ns 4ns

2.5 ns 3ns

13 ns

12 ns

Pipeline Delay, t15 (4¥ Oversampling) 67 Clock Cycles

TELETEXT PORT

Digital Output Access Time, t Data Setup Time, t Data Hold Time, t

11 ns

3ns

6ns

RESET CONTROL

RESET Low Time 3 20 ns

PLL

PLL Output Frequency 54 MHz

NOTES

Temperature range T

Guaranteed by characterization.

Pixel Port consists of: Data: P15–P0 Pixel Inputs, Control: HSYNC, VSYNC , BLANK, Clock: CLKIN Input.

Teletext Port consists of: Digital Output: TTXREQ, Data: TTX.

Speciﬁcations subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

REV. B

–7–

Page 8

ADV7190/ADV7191

SDA

SCL

CLOCK

Figure 1. MPU Port Timing Diagram

TTXREQ

CLOCK

TTX

CONTROL

I/PS

O/PS

HSYNC, VSYNC,

BLANK

PIXEL INPUT

DATA

HSYNC,

VSYNC,

BLANK,

CSO_HSO,

VSO, CLAMP

4 CLOCK

CYCLES

Cb Y Cr Y Cb Y

Figure 2. Pixel and Control Data Timing Diagram

4 CLOCK

CYCLES

4 CLOCK

CYCLES

Figure 3. Teletext Timing Diagram

3 CLOCK

CYCLES

4 CLOCK

CYCLES

–8–

REV. B

Page 9

ADV7190/ADV7191

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Input Pin . . . . GND – 0.5 V to V

Storage Temperature (T Junction Temperature (T

) . . . . . . . . . . . . . . –65∞C to +150∞C

) . . . . . . . . . . . . . . . . . . . . . 150∞C

+ 0.5 V

Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . 220∞C

Analog Outputs to GND2 . . . . . . . . . . . . GND – 0.5 to V

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Analog output short circuit to any power supply or common can be of an indeﬁnite

duration.

PIN CONFIGURATION

AGND

64 63 62 61 60 55 54 53 52 51 50 4959 58 57 56

P0 P1

P3 P4

P6 P7

P8 P9

P10

P11 P12

P13

P14 P15

NC = NO CONNECT

PIN 1

IDENTIFIER

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AGND

VSYNC

HSYNC

ADV7190/ADV7191

LQFP

TOP VIEW

(Not to Scale)

ALSB

AGND

BLANK

TTXREQ

PACKAGE THERMAL PERFORMANCE

The 64-lead package is used for this device. The junction-toambient (q

) thermal resistance in still air on a four-layer PCB

is 38∞C/W.

To reduce power consumption when using this part, the user can run the part on a 3.3 V supply, and turn off any unused DACs.

The user must at all times stay below the maximum junction temperature of 110∞C. The following equation shows how to calculate this junction temperature:

Junction Temperature = (V

= 10 mA + (sum of the average currents consumed by

DAC

¥ (I

DAC

+ I

)) ¥ qJA + 70∞C T

CCT

AMB

each powered-on DAC)

Average current consumed by each powered-on DAC =

¥ K )/R

REF

= 1.235 V

SET

K = 4.2146

NTSC

VSO/CLAMP

TTX

AGND

CLKIN

CLKOUT

PAL

SCL

RESET

CSO_HSO

SET1

REF

COMP 1

DAC A

DAC B V

AGND

DAC C

DAC D

AGND

DAC E

DAC F

COMP 2

SET2

AGND

SDA

SCRESET/RTC/TR

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7190KST 0∞C to 70∞C 64-Lead Quad Flatpack ST-64 ADV7191KST 0∞C to 70∞C 64-Lead Quad Flatpack ST-64

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7190/ADV7191 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–9–

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ADV7190/ADV7191

PIN FUNCTION DESCRIPTIONS

Pin Input/ No. Mnemonic Output Function

1–16 P0–P15 I 8-Bit or 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on

Pin P0.

17, 25, 29, V

38, 43, 54, 63

18, 24, 26, AGND G Analog Ground. 33, 39, 42, 55, 64

19 HSYNC I/O HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be conﬁgured to be an output

20 VSYNC I/O VSYNC Control Signal. This pin may be conﬁgured as an output (Master Mode) or as an

21 BLANK I/O Video Blanking Control Signal. This signal is optional. For further information see Vertical

22 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address. 23 TTXREQ O Teletext Data Request Output Signal, used to control teletext data transfer. 27 CLKIN I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alterna-

28 CLKOUT O Clock Output Pin. 30 SCL I MPU Port Serial Interface Clock Input. 31 SDA I/O MPU Port Serial Data Input/Output. 32 SCRESET/ I Multifunctional Input: Real-Time Control (RTC) Input, Timing Reset Input, Subcarrier Reset

RTC/TR Input.

34 R

SET2

35 COMP 2 O Compensation Pin for DACs D, E, and F. Connect a 0.1 mF Capacitor from COMP2 to V 36 DAC F O S-Video C/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. 37 DAC E O S-Video Y/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. 40 DAC D O Composite/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output. 41 DAC C O S-Video C/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. 44 DAC B O S-Video Y/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. 45 DAC A O Composite/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output. 46 COMP 1 O Compensation Pin for DACs A, B, and C. Connect a 0.1 mF Capacitor from COMP1 to V 47 V

48 R

REF

SET1

49 RESET IThe input resets the on-chip timing generator and sets the ADV7190/ADV7191 into default

50 CSO_HSO ODual Function CSO or HSO Output Sync Signal at TTL Level. 51 VSO/CLAMP I/O Multifunction Pin. VSO Output Sync Signal at TTL level. CLAMP TTL Output Signals

52 PAL_NTSC I Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL. 53, 57–62 NC No Connect. 56 TTX I Teletext Data Input Pin.

PAnalog Power Supply (3.3 V to 5 V).

(Master Mode) or an input (Slave Mode) and accept Sync Signals.

input (Slave Mode) and accept VSYNC as a Control Signal.

Blanking Data Insertion and BLANK Input section.

tively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

IA 1200 W resistor connected from this pin to ground is used to control full-scale amplitudes

of the Video Signals from DACs D, E, and F.

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external

cannot be used in 4¥ oversampling mode.

REF

IA 1200 W resistor connected from this pin to ground is used to control full-scale amplitudes

of the Video Signals from DACs A, B, and C.

mode. See Appendix 8 for Default Register settings.

can be used to drive external circuitry to enable clamping of all Video Signals.

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ADV7190/ADV7191

DETAILED DESCRIPTION OF FEATURES Clocking:

Single 27 MHz Clock Required to Run the Device 4 Oversampling with Internal 54 MHz PLL

Square Pixel Operation Advanced Power Management Programmable Video Control Features:

Digital Noise Reduction

Pedestal level

Hue, Brightness, Contrast and Saturation

Clamping Output Signal

VBI (Vertical Blanking Interval)

Subcarrier Frequency and Phase

LUMA Delay

CHROMA Delay

Gamma Correction

Luma and Chroma Filters

Luma SSAF (Super Subalias Filter) Average Brightness Detection Field Counter Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Programmable Multimode Master/Slave Operation CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Macrovision 7.1 Rev (ADV7190 Only) Closed Captioning Support Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface

C Registers Synchronized to VSYNC

(continued from page 1)

GENERAL DESCRIPTION

The ADV7190/ADV7191 is an integrated Digital Video Encoder that converts digital CCIR-601/656 4:2:2 8-bit or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards.

Six DACs are available on the ADV7190/ADV7191, each of which is capable of providing 4.33 mA of current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video and YUV Video. All YUV formats (Betacam, MII and (SMPTE/EBU N10) are supported.

Digital Noise Reduction allows improved picture quality in removing low amplitude, high frequency noise. The block diagram below shows the DNR functionality in the two modes available.

DNR MODE

Y DATA

INPUT

DNR CONTROL

BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

FILTER OUTPUT

<THRESHOLD?

FILTER OUTPUT>

THRESHOLD

GAIN

CORING GAIN DATA CORING GAIN BORDER

SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL

DNR OUT

DNR SHARPNESS MODE

Y DATA

INPUT

DNR CONTROL

BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

FILTER OUTPUT

>THRESHOLD?

FILTER OUTPUT<

THRESHOLD

GAIN

CORING GAIN DATA CORING GAIN BORDER

ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL

DNR OUT

Figure 5. Block Diagram for DNR Mode and DNR Sharpness Mode

HSYNC

VSYNC

BLANK

RESET

TTXREQ

CLKIN

CLKOUT

REV. B

TTX

P15

PAL_NTSC

YCrCb

YUV

MATRIX

10 1010

DEMUX

VSO/CLAMP

VIDEO TIMING

GENERATOR

TELETEXT

INSERTION

BLOCK

CORRECTION

PLL

DNR AND

GAMMA

CSO_HSO

CLOSED CAPTIONING

BRIGHTNESS

CONTROL

ADD SYNC

INTERPOLATOR

SATURATION

CONTROL

ADD BURST

INTERPOLATOR

ADV7190/ADV7191

CGMS/WSS

AND

CONTROL

AND

I2C MPU PORT

PROGRAMMABLE

LUMA FILTER

AND

SHARPNESS

FILTER

PROGRAMMABLE

CHROMA

FILTER

REAL-TIME

CONTROL

CIRCUIT

SCRESET/RTC/TR

ALSBSDASCL

MODULATOR

HUE CONTROL

YUV-TO-RGB

MATRIX

AND

YUV LEVEL

CONTROL

BLOCK

AND

SIN/COS

DDS

BLOCK

M U L T

I P L E X E R

10-BIT

DAC

T E

10-BIT

DAC

P O

10-BIT

DAC A T O R

DAC

CONTROL

BLOCK

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

CONTROL

BLOCK

I N T E R P O L A T O R

DAC A

DAC B

DAC C

REF

SET2

COMP2

DAC D

DAC F

DAC E

SET1

COMP1

Figure 4. Detailed Functional Block Diagram

–11–

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ADV7190/ADV7191

Programmable gamma correction is also available. Figure 6 shows the response of different gamma values to a ramp signal.

300

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES

250

200

150

100

GAMMA–CORRECTED AMPLITUDE

050100 150 200 250

SIGNAL OUTPUTS

0.3

0.5

1.5

SIGNAL INPUT

LOCATION

1.8

Figure 6. Signal Input (Ramp) and Selectable Gamma Output Curves

The on-board SSAF (Super Subalias Filter) with extended luminance frequency response and sharp stopband attenuation enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An additional sharpness control feature allows high-frequency enhancement on the luminance signal.

The device is driven by a 27 MHz clock. Data can be output at 27 MHz or 54 MHz (on-board PLL) when 4 enabled. Also, the output filter requirements in 4

⫻

oversampling is

⫻

oversampling

and 2⫻ oversampling differ, as can be seen in Figure 7.

0dB

–30dB

2 FILTER REQUIREMENTS

4 FILTER REQUIREMENTS

6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz

Figure 7. Output Filter Requirements in 4¥Oversampling Mode

54MHz



E R P O L A T

I O N

54MHz

OUTPUT

RATE

T P U T S

MPEG2

PIXEL BUS

27MHz

ADV7190/ADV7191

ENCODER

CORE

PLL

Figure 8. PLL and 4¥ Oversampling Block Diagram

The ADV7190/ADV7191 also supports both PAL and NTSC square pixel operation. In this case the encoder requires a

24.5454 MHz Clock for NTSC or 29.5 MHz Clock for PAL square pixel mode operation. All internal timing is generated on-chip.

An advanced power management circuit enables optimal control of power consumption in normal operating modes or sleep modes.

The Output Video Frames are synchronized with the incoming data Timing Reference Codes. Optionally, the Encoder accepts (and can generate) HSYNC, VSYNC, and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in master mode.

HSO/CSO and VSO TTL outputs are also available and are timed to the analog output video.

A separate teletext port enables the user to directly input teletext data during the vertical blanking interval.

The ADV7190/ADV7191 also incorporates WSS and CGMS-A data control generation. The ADV7190 incorporates Macrovision Rev 7.1.

The ADV7190/ADV7191 modes are set up over a 2-wire serial bidirectional port (I

C-compatible) with two slave addresses, and the device is register-compatible with the ADV7172/ADV7173.

The ADV7190ADV7191 is packaged in a 64-lead LQFP package.

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb 4:2:2 Data is input via the CCIR-656/601-compatible Pixel Port at a 27 MHz data rate. The pixel data is demultiplexed to form three data paths. Y typically has a range of 16 to 235, Cr and Cb typically have a range of 128+/–112; however, it is possible to input data from 1 to 254 on both Y, Cb, and Cr. The ADV7190/ADV7191 supports PAL (B, D, G, H, I, N) and NTSC M, N (with and without Pedestal) PAL.M (ADV7190 only) and PAL60 standards. Digital Noise Reduction can be applied to the Y signal. Programmable gamma correction can also be applied to the Y signal if required.

The Y data can be manipulated for contrast control and a set-up level can be added for brightness control. The Cr, Cb data can be scaled to achieve color saturation control. All settings become effective at the start of the next ﬁeld when double buffering is enabled.

The appropriate sync, blank, and burst levels are added to the YCrCb data. Macrovision antitaping, (ADV7190 only) ClosedCaptioning, and Teletext levels are also added to Y and the resultant data is interpolated to 54 MHz when 4¥ Oversampling is enabled. The interpolated data is ﬁltered and scaled by three digital FIR ﬁlters.

The U and V signals are modulated by the appropriate Subcarrier Sine/Cosine waveforms and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. The resulting U and V signals are added together to make up the Chrominance Signal. The Luma (Y) signal can be delayed by up to six clock cycles (at 27 MHz) and the Chroma signal can be delayed by up to eight clock cycles (at 27 MHz). The

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ADV7190/ADV7191

Luma and Chroma Signals are added together to make up the Composite Video Signal. All timing signals are controlled.

The YCrCb data is also used to generate RGB data with appropriate sync and blank levels. The YUV levels are scaled to output the suitable SMPTE/EBU N10, MII, or Betacam levels.

Each DAC can be individually powered off if not required. A complete description of DAC output conﬁgurations is given in the MR2 Bit Description section.

Video output levels are illustrated in Appendix 9.

Table I. Luminance Internal Filter Speciﬁcations (4 Oversampling)

Filter Type Filter Selection Ripple1 (dB) (MHz)

MR04 MR03 MR02

Low-Pass (NTSC) 0 0 0 0.16 4.24 Low-Pass (PAL) 0 0 1 0.1 4.81 Notch (NTSC) 0 1 0 0.09 2.3/4.9/6.6 Notch (PAL) 0 1 1 0.1 3.1/5.6/6.4 Extended (SSAF) 1 0 0 0.04 6.45 CIF 1 0 1 0.127 3.02 QCIF 1 1 0 Monotonic 1.5

NOTES

Passband ripple is deﬁned to be fluctuations from the 0 dB response in the passband, measured in (dB). The passband is deﬁned to have 0-fc frequency limits for a low-pass ﬁlter, 0–f1 and f2–inﬁnity for a notch ﬁlter, where fc, f1, f2 are the –3 dB points.

3 dB bandwidth refers to the –3 dB cutoff frequency.

INTERNAL FILTER RESPONSE

The Y Filter supports several different frequency responses including two low-pass responses, two notch responses, an Extended (SSAF) response with or without gain boost/attenuation, a CIF response and a QCIF response. The UV Filter supports several different frequency responses including ﬁve low-pass responses, a CIF response and a QCIF response, as can be seen on the following pages.

In Extended Mode there is the option of twelve responses in the range from –4 dB to +4 dB. The desired response can be chosen by the user by programming the correct value via the I2C. The variation of frequency responses can be seen on the following pages. For more detailed plots refer to AN-562 Analog Devices’ Application note.

Passband 3 dB Bandwidth

Table II. Chrominance Internal Filter Speciﬁcations (4 Oversampling)

Passband 3 dB Bandwidth

Filter Type Filter Selection Ripple1 (dB) (MHz)

MR07 MR06 MR05

1.3 MHz Low-Pass 0 0 0 0.09 1.395

0.65 MHz Low-Pass 0 0 1 Monotonic 0.65

1.0 MHz Low-Pass 0 1 0 Monotonic 1.0

2.0 MHz Low-Pass 0 1 1 0.048 2.2

3.0 MHz Low-Pass 1 1 1 Monotonic 3.2 CIF 1 0 1 Monotonic 0.65 QCIF 1 1 0 Monotonic 0.5

NOTES

3 dB bandwidth refers to the –3 dB cutoff frequency.

REV. B

–13–

Page 14

ADV7190/ADV7191

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 9. NTSC Low-Pass Luma Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 12. NTSC Notch Luma Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 10. PAL Low-Pass Luma Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 11. Extended Mode (SSAF) Luma Filter

–60

–70

24 10

FREQUENCY – MHz

Figure 13. PAL Notch Luma Filter

MAGNITUDE – dB

–1

FREQUENCY – MHz

Figure 14. Extended SSAF and Programmable Gain, Showing Range 0 dB/+4 dB Range

–14–

REV. B

Page 15

ADV7190/ADV7191

–1

–2

MAGNITUDE – dB

–3

–4

–5

FREQUENCY – MHz

Figure 15. Extended SSAF and Programmable Attenuation, Showing Range 0 dB/–4 dB

–2

–4

–6

MAGNITUDE – dB

–8

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 18. QCIF Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–12

FREQUENCY – MHz

Figure 16. Extended SSAF and Programmable Attenuation, Showing Range +4 dB/–12 dB

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 17. Luma CIF Filter

–70

24 10

FREQUENCY – MHz

Figure 19. Chroma 0.65 MHz Low-Pass Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 20. Chroma 1.0 MHz Low-Pass Filter

REV. B

–15–

Page 16

ADV7190/ADV7191

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 21. Chroma 1.3 MHz Low-Pass Filter

–10

–20

–30

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 24. Chroma CIF Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 22. Chroma 2 MHz Low-Pass Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

–40

MAGNITUDE – dB

–50

–60

–70

24 10

FREQUENCY – MHz

Figure 25. Chroma QCIF Filter

Figure 23. Chroma 3 MHz Low-Pass Filter

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ADV7190/ADV7191

FEATURES: FUNCTIONAL DESCRIPTION Brightness Detect

This feature is used to monitor the average brightness of the incoming Y signal on a ﬁeld-by-ﬁeld basis. The information is read from the I

C and based on this information, the color saturation, contrast and brightness controls can be adjusted (for example to compensate for very dark pictures). (Brightness Detect Register.)

Chroma/Luma Delay

The luminance data can be delayed by maximum of six clock cycles. Additionally the Chroma can be delayed by a maximum of eight clock cycles (one clock cycle at 27 MHz). (Timing Register 0 and Mode Register 9.)

CHROMA DELAY

LUMA DELAY

Figure 26. Chroma Delay Figure 27. Luma Delay

Clamp Output

The ADV7190/ADV7191 has a programmable clamp TTL output signal. This clamp signal is programmable to the front and back porch. The clamp signal can be varied by one to three clock cycles in a positive and negative direction from the default position. (Mode Register 5, Mode Register 7.)

CLAMP O/P SIGNALS

CVBS OUTPUT PIN

MR57 = 1

MR57 = 0

CLAMP OUTPUT PIN

Figure 28. Clamp Output Timing

CSO, HSO, and VSO Outputs

The ADV7190/ADV7191 supports three output timing signals, CSO (Composite Sync Signal), HSO (Horizontal Sync Signal) and VSO (Vertical Sync Signal). These output TTL signals are aligned with the analog video outputs. See Figure 29 for an example of these waveforms. (Mode Register 7.)

EXAMPLE:- NTSC

OUTPUT

525 1 234567891011–19

VIDEO

CSO

HSO

VSO

Figure 29.

CSO, HSO, VSO

Timing Diagram

Color Bar Generation

The ADV7190/ADV7191 can be conﬁgured to generate 100/

7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for PAL. (Mode Register 4.)

Color Burst Signal Control

The burst information can be switched on and off the composite and chroma video output. (Mode Register 4.)

Color Controls

The ADV7190/ADV7191 allows the user to control the brightness, contrast, hue, and saturation of the color. The control registers may be double-buffered, meaning that any modiﬁcation to the registers will be done outside the active video region and, therefore, changes made will not be visible during active video.

Contrast Control

Contrast adjustment is achieved by scaling the Y input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 150%. (Contrast Control Register.)

Brightness Control

The brightness is controlled by adding a programmable setup level onto the scaled Y data.

For NTSC with pedestal, the setup can vary from 0 IRE to

22.5 IRE. For NTSC without pedestal and PAL, the setup can vary from –7.5 IRE to +15 IRE. (Brightness Control Register.)

Color Saturation

Color adjustment is achieved by scaling the Cr and Cb input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 200%. (U Scale Register and V Scale Register.)

Hue Adjust Control

The hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodiﬁed, i.e., only the phase between the video and the colorburst is modiﬁed and thus the hue is shifted. The ADV7190/ADV7191 provides a range of ± 22∞ in increments of 0.17578125∞. (Hue Adjust Register.)

Chrominance Control

The color information can be switched on and off the composite, chroma and color component video outputs. (Mode Register 4.)

Undershoot Limiter

A limiter is placed after the digital ﬁlters. This prevents any synchronization problems for TVs. The level of undershoot is programmable between –1.5 IRE, –6 IRE, –11 IRE when operating in 4¥ Oversampling. In 2¥ Oversampling mode the limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing Register 0.)

Digital Noise Reduction

DNR is applied to the Y data only. A ﬁlter block selects the high frequency, low amplitude components of the incoming signal (DNR Input Select). The absolute value of the ﬁlter output is compared to a programmable threshold value (DNR Threshold Control).

Two DNR modes are available: DNR Mode and DNR Sharpness Mode.

REV. B

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ADV7190/ADV7191

In DNR Mode, if the absolute value of the ﬁlter output is smaller than the threshold, it is assumed to be noise. A programmable amount (Coring Gain Control) of this noise signal will be subtracted from the original signal.

In DNR Sharpness Mode, if the absolute value of the ﬁlter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identiﬁed as a valid signal, a fraction of the signal (Coring Gain Control) will be added to the original signal in order to boost high frequency components and to sharpen the video image.

In MPEG systems it is common to process the video information in blocks of 8 ¥ 8 pixels for MPEG2 systems, or 16 ¥ 16 pixels for MPEG1 systems (Block Size Control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally the block transition area contains two pixels. It is possible to deﬁne this area to contain four pixels (Border Area Control).

It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the (Block Offset Control). See Figure 82 for further information. (Mode Register 8, DNR Registers 0–2.)

Double Buffering

Double buffering can be enabled or disabled on the following registers: Closed Captioning Registers, Brightness Control, V Scale, U Scale, Contrast Control, Hue Adjust, the Gamma Curve Select bit, and Macrovision Registers (ADV7190 only). These registers are updated once per ﬁeld on the falling edge of the VSYNC signal. Double buffering improves the overall performance of the ADV7190/ADV7191, since modiﬁcations to register settings will not be made during active video, but take effect on the start of the active video. (Mode Register 8.)

Gamma Correction Control

Gamma correction may be performed on the luma data. The user has the choice to use either of two different gamma curves, A or B. At any one time one of these curves is operational if gamma correction is enabled. Gamma correction allows the mapping of the luma data to a user-deﬁned function. (See Gamma Correction Registers 0–13 section.) (Mode Register 8, Gamma Correction Registers 0–13.)

NTSC Pedestal Control

In NTSC mode it is possible to have the pedestal signal generated on the output video signal. (Mode Register 2.)

Power-On Reset

After power-up, it is necessary to execute a RESET operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port such that the data on the pixel input pins is ignored. See Appendix 8 for the register settings after RESET is applied.

Real-Time Control, Subcarrier Reset, and Timing Reset

Together with the SCRESET/RTC/TR pin of Mode Register 4 (Genlock Control), the ADV7190/ADV7191 can be used in (a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or (c) RTC Mode.

(a) A TIMING RESET is achieved in holding this pin high. In

this state the horizontal and vertical counters will remain reset. On releasing this pin (set to low), the internal counters will

(b) The SUBCARRIER PHASE will reset to that of Field 0 at

SCH Phase Mode

The SCH phase is conﬁgured in default mode to reset every four (NTSC) or eight (PAL) ﬁelds to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH.

Resetting the SCH phase every four or eight ﬁelds avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight ﬁeld sequence.

Automatically resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7190/ ADV7191 is conﬁgured in RTC mode. Under these conditions (unstable video) the Subcarrier Phase Reset should be enabled but no reset applied. In this conﬁguration the SCH Phase will never be reset; this means that the output video will now track the unstable input video.

The Subcarrier Phase Reset, when applied, will reset the SCH phase to Field 0 at the start of the next ﬁeld (e.g., Subcarrier Phase Reset applied in Field 5 (PAL) on the start of the next ﬁeld SCH phase will be reset to Field 0). (Mode Register 4.)

Sleep Mode

If, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins are both set high, the ADV7190/ADV7191 will power up in Sleep Mode to facilitate low power consumption before all registers have been initialized. If Power-Up in Sleep Mode is disabled, Sleep Mode control passes to the Sleep Mode control in Mode Register 2 (i.e., control via I and Mode Register 6.)

Square Pixel Mode

The ADV7190/ADV7191 can be used to operate in square pixel mode. For NTSC operation an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. Square pixel mode is not available in 4¥ Oversampling mode. (Mode Register 2.)

commence counting again. The minimum time the pin has to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise the reset signal might not be recognized.

the start of the following ﬁeld when a low-to-high transition occurs on this input pin.

lock to an external video source.

The real-time control mode allows the ADV7190/ADV7191 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital datastream in the RTC format such as an ADV7185 video decoder (see Figure 32), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital datastream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00Hex should be written into all four Subcarrier Frequency registers when using this mode. It is recommended to use the ADV7185 in this mode. (Mode Register 4.)

C). (Mode Register 2

–18–

REV. B

Page 19

ADV7190/ADV7191

Vertical Blanking Data Insertion and BLANK Input

It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not have line sync or pre-/postequalization pulses (see Figures 34 to 45). This mode of operation is called Partial Blanking. It allows the insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines. VBI is available in all timing modes.

It is possible to allow control over the BLANK signal using Timing Register 0. When the BLANK input is enabled (TR03 = 0 and input pin tied low), the BLANK input can be used to input externally generated blank signals in Slave Mode 1, 2, or 3. When the BLANK input is disabled (TR03 = 1 and input pin tied low or tied high), the BLANK input is not used and the ADV7190/ ADV7191 automatically blanks all normally blank lines as per CCIR-624. (Timing Register 0.)

YUV Levels

This functionality allows the ADV7190/ADV7191 to output SMPTE levels or Betacam levels on the Y output when conﬁgured in PAL or NTSC mode.

Sync Video

Betacam 286 mV 714 mV SMPTE 300 mV 700 mV MII 300 mV 700 mV

As the data path is branched at the output of the ﬁlters the luma signal relating to the CVBS or S-Video Y/C output is unaltered. It is only the Y output of the YCrCb outputs that is scaled. This control allows color component levels to have a peak-peak amplitude of 700 mV, 1000 mV or the default values of 934 mV in NTSC and 700 mV in PAL. (Mode Register 5.)

16-Bit Interface

It is possible to input data in 16-bit format. In this case, the interface only operates if the data is accompanied by separate HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not available in Slave Mode 0 since EAV/SAV timing codes are used. (Mode Register 8.)

4 Oversampling and Internal PLL

It is possible to operate all six DACs at 27 MHz (2¥ Oversam- pling) or 54 MHz (4¥ Oversampling).

The ADV7190/ADV7191 is supplied with a 27 MHz clock synced with the incoming data. Two options are available: to run the device throughout at 27 MHz or to enable the PLL. In the latter case, even if the incoming data runs at 27 MHz, 4¥ Oversam- pling and the internal PLL will output the data at 54 MHz.

NOTE In 4¥ Oversampling Mode the requirements for the optional output ﬁlters are different from those in 2¥ Oversampling. (Mode Register 1, Mode Register 6.) See Appendix 6 for further details.

ENCODER

ADV7190/ADV7191

MPEG2

PIXEL BUS

27MHz

2 FILTER

REQUIREMENTS

ENCODER

CORE

54MHz

PLL

FREQUENCY – MHz

T E R P



L A

I O N

REQUIREMENTS

27.0 40.5 54.013.56.75

D A C

4 FILTER

O U T

54MHz

OUTPUT

U T S

Figure 30. PLL and 4 Oversampling Block Diagram

VIDEO TIMING DESCRIPTION

The ADV7190/ADV7191 is intended to interface to off-theshelf MPEG1 and MPEG2 Decoders. As a consequence, the ADV7190/ADV7191 accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has several Video Timing Modes of operation that allow it to be conﬁgured as either System Master Video Timing Generator or a Slave to the System Video Timing Generator. The ADV7190/ADV7191 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs.

The ADV7190/ADV7191 calculates the width and placement of analog sync pulses, blanking levels, and color burst envelopes. Color bursts are disabled on appropriate lines and serration and equalization pulses are inserted where required.

In addition, the ADV7190/ADV7191 supports a PAL or NTSC square pixel operation. The part requires an input pixel clock of

24.5454 MHz for NTSC square pixel operation and an input pixel clock of 29.5 MHz for PAL square pixel operation. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies.

The ADV7190/ADV7191 has four distinct Master and four distinct Slave timing conﬁgurations. Timing Control is established with the bidirectional HSYNC, BLANK, and VSYNC pins. Timing Register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. (Mode Register 2, Timing Register 0, 1.)

RESET SEQUENCE

When RESET becomes active the ADV7190/ADV7191 reverts to the default output conﬁguration (see Appendix 8 for register settings). The ADV7190/ADV7191 internal timing is under the control of the logic level on the NTSC_PAL pin.

REV. B

–19–

Page 20

ADV7190/ADV7191

When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV7190/ADV7191. Output timing signals are still suppressed at this stage. DACs A, B, C are switched off and DACs D, E, F are switched on.

When the user requires valid data, Pixel Data Valid Control is enabled (MR26 = 1) to allow the valid pixel data to pass through the encoder. Digital output timing signals become active and the encoder timing is now under the control of the Timing Registers. If at this stage, the user wishes to select a different video standard

RESET

DAC D, DAC E

DAC A, DAC B, DAC C

PIXEL_DATA_VALID

DIGITAL TIMING

XXXXXXX XXXXXXX

DAC F

XXXXXXX XXXXXXX

XXXXXXX

MR26

XXXXXXX

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

to that on the NTSC_PAL pin, Standard I2C Control should be enabled (MR25 = 1) and the video standard required is selected by programming Mode Register 0 (Output Video Standard Selection). Figure 31 illustrates the RESET sequence timing.

BLACK VALUE WITH SYNC

BLACK VALUE

VALID VIDEO

TIMING ACTIVE

Figure 31.

RESET

Sequence Timing Diagram

–20–

REV. B

Page 21

ADV7190/ADV7191

RTC

CLOCK

COMPOSITE

VIDEO

e.g., VCR

OR CABLE

H/L TRANSITION

COUNT START

TIME SLOT: 01

NOTES:

FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7190/ADV7191. FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7190/ADV7191.

SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE

RESET BIT RESET ADV7190/ADV7191’s DDS

128

LOW

DECODER

ADV7185

14 BITS

RESERVED

NOT USED IN

ADV7190/

ADV7191

VIDEO

LCC1

P19–P12

4 BITS

RESERVED

GLL

21013

SCRESET/RTC/TR

P7–P0

SAMPLE

ADV7190/ADV7191

PLL INCREMENT

VALID

INVALID SAMPLE

GREEN/ COMPOSITE/ Y

BLUE/ LUMA/U

RED/ CHROMA/ V

GREEN/ COMPOSITE/ Y

BLUE/ LUMA/U

RED/ CHROMA/ V

RESERVED

8/LINE

LOCKED CLOCK

SEQUENCE

5 BITS

BIT

Figure 32. RTC Timing and Connections

67 68

RESET

BIT

RESERVED

Mode 0 (CCIR–656): Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7190/ADV7191 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 33. The

HSYNC

, VSYNC and

BLANK pins (if not used) should be tied high during this mode.

ANALOG

VIDEO

EAV CODE SAV CODE

INPUT PIXELS

NTSC/ PAL M SYSTEM

(525 LlNES/ 60Hz)

PAL SYSTEM

(625 LINES/ 50Hz)

FF0000XY8

4 CLOCK

END OF ACTIVE

VIDEO LINE

10801

FF00FFABABAB80108

ANCILLARY DATA

(HANC)

268 CLOCK

280 CLOCK

000

10F

4 CLOCK

START OF ACTIVE

VIDEO LINE

CrC

1440 CLOCK

Figure 33. Timing Mode 0, Slave Mode

REV. B

–21–

Page 22

ADV7190/ADV7191

Mode 0 (CCIR–656): Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7190/ADV7191 generates H, V, and F signals required for the SAV and EAV Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated in Figure 34 (NTSC) and Figure 35 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 36.

DISPLAY

522 523 524 525 1 2 3 4

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

ODD FIELD

ODD FIELDEVEN FIELD

EVEN FIELD

VERTICAL BLANK

Figure 34. Timing Mode 0, NTSC Master Mode

DISPLAY

10 11 20 21 22

DISPLAY

283

284

285

DISPLAY

622 623 624 625 1 2 3 4

F ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 314 315 316 317

ODD FIELD

313

EVEN FIELD

Figure 35. Timing Mode 0, PAL Master Mode

VERTICAL BLANK

318

319 320

DISPLAY

22 23

DISPLAY

335 336

334

–22–

REV. B

Page 23

ADV7190/ADV7191

ANALOG

VIDEO

Figure 36. Timing Mode 0 Data Transitions, Master Mode

Mode 1: Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7190/ADV7191 accepts Horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 37 (NTSC) and Figure 38 (PAL).

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

DISPLAY

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

VERTICAL BLANK

678

VERTICAL BLANK

Figure 37. Timing Mode 1, NTSC

HSYNC

BLANK

FIELD

DISPLAY

622 623 624 625 1234

ODD FIELDEVEN FIELD

VERTICAL BLANK

10 11

21 22 23

DISPLAY

20 21 22

DISPLAY

283

284

DISPLAY

285

REV. B

HSYNC

BLANK

FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD EVEN FIELD

VERTICAL BLANK

Figure 38. Timing Mode 1, PAL

–23–

317

318 319

320

DISPLAY

334 335 336

Page 24

ADV7190/ADV7191

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7190/ADV7191 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 37 (NTSC) and Figure 38 (PAL). Figure 39 illustrates the HSYNC, BLANK and FIELD for an odd or even ﬁeld transition relative to the pixel data.

HSYNC

FIELD

BLANK

PIXEL

DATA

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/ 2

PAL = 132  CLOCK/2 NTSC = 122  CLOCK/2

Cb Y Cr Y

Figure 39. Timing Mode 1, Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7190/ADV7191 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC

and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL).

DISPLAY

20 21 22

HSYNC

BLANK

VSYNC

DISPLAY

522 523 524 525

1234

VERTICAL BLANK

678

ODD FIELDEVEN FIELD

10 11

HSYNC

BLANK

VSYNC

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

ODD FIELD EVEN FIELD

VERTICAL BLANK

Figure 40. Timing Mode 2, NTSC

–24–

283

284

DISPLAY

285

REV. B

Page 25

ADV7190/ADV7191

HSYNC

BLANK

VSYNC

HSYNC

BLANK

VSYNC

DISPLAY

622 623 624 625 1234

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD EVEN FIELD

VERTICAL BLANK

ODD FIELDEVEN FIELD

VERTICAL BLANK

317

318 319

21 22 23

320

DISPLAY

334 335 336

Figure 41. Timing Mode 2, PAL

Mode 2: Master Option HSYNC,

VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode the ADV7190/ADV7191 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). Figure 42 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd ﬁeld transition relative to the pixel data. Figure 43 illustrates the HSYNC, BLANK and VSYNC for an odd-to-even ﬁeld transition relative to the pixel data.

HSYNC

VSYNC

BLANK

PIXEL DATA

HSYNC

VSYNC

BLANK

PIXEL DATA

PAL = 12  CLOCK/2 NTSC = 16  CLOCK/2

Cb Y Cr Y

PAL = 132  CLOCK/2 NTSC = 122  CLOCK/2

Figure 42. Timing Mode 2, Even-to-Odd Field Transition Master/Slave

PAL = 12  CLOCK/2 NTSC = 16  CLOCK/2

PAL = 132  CLOCK/2 NTSC = 122  CLOCK/2

PAL = 864  CLOCK/2 NTSC = 858  CLOCK/2

Cb Y Cr Y Cb

Figure 43. Timing Mode 2, Odd-to-Even Field Transition Master/Slave

REV. B

–25–

Page 26

ADV7190/ADV7191

Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode the ADV7190/ADV7191 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 44 (NTSC) and Figure 45 (PAL).

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

DISPLAY

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

VERTICAL BLANK

678

VERTICAL BLANK

10 11

Figure 44. Timing Mode 3, NTSC

DISPLAY

VERTICAL BLANK

DISPLAY

20 21 22

DISPLAY

283

284

DISPLAY

285

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

622 623 624 625 1 2 3 4

ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

EVEN FIELD

ODD FIELD

VERTICAL BLANK

Figure 45. Timing Mode 3, PAL

317

318 319

320

21 22 23

DISPLAY

334 335 336

–26–

REV. B

Page 27

ADV7190/ADV7191

MPU PORT DESCRIPTION

The ADV7190/ADV7191 supports a two-wire serial (I2Ccompatible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7190/ ADV7191 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 46 and Figure 47. The LSB sets either a read or write operation. Logic Level 1 corresponds to a read operation while Logic Level 0 corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7190/ADV7191 to Logic Level 0 or Logic Level 1.

1 X1010 1A1

ADDRESS CONTROL

SETUP BY

ALSB

READ/ WRITE

CONTROL

0 WRITE 1 READ

Figure 46a. Slave Address for ADV7190

ADDRESS CONTROL

SETUP BY

ALSB

X1010 1A1

READ/ WRITE

CONTROL

0 WRITE 1 READ

Figure 46b. Slave Address for ADV7191

To control the various devices on the bus the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, deﬁned by a high-to-low transition on SDA while SCL remains high. This indicates that an address/ data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data.

A Logic 0 on the LSB of the ﬁrst byte means that the master will write information to the peripheral. A Logic 1 on the LSB of the ﬁrst byte means that the master will read information from the peripheral.

The ADV7190/ADV7191 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long supporting the 7-bit addresses plus the R/W bit. It interprets the ﬁrst byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. There is one exception. The Subcarrier Frequency Registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The autoincrement function should be then used to increment and access Subcarrier Frequency Registers 1, 2, and 3. The Subcarrier Frequency Registers should not be accessed independently.

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If, an invalid subaddress is issued by the user, the ADV7190/ ADV7191 will not issue an acknowledge and will return to the idle condition. If in autoincrement mode, the user exceeds the highest subaddress, the following action will be taken:

1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A noacknowledge condition is where the SDA line is not pulled low on the ninth pulse.

2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7190/ADV7191 and the part will return to the idle condition.

SDATA

SCLOCK

START ADDR

89 89 89 PS

1–7 1–7 1–7

ACK SUBADDRESS ACK DATA ACK STOP

R/W

Figure 47. Bus Data Transfer

Figure 47 illustrates an example of data transfer for a read sequence and the start and stop conditions.

Figure 48 shows bus write and read sequences.

REV. B

WRITE

SEQUENCE

READ

SEQUENCE

LSB = 0

S SLAVE ADDR A(S) SUB ADDR

S = START BIT P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER

Figure 48. Write and Read Sequences

DATA A(S)S SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 1

A(S) S SLAVE ADDR A(S) DATA

A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER

–27–

DATA

A(M)

A(S)

DATA P

A(M )

Page 28

ADV7190/ADV7191

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the ADV7190/ADV7191 with the exception of the Subaddress Registers, which are write-only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register. Then a read/write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed.

REGISTER PROGRAMMING

The following section describes each register. All registers can be read from as well as written to.

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR7

ZERO SHOULD

BE WRITTEN

HERE

ADDRESS SR6 SR5 SR4 SR3 SR2 SR1 SR0

00H 0 0 0 0 0 0 0 MODE REGISTER 0 01H 0 0 0 0 0 0 1 MODE REGISTER 1 02H 0 0 0 0 0 1 0 MODE REGISTER 2 03H 0 0 0 0 0 1 1 MODE REGISTER 3 04H 0 0 0 0 1 0 0 MODE REGISTER 4 05H 0 0 0 0 1 0 1 MODE REGISTER 5 06H 0 0 0 0 1 1 0 MODE REGISTER 6 07H 0 0 0 0 1 1 1 MODE REGISTER 7 08H 0 0 0 1 0 0 0 MODE REGISTER 8 09H 0 0 0 1 0 0 1 MODE REGISTER 9 0AH 0 0 0 1 0 1 0 TIMING REGISTER 0 0BH 0 0 0 1 0 1 1 TIMING REGISTER 1 0CH 0 0 0 1 1 0 0 SUBCARRIER FREQUENCY REGISTER 0 0DH 0 0 0 1 1 0 1 SUBCARRIER FREQUENCY REGISTER 1 0EH 0 0 0 1 1 1 0 SUBCARRIER FREQUENCY REGISTER 2 0FH 0 0 0 1 1 1 1 SUBCARRIER FREQUENCY REGISTER 3 10H 0 0 1 0 0 0 0 SUBCARRIER PHASE REGISTER 11H 0 0 1 0 0 0 1 CLOSED CAPTIONING EXTENDED DATA BYTE 0 12H 0 0 1 0 0 1 0 CLOSED CAPTIONING EXTENDED DATA BYTE 1 13H 0 0 1 0 0 1 1 CLOSED CAPTIONING DATA BYTE 0 14H 0 0 1 0 1 0 0 CLOSED CAPTIONING DATA BYTE 1 15H 0 0 1 0 1 0 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 0 16H 0 0 1 0 1 1 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 1 17H 0 0 1 0 1 1 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 2 18H 0 0 1 1 0 0 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 3 19H 0 0 1 1 0 0 1 CGMS/WSS 0 1AH 0 0 1 1 0 1 0 CGMS/WSS 1 1BH 0 0 1 1 0 1 1 CGMS/WSS 2 1CH 0 0 1 1 1 0 0 TELETEXT REQUEST CONTROL REGISTER 1DH 0 0 1 1 1 0 1 CONTRAST CONTROL REGISTER 1EH 0 0 1 1 1 1 0 U SCALE 1FH 0 0 1 1 1 1 1 V SCALE 20H 0 1 0 0 0 0 0 HUE ADJUST CONTROL REGISTER 21H 0 1 0 0 0 0 1 BRIGHTNESS CONTROL REGISTER 22H 0 1 0 0 0 1 0 SHARPNESS CONTROL REGISTER 23H 0 1 0 0 0 1 1 DNR 0 24H 0 1 0 0 1 0 0 DNR 1 25H 0 1 0 0 1 0 1 DNR 2 26H 0 1 0 0 1 1 0 GAMMA CORRECTION REGISTER 0 27H 0 1 0 0 1 1 1 GAMMA CORRECTION REGISTER 1 28H 0 1 0 1 0 0 0 GAMMA CORRECTION REGISTER 2 29H 0 1 0 1 0 0 1 GAMMA CORRECTION REGISTER 3 2AH 0 1 0 1 0 1 0 GAMMA CORRECTION REGISTER 4 2BH 0 1 0 1 0 1 1 GAMMA CORRECTION REGISTER 5 2CH 0 1 0 1 1 0 0 GAMMA CORRECTION REGISTER 6 2DH 0 1 0 1 1 0 1 GAMMA CORRECTION REGISTER 7 2EH 0 1 0 1 1 1 0 GAMMA CORRECTION REGISTER 8 2FH 0 1 0 1 1 1 1 GAMMA CORRECTION REGISTER 9 30H 0 1 1 0 0 0 0 GAMMA CORRECTION REGISTER 10 31H 0 1 1 0 0 0 1 GAMMA CORRECTION REGISTER 11 32H 0 1 1 0 0 1 0 GAMMA CORRECTION REGISTER 12 33H 0 1 1 0 0 1 1 GAMMA CORRECTION REGISTER 13 34H 0 1 1 0 1 0 0 BRIGHTNESS DETECT REGISTER 35H 0 1 1 0 1 0 1 OUTPUT CLOCK REGISTER 36H 0 1 1 0 1 1 0 RESERVED 37H 0 1 1 0 1 1 1 RESERVED 38H 0 1 1 1 0 0 0 RESERVED 39H 0 1 1 1 0 0 1 RESERVED 3AH 0 1 1 1 0 1 0 MACROVISION REGISTER (ADV7190 ONLY) 3BH 0 1 1 1 0 1 1 MACROVISION REGISTER (ADV7190 ONLY) 3CH 0 1 1 1 1 0 0 MACROVISION REGISTER (ADV7190 ONLY) 3DH 0 1 1 1 1 0 1 MACROVISION REGISTER (ADV7190 ONLY) 3EH 0 1 1 1 1 1 0 MACROVISION REGISTER (ADV7190 ONLY) 3FH 1 1 1 1 1 1 1 MACROVISION REGISTER (ADV7190 ONLY) 40H 1 0 0 0 0 0 0 MACROVISION REGISTER (ADV7190 ONLY) 41H 1 0 0 0 0 0 1 MACROVISION REGISTER (ADV7190 ONLY) 42H 1 0 0 0 0 1 0 MACROVISION REGISTER (ADV7190 ONLY) 43H 1 0 0 0 0 1 1 MACROVISION REGISTER (ADV7190 ONLY) 44H 1 0 0 0 1 0 0 MACROVISION REGISTER (ADV7190 ONLY) 45H 1 0 0 0 1 0 1 MACROVISION REGISTER (ADV7190 ONLY) 46H 1 0 0 0 1 1 0 MACROVISION REGISTER (ADV7190 ONLY) 47H 1 0 0 1 1 1 1 MACROVISION REGISTER (ADV7190 ONLY) 48H 1 0 0 1 0 1 0 MACROVISION REGISTER (ADV7190 ONLY) 49H 1 0 0 1 0 0 1 MACROVISION REGISTER (ADV7190 ONLY) 4AH 1 0 0 1 0 0 0 MACROVISION REGISTER (ADV7190 ONLY) 4BH 1 0 0 1 0 1 1 MACROVISION REGISTER (ADV7190 ONLY)

ADV7190/ADV7191 SUBADDRESS REGISTER

Subaddress Register (SR7–SR0)

The Communications Register is an eight bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place.

Figure 49 shows the various operations under the control of the Subaddress Register 0 should always be written to SR7.

These bits are set up to point to the required starting address.

Figure 49. Subaddress Register

–28–

REV. B

Page 29

ADV7190/ADV7191

MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H)

Figure 50 shows the various operations under the control of Mode Register 0.

MR0 BIT DESCRIPTION Output Video Standard Selection (MR00–MR01)

These bits are used to set up the encoder mode. The ADV7190/ ADV7191 can be set up to output NTSC, PAL (B, D, G, H, I), PAL M or PAL N standard video.

Luminance Filter Select (MR02–MR04)

These bits specify which luma ﬁlter is to be selected. The ﬁlter selection is made independent of whether PAL or NTSC is selected.

Chrominance Filter Select (MR05–MR07)

These bits select the chrominance ﬁlter. A low-pass ﬁlter can be selected with a choice of cut-off frequencies (0.65 MHz, 1.0 MHz,

1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or QCIF ﬁlters.

MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00

MR07 MR06 MR05

CHROMA FILTER SELECT

0 0 0 1.3 MHz LOW-PASS FILTER 0 0 1 0.65 MHz LOW-PASS FILTER 0 1 0 1.0 MHz LOW-PASS FILTER 0 1 1 2.0 MHz LOW-PASS FILTER 1 0 0 RESERVED 1 0 1 CIF 1 1 0 QCIF 1 1 1 3.0 MHz LOW-PASS FILTER

MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H)

Figure 51 shows the various operations under the control of Mode Register 1.

MR1 BIT DESCRIPTION DAC Control (MR10–MR15)

Bits MR15–MR10 can be used to power down the DACs. This is used to reduce the power consumption of the ADV7190/ADV7191 or if any of the DACs are not required in the application.

4 Oversampling Control (MR16)

To enable 4¥ Oversampling this bit has to be set to 1. When enabled, the data is output at a frequency of 54 MHz.

Note that PLL Enable Control has to be enabled (MR61 = 0) in 4¥ Oversampling mode.

Reserved (MR17)

A Logical 0 must be written to this bit.

OUTPUT VIDEO

STANDARD SELECTION

MR01 MR00

0 0 NTSC 0 1 PAL (B, D, G, H, I) 1 0 PAL (M) (ADV7190 ONLY) 1 1 PAL (N)

LUMA FILTER SELECT

MR04 MR03 MR02

0 0 0 LOW-PASS FILTER (NTSC) 0 0 1 LOW-PASS FILTER (PAL) 0 1 0 NOTCH FILTER (NTSC) 0 1 1 NOTCH FILTER (PAL) 1 0 0 EXTENDED MODE 1 0 1 CIF 1 1 0 QCIF 1 1 1 RESERVED

Figure 50. Mode Register 0 (MR0)

MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10

MR17

ZERO MUST

BE WRITTEN

TO THIS BIT

4  OVERSAMPLING

CONTROL

MR16

02 OVERSAMPLING 14 OVERSAMPLING

DAC A

DAC CONTROL

MR15

0 POWER-DOWN 1 NORMAL

MR14

0 POWER-DOWN 1 NORMAL

MR13

0 POWER-DOWN 1 NORMAL

DAC B

DAC CONTROL

DAC C

DAC CONTROL

MR12

0 POWER-DOWN 1 NORMAL

MR11

0 POWER-DOWN 1 NORMAL

DAC D

DAC CONTROL

DAC E

DAC CONTROL

MR10

0 POWER-DOWN 1 NORMAL

Figure 51. Mode Register 1 (MR1)

DAC F

DAC CONTROL

REV. B

–29–

Page 30

ADV7190/ADV7191

MODE REGISTER 2 MR2 (MR27–MR20) (Address (SR4–SR0) = 02H)

Mode Register 2 is an 8-bit-wide register.

Figure 52 shows the various operations under the control of Mode Register.

MR2 BIT DESCRIPTION— RGB/YUV Control (MR20)

This bit enables the output from the small or large DACs to be set to YUV or RGB output video standard.

DAC Output Control (MR21)

This bit controls the output from DACs A, B, and C. When this bit is set to 1, Composite, Luma, and Chroma Signals are output from DACs A, B, and C (respectively). When this bit is set to 0, RGB or YUV may be output from these DACs.

SCART Enable Control (MR22)

This bit is used to switch the DAC outputs from SCART to a EUROSCART conﬁguration. A complete table of all DAC output conﬁgurations is shown in Table III.

Pedestal Control (MR23)

This bit speciﬁes whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid when the device is conﬁgured in PAL mode.

Square Pixel Control (MR24)

This bit is used to set up square pixel mode. This is available in Slave Mode only. For NTSC, a 24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied. Square pixel operation is not available in 4¥ Oversampling mode.

Standard I2C Control (MR25)

This bit controls the video standard used by the ADV7190/ ADV7191. When this bit is set to 1 the video standard as programmed in Output Video Standard Selection (MR00, MR01). When MR25 is set to 0, the ADV7190/ADV7191 is forced into the standard selected by the NTSC_PAL pin. When NTSC_PAL is low the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL.

Pixel Data Valid Control (MR26)

After resetting the device, this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is output from the DACs. The ADV7190/ADV7191 will be set to Master Mode timing. When this bit is set to 1 by the user (via the I

C), pixel data passes to the pins and the encoder

reverts to the Timing Mode deﬁned by Timing Register 0.

Sleep Mode Control (MR27)

When this bit is set (1), Sleep Mode is enabled. With this mode enabled, the ADV7190/ADV7191 current consumption is reduced to less than 1 mA. The I

C registers can be written to and read

from when the ADV7190/ADV7191 is in Sleep Mode.

When the device is in Sleep Mode and 0 is written to MR27, the ADV7190/ADV7191 will come out of Sleep Mode and resume normal operation. Also, if a RESET is applied during Sleep Mode, the ADV7190/ADV7191 will come out of Sleep Mode and resume normal operation.

For this to operate, Power Up in Sleep Mode Control has to be enabled (MR60 = 0), otherwise Sleep Mode is controlled by the PAL_NTSC and SCRESET/RTC/TR pins.

Table III. DAC Output Conﬁguration Matrix

SCART DAC O/P RGB/YUV MR22 MR21 MR20 DAC A DAC B DAC C DAC D DAC E DAC F

0 00GBR CVBS LUMA CHROMA 0 01YUV CVBS LUMA CHROMA 0 10CVBS LUMA CHROMA G B R 0 11CVBS LUMA CHROMA Y U V 1 00CVBS B R G LUMA CHROMA 1 01CVBS U V Y LUMA CHROMA 1 10CVBS LUMA CHROMA G B R 1 11CVBS LUMA CHROMA Y U V

MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20

RGB/ YUV CONTROL

MR20

0 RGB OUTPUT 1 YUV OUTPUT

CONTROL

SLEEP MODE

CONTROL

MR27

0 DISABLE 1 ENABLE

PIXEL DATA

VALID CONTROL

MR26

0 DISABLE 1 ENABLE

STANDARD I2C

CONTROL

MR25

0 DISABLE 1 ENABLE

SQUARE PIXEL

CONTROL

MR24

0 DISABLE 1 ENABLE

MR22

PEDESTAL

CONTROL

MR23

0 PEDESTAL OFF 1 PEDESTAL ON

SCART ENABLE

CONTROL

0 DISABLE 1 ENABLE

MR21

DAC OUTPUT

0 RGB/YUV/COMP 1 COMP/LUMA/CHROMA

Figure 52. Mode Register 2 (MR2)

–30–

REV. B

Page 31

ADV7190/ADV7191

MODE REGISTER 3 MR3 (MR37–MR30) (Address (SR4–SR0) = 03H)

Mode Register 3 is an 8-bit-wide register. Figure 53 shows the various operations under the control of Mode Register 3.

MR3 BIT DESCRIPTION Revision Code (MR30–MR31)

This bit is read only and indicates the revision of the device.

VBI_Open (MR32)

This bit determines whether or not data in the Vertical Blanking Interval (VBI) is output to the analog outputs or blanked. Note that this condition is also valid in Timing Slave Mode 0. For further information see Vertical Blanking Data Insertion and BLANK Input section.

Teletext Enable (MR33)

This bit must be set to 1 to enable teletext data insertion on the TTX pin.

Teletext Bit Request Mode Control (MR34)

This bit enables switching of the teletext request signal from a continuous high signal (MR34 = 0) to a bitwise request signal (MR34 = 1).

Closed Captioning Field Control (MR35–MR36)

These bits control the ﬁelds that closed captioning data is displayed on, closed captioning information can be displayed on an odd ﬁeld, even ﬁeld or both ﬁelds.

Reserved (MR37)

A Logic 0 must be written to this bit.

MODE REGISTER 4 MR4 (MR47–MR40) (Address (SR4–SR0) = 04H)

Mode Register 4 is an 8-bit-wide register. Figure 54 shows the various operations under the control of Mode Register 4.

MR4 BIT DESCRIPTION VSYNC_3H Control (MR40)

When this bit is enabled (1) in Slave Mode, it is possible to drive the VSYNC input low for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in Master Mode the ADV7190/ADV7191 outputs an active low VSYNC signal for three lines in NTSC mode and 2.5 lines in PAL mode.

Genlock Control (MR41–MR42)

These bits control the Genlock feature and timing reset of the ADV7190/ADV7191. Setting MR41 and MR42 to Logic 0 disables the SCRESET/RTC/TR pin and allows the ADV7190/ ADV7191 to operate in normal mode.

1. By setting MR41 to zero and MR42 to one a timing reset is

applied, resetting the horizontal and vertical counters. This has the effect of resetting the Field Count to Field 0.

If the SCRESET/RTC/TR pin is held high, the counters will remain reset. Once the pin is released the counters will commence counting again. For correct counter reset, the SCRESET/RTC/TR pin has to remain high for at least 37 ns (one clock cycle at 27 MHz).

2. If MR41 is set to one and MR42 is set to zero, the SCRESET/

RTC/TR pin is conﬁgured as a subcarrier reset input and the subcarrier phase will reset to Field 0 whenever a low-tohigh transition is detected on the SCRESET/RTC/TR pin (SCH phase resets at the start of the next ﬁeld).

3. If MR41 is set to one and MR42 is set to one, the SCRESET/

RTC/TR pin is conﬁgured as a real-time control input and the ADV7190/ADV7191 can be used to lock to an external video source working in RTC mode. For more information see Real-Time Control, Subcarrier Reset and Timing Reset section.

Active Video Line Duration (MR43)

This bit switches between two active video line durations. A zero selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one selects ITU-R BT. 470 standard for active video duration (710 pixels NTSC, 702 pixels PAL).

Chrominance Control (MR44)

This bit enables the color information to be switched on and off the chroma composite, color component outputs.

Burst Control (MR45)

This bit enables the color burst to be switched on and off the chroma and composite outputs.

Color Bar Control (MR46)

This bit can be used to generate and output an internal color bar test pattern. The color bar conﬁguration is 100/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that when color bars are enabled the ADV7190/ADV7191 is conﬁgured in a Master Timing mode.

REV. B

MR37 MR36 MR35 MR34 MR33 MR32 MR31 MR30

MR37

ZERO MUST BE

WRITTEN TO

THIS BIT

MR36 MR35

0 0 NO DATA OUT 01ODD FIELD ONLY 10EVEN FIELD ONLY 11DATA OUT

CLOSED CAPTIONING

FIELD CONTROL

(BOTH FIELDS)

TTX BIT REQUEST

MODE CONTROL

MR34

0 DISABLE 1 ENABLE

MR33

TELETEXT

ENABLE

0 DISABLE 1 ENABLE

VBI OPEN

MR32

0 DISABLE 1 ENABLE

Figure 53. Mode Register 3 (MR3)

–31–

MR31 MR30

RESERVED FOR REVISION CODE

Page 32

ADV7190/ADV7191

MR47 MR46 MR45 MR44 MR43 MR42 MR41 MR40

INTERLACED

MODE CONTROL

MR47

0 INTERLACED 1 NONINTERLACED

COLOR BAR

CONTROL

MR46

0 DISABLE 1 ENABLE

CONTROL

MR45

0 ENABLE BURST 1 DISABLE BURST

CHROMINANCE

MR44

0 ENABLE COLOR 1 DISABLE COLOR

BURST

CONTROL

MR43

0 720 PIXELS 1 710 PIXELS/ 702 PIXELS

Figure 54. Mode Register 4 (MR4)

Interlaced Mode Control (MR47)

This bit is used to setup the output to interlaced or noninterlaced mode.

MODE REGISTER 5 MR5 (MR57–MR50) (Address (SR4–SR0) = 05H)

Mode Register 5 is an 8-bit-wide register. Figure 55 shows the various operations under the control of Mode Register 5.

MR5 BIT DESCRIPTION Y-Level Control (MR50)

This bit controls the component Y output level on the ADV7190/ ADV7191. If this bit is set (0), the encoder outputs Betacam levels when conﬁgured in PAL or NTSC mode. If this bit is set (1), the encoder outputs SMPTE levels when conﬁgured in PAL or NTSC mode.

UV-Levels Control (MR51–MR52)

These bits control the component U and V output levels on the ADV7190/ADV7191. It is possible to have UV levels with a peak-to-peak amplitude of either 700 mV (MR52 + MR51 = 01 ) or 1000 mV (MR52 + MR51 = 10) in NTSC and PAL.

GENLOCK CONTROL

MR42 MR41

0 0 DISABLE GENLOCK 01ENABLE SUBCARRIER

10TIMING RESET 11ENABLE RTC PIN

ACTIVE VIDEO

LINE DURATION

RESET PIN

VSYNC 3H CONTROL

MR40

0 DISABLE 1 ENABLE

It is also possible to have default values of 934 mV for NTSC and 700 mV for PAL (MR52 + MR51 = 00).

RGB Sync (MR53)

This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs.

Clamp Delay Value (MR54–MR55)

These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7190/ADV7191. It is possible to delay or advance the pulse by zero, one, two, or three clock cycles.

Note: Pin 51 is a multifunctional pin (VSO/CLAMP). CLAMP/ VSO Select Control (MR77) has to be set accordingly.

Clamp Delay Direction (MR56)

This bit controls a positive or negative delay in the CLAMP signal. If this bit is set (1), the delay is negative. If it is set (0), the delay is positive.

Clamp Position (MR57)

This bit controls the position of the CLAMP signal. If this bit is set (1), the CLAMP signal is located in the back porch position. If this bit is set (0), the CLAMP signal is located in the front porch position.

MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50

CLAMP

POSITION

MR57

0 FRONT PORCH 1 BACK PORCH

CLAMP DELAY

DIRECTION

MR56

0 POSITIVE 1 NEGATIVE

CLAMP DELAY

MR55 MR54

0 0 NO DELAY 011  PCLK 102  PCLK 113  PCLK

RGB SYNC

MR53

0 DISABLE 1 ENABLE

UV LEVEL CONTROL

MR52 MR51

0 0 DEFAULT LEVELS 01700mV 101000mV 11RESERVED

Figure 55. Mode Register 5 (MR5)

–32–

Y LEVEL

CONTROL

MR50

0 DISABLE 1 ENABLE

REV. B

Page 33

ADV7190/ADV7191

MODE REGISTER 6 MR6 (MR67–MR60) (ADDRESS (SR4–SR0) = 06H)

Mode Register 6 is an 8-bit-wide register. Figure 56 shows the various operations under the control of Mode Register 6.

MR6 BIT DESCRIPTION Power-Up Sleep Mode Control (MR60)

After RESET is applied this control is enabled (MR60 = 0) if both SCRESET/RTC/TR and NTSC_PAL pins are tied high. The ADV7190/ADV7191 will then power up in Sleep Mode to facilitate low power consumption while the I When this control is disabled (MR60 = 1, via the I

C is initialized.

C) Sleep

Mode control passes to Sleep Mode Control, MR27.

PPL Enable Control (MR61)

The PLL control should be enabled (MR61 = 0 ) when 4¥ Oversampling is enabled (MR16 = 1). It is also used to reset the PLL when this bit is toggled.

Reserved (MR62, MR63, MR64)

A Logic 0 must be written to these bits.

Field Counter (MR65, MR66, MR67)

These three bits are read-only bits. The ﬁeld count can be read back over the I

C interface. In NTSC mode the ﬁeld count goes

from 0–3, in PAL Mode from 0–7.

MODE REGISTER 7 MR7 (MR77–MR70) (Address (SR4–SR0) = 07H)

Mode Register 7 is an 8-bit-wide register. Figure 57 shows the various operations under the control of Mode Register 7.

MR7 BIT DESCRIPTION Color Control Enable (MR70)

This bit is used to enable control of contrast and saturation of color. If this bit is set (1), color controls are enabled (Contrast Control Register, U-Scale Register, V-Scale Register). If this bit is set (0), the color control features are disabled.

Luma Saturation Control (MR71)

When this bit is set (1), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 (after scaling by the Contrast Control Register). This prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. When this bit is set (0), this control is disabled.

Hue Adjust Control (MR72)

This bit is used to enable hue adjustment on the composite and chroma output signals of the ADV7190/ADV7191. When this bit is set (1), the hue of the color is adjusted by the phase offset described in the Hue Adjust Control Register. When this bit is set (0), hue adjustment is disabled.

Brightness Enable Control (MR73)

This bit is used to enable the brightness control of the ADV7190/ ADV7191. The actual brightness level is programmed in the Brightness Control Register. This value or “setup” level is added to the scaled Y data. When this bit is set (1), brightness control is enabled. When this bit is set (0), brightness control is disabled.

Sharpness Filter Enable (MR74)

This bit is used to enable the sharpness control of the luminance signal on the ADV7190/ADV7191 (Luma Filter Select has to be set to Extended, i.e., MR04–MR02 = 100). The various responses of the ﬁlter are determined by the Sharpness Control Register. When this bit is set (1), the luma response is altered by the amount described in the Sharpness Control Register. When this bit is set (0), the sharpness control is disabled. See Internal Filter Response section for luma signal responses.

CSO_HSO Output Control (MR75)

This bit is used to determine whether HSO or CSO TTL output signal is output at the CSO_HSO pin. If this bit is set (1), the CSO TTL signal is output. If this bit is set 0, the HSO TTL signal is output.

REV. B

MR67 MR66 MR65 MR64 MR63 MR62 MR61 MR60

MR67 MR66 MR65

FIELD COUNTER

MR64 MR63 MR62

ZERO MUST BE WRITTEN TO THESE BITS

PLL ENABLE

CONTROL

MR61

0 ENABLED 1 DISABLED

Figure 56. Mode Register 6 (MR6)

MR77 MR76 MR75 MR74 MR73 MR72 MR71 MR70

CLAMP/ VSO SELECT

MR77

0 VSO OUTPUT 1 CLAMP OUTPUT

MR76

ZERO MUST BE WRITTEN TO THIS BIT

OUTPUT CONTROL

MR75

CSO_HSO

0 HSO OUT 1 CSO OUT

SHARPNESS FILTER

ENABLE

MR74

0 DISABLE 1 ENABLE

BRIGHTNESS

ENABLE CONTROL

MR73

0 DISABLE 1 ENABLE

HUE ADJUST

CONTROL

MR72

0 DISABLE 1 ENABLE

LUMA SATURATION

CONTROL

MR71

0 DISABLE 1 ENABLE

Figure 57. Mode Register 7 (MR7)

–33–

POWER-UP SLEEP

MODE CONTROL

MR60

0 ENABLED 1 DISABLED

COLOR CONTROL

ENABLE

MR70

0 DISABLE 1 ENABLE

Page 34

ADV7190/ADV7191

Reserved (MR76)

A Logic 0 must be written to this bit.

CLAMP/VSO Select (MR77)

This bit is used to select the functionality of Pin 51. A 1 selects CLAMP as the output signal. A 0 selects VSO output.

MODE REGISTER 8 MR8 (MR87–MR80) (Address (SR4–SR0) = 08H)

Mode Register 8 is an 8-bit-wide register. Figure 58 shows the various operations under the control of Mode Register 8.

MR8 BIT DESCRIPTION Reserved (MR80, MR81)

A Logic 0 must be written to these bits.

Double Buffer Control (MR82)

Double buffering can be enabled or disabled on the Contrast Control Register, U Scale Register, V Scale Register, Hue Adjust Control Register, Closed Captioning Register, Brightness Control Register, Gamma Curve Select Bit and the Macrovision Registers (ADV7190 only). Double Buffering is not available in Master Timing mode.

16-Bit Pixel Port (MR83)

This bit controls if the ADV7190/ADV7191 accepts 8-bit or 16-bit input data. In 8-bit mode the data will be input on Pins P0–P7. Unused pixel inputs should be grounded.

Reserved (MR84)

A Logic 0 must be written to this bit.

DNR Enable Control (MR85)

To enable the DNR process this bit has to be set to 1. If this bit is set to 0, the DNR processing is bypassed. For further information on DNR controls see DNR Registers 2–0, DNR1 Bit Description, and DNR2 Bit Description sections.

Gamma Enable Control (MR86)

To enable the programmable gamma correction this bit has to be set to enabled (MR86 is set to 1). For further information

on Gamma Correction controls see Gamma Correction Registers 0–13 (Gamma 0–13) (Address (SR5–SR0) = 26H–32H) section.

Gamma Curve Select Control (MR87)

This bit selects which of the two programmable gamma curves is used. When setting MR87 to 0, the gamma correction curve to be processed is Curve A. Otherwise, Curve B is selected. For further information on Gamma Correction controls see Gamma Correction Registers 0–13 (Gamma 0–13) (Address (SR5–SR0) = 26H–32H) section.

MODE REGISTER 9 MR9 (MR97–MR90) (Address (SR4–SR0) = 09H)

Mode Register 9 is an 8-bit-wide register. Figure 59 shows the various operations under the control of Mode Register 9.

MR9 BIT DESCRIPTION Undershoot Limiter (MR90–MR91)

This control ensures that no luma video data will go below a programmable level. This prevents any synchronization problems due to luma signals going below the blanking level. Available limit levels are –1.5 IRE, –6 IRE, –11 IRE.

Note that this facility is only available in 4¥ Oversampling mode (MR16 = 1). When the device is operated in 2¥ Oversampling mode (MR16 = 0) or RGB outputs without RGB sync are selected, the minimum luma level is set in Timing Register 0, TR06 (Min Luma Control).

Reserved (MR92–MR93)

A Logic 0 must be written to these bits.

Chroma Delay Control (MR94–MR95)

The Chroma Signal can be delayed by up to 296 ns (eight clock cycles at 27 MHz) using MR94–MR95. For further information see also Chroma/Luma Delay section.

Reserved (MR96–MR97)

A Logic 0 must be written to these bits.

MR87 MR86 MR85 MR84 MR83 MR82 MR81 MR80

GAMMA ENABLE

MR86

GAMMA CURVE

SELECT CONTROL MR87

0 CURVE A 1 CURVE B

CONTROL

0 DISABLE 1 ENABLE

MR85

DNR ENABLE

CONTROL

0 DISABLE 1 ENABLE

MR84

ZERO MUST BE WRITTEN TO THIS BIT

MR83

0 8-BIT PIXEL PORT 1 16-BIT PIXEL PORT

DOUBLE BUFFER

MR82

16-PIXEL PORT

CONTROL

0 DISABLE 1 ENABLE

Figure 58. Mode Register 8 (MR8)

MR97 MR96 MR95 MR94 MR93 MR92 MR91 MR90

MR97 MR96

ZERO MUST BE WRITTEN TO THESE BITS

CHROMA

DELAY CONTROL

MR95 MR94

0 0 0ns DELAY 01148ns DELAY 10296ns DELAY 11RESERVED

MR93 MR92

ZERO MUST BE WRITTEN TO THESE BITS

UNDERSHOOT

MR91 MR90

0 0 DISABLED 01–11 IRE 10–6 IRE 11–1.5 IRE

Figure 59. Mode Register 9 (MR9)

–34–

MR81 MR80

ZERO MUST BE WRITTEN TO THESE BITS

LIMITER

REV. B

Page 35

ADV7190/ADV7191

TIMING REGISTER 0 (TR07–TR00) (Address (SR4–SR0) = 0AH)

Figure 60 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.

TR0 BIT DESCRIPTION Master/Slave Control (TR00)

This bit controls whether the ADV7190/ADV7191 is in master or slave mode.

Timing Mode Selection (TR01–TR02)

These bits control the timing mode of the ADV7190/ADV7191. These modes are described in more detail in the Video Timing Description and RESET Sequence sections of the data sheet.

BLANK Input Control (TR03)

This bit controls whether the BLANK input is used to accept blank signals or whether blank signals are internally generated.

Note: When this input pin is tied high (to 5 V), the input is disabled regardless of the register setting. It, therefore, should be tied low (to Ground) to allow control over the I

C register.

Luma Delay (TR04–TR05)

The luma signal can be delayed by up to 222 ns (or six clock cycles at 27 MHz) using TR04–TR05. For further information see Chroma/Luma Delay section.

Min Luminance Value (TR06)

This bit is used to control the minimum luma output value by the ADV7190/ADV7191 in 2¥ Oversampling Mode (MR 16 =

0). When this bit is set to a Logic 1, the luma is limited to 7.5IRE below the blank level. When this bit is set to (0), the luma value can be as low as the sync bottom level (40IRE below blanking).

Timing Register Reset (TR07)

Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up, reset, or changing to a new timing mode.

TIMING REGISTER 1 (TR17–TR10) (Address (SR4–SR0) = 0BH)

Timing Register 1 is an 8-bit-wide register.

Figure 61 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.

TR1 BIT DESCRIPTION HSYNC Width (TR10–TR11)

These bits adjust the HSYNC pulsewidth.

= one clock cycle at 27 MHz.

PCLK

HSYNC to VSYNC Delay Control (TR12–TR13)

These bits adjust the position of the HSYNC output relative to the VSYNC output.

= one clock cycle at 27 MHz.

PCLK

HSYNC to VSYNC Rising Edge Control (TR14–TR15)

When the ADV7190/ADV7191 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the VSYNC output rising edge.

= one clock cycle at 27 MHz.

PCLK

VSYNC Width (TR14–TR15)

When the ADV7190/ADV7191 is conﬁgured in Timing Mode 2, these bits adjust the VSYNC pulsewidth.

= one clock cycle at 27 MHz.

PCLK

HSYNC to Pixel Data Adjust (TR16–TR17)

This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master and slave timing modes.

= one clock cycle at 27 MHz.

PCLK

REV. B

TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00

TIMING

TR07

MIN LUMINANCE VALUE

TR06

0 LUMA MIN =

SYNC BOTTOM

1 LUMA MIN =

BLANK –7.5 IRE

LUMA DELAY

TR05 TR04

0 0 0ns DELAY 0174ns DELAY 10148ns DELAY 11222ns DELAY

BLANK INPUT

CONTROL

TR03

0 ENABLE 1 DISABLE

TIMING MODE

CONTROL

TR02 TR01

0 0 MODE 0 01MODE 1 10MODE 2 11MODE 3

Figure 60. Timing Register 0

–35–

MASTER / SLAVE

CONTROL

TR00

0 SLAVE TIMING 1 MASTER TIMING

Page 36

ADV7190/ADV7191

TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10

HSYNC TO PIXEL

DATA ADJUST

TR17 TR16

0 0 0  T 011  T 102  T 113  T

TIMING MODE 1 (MASTER/ PAL)

HSYNC

VSYNC

PCLK

PCLK PCLK PCLK

HSYNC TO VSYNC

RISING EDGE DELAY

(MODE 1 ONLY)

TR15 TR14 T

 0 T  1TB + 32s

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

0 0 1  T 014  T 1016  T 11128  T

PCLK PCLK

PCLK

Figure 61. Timing Register 1

SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH)

These 8-bit-wide registers are used to set up the Subcarrier Frequency. The value of these registers are calculated by using the following equation:

HSYNC TO

VSYNC DELAY

TR13 TR12 T

0 0 0  T 014  T 108  T 1118  T

PCLK PCLK PCLK

PCLK

TR11 TR10 T

0 0 1  T 014  T 1016  T 11128  T

LINE 313 LINE 314LINE 1

HSYNC WIDTH

PCLK

SUBCARRIER PHASE REGISTER (FPH7–FPH0) (Address (SR4–SR0) = 10H)

This 8-bit-wide register is used to set up the Subcarrier Phase. Each bit represents 1.41∞. For normal operation this register is set to 00Hex.

Subcarrier Frequency

Example: NTSC Mode, f

CLK

Subcarrier Frequency alueV =

= 27 MHz, f

()

= 3.5795454 MHz

SCF

32 6

2135795454 10

¥¥

–.

27 10

¥21

–

SCF

CLK

Subcarrier Register Value = 21F07C16 Hex

Figure 62 shows how the frequency is set up by the four registers.

SUBCARRIER

FREQUENCY

SUBCARRIER

FREQUENCY

SUBCARRIER

FREQUENCY

SUBCARRIER

FREQUENCY

FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24

REG 3

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

REG 2

FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

REG 1

FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

REG 0

Figure 62. Subcarrier Frequency Registers

SUBCARRIER

FPH7 FPH6 FPH5 FPH4 FPH3 FPH2 FPH1 FPH0

PHASE

Figure 63. Subcarrier Phase Register

CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1–0 (CCD15–CCD0) (Address (SR4–SR0) = 11–12H)

These 8-bit-wide registers are used to set up the closed captioning extended data bytes on Even Fields. Figure 64 shows how the high and low bytes are set up in the registers.

CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8

BYTE 1

CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0

BYTE 0

Figure 64. Closed Captioning Extended Data Register

CLOSED CAPTIONING ODD FIELD DATA REGISTER 1–0 (CED15–CED0) (Subaddress (SR4–SR0) = 13–14H)

These 8-bit-wide registers are used to set up the closed captioning data bytes on Odd Fields. Figure 65 shows how the high and low bytes are set up in the registers.

BYTE 1

CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8

–36–

BYTE 0

CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0

Figure 65. Closed Captioning Data Register

REV. B

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ADV7190/ADV7191

NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0) (Subaddress (SR4–SR0) = 15–18H)

These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for both odd and even ﬁelds. Figures 66 and 67 show the four control registers. A Logic 1 in any of the bits of these registers has the effect of turning the Pedestal OFF on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of turning Teletext ON on the equivalent line when used in PAL.

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

FIELD 1/3

FIELD 2/4

PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8

Figure 66. Pedestal Control Registers

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

FIELD 1/3

FIELD 2/4

TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8

Figure 67. Teletext Control Registers

TELETEXT REQUEST CONTROL REGISTER (TC07–TC00) (Address (SR4–SR0) = 1CH)

Teletext Control Register is an 8-bit-wide register. See Figure 68.

TTXREQ Falling Edge Control (TC00–TC03)

These bits control the position of the falling edge of TTXREQ. It can be programmed from zero clock cycles to a maximum of 15 clock cycles. This controls the active window for Teletext data. Increasing this value reduces the amount of Teletext bits below the default of 360. If Bits TC00–TC03 are 00Hex when

Bits TC07–TC04 are changed then the falling edge of TTREQ will track that of the rising edge (i.e., the time between the falling and rising edge remains constant).

PCLK = clock cycle at 27 MHz.

TTXREQ Rising Edge Control (TC04–TC07)

These bits control the position of the rising edge of TTXREQ. It can be programmed from zero clock cycles to a maximum of 15 clock cycles.

PCLK = clock cycle at 27 MHz.

TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00

TTXREQ

RISING EDGE CONTROL

TC07 TC06 TC05 TC04

0 0 000 PCLK 00 0 11 PCLK '' '' '' '' '' PCLK 11 1 0 14 PCLK 11 1 1 15 PCLK

TC03 TC02 TC01 TC00

TTXREQ

FALLING EDGE CONTROL

0 0 000 PCLK 00 0 11 PCLK '' '' '' '' '' PCLK 11 1 014 PCLK 11 1 115 PCLK

Figure 68. Teletext Control Register

CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00) (Address (SR4–SR0) = 19H)

CGMS_WSS register 0 is an 8-bit-wide register. Figure 69 shows the operations under control of this register.

C/W0 BIT DESCRIPTION CGMS Data (C/W00–C/W03)

These four data bits are the ﬁnal four bits of CGMS data output stream. Note it is CGMS data ONLY in these bit positions, i.e., WSS data does not share this location.

CGMS CRC Check Control (C/W04)

When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check sequence, is internally calculated by the ADV7190/ADV7191. If this bit is disabled (0), the CRC values in the register are output to the CGMS data stream.

CGMS Odd Field Control (C/W05)

When this bit is set (1), CGMS is enabled for odd ﬁelds. Note this is only valid in NTSC mode.

CGMS Even Field Control (C/W06)

When this bit is set (1), CGMS is enabled for even ﬁelds. Note this is only valid in NTSC mode.

WSS Control (C/W07)

When this bit is set (1), wide screen signalling is enabled. Note this is only valid in PAL mode.

REV. B

C/W07 C/W06 C/W05 C/W04 C/W03 C/W02 C/W01 C/W00

WSS CONTROL

C/W07

0 DISABLE 1 ENABLE

CGMS ODD FIELD

C/W05

CGMS EVEN FIELD

CONTROL

C/W06

0 DISABLE 1 ENABLE

CONTROL

0 DISABLE 1 ENABLE

CGMS CRC CHECK

C/W04

CONTROL

0 DISABLE 1 ENABLE

C/W03 – C/W00

CGMS DATA

Figure 69. CGMS_WSS Register 0

–37–

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ADV7190/ADV7191

CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address (SR4–SR0) = 1AH)

CGMS_WSS Register 1 is an 8-bit-wide register. Figure 70 shows the operations under control of this register.

C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W10–C/W15)

These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data.

CGMS Data (C/W16–C/W17)

These bits are CGMS data bits only.

C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10

C/W17 – C/W16

CGMS DATA

C/W15 – C/W10

CGMS/WSS DATA

Figure 70. CGMS_WSS Register 1

CGMS_WSS REGISTER 2 C/W1 (C/W27–C/W20) (Address (SR4–SR0) = 1BH)

CGMS_WSS Register 2 is an 8-bit-wide register. Figure 71 shows the operations under control of this register.

C/W2 BIT DESCRIPTION CGMS/WSS Data (C/W20–C/W27)

These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data.

C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20

C/W27 – C/W20

CGMS/WSS DATA

Figure 71. CGMS_WSS Register 2

CONTRAST CONTROL REGISTER (CC00–CC07) (Address (SR4–SR0) = 1DH)

The contrast control register is an 8-bit-wide register used to scale the Y output levels. Figure 72 shows the operation under control of this register.

Y Scale Value (CC00–CC07)

These eight bits represent the value required to scale the Y pixel data from 0.0 to 1.5 of its initial level. The value of these eight bits is calculated using the following equation:

Y Scale Value = Scale Factor ¥ 128

Example:

Scale Factor = 1.18

Y Scale Value = 1.18 ¥ 128 = 151.04 Y Scale Value = 151 (rounded to the nearest integer) Y Scale Value = 10010111 Y Scale Value = 97

CC07 CC06 CC05 CC04 CC03 CC02 CC01 CC00

CC07 – CC00

Y SCALE VALUE

Figure 72. Contrast Control Register

COLOR CONTROL REGISTERS 2–1 (CC2–CC1) (Address (SR4–SR0) = 1EH–1FH)

The color control registers are 8-bit-wide registers used to scale the U and V output levels. Figure 73 shows the operations under control of these registers.

CC17 CC16 CC15 CC14 CC13 CC12 CC11 CC10

CC17 – CC10

U SCALE VALUE

CC27 CC26 CC25 CC24 CC23 CC22 CC21 CC20

CC27 – CC20

V SCALE VALUE

Figure 73. Color Control Registers

CC1 BIT DESCRIPTION U Scale Value (CC10–CC17)

These eight bits represent the value required to scale the U level from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation:

U Scale Value = Scale Factor ¥ 128

Example:

Scale Factor = 1.18

U Scale Value = 1.18 ¥ 128 = 151.04 U Scale Value = 151 (rounded to the nearest integer) U Scale Value = 10010111 U Scale Value = 97

CC2 BIT DESCRIPTION V Scale Value (CC20–CC27)

These eight bits represent the value required to scale the V pixel data from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation:

V Scale Value = Scale Factor ¥ 128

Example:

Scale Factor = 1.18

V Scale Value = 1.18 ¥ 128 = 151.04 V Scale Value = 151 (rounded to the nearest integer) V Scale Value = 10010111 V Scale Value = 97

–38–

REV. B

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ADV7190/ADV7191

HUE ADJUST CONTROL REGISTER (HCR) (Address (SR5–SR0) = 20H)

he hue control register is an 8-bit-wide register used to adjust

the hue on the composite and chroma outputs. Figure 74 shows the operation under control of this register.

HCR7 HCR6 HCR5 HCR4 HCR3 HCR2 HCR1 HCR0

HCR7 – HCR0

HUE ADJUST VALUE

Figure 74. Hue Adjust Control Register

HCR Bit Description Hue Adjust Value (HCR0–HCR7)

These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. The ADV7190/ADV7191 provides a range of ± 22.5∞ increments of 0.17578125∞. For normal operation (zero adjustment) this register is set to 80Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable.

Hue Adjust [∞] = 0.17578125∞ ¥ (HCR

– 128); for positive Hue

Adjust Value

Example:

To adjust the hue by 4∞ write 97

to the Hue Adjust Control

(4/0.17578125) + 128 = 151

* = 97

To adjust the hue by (–4∞) write 69h to the Hue Adjust Control Register:

(–4/0.17578125) + 128 = 10d

*Rounded to the nearest integer.

* = 69

BRIGHTNESS CONTROL REGISTERS (BCR) (Address (SR5–SR0) = 21H)

The brightness register is an 8-bit-wide register which allows brightness control. Figure 75 shows the operation under control of this register.

BCR BIT DESCRIPTION Brightness Value (BCR0–BCR6)

Seven bits of this 8-bit-wide register are used to control the brightness level. The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level can be a positive or negative value.

The programmable brightness level in NTSC without pedestal and PAL are max 15 IRE and min –7.5 IRE, in NTSC with pedestal max 22.5 IRE and min 0 IRE.

Table IV. Brightness Control Register Value

etup Setup Brightness Level in Level in Setup Control NTSC with NTSC No Level in Register Pedestal Pedestal PAL Value

22.5 IRE 15 IRE 15 IRE 1E 15 IRE 7.5 IRE 7.5 IRE 0F

7.5 IRE 0 IRE 0 IRE 00 0 IRE –7.5 IRE –7.5 IRE 71

NOTE Values in the range from 3Fh to 44h might result in an invalid output signal.

EXAMPLE

1. Standard: NTSC with Pedestal. To add +20 IRE brightness level, write 28h into the Brightness Control Register:

[Brightness Control Register Value]

= [IRE Value ⫻ 2.015631]h = [20 ¥ 2.015631]h = [40.31262]h = 28

2. Standard: PAL. To add –7 IRE brightness level write 72h into the Brightness Control Register:

[|IRE Value| ¥ 2.015631]

NTSC WITHOUT PEDESTAL

100 IRE

0 IRE

NO SETUP VALUE ADDED

ZERO MUST BE WRITTEN TO THIS BIT

[0001110] into two’s complement = 1110010b = 72

BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0

BCR7

= [7 ¥ 2.015631] = [14.109417] = 0001110

POSITIVE SETUP VALUE ADDED

WRITE TO BRIGHTNESS CONTROL REGISTER: 12

BCR6 – BCR0

BRIGHTNESS VALUE

NEGATIVE SETUP VALUE ADDED

WRITE TO BRIGHTNESS CONTROL REGISTER: 6E

+7.5 IRE

–7.5 IRE

Figure 75. Brightness Control Register

REV. B

–39–

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ADV7190/ADV7191

SHARPNESS CONTROL REGISTER (PR) (Address (SR5–SR0) = 22H)

The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to select a desired ﬁlter response. Figure 76 shows the operation under control of this register.

PR BIT DESCRIPTION Sharpness Response Value (PR3–PR0)

These four bits are used to select the desired luma ﬁlter response. The option of twelve responses is given supporting a gain boost/ attenuation in the range –4 dB to +4 dB. The value 12 (1100) written to these four bits corresponds to a boost of +4 dB while the value 0 (0000) corresponds to –4 dB. For normal operation these four bits are set to 6 (0110).

Note: Luma Filter Select has to be set to Extended Mode and Sharpness Filter Enable Control has to be enabled for settings in the Sharpness Control Register to take effect (MR02–04 = 100; MR74 = 1). See Internal Filter Response section.

Reserved (PR4–PR7)

A Logic 0 must be written to these bits.

PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0

PR7 – PR4

ZERO MUST BE

WRITTEN TO

THESE BITS

PR3 – PR0

SHARPNESS

RESPONSE VALUE

Figure 76. Sharpness Control Register

DNR REGISTERS 2–0 (DNR 2–DNR 0) (Address (SR5–SR0) = 23H–25H)

The Digital Noise Reduction Registers are three 8-bit-wide registers. They are used to control the DNR processing. See Digital Noise Reduction section.

Coring Gain Border (DNR00–DNR03)

These four bits are assigned to the gain factor applied to border areas.

In DNR Mode the range of gain values is 0–1, in increments of 1/8. This factor is applied to the DNR ﬁlter output which lies below the set threshold range. The result is then subtracted from the original signal.

In DNR Sharpness Mode the range of gain values is 0–0.5 in increments of 1/16. This factor is applied to the DNR ﬁlter output which lies above the threshold range.

The result is added to the original signal.

Coring Gain Data (DNR04–DNR07)

These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block.

In DNR Sharpness Mode the range of gain values is 0–0.5, in increments of 1/16. This factor is applied to the DNR ﬁlter output which lies above the threshold range. The result is added to the original signal.

Figures 77 and 78 show the various operations under the control of DNR Register 0.

DNR07 DNR06 DNR05 DNR04 DNR03 DNR02 DNR01 DNR00

CORING GAIN DATA

DNR DNR DNR DNR 07 06 05 04

0 0 0 0 0 00011/16 00102/16 00113/16 01004/16 01015/16 01106/16 01117/16 10008/16

CORING GAIN BORDER

DNR DNR DNR DNR 03 02 01 00

0 0 0 0 0 00011/16 00102/16 00113/16 01004/16 01015/16 01106/16 01117/16 10008/16

Figure 77. DNR Register 0 in Sharpness Mode

DNR07 DNR06 DNR05 DNR04 DNR03 DNR02 DNR01 DNR00

CORING GAIN DATA

DNR DNR DNR DNR 07 06 05 04

0 0 0 0 0 00011/8 00102/8 00113/8 01004/8 01015/8 01106/8 01117/8 10001

CORING GAIN BORDER

DNR DNR DNR DNR 03 02 01 00

0 0 0 0 0 00011/8 00102/8 00113/8 01004/8 01015/8 01106/8 01117/8 10001

Figure 78. DNR Register 0 in DNR Mode

NR1 BIT DESCRIPTION

DNR Threshold (DNR10–DNR15)

These six bits are used to deﬁne the threshold value in the range of 0 to 63. The range is an absolute value.

Border Area (DNR16)

In setting DNR16 to a Logic 1 the block transition area can be deﬁned to consist of four pixels. If this bit is set to a Logic 0 the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.

Block Size Control (DNR17)

This bit is used to select the size of the data blocks to be processed (see Figure 79). Setting the block size control function to a Logic 1 deﬁnes a 16 ¥ 16 pixel data block, a Logic 0 deﬁnes an 8 ¥ 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.

720  485 PIXELS

(NTSC)

BORDER DATA

8  8

PIXEL BLOCK

2 PIXEL

PIXEL BLOCK

8  8

Figure 79. MPEG Block Diagram

–40–

REV. B

Page 41

ADV7190/ADV7191

DNR17 DNR16 DNR15 DNR14 DNR13 DNR12 DNR11 DNR10

BLOCK SIZE

CONTROL

DNR17

08 PIXELS 1 16 PIXELS

BORDER AREA

DNR16

02 PIXELS 14 PIXELS

Figure 80. DNR Register 1

DNR2 BIT DESCRIPTION DNR Input Select (DNR20–DNR22)

Three bits are assigned to select the ﬁlter that is applied to the incoming Y data. The signal that lies in the passband of the selected ﬁlter is the signal that will be DNR processed. Figure 81 shows the ﬁlter responses selectable with this control.

0.8

FILTER D

FILTER C

0.6

0.4

MAGNITUDE – dB

0.2

FILTER B

FILTER A

234 65

FREQUENCY – MHz

Figure 81. Filter Response of Filters Selectable

DNR Mode Control (DNR23)

This bit controls the DNR mode selected. A Logic 0 selects DNR mode, a Logic 1 selects DNR Sharpness mode.

DNR works on the principle of deﬁning low amplitude, highfrequency signals as probable noise and subtracting this noise from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1.

When DNR Sharpness mode is enabled it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. The overall effect being that the signal will be boosted (similar to using Extended SSAF Filter).

DNR THRESHOLD

DNR DNR DNR DNR DNR DNR 15 14 13 12 11 10

0 0 0 0 0 0 0 0000011

•••••••

••••••• 11111062 11111163

GAIN CONTROL

BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET

GAIN

CORING GAIN DATA CORING GAIN BORDER

FILTER OUTPUT

< THRESHOLD ?

FILTER OUTPUT

> THRESHOLD

GAIN CONTROL

BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET

GAIN

CORING GAIN DATA CORING GAIN BORDER

FILTER OUTPUT

> THRESHOLD ?

FILTER OUTPUT

< THRESHOLD

SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL

DNR OUT

ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL

DNR OUT

Y DATA

INPUT

Y DATA

INPUT

DNR MODE

NOISE SIGNAL PATH

FILTER BLOCK

MAIN SIGNAL PATH

DNR SHARPNESS MODE

NOISE SIGNAL PATH

FILTER BLOCK

MAIN SIGNAL PATH

Figure 82. Block Diagram for DNR Mode and DNR Sharpness Mode

Block Offset (DNR24–DNR27)

Four bits are assigned to this control which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions ﬁxed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.

APPLY DATA CORING GAIN

APPLY BORDER CORING GAIN

REV. B

DNR27 – DNR24

–41–

= 01 HEX

O X X X X X X O O X X X X X X O

OFFSET CAUSED BY VARIATIONS IN INPUT TIMING

Figure 83. DNR27–DNR24, Block Offset Control

Page 42

ADV7190/ADV7191

DNR27 DNR26 DNR25 DNR24 DNR23 DNR22 DNR21 DNR20

BLOCK OFFSET

DNR DNR DNR DNR 27 26 25 24

0000 0 PIXEL OFFSET 0001 1 PIXEL OFFSET 0010 2 PIXEL OFFSET

•••• •

•••• • 110113 PIXEL OFFSET 111014 PIXEL OFFSET 111115 PIXEL OFFSET

DNR MODE

CONTROL

DNR23

0 DNR MODE 1 DNR

Figure 84. DNR Register 2

GAMMA CORRECTION REGISTERS 0–13 (GAMMA CORRECTION 0–13) (Address (SR5–SR0) = 26H–32H)

The Gamma Correction Registers are fourteen 8-bit-wide registers. They are used to program the gamma correction Curves A and B.

Gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used.

Gamma correction uses the function:

Signal

= (Signal

OUT

IN )

where

g = gamma power factor

Gamma correction is performed on the luma data only. The user has the choice to use two different curves, Curve A, or Curve B. At any one time only one of these curves can be used.

The response of the curve is programmed at seven predeﬁned locations. In changing the values at these locations the gamma curve can be modiﬁed. Between these points linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, and 224.

Values at Location 0, 16, 240, and 255 are ﬁxed and cannot be changed.

For the length of 16 to 240 the gamma correction curve has to be calculated as below:

y = x

where

y = gamma corrected output x = linear input signal

g = gamma power factor

To program the gamma correction registers, the seven values for y have to be calculated using the following formula:

= [x(

/(240–16) ]g ¥ (240–16) + 16

n–16)

where

x y

Value for x along x-axis

(n-16) =

Value for y along the y-axis, which has to be written

n =

into the gamma correction register

n = 32, 64, 96, 128, 160, 192, or 224

Example:

= [(16/224)

= [(48/224)

0.5

¥ 224] + 16 = 76*

0.5

¥ 224] + 16 =120*

–42–

DNR INPUT SELECT

DNR DNR DNR 22 21 20

001FILTER A

SHARPNESS MODE

= [(80/224)

= [(112/224)

128

*Rounded to the nearest integer.

010FILTER B 011FILTER C 100FILTER D

0.5

¥ 224] + 16 = 150*

0.5

¥ 224] + 16 = 174*

The above will result in a gamma curve shown below, assuming a ramp signal as an input.

300

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

250

300

200

250

200

150

100

GAMMA–CORRECTED AMPLITUDE

050100 150 200 250

SIGNAL OUTPUT

0.5

SIGNAL INPUT

LOCATION

Figure 85. Signal Input (Ramp) and Signal Output for Gamma 0.5

300

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES

250

200

150

100

SIGNAL INPUT

GAMMA–CORRECTED AMPLITUDE

050100 150 200 250

SIGNAL OUTPUTS

0.3

0.5

1.5

LOCATION

1.8

Figure 86. Signal Input (Ramp) and Selectable Gamma Output Curves

The gamma curves shown above are examples only, any userdeﬁned curve is acceptable in the range of 16–240.

REV. B

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ADV7190/ADV7191

BRIGHTNESS DETECT REGISTER (Address (SR5–SR0) = 34H)

he Brightness Detect Register is an 8-bit-wide register used only

to read back data in order to monitor the brightness/darkness of the incoming video data on a ﬁeld-by-ﬁeld basis. The brightness information is read from the I

C and based on this information, the color controls or the gamma correction controls may be adjusted.

The luma data is monitored in the active video area only. The average brightness I

C register is updated on the falling edge of

every VSYNC signal.

UTPUT CLOCK REGISTER (OCR 9–0)

(Address (SR4–SR0) = 35H)

he Output Clock Register is an 8-bit-wide register. Figure

87 shows the various operations under the control of this register.

OCR07 OCR06 OCR05

OCR07

ZERO MUST BE

WRITTEN TO

THIS BIT

OCR06 – OCR04

ONE MUST BE

WRITTEN TO

THESE BITS

OCR04

CR BIT DESCRIPTION

Reserved (OCR00)

A Logic 0 must be written to this bit.

CLKOUT Pin Control (OCR01)

This bit enables the CLKOUT pin when set to 1 and, therefore, outputs a 54 MHz clock generated by the internal PLL. The PLL and 4¥ Oversampling have to be enabled for this control to take effect (MR61 = 0; MR16 = 1).

Reserved (OCR02–03)

A Logic 0 must be written to these bits.

Reserved (OCR04–06)

A Logic 1 must be written to these bits.

Reserved (OCR07)

A Logic 0 must be written to this bit.

OCR03 OCR02 OCR01 OCR00

OCR03 – OCR02

ZERO MUST BE

WRITTEN TO

THESE BITS

CLKOUT

PIN CONTROL

OCR01

0 ENSABLED 1 DISABLED

OCR00

ZERO MUST BE

WRITTEN TO

THIS BIT

Figure 87. Output Clock Register (OCR)

REV. B

–43–

Page 44

ADV7190/ADV7191

APPENDIX 1

BOARD DESIGN AND LAYOUT CONSIDERATIONS

The ADV7190/ADV7191 is a highly integrated circuit containing both precision analog and high-speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high-speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design such that high-speed, accurate performance is achieved. The Recommended Analog Circuit Layout shows the analog interface between the device and monitor.

The layout should be optimized for lowest noise on the ADV7190/ ADV7191 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of V

and AGND pins should by minimized in order to mini-

mize inductive ringing.

Ground Planes

The ground plane should encompass all ADV7190/ADV7191 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7190/ADV7191, the analog output traces, and all the digital signal traces leading up to the ADV7190/ADV7191.

Power Planes

The ADV7190/ADV7191 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (V regular PCB power plane (V

). This power plane should be connected to the

) at a single point through a

ferrite bead. This bead should be located within three inches of the ADV7190/ADV7191.

The metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board.

The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7190/ADV7191 power pins and voltage reference circuitry.

Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged so the plane-to-plane noise is common-mode.

Supply Decoupling

For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation,

to reduce the lead inductance. Best performance is obtained with 0.1 mF ceramic capacitor decoupling. Each group of V

pins on the ADV7190/ADV7191 must have at least one 0.1 mF decoupling capacitor to AGND. These capacitors should be placed as close as possible to the device.

It is important to note that while the ADV7190/ADV7191 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high-frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane.

Digital Signal Interconnect

The digital inputs to the ADV7190/ADV7191 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane.

Due to the high clock rates involved, long clock lines to the ADV7190/ADV7191 should be avoided to reduce noise pickup.

Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V

), and not the

analog power plane.

Analog Signal Interconnect

The ADV7190/ADV7191 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch.

The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection.

Digital inputs, especially pixel data inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible.

For best performance, the outputs should each have a 300 W load resistor connected to AGND. These resistors should be placed as close as possible to the ADV7190/ADV7191 so as to minimize reflections.

The ADV7190/ADV7191 should have no inputs left floating. Any inputs that are not required should be tied to ground.

–44–

REV. B

Page 45

5V (VAA)

UNUSED INPUTS SHOULD BE GROUNDED

5V (VAA)

4.7k

4.7F

6.3V

27MHz CLOCK

(SAME CLOCK AS

USED BY MPEG2

DECODER)

0.1F

5V (V

)

0.1F

)

4.7k

APPENDIX 1

BOARD LAYOUT

POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP

10nF

17, 25, 29, 38, 43, 54, 63

COMP1

COMP2

REF

ADV7190/

P15

ADV7191

CSO_HSO

VSO/CLAMP

PAL_NTSC

SCRESET/RTC/TR

HSYNC

VSYNC

BLANK

RESET

TTX

TTXREQ

CLKIN

CLKOUT

AGNDALSB

DAC A

18, 24, 26, 33, 39, 42, 55, 64

DAC B

DAC C

DAC D

DAC E

DAC F

SCL

SDA

SET2

SET1

0.1F

300

1.2k

100

1.2k

ADV7190/ADV7191

5V (VAA)

CONNECT DAC OUTPUTS TO OPTIONAL OUTPUT FILTER AND BUFFER CIRCUIT

5V (VAA)

5k

5V (VAA)

5k

MPU BUS

REV. B

Figure 88. Recommended Analog Circuit Layout

–45–

Page 46

ADV7190/ADV7191

APPENDIX 2

CLOSED CAPTIONING

The ADV7190/ADV7191 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd ﬁelds and Line 284 of even ﬁelds.

Closed captioning consists of a seven-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic Level 1 start bit. Sixteen bits of data follow the start bit. These consist of two eight-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in Closed Captioning Data Registers 0 and 1.

The ADV7190/ADV7191 also supports the extended closed captioning operation that is active during even ﬁelds and is encoded on Scan Line 284. The data for this operation is stored in Closed Captioning Extended Data Registers 0 and 1.

All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7190/ ADV7191 All pixel inputs are ignored during Lines 21 and 284 if closed captioning is enabled.

10.5  0.25s

50 IRE

12.91s

7 CYCLES

OF 0.5035 MHz

(CLOCK RUN-IN)

FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284.

The ADV7190/ADV7191 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data, unlike other two byte deep buffering systems. The data must be loaded one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn, will load the new data (two bytes) every ﬁeld. If no new data is required for transmission, 0s must be inserted in both data registers, this is called NULLING. It is also important to load control codes, all of which are double bytes on Line 21, or a TV will not recognize them. If there is a message like Hello World, which has an odd number of characters, it is important to pad it out to even in order to get end of caption 2-byte control code to land in the same ﬁeld.

TWO 7-BIT + PARITY ASCII CHARACTERS

(DATA)

S T

D0–D6

A R T

BYTE 0 BYTE 1

P A

D0–D6

I T Y

P A R

I T Y

40 IRE

REFERENCE COLOR BURST

FREQUENCY = F AMPLITUDE = 40 IRE

(9 CYCLES)

10.003s

= 3.579545MHz

27.382s

Figure 89. Closed Captioning Waveform (NTSC)

–46–

33.764s

REV. B

Page 47

ADV7190/ADV7191

APPENDIX 3

COPY GENERATION MANAGEMENT SYSTEM (CGMS)

The ADV7190/ADV7191 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd ﬁelds and Line 283 of even ﬁelds. Bits C/W05 and C/W06 control whether or not CGMS data is outputed on ODD and EVEN ﬁelds. CGMS data can only be transmitted when the ADV7190/ADV7191 is conﬁgured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see Figure 94. These bits are output from the conﬁguration registers in the following order: C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the bit C/W04 is set to a Logic 1, the last six bits C19–C14 which comprise the 6-bit CRC check sequence are calculated automatically on the ADV7190/ADV7191 based on the lower 14 bits (C0–C13) of the data in the data registers and output with the remaining 14-bits to form the complete 20-bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X

+ X + 1 with a preset value of 111111. If C/W04 is set to a Logic 0, all 20 bits (C0–C19) are output directly from the CGMS registers (no CRC calculated, must be calculated by the user).

Function of CGMS Bits

Word 0 – 6 Bits Word 1 – 4 Bits Word 2 – 6 Bits CRC – 6 Bits CRC Polynomial = X6 + X + 1 (Preset to

111111)

WORD 0 1 0 B1 Aspect Ratio 16:9 4:3 B2 Display Format Letterbox Normal B3 Undeﬁned

WORD 0 B4, B5, B6 Identiﬁcation Information About Video and

Other Signals (e.g., Audio) WORD 1 B7, B8, B9, Identiﬁcation Signal Incidental to Word 0 B10

WORD 2 B11, B12, Identiﬁcation Signal and Information B13, B14 Incidental to Word 0

100 IRE

70 IRE

0 IRE

–40 IRE

11.2s

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

2.235s  20ns

Figure 90. CGMS Waveform Diagram

49.1s  0.5s

CRC SEQUENCE

C13 C14 C15 C16

C17 C18 C19

REV. B

–47–

Page 48

ADV7190/ADV7191

APPENDIX 4

WIDE SCREEN SIGNALING (WSS)

The ADV7190/ADV7191 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7190/ADV7191 is conﬁgured in PAL mode. The WSS data is 14-bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code, see Figure 91. The bits are output from the conﬁguration registers in the following order: C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13. If the bit C/W07 is set to a Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 ms from the falling edge of HSYNC) is available for the insertion of video.

Function of CGMS Bits

Bit 0–Bit 2 Aspect Ratio/Format/Position Bit 3 Is Odd Parity Check of Bit 0–Bit 2

Aspect B0, B1, B2, B3 Ratio Format Position 00 014:3 Full Format Nonapplicable 10 0014:9 Letterbox Center 01 0014:9 Letterbox Top 11 0116:9 Letterbox Center 00 1016:9 Letterbox Top 10 11>16:9 Letterbox Center 01 1114:9 Full Format Center 11 1016:9 Nonapplicable Nonapplicable

B4 0Camera Mode 1 Film Mode

B5 0 Standard Coding 1Motion Adaptive Color Plus

B6 0No Helper 1Modulated Helper

B7 RESERVED

B9 B10 00No Open Subtitles 10Subtitles in Active Image Area 01Subtitles Out of Active Image Area 11RESERVED

B11 0No Surround Sound Information 1 Surround Sound Mode

B12 RESERVED

B13 RESERVED

500mV

11.0s

RUN-IN

SEQUENCE

START

CODE

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12

38.4s

42.5s

Figure 91. WSS Waveform Diagram

W13

ACTIVE

VIDEO

–48–

REV. B

Page 49

APPENDIX 5

TELETEXT INSERTION

ADV7190/ADV7191

Time, tPD, is the time needed by the ADV7190/ADV7191 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears t

SYNTTXOUT

leading edge of the horizontal signal. Time, TTX

= 10.2 ms after the

, is the

DEL

pipeline delay time by the source that is gated by the TTXREQ signal in order to deliver TTX data.

With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct position of 10.2 ms after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline delays.

The width of the TTXREQ signal must always be maintained so it allows the insertion of 360 (in order to comply with the Teletext Standard PAL-WST) teletext bits at a text data rate of

6.9375 Mbits/s. This is achieved by setting TC03–TC00 to 0. The insertion window is not open if the Teletext Enable bit (MR33) is set to 0.

45 BYTES (360 BITS) – PAL

TELETEXT VBI LINE

Teletext Protocol

The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:

(27 MHz/4) = 6.75 MHz

(6.9375 ¥ 10

/6.75 ¥ 106 = 1.027777

Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit has a width of almost four clock cycles. The ADV7190/ADV7191 uses an internal sequencer and variable phase interpolation ﬁlter to minimize the phase jitter and thus generate a bandlimited signal which can be output on the CVBS and Y outputs.

At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are Bits 47, 56, 65, and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers.

ADDRESS & DATA

CVBS/Y

HSYNC

TTX

DATA

TTXREQ

RUN-IN CLOCK

Figure 92. Teletext VBI Line

SYNTTXOUT

10.2s

TTX

DEL

TTX

SYNTTXOUT

= PIPELINE DELAY THROUGH ADV7190/ADV7191

TTX

= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])

DEL

= 10.2s

PROGRAMMABLE PULSE EDGES

Figure 93. Teletext Functionality Diagram

REV. B

–49–

Page 50

ADV7190/ADV7191

APPENDIX 6

OPTIONAL OUTPUT FILTER

If an output ﬁlter is required for the CVBS, YUV, Chroma, and RGB outputs of the ADV7190/ADV7191, the ﬁlter in Figure 94 can be used in 2¥ Oversampling Mode. Figure 96 shows a filter that can be used in 4¥ Oversampling Mode. The plot of the ﬁlter characteristics are shown in Figures 95 and 97. An output ﬁlter is not required if the outputs of the ADV7190/ADV7191 are connected to most analog monitors, or TVs; however, if the output signals are applied to a system where sampling is used (e.g., Digital TVs), a ﬁlter is required to prevent aliasing.

22H

68pF

6.8H

FILTER O/P

FILTER I/P

22H

22pF 56pF

600 600

Figure 94. Output Filter for 2¥ Oversampling Mode

–10

–20

–30

FILTER I/P

22H

600 600

27pF

10H

FILTER O/P

68pF

Figure 96. Output Filter for 4¥ Oversampling Mode

–7

–14

–21

–28

–35

–42

MAGNITUDE – dB

–49

–56

–63

–70

100k

1.0M 10M FREQUENCY – Hz

100M

Figure 97. Output Filter Plot for 4¥ Oversampling Filter

–40

MAGNITUDE – dB

–50

–60

–70

100k

1.0M 10M

FREQUENCY – Hz

100M

Figure 95. Output Filter Plot for 2¥ Oversampling Filter

2 FILTER REQUIREMENTS

FREQUENCY – MHz

Figure 98. Output Filter Requirements in 4¥ Oversampling Mode

4 FILTER REQUIREMENTS

27.0 40.5 54.013.56.75

–50–

REV. B

Page 51

APPENDIX 7

DAC BUFFERING

ADV7190/ADV7191

External buffering is needed on the ADV7190/ADV7191 DAC outputs. The conﬁguration in Figure 99 is recommended.

When calculating absolute output full-scale current and voltage use the following equations:

= I

OUT

REF

¥ R

LOAD

¥ K)/R

REF

SET

= 1.235 V

OUT

= (V

OUT

K = 4.2146 constant, V

ADV7190/ADV7191

OUTPUT BUFFER

LUMA

CHROMA

1.2k

PIXEL PORT

SET1

SET2

REF

DIGITAL

CORE

DAC A CVBS

DAC B

DAC C

DAC D

DAC E

DAC F

Figure 99. Output DAC Buffering Conﬁguration

INPUT/

OPTIONAL

FILTER O/P

AD8051

–V

OUTPUT TO TV MONITOR

Figure 100. Recommended DAC Output Buffer Using an Op Amp

REV. B

–51–

Page 52

ADV7190/ADV7191

APPENDIX 8

RECOMMENDED REGISTER VALUES

The ADV7190/ADV7191 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards.

NTSC (F

Address Data

00Hex Mode Register 0 10Hex 01Hex Mode Register 1 3FHex 02Hex Mode Register 2 62Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 04Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 16Hex 0DHex Subcarrier Frequency Register 1 7CHex 0EHex Subcarrier Frequency Register 2 F0Hex 0FHex Subcarrier Frequency Register 3 21Hex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 44Hex 24Hex DNR 1 20Hex 25Hex DNR 2 00Hex 35Hex Output Clock Register 70Hex

= 3.5795454 MHz)

PAL B, D, G, H, I (FSC = 4.43361875 MHz)

Address Data

00Hex Mode Register 0 11Hex 01Hex Mode Register 1 3FHex 02Hex Mode Register 2 62Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 04Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 CBHex 0DHex Subcarrier Frequency Register 1 8AHex 0EHex Subcarrier Frequency Register 2 09Hex 0FHex Subcarrier Frequency Register 3 2AHex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR0 44Hex 24Hex DNR1 20Hex 25Hex DNR2 00Hex 35Hex Output Clock Register 70Hex

–52–

REV. B

Page 53

ADV7190/ADV7191

PAL N (FSC = 4.43361875 MHz)

Address Data

00Hex Mode Register 0 13Hex 01Hex Mode Register 1 3FHex 02Hex Mode Register 2 62Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 04Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 CBHex 0DHex Subcarrier Frequency Register 1 8AHex 0EHex Subcarrier Frequency Register 2 09Hex 0FHex Subcarrier Frequency Register 3 2AHex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 44Hex 24Hex DNR 1 20Hex 25Hex DNR 2 00Hex 35Hex Output Clock Register 70Hex

PAL 60 (FSC = 4.43361875 MHz)

Address Data

00Hex Mode Register 0 12Hex 01Hex Mode Register 1 3FHex 02Hex Mode Register 2 62Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 04Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 CBHex 0DHex Subcarrier Frequency Register 1 8AHex 0EHex Subcarrier Frequency Register 2 09Hex 0FHex Subcarrier Frequency Register 3 2AHex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 44Hex 24Hex DNR 1 20Hex 25Hex DNR 2 00Hex 35Hex Output Clock Register 70Hex

REV. B

–53–

Page 54

ADV7190/ADV7191

PAL M (FSC = 3.57561149 MHz)

Address Data

14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 44Hex 24Hex DNR 1 20Hex 25Hex DNR 2 00Hex 35Hex Output Clock Register 70Hex

–54–

REV. B

Page 55

POWER-ON RESET REGISTER VALUES

ADV7190/ADV7191

POWER-ON RESET REG VALUES

(PAL_NTSC = 0, NTSC Selected)

Address Data

00Hex Mode Register 0 00Hex 01Hex Mode Register 1 07Hex 02Hex Mode Register 2 08Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 00Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 16Hex 0DHex Subcarrier Frequency Register 1 7CHex 0EHex Subcarrier Frequency Register 2 F0Hex 0FHex Subcarrier Frequency Register 3 21Hex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 00Hex 24Hex DNR 1 00Hex 25Hex DNR 2 00Hex 26Hex Gamma 0 xxHex 27Hex Gamma 1 xxHex 28Hex Gamma 2 xxHex 29Hex Gamma 3 xxHex 2AHex Gamma 4 xxHex 2BHex Gamma 5 xxHex 2CHex Gamma 6 xxHex 2DHex Gamma 7 xxHex 2EHex Gamma 8 xxHex 2FHex Gamma 9 xxHex 30Hex Gamma 10 xxHex 31Hex Gamma 11 xxHex 32Hex Gamma 12 xxHex 33Hex Gamma 13 xxHex 34Hex Brightness Detect Register xxHex 35Hex Output Clock Register 72Hex

POWER-ON RESET REG VALUES

(PAL_NTSC = 1, PAL Selected)

Address Data

00Hex Mode Register 0 01Hex 01Hex Mode Register 1 07Hex 02Hex Mode Register 2 08Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 05Hex Mode Register 5 00Hex 06Hex Mode Register 6 00Hex 07Hex Mode Register 7 00Hex 08Hex Mode Register 8 00Hex 09Hex Mode Register 9 00Hex 0AHex Timing Register 0 08Hex 0BHex Timing Register 1 00Hex 0CHex Subcarrier Frequency Register 0 CBHex 0DHex Subcarrier Frequency Register 1 8AHex 0EHex Subcarrier Frequency Register 2 09Hex 0FHex Subcarrier Frequency Register 3 2AHex 10Hex Subcarrier Phase Register 00Hex 11Hex Closed Captioning Ext Register 0 00Hex 12Hex Closed Captioning Ext Register 1 00Hex 13Hex Closed Captioning Register 0 00Hex 14Hex Closed Captioning Register 1 00Hex 15Hex Pedestal Control Register 0 00Hex 16Hex Pedestal Control Register 1 00Hex 17Hex Pedestal Control Register 2 00Hex 18Hex Pedestal Control Register 3 00Hex 19Hex CGMS_WSS Reg 0 00Hex 1AHex CGMS_WSS Reg 1 00Hex 1BHex CGMS_WSS Reg 2 00Hex 1CHex Teletext Control Register 00Hex 1DHex Contrast Control Register 00Hex 1EHex Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 00Hex 24Hex DNR 1 00Hex 25Hex DNR 2 00Hex 26Hex Gamma 0 xxHex 27Hex Gamma 1 xxHex 28Hex Gamma 2 xxHex 29Hex Gamma 3 xxHex 2AHex Gamma 4 xxHex 2BHex Gamma 5 xxHex 2CHex Gamma 6 xxHex 2DHex Gamma 7 xxHex 2EHex Gamma 8 xxHex 2FHex Gamma 9 xxHex 30Hex Gamma 10 xxHex 31Hex Gamma 11 xxHex 32Hex Gamma 12 xxHex 33Hex Gamma 13 xxHex 34Hex Brightness Detect Register xxHex 35Hex Output Clock Register 72Hex

REV. B

–55–

Page 56

ADV7190/ADV7191

APPENDIX 9

NTSC WAVEFORMS (WITH PEDESTAL)

130.8 IRE

100 IRE

7.5 IRE

–40 IRE

100 IRE

7.5 IRE 0 IRE

–40 IRE

963.8mV

650mV

0 IRE

286mV (p-p)

714.2mV

Figure 101. NTSC Composite Video Levels

714.2mV

Figure 102. NTSC Luma Video Levels

629.7mV (p-p)

PEAK COMPOSITE

REF WHITE

BLACK LEVEL BLANK LEVEL

SYNC LEVEL

REF WHITE

BLACK LEVEL BLANK LEVEL

SYNC LEVEL

PEAK CHROMA

BLANK/BLACK LEVEL

1268.1mV

1048.4mV

387.6mV

334.2mV

48.3mV

1048.4mV

387.6mV

334.2mV

48.3mV

335.2mV

0mV

100 IRE

7.5 IRE 0 IRE

–40 IRE

Figure 103. NTSC Chroma Video Levels

720.8mV

Figure 104. NTSC RGB Video Levels

PEAK CHROMA

REF WHITE

BLACK LEVEL BLANK LEVEL

SYNC LEVEL

1052.2mV

387.5mV

331.4mV

45.9mV

–56–

REV. B

Page 57

NTSC WAVEFORMS (WITHOUT PEDESTAL)

ADV7190/ADV7191

130.8 IRE

100 IRE

0 IRE

–40 IRE

100 IRE

0 IRE

–40 IRE

978mV

650mV

307mV (p-p)

714.2mV

BLANK/BLACK LEVEL

Figure 105. NTSC Composite Video Levels

714.2mV

BLANK/BLACK LEVEL

Figure 106. NTSC Luma Video Levels

694.9mV (p-p)

PEAK COMPOSITE

REF WHITE

SYNC LEVEL

REF WHITE

SYNC LEVEL

PEAK CHROMA

BLANK/BLACK LEVEL

1289.8mV

1052.2mV

338mV

52.1mV

1052.2mV

338mV

52.1mV

283mV

0mV

100 IRE

0 IRE

–40 IRE

Figure 107. NTSC Chroma Video Levels

715.7mV

Figure 108. NTSC RGB Video Levels

PEAK CHROMA

REF WHITE

BLANK/BLACK LEVEL

SYNC LEVEL

1052.2mV

336.5mV

51mV

REV. B

–57–

Page 58

ADV7190/ADV7191

PAL WAVEFORMS

990mV

650mV

1284.2mV

1047.1mV

350.7mV

50.8mV

1047mV

350.7mV

50.8mV

300mV (p-p)

PEAK COMPOSITE

REF WHITE

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 109. PAL Composite Video Levels

REF WHITE

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 110. PAL Luma Video Levels

PEAK CHROMA

672mV (p-p)

BLANK/BLACK LEVEL

318mV

0mV

1050.2mV

351.8mV

51mV

PEAK CHROMA

Figure 111. PAL Chroma Video Levels

REF WHITE

698.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 112. PAL RGB Video Levels

–58–

REV. B

Page 59

WHITE

BETACAM LEVEL

0mV

82mV

423mV

505mV

0mV

–82mV

–505mV

–423mV

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

BETACAM LEVEL

0mV

76mV

391mV

467mV

0mV

–76mV

–467mV

–391mV

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

SMPTE LEVEL

0mV

57mV

293mV

350mV

0mV

–57mV

–350mV

–293mV

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

YELLOW

CYAN

GREEN

334mV

MAGENTA

RED

505mV

BLUE

ADV7190/ADV7191

UV WAVEFORMS

BLACK

BETACAM LEVEL

0mV

171mV

0mV

171mV

334mV

505mV

Figure 113. NTSC 100% Color Bars, No Pedestal U Levels

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

467mV

309mV

BETACAM LEVEL

0mV

158mV

0mV

Figure 116. NTSC 100% Color Bars, No Pedestal V Levels

–158mV

–309mV

–467mV

Figure 114. NTSC 100% Color Bars with Pedestal U Levels

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

SMPTE LEVEL

–350mV

0mV

Figure 115. PAL 100% Color Bars U Levels

118mV

–232mV

232mV

350mV

0mV

–118mV

Figure 117. NTSC 100% Color Bars with Pedestal V Levels

Figure 118. PAL 100% Color Bars V Levels

REV. B

–59–

Page 60

ADV7190/ADV7191

0.6

0.4

VOLTS

0.2

0.0

OUTPUT WAVEFORMS

0.2

0.0 10.0 20.0 30.0 40.0 50.0 60.0

NOISE REDUCTION: 0.00 dB APL = 39.1% PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = SOURCE

SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2 3 4

L608

MICROSECONDS

Figure 119. 100/0/75/0 PAL Color Bars

0.5

VOLTS

0.0

L575

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 MICROSECONDS

APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A

SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1

Figure 120. 100/0/75/0 PAL Color Bars Luminance

–60–

REV. B

Page 61

0.5

0.0

VOLTS

ADV7190/ADV7191

–0.5

APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A

SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1

L575

10.0 30.0 40.0 50.0 60.020.0

MICROSECONDS

NO BRUCH SIGNAL

Figure 121. 100/0/75/0 PAL Color Bars Chrominance

100.0

0.5

50.0

VOLTS

0.0

IRE:FLT

0.0

REV. B

–50.0

L76

0.0 10.0 20.0 30.0 40.0 50.0 60.0

APL = 44.6% PRECISION MODE OFF

525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = A

SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2

MICROSECONDS

Figure 122. 100/7.5/75/7.5 NTSC Color Bars

–61–

Page 62

ADV7190/ADV7191

100.0

0.6

0.4

VOLTS

0.2

0.0

–0.2

NOISE REDUCTION: 15.05dB APL = 44.7% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE

SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2

50.0

IRE:FLT

0.0

F2 L238

10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS

Figure 123. 100/7.5/75/7.5 NTSC Color Bars Luminance

0.4

50.0

0.2

VOLTS

–0.2

–0.4

NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! PRECISION MODE OFF

525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = B

SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2

IRE:FLT

0.0

–50.0

F1 L76

0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS

Figure 124. 100/7.5/75/7.5 NTSC Color Bars Chrominance

–62–

REV. B

Page 63

PARADE SMPTE/EBU PAL

mV Y(A) mV Pb(B) mV Pr(C)

700

600

500

250

200

150

ADV7190/ADV7191

250

200

150

400

300

200

100

–100

–200

–300

100

–50

–100

–150

–200

–250

Figure 125. PAL YUV Parade Plot

mV GREEN (A) mV BLUE (B) mV RED (C)

700

600

500

400

300

200

100

–100

–200

–300

700

600

500

400

300

200

100

–100

–200

–300

100

–50

–100

–150

–200

–250

700

600

500

400

300

200

100

–100

–200

–300

REV. B

Figure 126. PAL RGB Waveforms

–63–

Page 64

ADV7190/ADV7191

COLOR BAR (NTSC) FIELD = 1 LINE = 21

LUMINANCE LEVEL (IRE)

99.6 69.0 55.9 48.1 36.3 28.3 15.7 7.7

100

GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

CHROMINANCE LEVEL (IRE)

0.0 62.1 87.6 81.8 81.8 87.8 62.1 0.0

100

GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

CHROMINANCE PHASE (DEGREE)

400

VIDEO MEASUREMENT PLOTS

WFM

167.3 283.8 240.9 60.80 103.6 347.1

FCC COLOR BAR

200

GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

AVERAGE 32

COLOR BAR (PAL) LINE = 570

LUMINANCE LEVEL (mV)

1000

500

1000

500

695.7 464.8 366.6 305.7 217.3 156.4 61.2 –0.4

GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

CHROMINANCE LEVEL (mV)

0.0 474.4 669.1 623.5 624.7 669.6 475.2 0.0

GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

Figure 127. NTSC Color Bar Measurement

WFM COLOR BAR

CHROMINANCE PHASE (DEGREE)

400

300

200

100

GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

AVERAGE 32 32

166.7 283.3 240.4 60.4 103.2 346.7

Figure 128. PAL Color Bar Measurement

–64–

REV. B

Page 65

ADV7190/ADV7191

DG DP (NTSC) WFM

FIELD = 1, LINE = 21

DIIFFERENTIAL GAIN (PERCENT)

0.00 0.21 0.02 0.07 0.27 0.08

2.5

1.5

0.5

–0.5

–1.5

–2.5

DIFFERENTIAL PHASE (DEGREE)

0.00 0.10 0.12 0.15 0.13 0.10

2.5

1.5

0.5

–0.5

–1.5

–2.5

AVERAGE 32

Figure 129. NTSC DG DP Measurement

MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27

MIN = 0.00, MAX = 0.20, pk-pk = 0.20

MOD 5 STEP

DG DP (PAL) WFM

LINE = 570

DIIFFERENTIAL GAIN (PERCENT)

0.00 0.30 0.15 0.24 0.32 0.26

2.5

1.5

0.5

–0.5

–1.5

–2.5

DIFFERENTIAL PHASE (DEGREE)

0.00 0.09 0.13 0.16 0.12 0.14

2.5

1.5

0.5

–0.5

–1.5

–2.5

AVERAGE 32

Figure 131. PAL DG DP Measurement

MOD 5 STEP

MIN = 0.00, MAX = 0.32, pk-pk = 0.32

MIN = 0.00, MAX = 0.16, pk-pk = 0.16

LUMINANCE NONLINEARITY (NTSC) WFM

FIELD = 2, LINE = 77

LUMINANCE NONLINEARITY (PERCENT)

111

99.90 99.90 99.60 100.0 99.90

109

107

105

103

101

AVERAGE 32

Figure 130. NTSC Luminance Nonlinearity

MOD 5 STEP

LUMINANCE NONLINEARITY (PAL) WFM

MOD 5 STEP

LINE = 570

pk-pk = 0.4

LUMINANCE NONLINEARITY (PERCENT)

113

99.6 99.9 100.0 99.6 99.9

pk-pk = 0.8

111

109

107

105

103

101

AVERAGE 32

Figure 132. PAL Luminance Nonlinearity

REV. B

–65–

Page 66

ADV7190/ADV7191

(

)

(

)

CHROMINANCE NONLINEARITY(NTSC) WFM NTSC–7 COMBINATION FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) REF = 40IRE PACKET

0.5 0.0 –0.3

–10

20IRE

CHROMINANCE PHASE ERROR (DEGREE) REF = 40IRE PACKET

–5

CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714mV)

0.2

0.1

0.0

–0.1

–0.2

AVERAGE 32

–0.0 0.0 0.0

20IRE

0.0 0.1 0.1

20IRE

40IRE 80IRE

Figure 133. NTSC Chrominance Nonlinearity

CHROMINANCE NONLINEARITY(PAL) WFM MOD 3 STEP LINE = 572 CHROMINANCE AMPLITUDE ERROR (PERCENT) REF = 420mV PACKET

–10

CHROMINANCE PHASE ERROR (DEGREE) REF = 420mV PACKET

–5

CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 700mV)

0.2

0.0

–0.2

AVERAGE 32

0.6 0.0 –0.4

140mV

–0.3 0.0 –0.3

140mV

0.0 0.0 0.1

140mV

420mV 700mV

Figure 135. PAL Chrominance Nonlinearity

CHROMINANCE AM/PM (NTSC) WFM RED FIELD FIELD = 2, LINE = 217

BANDWIDTH 10kHz TO 100kHz

AM NOISE –86.5dB RMS

–95 –90 –85 –80 –75 –70 –65 –60

PM NOISE –82.7dB RMS

–95 –90 –85 –80 –75 –70 –65 –60

0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL

Figure 134. NTSC Chrominance AM/PM

dB RMS

CHROMINANCE AM/PM (PAL) WFM APPROPRIATE LINE = 572

BANDWIDTH 10kHz TO 100kHz

AM NOISE –84.2dB RMS

–95 –90 –85 –80 –75 –70 –65 –60

PM NOISE –80.5dB RMS

–95 –90 –85 –80 –75 –70 –65 –60

0dB = 700mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL

Figure 136. PAL Chrominance AM/PM

dB RMS

–66–

REV. B

Page 67

ADV7190/ADV7191

NOISE SPECTRUM (NTSC) WFM

FIELD = 2, LINE = 223

AMPLITUDE (0dB = 714mV p-p)

BANDWIDTH 10kHz TO FULL

–20

–40

–60

–80

–100

123456

MHz

NOISE LEVEL = –79.7dB RMS

Figure 137. NTSC Noise Spectrum: Pedestal

NOISE SPECTRUM (NTSC) WFM

FIELD = 2, LINE = 217

AMPLITUDE (0dB = 714mV p-p)

BANDWIDTH 100kHz TO FULL (TILT NULL)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1234 56

MHz

NOISE LEVEL = –63.1dB RMS

Figure 138. NTSC Noise Spectrum: Ramp

PEDESTAL

RAMP

NOISE SPECTRUM (PAL) WFM

LINE = 511

AMPLITUDE (0dB = 714mV p-p)

BANDWIDTH 10kHz TO FULL

–20

–40

–60

–80

–100

123 4 57

Figure 139. PAL Noise Spectrum: Pedestal

NOISE SPECTRUM (PAL) WFM

LINE = 572

AMPLITUDE (0dB = 700mV p-p)

BANDWIDTH 100kHz TO FULL (TILT NULL)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

123 45

Figure 140. PAL Noise Spectrum: Ramp

MHz

PEDESTAL

NOISE LEVEL = –79.1dB RMS

RAMP

NOISE LEVEL = –62.3dB RMS

REV. B

–67–

Page 68

ADV7190/ADV7191

APL = 39.6%

APPENDIX 10

VECTOR PLOTS

SYSTEM LINE L608 ANGLE (DEG) 0.0

75%

M g

100%

GAIN  1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND –V

SOUND IN SYNC OFF

APL = 45.1%

m g

Figure 141. PAL Vector Plot

R-Y

SYSTEM LINE L76F1 ANGLE (DEG) 0.0

100%

M g

GAIN  1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE

B-Y

–Q

SETUP 7.5%

75%

Figure 142. NTSC Vector Plot

–68–

–I

REV. B

Page 69

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

64-Lead Quad Flatpack [LQFP]

(ST-64)

ADV7190/ADV7191

0.030 (0.75)

0.024 (0.60)

0.018 (0.45)

SEATING

PLANE

0.004 (0.102) MAX LEAD

COPLANARITY

0.063 (1.60) MAX

0.007 (0.17) MAX

12 TYP

10

0.640 (16.25)

0.630 (16.00) SQ

0.620 (15.75)

TOP VIEW

(PINS DOWN)

6 2

0.031 (0.80) BSC

7 0

0.014 (0.35)

4964

0.555 (14.10)

0.551 (14.00) SQ

0.547 (13.90)

0.057 (1.45)

0.055 (1.40)

0.053 (1.35)

REV. B

–69–

Page 70

ADV7190/ADV7191

Revision History

Location Page

5/02—Data Sheet changed from REV. A to REV. B.

Added Figure 46b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Changes to Color Bar Control (MR46) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

–70–

REV. B

Page 71

–71–

Page 72

C00230–0–5/02(B)

–72–

PRINTED IN U.S.A.

Datasheet ADV7190 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

CONTENTS

SPECIFICATIONS

V

5 V TIMING CHARACTERISTICS

3.3 V TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

PACKAGE THERMAL PERFORMANCE

ORDERING GUIDE

PIN FUNCTION DESCRIPTIONS

GENERAL DESCRIPTION

DATA PATH DESCRIPTION

INTERNAL FILTER RESPONSE

Chroma/Luma Delay

Clamp Output

CSO, HSO, and VSO Outputs

Color Bar Generation

Color Burst Signal Control

Color Controls

Chrominance Control

Undershoot Limiter

Digital Noise Reduction

Double Buffering

Gamma Correction Control

NTSC Pedestal Control

Power-On Reset

Real-Time Control, Subcarrier Reset, and Timing Reset

SCH Phase Mode

Sleep Mode

Square Pixel Mode

Vertical Blanking Data Insertion and BLANK Input

YUV Levels

16-Bit Interface

4 Oversampling and Internal PLL

VIDEO TIMING DESCRIPTION

RESET SEQUENCE

MPU PORT DESCRIPTION

REGISTER ACCESSES

REGISTER PROGRAMMING

NTSC WAVEFORMS (WITHOUT PEDESTAL)

PAL WAVEFORMS

UV WAVEFORMS

OUTPUT WAVEFORMS

VIDEO MEASUREMENT PLOTS

OUTLINE DIMENSIONS

Revision History