Datasheet ADV7176, ADV7175 Datasheet (Analog Devices)

Integrated Digital CCIR-601

a

FEATURES
CCIR-601 YCrCb to PAL/NTSC Video Encoder
Single 27 MHz Clock Required (32 Oversampling)
Pixel Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
SMPTE 170M NTSC Compatible Composite Video Output
CCIR624/CCIR601 PAL Compatible Composite Video Output
SCART/PeriTV Support
YUV Output Mode
Simultaneous Composite and S-VHS Y/C or RGB YUV

Video Outputs
Programmable Luma Filters (Low-Pass/Notch)
Square Pixel Support (Slave Mode)
Allows Subcarrier Phase Locking with External Video

Source
10-Bit DAC Resolution for Encoded Video Channels
8-Bit DAC Resolution for RGB Output
YUV Interpolation for Accurate Subcarrier Construction
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Master/Slave Operation Supported
Master Mode Timing Programmability
Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)*

FUNCTIONAL BLOCK DIAGRAM

YCrCb to PAL/NTSC Video Encoder

ADV7175/ADV7176

Close Captioning Support
Teletext Support (Passthrough Mode)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I
+5 V CMOS Monolithic Construction
44-Pin PQFP Thermally Enhanced Package

APPLICATIONS
MPEG-1 and MPEG-2 Video
DVD
Digital Satellite/Cable Systems (Set Top Boxes/IRDs)
Video Games
CD Video/Karaoke
Professional Studio Quality
PC Video/Multimedia

GENERAL DESCRIPTION

The ADV7175/ADV7176 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 component video data into a
standard analog baseband television signal compatible with world
wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In
addition to the composite output signal, there is the facility to out­put S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or
RGB format is simultaneously available at the analog outputs with
the composite video signal. Each analog output generates a
standard video-level signal into a doubly terminated 75 Ω load.

2

C Compatible)

(Continued on page 6)

V

RESET

COLOR

DATA
P7–P0

P15–P8

HSYNC

FIELD/VSYNC

BLANK

AA

YUV TO

RBG

MATRIX

ADD

SYNC

ADD

BURST

ADD

BURST

8

8

88

INTER-

POLATOR

INTER-

POLATOR

INTER-

POLATOR

4:2:2 TO

4:4:4

INTER-

POLATOR

VIDEO TIMING

GENERATOR

8

8

8

CLOCK

YCrCb

TO

YUV

MATRIX

8

8 10

2

I

C MPU PORT

SCLOCK SDATA ALSB

8

8

8

8

LOW-PASS

FILTER

8

LOW-PASS

FILTER

8

LOW-PASS

FILTER

REAL-TIME

CONTROL

CIRCUIT

SCRESET/RTC

Y

U

V

10

10

10

SIN/COS

DDS BLOCK

10

M
U

10

10-BIT

L

DAC

T

I

10

P

10-BIT

L

DAC

E

10

X

10-BIT

E

DAC

R

10

10-BIT

DAC

ADV7175/ADV7176

VOLTAGE

REFERENCE

CIRCUIT

GND

GREEN/
LUMA/
Y

RED/
CHROMA/
V

BLUE/
COMPOSITE/
U

COMPOSITE

V

REF

R

SET

COMP

*This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 a nd other intellectual property rights. The Macrovision anticopy process is

licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

© Analog Devices, Inc., 1996

(VAA = +5 V1, V
T

ADV7175/ADV7176–SPECIFICA TIONS

Model ADV7175/ADV7176
Parameter Conditions

1

MIN

to T

MAX

= 1.235 V R

REF

2

unless otherwise noted)

= 150 V. All specifications

SET

Min Typ Max Units

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±1 LSB

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

VIN = 0.4 V or 2.4 V ±1 µA

2V

0.8 V

10 pF

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

I
I

= 400 µA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

Floating-State Leakage Current 10 µA
Floating-State Output Capacitance 10 pF

ANALOG OUTPUTS

Output Current
Output Current

3
4

33 34.7 37 mA

8mA
Full-Scale DAC Output 182.5 IRE
LSB Size 33.9 µA
DAC-to-DAC Matching 25%
Output Compliance, V
Output Impedance, R

OC

OUT

Output Capacitance, C

OUT

I

= 0 mA 30 pF

OUT

0 +1.4 V

15 kΩ

VOLTAGE REFERENCE

Voltage Reference Range, V

POWER REQUIREMENTS

V

AA

6

I

DAC

7

I

CCT

5

REF

I

VREFOUT

= 20 µA 1.112 1.235 1.359 V

5V

140 155 mA

110 150 mA
Power Supply Rejection Ratio COMP = 0.1 µF 0.02 0.5 %/%

DYNAMIC PERFORMANCE

8

Luma Bandwidth9 (Low-Pass Filter) NTSC Mode

Stopband Cutoff >50 dB Attenuation 7.5 MHz
Pass Band Cutoff <0.06 dB Attenuation 2.3 MHz

Chroma Bandwidth NTSC Mode

Stopband Cutoff <40 dB Attenuation 3.6 MHz
Pass Band Cutoff >0.1 dB Attenuation 1.0 MHz

Luma Bandwidth

9

(Low-Pass Filter) PAL MODE
Stopband Cutoff >50 dB Attenuation 8.0 MHz
Pass Band Cutoff <0.06 dB Attenuation 3.4 MHz

Chroma Bandwidth PAL MODE

Stopband Cutoff <40 dB Attenuation 4.0 MHz
Pass Band Cutoff >0.1 dB Attenuation 1.3 MHz
Differential Gain 0.8 %
Differential Phase 0.8 Degree
Differential Gain Lower Power Mode 7 %
Differential Phase Lower Power Mode 2 Degree
SNR RMS 60 dB rms
SNR Peak Periodic 56 dB p-p
Hue Accuracy 1.0 Degree
Color Saturation Accuracy 1.0 %

NOTES

1

± 5% for all versions.

2

Temperature range T

3

Full drive into 37.5 Ω load.

4

Minimum drive with buffered/scaled output load.

5

Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 100°C.

6

I

is the total current to drive all four DACs. Turning off one DAC reduces I

DAC

7

I

(Circuit Currrent) is the continuous currrent required to drive the device.

CCT

8

Guaranteed by characterization.

9

These specifications are for the low-pass filter only. For the other internal filters please see Figure 3.

Specifications subject to change without notice.

MIN

to T

: 0°C to 70°C.

MAX

correspondingly.

DAC

–2–

REV. A

ADV7175/ADV7176

AC CHARACTERISTICS

Parameter Min Typ Max Units Condition

Chroma Nonlinear Gain 0.6 ±% Referenced to 40 IRE
Chroma Nonlinear Phase 1 ±° NTSC
Chroma Nonlinear Phase 1.7 ±° PAL
Chroma/Luma Intermod 0.2 ±% Referenced to 714 mV (NTSC)
Chroma/Luma Intermod 0.4 ±% Referenced to 700 mV (PAL)
Chroma/Luma Gain Ineq 0.6 ±%
Chroma/Luma Delay Ineq 1 ns
Luminance Nonlinearity 0.8 ±%
Chroma AM Noise 60 dB
Chroma PM Noise 59 dB

1

TIMING–SPECIFICATIONS

2

(VAA = +5 V3, V

= 1.235 V R

REF

= 150 V. All specifications T

SET

MIN

4

to T

unless otherwise noted)

MAX

Parameter Min Typ Max Units Condition

MPU PORT

1

SCLOCK Frequency 0 100 kHz
SCLOCK High Pulse Width, t
SCLOCK Low Pulse Width, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

ANALOG OUTPUTS

1, 5

1

2

3

4

6

7

8

4.0 µs

4.7 µs

4.0 µs After this period the first clock pulse is generated

4.7 µs Relevant for repeated start condition.
250 ns

1 µs
300 ns

4.7 µs

Analog Output Delay 5 ns
DAC Analog Output Skew 0 ns

CLOCK CONTROL
AND PIXEL PORT

F

CLOCK

Clock High Time t
Clock Low Time t
Data Setup Time t
Data Hold Time t
Control Setup Time t
Control Hold Time t
Digital Output Access Time t
Digital Output Hold Time t
Pipeline Delay t

NOTES

1

Guaranteed by characterization.

2

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog Output Load ≤ 3 pF.

3

±5% for all versions.

4

Temperature range (T

5

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6

Pixel Port consists of the following inputs:
Pixel Inputs: P15–P0
Pixel Controls: HSYNC, FIELD/VSYNC, BLANK
Clock Input: CLOCK

Specifications subject to change without notice.

15

MIN

6

9

10

11

12

to T

11

12

); 0°C to +70°C.

MAX

24.52 27 29.5 MHz
8ns
8ns

3.5 ns
1ns
4ns
2ns

13

14

6ns

24 ns

37 Clock Cycles

REV. A

–3–

ADV7175/ADV7176

WARNING!

ESD SENSITIVE DEVICE

CONTROL

SDATA

SCLOCK

I/PS

CLOCK

HSYNC,

FIELD/VSYNC,

BLANK

t

t

3

t

6

t

1

5

t

2

t

7

Figure 1. MPU Port Timing Diagram

t

t

9

10

t

12

t

3

t

4

t

8

CONTROL

O/PS

PIXEL INPUT

DATA

HSYNC,

FIELD/VSYNC,

BLANK

Cb Y Cr Y Cb Y

Figure 2. Pixel and Control Data Timing Diagram

ABSOLUTE MAXIMUM RATINGS

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Input Pin . GND – 0.5 V to V
Storage Temperature (T
Junction Temperature (T

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C

Analog Outputs to GND

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.

) . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . +150°C

J

2

. . . . . . . . . . . . . GND –0.5 to V

+ 0.5 V

AA

AA

t

11

t

13

t

14

ORDERING GUIDE

Temperature Package

Model Range Option

ADV7175KS 0°C to +70°C S-44
ADV7176KS 0°C to +70°C S-44

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175/ADV7176 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

ADV7175/ADV7176

PIN DESCRIPTION

Mnemonic Input/Output Function

P15-P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or

16-Bit YCrCb Pixel Port (P15–P0). P0 represents the LSB.

CLOCK I TTL Clock Input. Requires a stable 27 MHz reference Clock for proper operation.

Alternatively a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel
operation.

HSYNC I/O HSYNC (Modes 1 & 2) Control Signal. This pin may be configured to output (Mas-

ter Mode) or accept (Slave Mode) Sync signals.

FIELD/VSYNC I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may

be configured to output (Master Mode) or accept (Slave Mode) these control signals.

BLANK I/O Video Blanking Control Signal. The pixel inputs are ignored when this is logic level

“0.” This signal is optional.

SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode

Register 2. It can be configured as a subcarrier reset pin, in which case a high to low
transition on this pin will reset the subcarrier to field 0. Alternatively it may be con­figured as a Real Time Control (RTC) input.

V

REF

R

SET

COMP O Compensation Pin. Connect a 0.1 µF capacitor from COMP to V
COMPOSITE O PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for

RED/CHROMA/V O RED/S-VHS C/V Analog Output.
GREEN/LUMA/Y O GREEN/S-VHS Y/Y Analog Output.
BLUE/COMPOSITE/U O BLUE/Composite/U Analog Output.
SCLOCK I MPU Port Serial Interface Clock Input.
SDATA I/O MPU Port Serial Data Input/Output.
ALSB I TTL Address Input. This signal set up the LSB of the MPU address.
RESET I The input resets the on chip timing generator and sets the ADV7175/ADV7176 into

V

AA

GND G Ground Pin.

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
I A 150 Ω resistor connected from this pin to GND is used to control full-scale ampli-

tudes of the video signals.

.

AA

NTSC and 1300 mV for PAL.

default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 ×
composite & S VHS out.

P +5 V Supply.

REV. A

PIN CONFIGURATION

CLOCK

GND

P3

P4

42

4344 36

1

V

AA

PIN 1
IDENTIFIER

2

P5

3

P6

4

P7

5

P8

6

P9

7

P10

8

P11

9

P12

10

GND

11

V

AA

12 13 14 15 16 17 18 192021 22

P13

40

ADV7175/ADV7176

(Not to Scale)

P14

P15

FIELD/

HSYNC

P2

P1

39 3841

PQFP

TOP VIEW

VSYNC

BLANK

–5–

P0

ALSB

AA

V

GND

GND

AA

V

35 3437

SCRESET/

GND

RTC

SET

R

RESET

33

V

32

COMPOSITE

31
30
29

GND

28

V

27

GREEN/LUMA/Y

26

RED/CHROMA/V

25

COMP

24

SDATA

23

SCLOCK

REF

BLUE/COMPOSITE/U
V

AA

AA

ADV7175/ADV7176

(Continued from page 1)

The ADV7175/ADV7176 also supports both a PAL and NTSC
square pixel mode in slave mode.

The video encoder accepts an 8-bit parallel pixel data stream in
CCIR-656 format or a 16-bit parallel data stream. This 4:2:2
data stream is interpolated into 4:4:4 component video (YUV).
The YUV video is interpolated to two times the pixel rate. The
color-difference components (UV) are quadrature modulated
using a subcarrier frequency generated by an on-chip synthesizer
(also running at two times the pixel rate). The two times pixel
rate sampling allows more accurate generation of the subcarrier
because frequency and phase errors are reduced by the higher
sampling rate. The ADV7175/ADV7176 also offers the option to
output the YUV information directly.

The luminance and chrominance components are digitally com­bined and the resulting composite signal is output via a 10-bit
DAC. Three additional 10-/8-bit DACs are provided to output
S-VHS Y/C Video (10 bits), YUV or RGB Video (8 bits).

The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts (and
can generate)

HSYNC, VSYNC & FIELD timing signals. These
timing signals can be adjusted to change pulse width and posi­tion while the part is in the master mode. The encoder requires a
single two times pixel rate (27 MHz) clock for standard operation.
Alternatively the encoder requires 24.54 MHz clock for NTSC
or 29.5 MHz clock for PAL square pixel mode operation. All in­ternal clocks are generated on-chip. The ADV7175/ADV7176
modes are set up over a two wire serial bidirectional port (I

2

C

Compatible) with two slave addresses.
Additionally, the ADV7175/ADV7176 allows a subcarrier phase

lock with an external video source and has a color bar generator
on-board.

Functionally the ADV7175 and ADV7176 are the same with
the exception that the ADV7175 can output the Macrovision
(Revision 6.1/7.x) anticopy algorithm.

The ADV7175/ADV7176 is fabricated in a +5 V CMOS pro­cess. Its monolithic CMOS construction ensures greater func­tionality with low power dissipation.

The ADV7175/ADV7176 is packaged in a 44-pin thermally en­hanced PQFP package (patent pending).

The ADV7175/ADV7176 is protected by U.S. Patent Numbers
5,343,196 and 5,442,355 and other intellectual property rights.

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a

13.5 MHz data rate. The pixel data is de-multiplexed to form
three data paths. Y has a range of 16 to 235, Cr and Cb have a
range of 128 ± 112. The ADV7175/ADV7176 supports PAL
(B, D, G, H, I, N, M) and NTSC (with and without Pedestal)
standards. The appropriate SYNC, BLANK and burst levels are
added to the YCrCb data. Macrovision antitaping (ADV7175
only) and close-captioning levels are also added to Y and the
resultant data is interpolated to a rate of 27 MHz. The interpo­lated data is filtered and scaled by three digital FIR filters.

The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi­nance signal. The luma (Y) signal can be delayed 1-3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.

The YCrCb data is also used to generate RGB data with appro­priate SYNC and BLANK levels. The RGB data is in sychro­nization with the composite video output. Alternatively analog
YUV data can be generated instead of RGB.

The four 10-bit DACs can be used to output:

1. 10-bit composite video + 8-bit RGB video.

2. 10-bit composite video + 8-bit YUV video.

3. Two 10-bit composite video signals
+ 10-bit LUMA & CHROMA (Y/C) signals.

Alternatively, each DAC can be individually powered off if not
required.

All possible video outputs are illustrated in Appendix 3, 4 and 5.

INTERNAL FILTER RESPONSE

The Y filter supports several different frequency responses in­cluding two 4.5/5.0 MHz low-pass and PAL/NTSC subcarrier
notch responses. The U and V filters have a 0.6/1 0.3 MHz
low-pass response.

These filter characteristics are illustrated in Figures 3 to 11.

FILTER SELECTION

MR04 MR03
NTSC 0 0 2.3 0.026 7.5
PAL 0 0 3.4 0.098 8.0
NTSC 0 1 1.0 0.085 3.57
PAL 0 1 1.4 0.107 4.43
NTSC/PAL 1 0 4.0 0.150 8.0
NTSC 1 1 2.3 0.054 7.5
PAL 1 1 3.4 0.106 8.0

PASSBAND

CUT OFF (MHz)

PASSBAND

RIPPLE (dB)

Figure 3. Y Filter Specifications

FILTER SELECTION

NTSC 1.0 0.085 3.6
PAL 1.3 0.04 4.0

PASSBAND

CUT OFF (MHz)

PASSBAND

RIPPLE (dB)

CUT OFF (MHz)

Figure 4. UV Filter Specifications

–6–

STOPBAND

STOPBAND

CUT OFF (MHz)

STOPBAND

ATTENUATION (dB)

>

40 0.3 2.05

>

40 0.02 2.45

STOPBAND

ATTENUATION (dB)

>

50 4.2

>

51.3 5.0

>

27.6 2.1

>

29.3 2.7

>

40 5.65

>

54 4.2

>

50.3 5.0

ATTENUATION @

1.3MHz (dB)

F

3dB

F

3dB

REV. A

ADV7175/ADV7176

FREQUENCY – MHz

0

–120

–100

–80

–20

–40

–60

02468 1210

AMPLITUDE – dB

TYPE A

TYPE B

FREQUENCY – MHz

0

–120

–100

–80

–20

–40

–60

02468 1210

AMPLITUDE – dB

0

–20

–40

–60

AMPLITUDE – dB

–80

–100

–120

02468 1210

TYPE A

FREQUENCY – MHz

Figure 5. NTSC Low-Pass Filter

0

–20

–40

–60

TYPE B

Figure 7. PAL Low-Pass Filter

AMPLITUDE – dB

–80

–100

–120

02468 1210

Figure 6. NTSC Notch Filter

FREQUENCY – MHz

0

–20

–40

–60

AMPLITUDE – dB

–80

–100

–120

02468 1210

FREQUENCY – MHz

Figure 8. PAL Notch Filter

REV. A

Figure 9. NTSC/PAL Extended Mode Filter

–7–

ADV7175/ADV7176

FREQUENCY – MHz

02468 1210

AMPLITUDE – dB

–10

–40

–20

0

–80

–60

–100

–50

–30

–90

–70

0

–10

–20

–30

–40

–50

–60

AMPLITUDE – dB

–70

–80

–90

–100

02468 1210

FREQUENCY – MHz

Figure 10. NTSC UV Filter

COLOR BAR GENERATION

The ADV7175/ADV7176 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”

SQUARE PIXEL MODE

The ADV7175/ADV7176 can be used to operate in square
pixel mode. For NTSC operation an input clock of 24.54MHz
is required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal filters scale accordingly for
square pixel mode operation.

COLOR SIGNAL CONTROL

The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.

BURST SIGNAL CONTROL

The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.

NTSC PEDESTAL CONTROL

The pedestal information on both odd and even fields can be
controlled on a line by line basis using the NTSC Pedestal
Control Registers. This allows the pedestals to be controlled
during the vertical blanking interval (Lines 10 to 25).

SUBCARRIER RESET

Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used in subcarrier reset mode. The subcarrier will reset to field
0 at the start of the following field when a high to low transition
occurs on this input pin.

REAL TIME CONTROL

Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used to lock an external video source. The real time control
mode allows the ADV7175/ADV7176 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs out a digi­tal datastream in the RTC format (such as a Phillips SAA7110
video decoder), the part will automatically change to the com­pensated subcarrier frequency on a line by line basis. This
digital datastream is 67 bits wide and the subcarrier is con­tained in bits 0 to 21. Each bit is 2 clock cycles long.

Figure 11. PAL UV Filter

CLOCK

COMPOSITE

VIDEO

e.g. VCR

OR CABLE

VIDEO

DECODER

(e.g.SAA7110)

MPEG

DECODER

M
U
X

SCRESET/RTC

P7–P0

BLUE/COMPOSITE/U

HSYNC

FIELD/VSYNC

GREEN/LUMA/Y

RED/CHROMA/V

COMPOSITE

ADV7175/ADV7176

Figure 12. RTC Connections

PIXEL TIMING DESCRIPTION

The ADV7175/ADV7176 can operate in either 8-bit or 16-bit
YCrCb Mode.

8-Bit YCrCb Mode

This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on
a rising clock edge.

16-Bit YCrCb Mode

This mode accepts Y inputs through the P7-P0 pixel inputs and
multiplexed CrCb inputs through the P15-P8 pixel inputs. The
data is loaded on every second rising clock edge of CLOCK.
The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.

VIDEO TIMING DESCRIPTION

The ADV7175/ADV7176 is intended to interface to off the shelf
MPEG1 and MPEG2 Decoders. As a consequence the
ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing gen­erator. The ADV7175/ADV7176 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.

The ADV7175/ADV7176 calculates the width and placement
of analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.

(Continued on page 15)

–8–

REV. A

ADV7175/ADV7176

Mode 0 (CCIR-656): Slave Option.

(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before

and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. The
(if not used) pins should be tied high in this mode.

ANALOG

VIDEO

HSYNC, FIELD/VSYNC and BLANK

INPUT PIXELS

NTSC SYSTEM

PAL SYSTEM

EAV CODE

FF0000X

CrC

Y

b

4 PIXELS

4 PIXELS

END OF ACTIVE

VIDEO LINE

8

10801

0

Y

0

FF00FFABABA

B

ANCILLARY DATA

(HANC)

268 PIXELS

280 PIXELS

801

0

SAV CODE

8

10FF0

0

0

XYC

Y

0

b

0

4 PIXELS

4 PIXELS

START OF ACTIVE

VIDEO LINE

CrC

C

C

Y

r

b

1440 PIXELS

1440 PIXELS

C

Y

b

r

Figure 13. Timing Mode 0 (Slave Mode)

Mode 0 (CCIR-656): Master Option.

(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time

codes in the CCIR656 standard. The H bit is output on the
output on the FIELD/

VSYNC pin. Mode 0 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL). The H, V and F transitions

HSYNC pin, the V bit is output on the BLANK pin and the F bit is

relative to the video waveform are illustrated in Figure 16.

DISPLAY

522 523 524 525 1 2 3 4

H

VERTICAL BLANK

67

5

8

10 11 20 21 22

9

DISPLAY

REV. A

V

F

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

H

V

F

ODD FIELD

ODD FIELDEVEN FIELD

VERTICAL BLANK

EVEN FIELD

Figure 14. Timing Mode 0 (NTSC Master Mode)

–9–

283

284

DISPLAY

285

ADV7175/ADV7176

DISPLAY

622 623 624 625 1 2 3 4

H

V

F

DISPLAY

309 310 311 312 314 315 316 317

H

V

F

ODD FIELD EVEN FIELD

ODD FIELDEVEN FIELD

313

Figure 15. Timing Mode 0 (PAL Master Mode)

VERTICAL BLANK

5

VERTICAL BLANK

67

318

319 320 334

DISPLAY

22 23

21

DISPLAY

335 336

ANALOG

VIDEO

H

F

V

Figure 16. Timing Mode 0 Data Transitions (Master Mode)

–10–

REV. A

ADV7175/ADV7176

Mode 1: Slave Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when

HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NTSC)
and Figure 18 (PAL).

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

284

DISPLAY

285

DISPLAY

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

VERTICAL BLANK

678

5

VERTICAL BLANK

9

10 11

20 21 22

283

Figure 17. Timing Mode 1 (NTSC)

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

DISPLAY

622 623 624 625 1 2 3 4

ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 18. Timing Mode 1 (PAL)

5

317

67

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

REV. A

–11–

ADV7175/ADV7176

Mode 1: Master Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7175/ADV7176 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when
disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 17 (NTSC) and Figure 18 (PAL). Figure 19 illus­trates the

HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is

HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.

HSYNC

FIELD

PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2

BLANK

PIXEL

DATA

Cb Y

PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2

Cr Y

Figure 19. Timing Mode 1 Odd/Even Field Transitions

Mode 2: Slave Option. HSYNC, VSYNC, BLANK.
(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode the ADV7175/ADV7176 accepts horizontal and vertical SYNC signals. A coincident low transition of both
and

VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even

field. The

BLANK signal is optional. When the BLANK input is disabled, the ADV7175/ADV7176 automatically blanks all nor-

HSYNC

mally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL).

DISPLAY

HSYNC

BLANK

VSYNC

DISPLAY

522 523 524 525

1234

ODD FIELDEVEN FIELD

VERTICAL BLANK

678

5

9

10 11

20 21 22

HSYNC

BLANK

VSYNC

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

ODD FIELD EVEN FIELD

VERTICAL BLANK

Figure 20. Timing Mode 2 (NTSC)

–12–

283

DISPLAY

284

285

REV. A

ADV7175/ADV7176

HSYNC

BLANK

VSYNC

HSYNC

BLANK

VSYNC

DISPLAY

622 623 624 625 1 2 3 4

ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

5

317

67

318 319

21 22 23

320

DISPLAY

DISPLAY

334 335 336

Figure 21. Timing Mode 2 (PAL)

Mode 2: Master Option. HSYNC, VSYNC, BLANK.
(Timing Register 0 TR0 = X X X X X 1 0 1 )

In this mode the ADV7175/ADV7176 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The

BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all

normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL). Figure 22 illustrates the

HSYNC, BLANK and VSYNC for an even to odd field transition relative to the pixel data. Figure 23 illustrates the HSYNC,
BLANK and VSYNC for an odd to even field transition relative to the pixel data.

REV. A

HSYNC

VSYNC

BLANK

PIXEL
DATA

PAL = 12* CLOCK/2
NTSC = 16 * CLOCK/2

PAL = 132* CLOCK/2
NTSC = 118 * CLOCK/2

LINE 3 LINE 4

Figure 22. Timing Mode 2 Even-to-Odd Field Transition

–13–

Cb Y Cr

Y

ADV7175/ADV7176

HSYNC

VSYNC

BLANK

PIXEL
DATA

PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2

LINE 265

PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2

LINE 266

PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2

Cb Y Cr Y Cb

Figure 23. Timing Mode 2 Odd-to-Even Field Transition

Mode 3: Master/Slave Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode the ADV7175/ADV7176 accepts or generates Horizontal SYNC and odd/even FIELD signals. A transition of the
FIELD input when

HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 24 (NTSC) and Figure 25 (PAL).

DISPLAY

HSYNC

DISPLAY

522 523 524 525

1234

VERTICAL BLANK

678

5

9

10 11

20 21 22

BLANK

FIELD

HSYNC

BLANK

FIELD

ODD FIELDEVEN FIELD

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

ODD FIELD EVEN FIELD

VERTICAL BLANK

283

284

285

Figure 24. Timing Mode 3 (NTSC)

–14–

REV. A

ADV7175/ADV7176

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

DISPLAY

622 623 624 625 1 2 3 4

ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

EVEN FIELD

ODD FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 25. Timing Mode 3 (PAL)

5

317

67

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

(Continued from page 8)

In addition the ADV7175/ADV7176 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an in­put pixel clock of 24.54 MHz for NTSC and an input pixel
clock of 29.5 MHz for PAL. The internal horizontal line
counters place the various video waveform sections in the cor­rect location for the new clock frequencies.

The ADV7175/ADV7176 has 8 distinct master or slave timing
configurations. These are divided into 4 timing modes which
operate at one discrete clock frequency (27 MHz). Timing con­trol is established with the bidirectional
FIELD/

VSYNC pins. Timing Mode Register 1 can also be

SYNC, BLANK and

used to vary the timing pulse widths and the where they occur in
relation to each other.

OUTPUT VIDEO TIMING

The video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. These sequences are summarized below. In slave
modes the following sequences are synchronized with the input
timing control signals. In master modes the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.

NTSC–Interlaced: Scan lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for close captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.

NTSC–Noninterlaced: Scan lines 1–9 are always blanked
and vertical sync pulses are included. Scan lines 10–21 are also
blanked and can be used for close captioning data. Burst is dis­abled on lines 1–6, 261–262.

PAL–Interlaced: Scan lines 1–6, 311–318 and 624–625 are al­ways blanked and vertical sync pulses are included in Fields 1,
2, 5 and 6. Scan lines 1–5, 311–319 and 624–625 are always
blanked and vertical sync pulses are included in Fields 3, 4, 7
and 8. The remaining scan lines in the vertical interval are also
blanked and can be used for close captioning data. Burst is dis­abled on lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and

6. Burst is disabled on lines 1–5, 311–319 and 623–625 in
Fields 3, 4, 7 and 8.

PAL–Noninterlaced: Scan lines 1–6 and 311–312 are always
blanked and vertical sync pulses are included. The remaining
scan lines in the vertical interval are also blanked and can be
used for close captioning data. Burst is disabled on lines 1–5,
310–312.

POWER-ON RESET

After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high to low transition on the
RESET pin. This initializes the pixel port such that the pixel
inputs P7–P0 are selected. After reset, the ADV7175/ADV7176
is automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16 HEX is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. All bits in Mode Register 0
are set to Logic Level “0” except Bit MR02. Bit MR02 of
Mode Register 0 is set to Logic “1.” This enables the 7.5 IRE
pedestal.

REV. A

–15–

ADV7175/ADV7176

1-7 8

9

1-7

8

9 1-7 8 9

P

S

START ADDR R/W ACK

SUBADDRESS

ACK

DATA ACK

STOP

SDATA

SCLOCK

MPU PORT DESCRIPTION

The ADV7175 and ADV7176 support a two wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7175 and ADV7176 each have four possible slave ad­dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 26 and
Figure 27. The LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or
Logic Level “1.”

1 X10101A1

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Fig 26. ADV7175 Slave Address

0 X10101A1

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Fig 27. ADV7176 Slave Address

To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by es­tablishing a start condition, defined by a high to low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/

W bit). The bits transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/

W bit determines the direction of the data. A

Logic “0” on the LSB of the first byte means that the master

will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa­tion from the peripheral.

The ADV7175/ADV7176 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long supporting the
7-bit addresses plus the R/

W bit. The ADV7175 has 33 sub­addresses and the ADV7176 has 19 subaddresses to enable ac­cess to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allowing data to
be written to or from the starting subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one by one basis without
having to update all the registers. There is one exception. The
Subcarrier Frequency Registers should be updated in sequence,
starting with Subcarrier Frequency Register 0. The auto incre­ment function should be then used to increment and access
subcarrier frequency registers 1, 2 and 3. The subcarrier fre­quency registers should not be accessed independently.

Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of se­quence with normal read and write operations, then these cause
an immediate jump to the idle condition. During a given
SCLOCK high period the user should only issue one start con­dition, one stop condition or a single stop condition followed by
a single start condition. If an invalid subaddress is issued by the
user, the ADV7175/ADV7176 will not issue an acknowledge
and will return to the idle condition. If in auto-increment
mode, the user exceeds the highest subaddress then the follow­ing action will be taken:

1. In Read Mode the highest subaddress register contents will

continue to be output until the master device issues a no-ac­knowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDATA line is not pulled low on the
ninth pulse.

2. In Write Mode, the data for the invalid byte will be not be

loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175/ADV7176 and the part will re­turn to the idle condition.

Figure 28 illustrates an example of data transfer for a read se­quence and the start and stop conditions.

Figure 28. Bus Data Transfer

Figure 29 shows bus write and read sequences.

WRITE

SEQUENCE

READ

SEQUENCE

S

SLAVE ADDR

S SLAVE ADDR

S = START BIT
P = STOP BIT

A(S)

SUB ADDR

LSB = 0

SUB ADDR A(S)SSLAVE ADDR

A(S)

A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER

A(S)

DATA A(S)

LSB = 1

Figure 29. Write and Read Sequences

–16–

DATA A(S)

A(S)

DATA A(M)

A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER

P

A(M)DATA P

REV. A

ADV7175/ADV7176

SR4 SR3 SR2

SR7–SR5

(000)

ZERO SHOULD

BE WRITTEN TO

THESE BITS

SR4 SR3 SR2 SR1 SR0

0 0 0 0 0 MODE REGISTER 0
0 0 0 0 1 MODE REGISTER 1
0 0 0 1 0 SUB CARRIER FREQ REGISTER 0
0 0 0 1 1 SUB CARRIER FREQ REGISTER 1
0 0 1 0 0 SUB CARRIER FREQ REGISTER 2
0 0 1 0 1 SUB CARRIER FREQ REGISTER 3
0 0 1 1 0 SUB CARRIER PHASE REGISTER
0 0 1 1 1 TIMING MODE REGISTER 0
0 1 0 0 0 CLOSED CAPTIONING EXTENDED DATA – BYTE 0
0 1 0 0 1 CLOSED CAPTIONING EXTENDED DATA – BYTE 1
0 1 0 1 0 CLOSED CAPTIONING DATA – BYTE 0
0 1 0 1 1 CLOSED CAPTIONING DATA – BYTE 1
0 1 1 0 0 TIMING MODE REGISTER 1
0 1 1 0 1 MODE REGISTER 2
0 1 1 1 0 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
0 1 1 1 1 NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
1 0 0 0 0 NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
1 0 0 0 1 NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
1 0 0 1 0 MODE REGISTER 3
1 0 0 1 1 MACROVISION REGISTERS (ADV7175 ONLY)

• • • • • " " "

• • • • • " " "
1 1 1 1 1 MACROVISION REGISTERS (ADV7175 ONLY)

Figure 30. Subaddress Register

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the
ADV7175/ADV7176 except the subaddress register which is a
write only register. The subaddress register determines which
register the next read or write operation accesses. All communi­cations with the part through the bus start with an access to the
subaddress register. Then a read/write operation is performed
from/to the target address which then increments to the next
address until a stop command on the bus is performed.

REGISTER PROGRAMMING

The following section describes each register, including
subaddress register, mode registers, subcarrier frequency regis­ters, subcarrier phase register, timing registers, closed captioning
extended data registers, closed captioning data registers and
NTSC pedestal control registers in terms of its configuration.

SR1

SUBADDRESS REGISTER

SR0SR7 SR6 SR5

Subaddress Register (SR7–SR0)

The communications register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress set up. The subaddress
register determines to/from which register the operation takes
place.

Figure 30 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–
SR5.

Register Select (SR4–SR0):

These bits are setup to point to the required starting address.

MODE REGISTER 0 MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)

Mode Register 0 is a 8-bit wide register.
Figure 31 shows the various operations under the control of

Mode Register 0. This register can be read from as well written to.

REV. A

MR06

MR07

(0)

ZERO SHOULD

BE WRITTEN TO

THIS BIT

MR07

OUTPUT SELECT

0 YC OUTPUT
1 RGB/YUV OUTPUT

MR05

FILTER SELECT

MR03

MR04

0 0 LOW PASS FILTER (A)
0 1 NOTCH FILTER
1 0 EXTENDED MODE
1 1 LOW PASS FILTER (B)

RGB SYNC

0 DISABLE
1 ENABLE

Figure 31. Mode Register 0

–17–

MR02MR04 MR03MR05MR06

MR01

PEDESTAL CONTROL

MR02

0 PEDESTAL OFF
1 PEDESTAL ON

MR01 MR00

OUTPUT VIDEO

STANDARD SELECTION

MR00

0 0 NTSC
0 1 PAL (B, D, G, H, I)
1 0 PAL (M)
1 1 RESERVED

ADV7175/ADV7176

MODE REGISTER 0 (MR07–MR00) BIT DESCRIPTION
Encode Mode Control (MR01–MR00):

These bits are used to set up the encode mode. The ADV7175/
ADV7176 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL (M) and PAL (N) standard video.

Pedestal Control (MR02)

This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the
ADV7175/ADV7176 is configured in PAL mode.

Luminance Filter Control (MR04–MR03)

These bits are used for selecting between a filter for the lumi­nance signal. These filters automatically are set to the cutoff fre­quency for the low-pass filters and the subcarrier frequency for
the notch filter. The extended mode filter is a 5.5 MHz low-pass
filter. The filters are illustrated in Figures 3 to 11.

RGB Sync (MR05)

This bit is used to set up the RGB outputs with the sync infor­mation encoded.

Output Control (MR06)

This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that in RGB/YUV mode the main composite
signal is still available.

MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)

Mode Register 1 is a 8-bit wide register.
Figure 32 shows the various operations under the control of Mode

Register 1. This register can be read from as well written to.

MODE REGISTER 1 (MR17–MR10) BIT DESCRIPTION
Interlaced Mode Control (MR10):

This bit is used to setup the output to interlaced or non-inter­laced mode. This mode is only relevant when the part is in
composite video mode.

Closed Captioning Field Control (MR12–MR11)

These bits control the field that close captioning data is displayed
on close captioning information can be displayed on an odd field,
even field or both fields.

DAC Control (MR16–MR13)

These bits can be used to power down the DACs. This can be
used to reduce the power consumption of the ADV7175/ADV7176
if any of the DACs are not required in the application.

Color Bar Control (MR17)

This bit can be used to generate and output an internal color
bar. The color bar configuration is 75/75/75/7.5 for NTSC and
100/0/75/0 for PAL.

COLOR BAR

CONTROL

MR17

0 DISABLE
1 ENABLE

COMPOSITE DAC

CONTROL

MR16

0 NORMAL
1 POWER DOWN

MR15

GREEN/LUMA

DAC CONTROL

MR14

0 NORMAL
1 POWER DOWN

BLUE/COMPOSITE

DAC CONTROL

0 NORMAL
1 POWER DOWN

MR13

0 NORMAL
1 POWER DOWN

Figure 32. Mode Register 1

MR12

RED/CHROMA

DAC CONTROL

MR11 MR10MR17 MR12MR13MR15MR16 MR14

CLOSED CAPTIONING

FIELD SELECTION

MR11

0 0 NO DATA OUT
0 1 ODD FIELD ONLY
1 0 EVEN FIELD ONLY
1 1 DATA OUT

(BOTH FIELDS)

MR10

0 INTERLACED
1 NON-INTERLACED

INTERLACE

CONTROL

–18–

REV. A

ADV7175/ADV7176

SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0)
(Address (SR4–SR0) = 05H–02H)

These 8-bit wide registers are used to set up the subcarrier fre­quency. The value of these registers are calculated by using the
following equation:

232–1

Subcarrier Frequency Register =
i.e.: NTSC Mode, F

= 27 MHz, F

CLK

Subcarrier Frequency Register =

F

CLK

232–1

27×10

*F

SCF

= 3.5796 MHz

SCF

*3.579545 ×10

6

6

Subcarrier Frequency Register = 21F07C16 HEX

Figure 33 shows how the frequency is set up by the 4 registers.

SUBCARRIER
FREQUENCY
REG 0

SUBCARRIER
FREQUENCY
REG 1

SUBCARRIER
FREQUENCY
REG 2

SUBCARRIER
FREQUENCY
REG 3

FSC30 FSC29 FSC27 FSC25FSC28 FSC26 FSC24FSC31

FSC22 FSC21 FSC19 FSC17FSC20 FSC18 FSC16FSC23

FSC14 FSC13 FSC11 FSC9FSC12 FSC10 FSC8FSC15

FSC6 FSC5 FSC3 FSC1FSC4 FSC2 FSC0FSC7

Figure 33. Subcarrier Frequency Register

SUBCARRIER PHASE REGISTER (FP7–FP0):
(Address (SR4–SR0) = 06H)

This 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.

TIMING REGISTER 0 (TR07–TR00)
(Address (SR4-SR0) = 07H)

Timing Register 0 is a 8-bit wide register.
Figure 34 shows the various operations under the control of

Timing Register 0. This register can be read from as well
written to.

TIMING REGISTER 0 (TR07–TR00)
BIT DESCRIPTION
Master/Slave Control (TR00)

This bit controls whether the ADV7175/ADV7176 is in master
or slave mode.

Timing Mode Control (TR02–TR01)

These bits control the timing mode of the ADV7175/ADV7176
These modes are described in the Timing and Control section
of the data sheet.

BLANK Control (TR03)

This bit controls whether the BLANK input is used when the
part is in slave mode.

Luma Delay Control (TR05–TR04)

These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.

Pixel Port Select (TR06)

This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on
Pins P7–P0.

Timing Register Reset (TR07)

Toggling TR07 from low to high and low again resets the inter­nal timing counters. This bit should be toggled after setting up a
new timing mode.

TIMING

REGISTER RESET

TR07

PIXEL PORT

CONTROL

TR06

0 8-BIT
1 16-BIT

BLACK INPUT

CONTROL

TR03

0 ENABLE
1 DISABLE

LUMA DELAY

TR04

TR05

0 0 0ns DELAY
0 1 74ns DELAY
1 0 148ns DELAY
1 1 222ns DELAY

TR02

0 0 MODE 0
0 1 MODE 1
1 0 MODE 2
1 1 MODE 3

Figure 34. Timing Register 0

TR02TR03TR05TR06 TR04

TIMING MODE

SELECTION

TR01

TR01

TR00TR07

MASTER/SLAVE

CONTROL

TR00

0 SLAVE TIMING
1 MASTER TIMING

REV. A

–19–

ADV7175/ADV7176

CLOSED CAPTIONING EXTENDED DATA REGISTERS
1–0 (CED15–CED00)
(Address (SR4–SR0) = 09–08H)

These 8-bit wide registers are used to set up the closed
captioning extended data bytes. Figure 35 shows how the high
and low bytes are set up in the registers.

BYTE 1

BYTE 0

CED14 CED13 CED11 CED9CED12 CED10 CED8CED15

CED6 CED5 CED3 CED1CED4 CED2 CED0CED7

Figure 35. Closed Captioning Extended Data Register

CLOSED CAPTIONING DATA REGISTERS 1–0
(CCD15–CCD00)
(Subaddress (SR4–SR0) = 0B–0AH)

These 8-bit wide registers are used to set up the closed
captioning data bytes. Figure 36 shows how the high and low
bytes are set up in the registers.

BYTE 1

BYTE 0

CCD14 CCD13 CCD11 CCD9CCD12 CCD10 CCD8CCD15

CCD6 CCD5 CCD3 CCD1CCD4 CCD2 CCD0CCD7

Figure 36. Closed Captioning Data Register

TIMING REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 0CH)

Timing Register 1 is an 8-bit wide register.
Figure 37 shows the various operations under the control of

Timing Register 1. This register can be read from as well
written to. This register can be used to adjust the width and
position of the master mode timing signals.

TIMING REGISTER 1 (TR17–TR10) BIT DESCRIPTION
HSYNC Width (TR11–TR10)

These bits adjust the HSYNC pulse width.

HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)

These bits adjust the position of the
the FIELD/

VSYNC output.

HSYNC output relative to

HSYNC to FIELD Delay Control (TR15–TR14)

When the ADV7175/ADV7176 is in Timing Mode 1, these bits
adjust the position of the

HSYNC output relative to the FIELD

output rising edge.

VSYNC Width (TR15–TR14)

When the ADV7175/ADV7176 is in Timing Mode 2, these bits
adjust the

VSYNC pulse width.

HSYNC to Pixel Data Adjust (TR17–TR16)

This enables the

HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.

MODE REGISTER 2 MR2 (MR27–MR20)
(Address (SR4-SR0) = 0DH)

Mode Register 2 is an 8-bit wide register.
Figure 38 shows the various operations under the control of

Mode Register 2. This register can be read from as well written to.

MODE REGISTER 2 (MR27–MR20) BIT DESCRIPTION
Square Pixel Mode Control (MR20)

This bit is used to setup square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be sup­plied. For PAL, a 29.5 MHz clock must be supplied.

Genlock Control (MR22–MR21)

These bits control the genlock feature of the ADV7175/
ADV7176 Setting MR21 to a Logic “1” configures the
SCRESET/RTC pin as an input. Setting MR22 to logic level
“0” configures the SCRESET/RTC pin as a subcarrier reset in­put. Therefore, the subcarrier will reset to Field 0 following a
low to high transition on the SCRESET/RTC pin. Setting
MR22 to Logic Level “1” configures the SCRESET/RTC pin as
a real time control input.

HSYNC TO PIXEL

DATA ADJUSTMENT

TR16

TR17

0 0 0 x T
0 1 1 x T
1 0 2 x T
1 1 3 x T

TIMING MODE 1 (MASTER/PAL)

HSYNC

FIELD/VSYNC

PCLK
PCLK
PCLK
PCLK

TR15

x0T
x1Tb + 32µs

TR15

0 0 1 x T
0 1 4 x T
1 0 16 x T
1 1 64 x T

T

a

T

b

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

TR14

VSYNC WIDTH

(MODE 2 ONLY)

TR14

T

b

c

PCLK
PCLK

PCLK
PCLK

HSYNC TO

FIELD/VSYNC DELAY

TR13

TR12

0 0 1 x T
0 1 3 x T
1 0 16 x T
1 1 64 x T

Figure 37. Timing Register 1

–20–

PCLK
PCLK

PCLK
PCLK

LINE 313 LINE 314LINE 1

c

TR11

TR10TR17

HSYNC WIDTH

TR11 TR10

0 0 1 x T
0 1 4 x T
1 0 16 x T
1 1 128 x T

T

a

PCLK
PCLK

PCLK

PCLK

TR12TR13TR15TR16 TR14

T

REV. A

ADV7175/ADV7176

FIELD 1/3

PCO6 PCO5 PCO3 PCO1PCO4 PCO2 PCO0PCO7

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCO14 PCO13 PCO11 PCO9PCO12 PCO10 PCO8PCO15

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

FIELD 1/3

FIELD 2/4

PCE6 PCE5 PCE3 PCE1PCE4 PCE2 PCE0PCE7

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCE14 PCE13 PCE11 PCE9PCE12 PCE10 PCE8PCE1 5

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

FIELD 2/4

MR21MR27 MR22MR23MR26 MR25 MR24 MR20

CHROMINANCE

MR24

0 ENABLE COLOR
1 DISABLE COLOR

BURST

CONTROL

CONTROL

MR23

CCIR624/CCIR601

0 CCIR624 OUTPUT
1 CCIR601 OUTPUT

MR26

LOWER POWER

MODE

MR27

0 DISABLE
1 ENABLE

RGB/YUV

CONTROL

0 RGB OUTPUT
1 YUV OUTPUT

MR25

0 ENABLE BURST
1 DISABLE BURST

Figure 38. Mode Register 2

CCIR624/CCIR601 Control (MR23)

This bit switches the video output between CCIR624 and
CCIR601 video standard.

Chrominance Control (MR24)

This bit enables the color information to be switched on and off
the video output.

Burst Control (MR25)

This bit enables the burst information to be switched on and off
the video output.

RGB/YUV Control (MR26)

This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.

Lower Power Control (MR27)

This bit enables the lower power mode of the ADV7175/
ADV7176.

NTSC PEDESTAL CONTROL REGISTERS 3–0
(PCE15–0, PCO15–0)

(Subaddress (SR4–SR0) = 11-0EH)

These 8-bit wide registers are used to set up the NTSC pedestal
on a line by line basis in the vertical blanking interval for both
odd and even fields. Figure 39 shows the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal off on the equivalent line.

GENLOCK SELECTION

MR21

MR22

x 0 DISABLE GENLOCK
0 1 ENABLE SUBCARRIER

1 1 ENABLE RTC PIN

CONTROL

RESET PIN

SQUARE PIXEL

CONTROL

MR20

0 DISABLE
1 ENABLE

Figure 39. Pedestal Control Registers

MODE REGISTER 3 MR3 (MR37–30)
(Address (SR4–SR0) = 12H)

Mode Register 3 is an 8-bit wide register.
Figure 34 shows the various operations under the control of

Mode Register 3. Bits MR36–MR30 are reserved and Logic “0”
should be written to them.

MODE REGISTER 3 (MR37–MR30) DESCRIPTION
DAC Switching Control (MR37)

This bit is used to switch the luminance signal onto the compos­ite DAC. Figure 40 illustrates the DAC outputs and how they
switch when MR 37 is set to Logic “1”.

0

COMPOSITE

1

GREEN/LUMA/Y

DAC A

REV. A

MR37

MR36-MR30

(RESERVED)

ZERO SHOULD BE

WRITTEN TO THESE BITS

DAC OUTPUT

SWITCHING

DAC B

BLUE/COMP/U
BLUE/COMP/U

DAC C

RED/CHROMA/V
RED/CHROMA/V

GREEN/LUMA/Y
COMPOSITE

Figure 40. Mode Register 3

–21–

MR31MR37 MR32MR33MR36 MR35 MR34 MR30

DAC D

ADV7175/ADV7176

APPENDIX 1

BOARD DESIGN AND LAYOUT CONSIDERATIONS

The ADV7175/ADV7176 is a highly integrated circuit contain­ing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be ap­plied to the system level design such that high speed, accurate
performance is achieved. The “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.

The layout should be optimized for lowest noise on the
ADV7175/ADV7176 power and ground lines by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V
as to minimize inductive ringing.

Ground Planes

The ground plane should encompass all ADV7175/ADV7176
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7175/ADV7176, the analog output traces,
and all the digital signal traces leading up to the ADV7175/
ADV7176. The ground plane is the board’s common ground
plane.

Power Planes

The ADV7175/ADV7176 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (V
the regular PCB power plane (V
ferrite bead. This bead should be located within three inches of
the ADV7175/ADV7176.

The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7175/ADV7176 power pins and voltage refer­ence circuitry.

Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.

Supply Decoupling

For optimum performance, bypass capacitors should be in­stalled using the shortest leads possible, consistent with reliable

and GND pins should by minimized so

AA

). This power plane should be connected to

AA

) at a single point through a

CC

operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each group
of V

pins on the ADV7175/ADV7176 must have at least one

AA

0.1 µF decoupling capacitor to GND. These capacitors should
be placed as close as possible to the device.

It is important to note that while the ADV7175/ADV7176
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc­ing power supply noise and consider using a three terminal volt­age regulator for supplying power to the analog power plane.

Digital Signal Interconnect

The digital inputs to the ADV7175/ADV7176 should be iso­lated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay
the analog power plane.

Due to the high clock rates involved, long clock lines to the
ADV7175/ADV7176 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V

), and not the

CC

analog power plane.

Analog Signal Interconnect

The ADV7175/ADV7176 should be located as close as possible
to the output connectors to minimize noise pickup and reflec­tions due to impedance mismatch.

The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.

Digital inputs, especially pixel data inputs and clocking signals
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.

For best performance, the outputs should each have a 75 Ω
load resistor connected to GND. These resistors should be
placed as close as possible to the ADV7175/ADV7176 so as to
minimize reflections.

The ADV7175/ADV7176 should have no inputs left floating.
Any inputs that are not required should be tied to ground.

–22–

REV. A

+5V (V

AA

0.1µF

)

+5V (VAA)

2–9, 12–14

0.1µF

38–42,

25

33

COMP

V

REF

P15–P0

POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP

0.1µF 0.01µF

1, 11, 20, 28, 30, 37

V

AA

GREEN/

LUMA/

27

ADV7175

Y

ADV7176

RED/

CHROMA/

26

V

75Ω

75Ω

+5V (VAA)

10µF

ADV7175/ADV7176

L1

(FERRITE BEAD)

33µF

S VIDEO

+5V (VCC)

GND

“UNUSED
INPUTS
SHOULD BE
GROUNDED”

(SAME CLOCK AS USED BY

27MHz CLOCK

MPEG2 DECODER)

+5V (VAA)

10kΩ

35

SCRESET/RTC

15

HSYNC

16

FIELD/VSYNC

BLANK

17

22

RESET

44

CLOCK

ALSB

18

BLUE/

COMPOSITE/

COMPOSITE

SCLOCK

SDATA

R

SET

GND

10, 19, 21
29, 36, 43

31

U

32

23

24

34

75Ω

75Ω

150Ω

+5V (VCC)

5kΩ

+5V (VCC)

5kΩ

MPU BUS

Figure 41. Recommended Analog Circuit Layout

The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if

13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the
ADV7175/ADV7176 in the correct sequence.

D

CLOCK

HSYNC

CK

Q

D

Q

CK

13.5MHz

REV. A

Figure 42. Circuit to Generate 13.5 MHz

–23–

ADV7175/ADV7176

APPENDIX 2

CLOSED CAPTIONING

The ADV7175/ADV7176 supports closed captioning conforming to the standard television synchronizing waveform for color trans­mission. Closed captioning is transmitted during the blanked active line time of line 21 of the odd fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run in
signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. Sixteen bits of data follow the start
bit. These consist of two 8-bit bytes. The data for these bytes is stored in closed captioning data registers 0 and 1.

The ADV7175/ADV7176 also supports the extended closed captioning operation which is active during even fields and is encoded
on scan line 284. The data for this operation is stored in closed captioning extended data registers 0 and 1.

All clock run-in signals and timing to support closed captioning on lines 21 and 282 are generated automatically by the ADV7175/
ADV7176. All pixels inputs are ignored during lines 21 and 282.

FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA208 describe the closed captioning information for lines
21 and 284.

13.407µs

P
A

D6–D0

R

I
T
Y

P
A
R

I
T
Y

50 IRE

S
T

D6–D0

A
R
T

40 IRE

REFERENCE COLOR BURST

(9 CYCLES)
FREQUENCY = F
AMPLITUDE = 40 IRE

= 3.579545MHz

SC

10.003µs 17.379µs 33.764µs

Figure 43. Closed Captioning Waveform (NTSC)

–24–

REV. A

APPENDIX 3

NTSC WAVEFORMS (With Pedestal)

ADV7175/ADV7176

130.8 IRE

100 IRE

7.5 IRE
0 IRE

–40 IRE

100 IRE

7.5 IRE
0 IRE

–40 IRE

1067.7mV

650mV

286mV (pk-pk)

714.2mV

Figure 44. NTSC Composite Video Levels

714.2mV

Figure 45. NTSC Luma Video Levels

835mV (pk-pk)

PEAK COMPOSITE

REF WHITE

BLACK LEVEL
BLANK LEVEL

SYNC LEVEL

REF WHITE

BLACK LEVEL
BLANK LEVEL

SYNC LEVEL

PEAK CHROMA

BLANK/BLACK LEVEL

1268.1mV

1048.4mV

387.6mV

334.2mV

48.3mV

1048.4mV

387.6mV

334.2mV

48.3mV

232.2mV

0mV

100 IRE

7.5 IRE
0 IRE

–40 IRE

Figure 46. NTSC Chroma Video Levels

720.8mV

Figure 47. NTSC RGB Video Levels

PEAK CHROMA

REF WHITE

BLACK LEVEL
BLANK LEVEL

SYNC LEVEL

1052.2mV

387.5mV

331.4mV

45.9mV

REV. A

–25–

ADV7175/ADV7176

NTSC WAVEFORMS (Without Pedestal)

130.8 IRE

100 IRE

0 IRE

–40 IRE

100 IRE

0 IRE

–40 IRE

1101.6mV

650mV

307mV (pk-pk)

714.2mV

Figure 48. NTSC Composite Video Levels

714.2mV

Figure 49. NTSC Luma Video Levels

903.2mV (pk-pk)

PEAK COMPOSITE

REF WHITE

BLANK/BLACK LEVEL

SYNC LEVEL

REF WHITE

BLANK /BLACK LEVEL

SYNC LEVEL

PEAK CHROMA

BLANK/BLACK LEVEL

1289.8mV

1052.2mV

338mV

52.1mV

1052.2mV

338mV

52.1mV

198.4mV

0mV

100 IRE

0 IRE

–40 IRE

Figure 50. NTSC Chroma Video Levels

715.7mV

Figure 51. NTSC RGB Video Levels

PEAK CHROMA

REF WHITE

BLANK/BLACK LEVEL

SYNC LEVEL

1052.2mV

336.5mV

51mV

–26–

REV. A

PAL WAVEFORMS

ADV7175/ADV7176

1092.5mV

650mV

1284.2mV

1047.1mV

350.7mV

50.8mV

1047mV

350.7mV

50.8mV

300mV (pk-pk)

PEAK COMPOSITE

REF WHITE

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 52. PAL Composite Video Levels

REF WHITE

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 53. PAL Luma Video Levels

PEAK CHROMA

885mV (pk-pk)

BLANK/BLACK LEVEL

207.5mV

0mV

1050.2mV

351.8mV

51mV

PEAK CHROMA

Figure 54. PAL Chroma Video Levels

REF WHITE

698.4mV

BLANK /BLACK LEVEL

SYNC LEVEL

Figure 55. PAL RGB Video Levels

REV. A

–27–

ADV7175/ADV7176

APPENDIX 4

REGISTER VALUES

The ADV7175/ADV7176 registers can be set depending on the
user standard required.

The following examples give the various register formats for
several video standards.

In each case the output is set to composite o/p with all DACs
powered up and with the
ditionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown the timing mode is set to Mode 0 in slave
format. TR02–TR00 of the timing register 0 control the timing
modes. For a detailed explanation of each bit in the command
registers, please turn to the register programming section of the
data sheet. TR07 should be toggled after setting up a new tim­ing mode. Timing Register 1 provides additional control over
the position and duration of the timing signals. In the examples
this register is programmed in default mode.

NTSC

Mode Register 0 04 Hex
Mode Register 1 00 Hex
Subcarrier Frequency Register 0 16 Hex
Subcarrier Frequency Register 1 7C Hex
Subcarrier Frequency Register 2 F0 Hex
Subcarrier Frequency Register 3 21 Hex
Subcarrier Phase Register 00 Hex
Timing Register 0 08 Hex
Closed Captioning Ext Register 0 00 Hex
Closed Captioning Ext Register 1 00 Hex
Closed Captioning Register 0 00 Hex
Closed Captioning Register 1 00 Hex
Timing Register 1 00 Hex
Mode Register 2 00 Hex
Pedestal Control Register 0 00 Hex
Pedestal Control Register 1 00 Hex
Pedestal Control Register 2 00 Hex
Pedestal Control Register 3 00 Hex
Mode Register 3 00 Hex

PAL (B, D, G, H, I)

Mode Register 0 01 Hex
Mode Register 1 00 Hex
Subcarrier Frequency Register 0 CB Hex
Subcarrier Frequency Register 1 8A Hex
Subcarrier Frequency Register 2 09 Hex
Subcarrier Frequency Register 3 2A Hex
Subcarrier Phase Register 00 Hex
Timing Register 0 08 Hex
Closed Captioning Ext Register 0 00 Hex
Closed Captioning Ext Register 1 00 Hex
Closed Captioning Register 0 00 Hex
Closed Captioning Register 1 00 Hex
Timing Register 1 00 Hex
Mode Register 2 00 Hex
Pedestal Control Register 0 00 Hex
Pedestal Control Register 1 00 Hex
Pedestal Control Register 2 00 Hex
Pedestal Control Register 3 00 Hex
Mode Register 3 00 Hex

BLANK input control disabled. Ad-

PAL (M)

Mode Register 0 06 Hex
Mode Register 1 00 Hex
Subcarrier Frequency Register 0 A3 Hex
Subcarrier Frequency Register 1 EF Hex
Subcarrier Frequency Register 2 E6 Hex
Subcarrier Frequency Register 3 21 Hex
Subcarrier Phase Register 00 Hex
Timing Register 0 08 Hex
Closed Captioning Ext Register 0 00 Hex
Closed Captioning Ext Register 1 00 Hex
Closed Captioning Register 0 00 Hex
Closed Captioning Register 1 00 Hex
Timing Register 1 00 Hex
Mode Register 2 00 Hex
Pedestal Control Register 0 00 Hex
Pedestal Control Register 1 00 Hex
Pedestal Control Register 2 00 Hex
Pedestal Control Register 3 00 Hex
Mode Register 3 00 Hex

PAL (N)

Mode Register 0 05 Hex
Mode Register 1 00 Hex
Subcarrier Frequency Register 0 CB Hex
Subcarrier Frequency Register 1 8A Hex
Subcarrier Frequency Register 2 09 Hex
Subcarrier Frequency Register 3 2A Hex
Subcarrier Phase Register 00 Hex
Timing Register 0 08 Hex
Closed Captioning Ext Register 0 00 Hex
Closed Captioning Ext Register 1 00 Hex
Closed Captioning Register 0 00 Hex
Closed Captioning Register 1 00 Hex
Timing Register 1 00 Hex
Mode Register 2 00 Hex
Pedestal Control Register 0 00 Hex
Pedestal Control Register 1 00 Hex
Pedestal Control Register 2 00 Hex
Pedestal Control Register 3 00 Hex
Mode Register 3 00 Hex

–28–

REV. A

ADV7175/ADV7176

APPENDIX 5

OUTPUT FILTER

If an output filter is required for the composite output of the ADV7175/ADV7176. The following filter can be used.
Plots of the filter characteristics can be produced on request.

C
470pF

L

2.7µH

L

1µH

IN OUT

C
330pF

L

0.7µH

C
56pF

Figure 56. Output Filter

REV. A

–29–

ADV7175/ADV7176

APPENDIX 6

OUTPUT WAVEFORMS

Figure 57. 100/75% Color Bars NTSC

Figure 58. 100/75% Color Bars NTSC (Chrominance Only)

–30–

REV. A

ADV7175/ADV7176

Figure 59. 100/75% Color Bars NTSC (Luminance Only)

REV. A

Figure 60. 100/75% Color Bars PAL

–31–

ADV7175/ADV7176

Figure 61. Differential Phase and Gain Measurements (PAL)

Figure 62. Vectorscope Measurements (PAL)

–32–

REV. A

ADV7175/ADV7176

Figure 63. Modulated Ramp Measurements (PAL)

REV. A

–33–

ADV7175/ADV7176

INDEX

Contents Page No.

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1

ADV7175/ADV7176 SPECIFICATIONS . . . . . . . . . . . . . . 2

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 3

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .4

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PIN DESCRIPTION/PIN CONFIGURATION . . . . . . . . . 5

DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 6

INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 6

COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 8

SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 8

COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8

BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8

NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 8

SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 8

VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 8

Timing Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Timing Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . 15

POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 16

Contents Page No.

REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 17

REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 17

Subaddress Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . 19

Subcarrier Phase Register . . . . . . . . . . . . . . . . . . . . . . . . 19

Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Closed Captioning Extended Data Registers 1-0 . . . . . . 20

Closed Captioning Data Registers 1-0 . . . . . . . . . . . . . . 20

Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Mode Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

NTSC Pedestal Control Registers 3-0 . . . . . . . . . . . . . . 21

APPENDIX 1. BOARD DESIGN AND LAYOUT

CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 22

APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . 24

APPENDIX 3. VIDEO WAVEFORMS . . . . . . . . . . . . . . 25

APPENDIX 4. REGISTER VALUES . . . . . . . . . . . . . . . 28

APPENDIX 5. OUTPUT FILTER . . . . . . . . . . . . . . . . . 29

APPENDIX 6. OUTPUT WAVEFORMS . . . . . . . . . . . . 30

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 35

–34–

REV. A

0.037 (0.94)

0.025 (0.64)

SEATING

PLANE

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic Quad Flatpack

(S-44)

0.548 (13.925)

0.096 (2.44)
MAX

8°

0.8°

0.546 (13.875)

0.398 (10.11)

0.390 (9.91)

33

34

TOP VIEW

(PINS DOWN)

ADV7175/ADV7176

23

22

0.040 (1.02)

0.032 (0.81)

0.083 (2.11)

0.077 (1.96)

0.040 (1.02)

0.032 (0.81)

4
4

1

0.033 (0.84)

0.029 (0.74)

12

11

0.016 (0.41)

0.012 (0.30)

REV. A

–35–

C213a–4– /96

–36–

PRINTED IN U.S.A.