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ADV7123
Datasheet (Analog Devices)
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Datasheet (Analog Devices)
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Datasheet ADV7123 Datasheet (Analog Devices)

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Page 1
CMOS, 330 MHz
R9–R0
GND
R
SET
IOR
IOR
COMP
ADV7123
V
REF
VOLTAGE
REFERENCE
CIRCUIT
G9–G0
B9–B0
IOG
IOG
IOB
IOB
PSAVE
POWER-DOWN
MODE
BLANK
SYNC
CLOCK
V
AA
DAC10
DATA
REGISTER
10
DAC10
DATA
REGISTER
10
DAC10
DATA
REGISTER
10
BLANK AND
SYNC LOGIC
a
FEATURES 330 MSPS Throughput Rate Triple 10-Bit D/A Converters SFDR
–70 dB at f –53 dB at f
= 50 MHz; f
CLK
= 140 MHz; f
CLK
RS-343A/RS-170 Compatible Output Complementary Outputs DAC Output Current Range 2 mA to 26 mA TTL Compatible Inputs Internal Reference (1.23 V) Single-Supply 5 V/3.3 V Operation 48-Lead LQFP Package Low Power Dissipation (30 mW Min @ 3 V) Low Power Standby Mode (6 mW Typ @ 3 V) Industrial Temperature Range (–40ⴗC to +85ⴗC)
APPLICATIONS Digital Video Systems (1600 ⴛ 1200 @ 100 Hz) High Resolution Color Graphics Digital Radio Modulation Image Processing Instrumentation Video Signal Reconstruction
= 1 MHz
OUT
= 40 MHz
OUT
Triple 10-Bit High Speed Video DAC
ADV7123

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADV7123 (ADV®) is a triple high speed, digital-to-analog converter on a single monolithic chip. It consists of three high speed, 10-bit, video D/A converters with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source.
The ADV7123 has three separate 10-bit-wide input ports. A single 5 V/3.3 V power supply and clock are all that are required to make the part functional. The ADV7123 has additional video control signals, composite SYNC and BLANK.
The ADV7123 also has a Power-Save Mode.
The ADV7123 is fabricated in a 5 V CMOS process. Its mono­lithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7123 is available in a 48-lead LQFP package.
ADV is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. 330 MSPS throughput
2. Guaranteed monotonic to 10 bits
3. Compatible with a wide variety of high resolution color graphics systems, including RS-343A and RS-170
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
Page 2
ADV7123–SPECIFICATIONS
to T
MAX
DD
1
, unless other-
1

5 V SPECIFICATIONS

(VAA = 5 V ⴞ 5%, V wise noted, TJ
REF
= 110ⴗC.)
MAX
= 1.235 V, R
= 560 ⍀, CL = 10 pF. All specifications T
SET
MIN
Parameter Min Typ Max Unit Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits Integral Nonlinearity (BSL) –1 ± 0.4 +1 LSB Differential Nonlinearity –1 ± 0.25 +1 LSB Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, V Input Low Voltage, V Input Current, I
IL
IN
IH
2V
0.8 V
–1 +1 µAV
= 0.0 V or V
IN
PSAVE Pull-Up Current 20 µA Input Capacitance, C
IN
10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, Sync = High
2.0 18.5 mA RGB DAC, Sync = Low DAC to DAC Matching 1.0 5 % Output Compliance Range, V Output Impedance, R
OUT
Output Capacitance, C Offset Error –0.025 +0.025 % FSR Tested with DAC Output = 0 V Gain Error
2
OC
OUT
0 1.4 V
100 kΩ 10 pF I
OUT
= 0 mA
–5.0 +5.0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE (Ext. and Int.)
Reference Range, V
POWER DISSIPATION
Digital Supply Current
REF
3
Analog Supply Current 67 72 mA R
Standby Supply Current
4
1.12 1.235 1.35 V
3.4 9 mA f
10.5 15 mA f 18 25 mA f
8mAR
2.1 5.0 mA PSAVE = Low, Digital, and Control
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
Inputs at V
DD
Power Supply Rejection Ratio 0.1 0.5 %/%
NOTES
1
Temperature range T
2
Gain error = {(Measured (FSC)/Ideal (FSC) –1) × 100}, where Ideal = V
3
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4
These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
Specifications subject to change without notice.
MIN
to T
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MAX
/R
× K × (3FFH) and K = 7.9896.
REF
SET
–2–
REV. B
Page 3
ADV7123
to T
2
DD
MAX
2
, unless

3.3 V SPECIFICATIONS

(VAA = 3.0 V–3.6 V, V
1
otherwise noted, TJ
= 1.235 V, R
REF
= 110ⴗC.)
MAX
= 560 ⍀, CL = 10 pF. All specifications T
SET
MIN
Parameter Min Typ Max Unit Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits R Integral Nonlinearity (BSL) –1 +0.5 +1 LSB R Differential Nonlinearity –1 +0.25 +1 LSB R
= 680 Ω
SET
= 680 Ω
SET
= 680 Ω
SET
DIGITAL AND CONTROL INPUTS
Input High Voltage, V Input Low Voltage, V Input Current, I
IL
IN
IH
2.0 V
0.8 V
–1 +1 µAV
= 0.0 V or V
IN
PSAVE Pull-Up Current 20 µA Input Capacitance, C
IN
10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, Sync = High
2.0 18.5 mA RGB DAC, Sync = Low DAC to DAC Matching 1.0 % Output Compliance Range, V Output Impedance, R
OUT
Output Capacitance, C Offset Error 0 0 % FSR Tested with DAC Output = 0 V Gain Error
3
OC
OUT
0 1.4 V
70 kΩ 10 pF
0% FSR FSR = 17.62 mA
VOLTAGE REFERENCE (Ext.)
Reference Range, V
REF
1.12 1.235 1.35 V
VOLTAGE REFERENCE (Int.)
Reference Range, V
POWER DISSIPATION
Digital Supply Current
REF
4
Analog Supply Current 67 72 mA R
1.235 V
2.2 5.0 mA f
6.5 12.0 mA f 11 15 mA f 16 mA f
8mAR
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 330 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
Standby Supply Current 2.1 5.0 mA PSAVE = Low, Digital, and Control
Inputs at V
DD
Power Supply Rejection Ratio 0.1 0.5 %/%
NOTES
1
These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
2
Temperature range T
3
Gain error = {(Measured (FSC)/Ideal (FSC) –1) × 100}, where Ideal = V
4
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
Specifications subject to change without notice.
MIN
to T
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MAX
/R
× K × (3FFH) and K = 7.9896.
REF
SET
–3–REV. B
Page 4
ADV7123

5 V DYNAMIC SPECIFICATIONS

(VAA = 5 V ⴞ 5%1, V
1
TA = 25ⴗC, unless otherwise noted, TJ
= 1.235 V, R
REF
= 560 ⍀, CL = 10 pF. All specifications are
SET
= 110ⴗC.)
MAX
Parameter Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
2
Single-Ended Output
f
= 50 MHz; f
CLK
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
= 100 MHz; f
f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
= 100 MHz; f
f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
= 140 MHz; f
f
CLK
f
= 140 MHz; f
CLK
= 1.00 MHz 67 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 60 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 40.4 MHz 48 dBc
OUT
= 2.51 MHz 57 dBc
OUT
= 5.04 MHz 58 dBc
OUT
= 20.2 MHz 52 dBc
OUT
= 40.4 MHz 41 dBc
OUT
Double-Ended Output
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
= 50 MHz; f
f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
= 100 MHz; f
f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
= 140 MHz; f
f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.00 MHz 70 dBc
OUT
= 2.51 MHz 70 dBc
OUT
= 5.04 MHz 65 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 58 dBc
OUT
= 40.4 MHz 52 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 61 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 40.4 MHz 53 dBc
OUT
Spurious-Free Dynamic Range within a Window
Single-Ended Output
= 50 MHz; f
f
CLK
= 50 MHz; f
f
CLK
f
= 140 MHz; f
CLK
= 1.00 MHz; 1 MHz Span 77 dBc
OUT
= 5.04 MHz; 2 MHz Span 73 dBc
OUT
= 5.04 MHz; 4 MHz Span 64 dBc
OUT
Double-Ended Output
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.00 MHz; 1 MHz Span 74 dBc
OUT
= 5.00 MHz; 2 MHz Span 73 dBc
OUT
= 5.00 MHz; 4 MHz Span 60 dBc
OUT
Total Harmonic Distortion
= 50 MHz; f
f
CLK
T
= 25°C66dBc
A
to T
T
MIN
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
MAX
= 1.00 MHz
OUT
65 dBc
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 63 dBc
OUT
= 2.00 MHz 55 dBc
OUT
DAC PERFORMANCE
Glitch Impulse 10 pVs DAC Crosstalk Data Feedthrough Clock Feedthrough
NOTES
1
These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
3
DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of –3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
Specifications subject to change without notice.
3
4, 5
4, 5
23 dB 22 dB 33 dB
.
REF
–4–
REV. B
Page 5
ADV7123
(VAA = 3.0 V–3.6 V1, V

3.3 V DYNAMIC SPECIFICATIONS

TA = 25ⴗC, unless otherwise noted, TJ
Parameter Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
2
Single-Ended Output
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
= 50 MHz; f
f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
= 100 MHz; f
f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
= 140 MHz; f
f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.00 MHz 67 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 60 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 40.4 MHz 48 dBc
OUT
= 2.51 MHz 57 dBc
OUT
= 5.04 MHz 58 dBc
OUT
= 20.2 MHz 52 dBc
OUT
= 40.4 MHz 41 dBc
OUT
Double-Ended Output
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
= 100 MHz; f
f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
= 140 MHz; f
f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
= 140 MHz; f
f
CLK
= 1.00 MHz 70 dBc
OUT
= 2.51 MHz 70 dBc
OUT
= 5.04 MHz 65 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 58 dBc
OUT
= 40.4 MHz 52 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 61 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 40.4 MHz 53 dBc
OUT
Spurious-Free Dynamic Range within a Window
Single-Ended Output
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.00 MHz; 1 MHz Span 77 dBc
OUT
= 5.04 MHz; 2 MHz Span 73 dBc
OUT
= 5.04 MHz; 4 MHz Span 64 dBc
OUT
Double-Ended Output
= 50 MHz; f
f
CLK
f
= 50 MHz; f
CLK
= 140 MHz; f
f
CLK
= 1.00 MHz; 1 MHz Span 74 dBc
OUT
= 5.00 MHz; 2 MHz Span 73 dBc
OUT
= 5.00 MHz; 4 MHz Span 60 dBc
OUT
Total Harmonic Distortion
f
= 50 MHz; f
CLK
= 25°C66dBc
T
A
T
to T
MIN
f
= 50 MHz; f
CLK
= 100 MHz; f
f
CLK
f
= 140 MHz; f
CLK
MAX
= 1.00 MHz
OUT
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 55 dBc
OUT
DAC PERFORMANCE
Glitch Impulse 10 pVs DAC Crosstalk Data Feedthrough Clock Feedthrough
NOTES
1
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
3
DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of –3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
Specifications subject to change without notice.
3
4, 5
4, 5
= 1.235 V, R
REF
= 680 ⍀, CL = 10 pF. All specifications are
SET
= 110ⴗC.)
MAX
65 dBc
23 dB 22 dB 33 dB
.
REF
–5–REV. B
Page 6
ADV7123
(VAA = 5 V ⴞ 5%2, V

5 V TIMING SPECIFICATIONS

1
unless otherwise noted, TJ
Parameter Min Typ Max Unit Condition
ANALOG OUTPUTS
Analog Output Delay, t Analog Output Rise/Fall Time, t Analog Output Transition Time, t Analog Output Skew, t
CLOCK CONTROL
7
f
CLK
7
f
CLK
7
f
CLK
Data and Control Setup, t Data and Control Hold, t Clock Pulsewidth High, t Clock Pulsewidth Low t Clock Pulsewidth High t Clock Pulsewidth Low t Clock Pulsewidth High t Clock Pulsewidth Low t Pipeline Delay, t PSAVE Up Time, t
NOTES
1
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
max specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
CLK
Specifications subject to change without notice.
PD
MIN
6
6
9
4
7
5
8
0.5 50 MHz 50 MHz Grade
0.5 140 MHz 140 MHz Grade
0.5 240 MHz 240 MHz Grade
1
2
4
5
4
5
4
5
6
6
10
to T
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
MAX
0.5 ns
1.5 ns
1.875 ns f
1.875 ns f
2.85 ns f
2.85 ns f
8.0 ns f
8.0 ns f
1.0 1.0 1.0 Clock Cycles
= 1.235 V, R
REF
MAX
= 560 ⍀, CL = 10 pF. All specifications T
SET
= 110ⴗC.)
5.5 ns
1.0 ns 15 ns 12 ns
210 ns
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 240 MHz = 240 MHz = 140 MHz = 140 MHz = 50 MHz = 50 MHz
MIN
to T
MAX
3
,
–6–
REV. B
Page 7
ADV7123

3.3 V TIMING SPECIFICATIONS

(VAA = 3.0 V–3.6 V2, V
1
3
T
, unless otherwise noted, TJ
MAX
= 1.235 V, R
REF
= 560 ⍀, CL = 10 pF. All specifications T
SET
= 110ⴗC.)
MAX
Parameter Min Typ Max Unit Condition
ANALOG OUTPUTS
Analog Output Delay, t Analog Output Rise/Fall Time, t Analog Output Transition Time, t Analog Output Skew, t
CLOCK CONTROL
7
f
CLK
7
f
CLK
7
f
CLK
7
f
CLK
Data and Control Setup, t Data and Control Hold, t Clock Pulsewidth High, t Clock Pulsewidth Low, t Clock Pulsewidth High, t Clock Pulsewidth Low t Clock Pulsewidth High t Clock Pulsewidth Low t Clock Pulsewidth High t Clock Pulsewidth Low t Pipeline Delay, t PSAVE Up Time, t
NOTES
1
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
max specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
CLK
Specifications subject to change without notice.
PD
MIN
6
10
to T
6
6
9
2
4
6
5
4
5
4
5
4
5
6
MAX
4
7
5
8
1
6
0.2 ns
1.5 ns
1.4 ns f
1.4 ns f
1.875 ns f
1.875 ns f
2.85 ns f
2.85 ns f
8.0 ns f
8.0 ns f
1.0 1.0 1.0 Clock Cycles
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
7.5 ns
1.0 ns 15 ns 12 ns
50 MHz 50 MHz Grade 140 MHz 140 MHz Grade 240 MHz 240 MHz Grade 330 MHz 330 MHz Grade
410 ns
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 330 MHz
= 330 MHz = 240 MHz = 240 MHz = 140 MHz = 140 MHz = 50 MHz = 50 MHz
MIN
to
t
4
CLOCK
DIGITAL INPUTS
(R9–R0, G9–G0, B9–B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY ( TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
3. TRANSITION TIME ( TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
t
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK
6
t
) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
7
t
) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION
8
Figure 1. Timing Diagram
t
3
t
5
t
2
DATA
t
1
t
8
t
6
t
7
–7–REV. B
Page 8
ADV7123

ABSOLUTE MAXIMUM RATINGS

1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on any Digital Pin . . . . . GND – 0.5 V to V
Ambient Operating Temperature (T Storage Temperature (T Junction Temperature (T
) . . . . . . . . . . . . . . –65°C to +150°C
S
) . . . . . . . . . . . . . . . . . . . . . . 150°C
J
) . . . . . –40°C to +85°C
A
+ 0.5 V
AA
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.
2
Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.
Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . . 220°C
to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
I
OUT
AA

ORDERING GUIDE

Speed Options
Package 50 MHz
1
140 MHz
1
240 MHz
2
Plastic LQFP
(ST-48) ADV7123KST50 ADV7123KST140 ADV7123JST240 ADV7123JST330
NOTES
1
Specified for –40°C to +85°C operation.
2
Specified for 0°C to 70°C operation.
3
Available in 3.3 V version only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7123 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
330 MHz
2, 3
BLANK
SYNC

PIN CONFIGURATION

R5
R7
R9
R6
R8
48 47 46 45 44 39 38 3743 42 41 40
1
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
AA
V
B0
B1
ADV7123
TOP VIEW
(Not to Scale)
B3
B2
R4
R3
B5
B4
PSAVE
R1
R
36
V
REF
35
COMP
34
IOR
33
IOR
32
IOG
31
IOG
V
30
AA
29
V
AA
28
IOB
27
IOB
26
GND
25
GND
B9
B8
B7
B6
CLOCK
SET
R0
R2
–8–
REV. B
Page 9
ADV7123

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function
1–10 G0–G9 R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to
either the regular PCB power or ground plane.
11 BLANK Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the analog
outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a logical zero, the R0–R9, G0–G9, and B0–B9 pixel inputs are ignored.
12 SYNC Composite Sync Control Input (TTL Compatible). A logical zero on the SYNC input switches off a
40 IRE current source. This is internally connected to the IOG analog output. SYNC does not over­ride any other control or data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.
If sync information is not required on the green channel, the SYNC input should be tied to logical zero.
13, 29, 30 V
AA
14–23 B0–B9 R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to
24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9,
25, 26 GND Ground. All GND pins must be connected. 27, 31, 33 IOB, IOG, IOR Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB
28, 32, 34 IOB, IOG, IOR Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly
35 COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic
36 V
37 R
REF
SET
38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.
39–48 R0–R9 Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of
Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7123 must be connected.
either the regular PCB power or ground plane.
SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer.
video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If the complementary outputs are not required, these outputs should be tied to ground.
driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used.
capacitor must be connected between COMP and V
AA
.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)
A resistor (R
) connected between this pin and GND controls the magnitude of the full-scale video
SET
signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. For nominal video levels into a doubly terminated 75 Ω load, R
The relationship between R
and the full-scale output current on IOG (assuming I
SET
= 530 Ω.
SET
is connected
SYNC
to IOG) is given by:
R
SET
The relationship between R
SET
IOG (mA) = 11,445 × V IOR, IOB (mA) = 7,989.6 × V
(Ω)= 11,445 × V
and the full-scale output current on IOR, IOG, and IOB is given by:
(V)/IOG (mA)
REF
(V)/R
REF
REF
(V)/R
SET
SET
(Ω) (SYNC being asserted)
(Ω)
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used, i.e., SYNC tied permanently low.
CLOCK.
–9–REV. B
Page 10
ADV7123
TERMINOLOGY Blanking Level
The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level that will shut off the picture tube, resulting in the blackest possible picture.

Color Video (RGB)

This usually refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color.

Sync Signal (SYNC)

The position of the composite video signal that synchronizes the scanning process.

Gray Scale

The discrete levels of video signal between reference black and reference white levels. A 10-bit DAC contains 1024 different levels, while an 8-bit DAC contains 256.

Raster Scan

The most basic method of sweeping a CRT one line at a time to generate and display images.

Reference Black Level

The maximum negative polarity amplitude of the video signal.

Reference White Level

The maximum positive polarity amplitude of the video signal.

Sync Level

The peak level of the SYNC signal.

Video Signal

The portion of the composite video signal that varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion that may be visually observed.
–10–
REV. B
Page 11

5 V–Typical Performance Characteristics

(VAA = 5 V, V
= 1.235 V, I
REF
= 17.62 mA, 50 ⍀ Doubly Terminated Load, Differential Output Loading, TA = 25ⴗC)
OUT
ADV7123
70
60
50
40
30
SFDR – dBc
20
10
0
0.1 1001
TPC 1. SFDR vs. f
SFDR (DE)
SFDR (SE)
2.51 5.04 20.2 40.4 f
– MHz
OUT
@ f
OUT
CLOCK
140 MHz (Single-Ended and Differential)
76
74
72
70
68
66
THD – dBc
64
62
60
58
FOURTH
HARMONIC
0 160
50 100 140
f
CLOCK
– MHz
SECOND HARMONIC
THIRD HARMONIC
=
80
70
60
50
40
SFDR – dBc
30
20
10
0
TPC 2. SFDR vs. f
0.1 1001
SFDR (DE)
SFDR (SE)
2.51 5.04 20.2 40.4 f
– MHz
OUT
@ f
OUT
CLOCK
=
50 MHz (Single-Ended and Differential)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
LINEARITY – LSBs
0.3
0.2
0.1
0
020
2 17.62
I
– mA
72.0
71.8
71.6
71.4
71.2
SFDR – dBc
71.0
70.8
70.6
70.4
TPC 3. SFDR vs. Temperature @ f
= 50 MHz (f
CLOCK
1.00
0.50
0.00
ERROR – LSB
–0.50
–1.00
–10
+25 +85
TEMPERATURE – ⴗC
= 1 MHz)
OUT
CODE – INL
0.75
1023
–0.16
TPC 4. THD vs. f
CLOCK
@ f
= 2 MHz
OUT
(Second, Third, and Fourth Harmonics)
–5.0
–45.0
SFDR – dBm
–85.0
0kHz
START
TPC 7. Single-Tone SFDR @ f 140 MHz (f
OUT
35.0MHz 70.0MHz
= 2 MHz)
CLOCK
STOP
=
TPC 5. Linearity vs. I
–5.0
–45.0
SFDR – dBm
–85.0
0kHz
START
35.0MHz 70.0MHz
OUT
TPC 8. Single-Tone SFDR @ f 140 MHz (f
= 20 MHz)
OUT1
–11–REV. B
CLOCK
STOP
=
TPC 6. Typical Linearity (INL)
–5.0
–45.0
SFDR – dBm
–85.0
0kHz
START
35.0MHz
TPC 9. Dual-Tone SFDR @ f 140 MHz (f
= 13.5 MHz, f
OUT1
14.5 MHz)
CLOCK
OUT2
70.0MHz STOP
=
=
Page 12
ADV7123

3 V–Typical Performance Characteristics

(VAA = 3 V, V
70
60
50
40
30
SFDR – dBc
20
10
0
0.1 100
TPC 10. SFDR vs. f 140 MHz (Single-Ended and Differential)
= 1.235 V, I
REF
SFDR (SE)
2.51 5.04 20.2 40.4 f
OUT
= 17.62 mA, 50 ⍀ Doubly Terminated Load, Differential Output Loading, TA = 25ⴗC)
OUT
SFDR (DE)
– MHz
@ f
OUT
CLOCK
=
80
70
60
50
40
SFDR – dBc
30
20
10
0
0.1 1001.0
SFDR (DE)
SFDR (SE)
2.51 5.04 20.2 40.4
TPC 11. SFDR vs. f 140 MHz (Single-Ended and Differential)
f
OUT
– MHz
OUT
@ f
CLOCK
=
72.0
71.8
71.6
71.4
71.2
SFDR – dBc
71.0
70.8
70.6
70.4 20 85 145
TEMPERATURE – ⴗC
TPC 12. SFDR vs. Temperature @ f
= 50 MHz, (f
CLOCK
= 1 MHz)
OUT
1650
76
74
72
70
THIRD HARMONIC
68
66
THD – dBc
64
62
60
58
0 160
TPC 13. THD vs. f
SECOND HARMONIC
FOURTH HARMONIC
50 100 140
FREQUENCY – MHz
@ f
CLOCK
OUT
= 2 MHz (Second, Third, and Fourth Harmonics)
–5.0
–45.0
SFDR – dBm
1.0
0.9
0.8
0.7
0.6
0.5
0.4
LINEARITY – LSBs
0.3
0.2
0.1
0
020
TPC 14. Linearity vs. I
–5.0
–45.0
SFDR – dBm
2 17.62
I
– mA
OUT
OUT
1.00
0.50
0.00
LINEARITY – LSB
–0.50
–1.00
TPC 15. Typical Linearity
–5.0
–45.0
SFDR – dBm
0.75
1023
–0.42
CODE – INL
–85.0
0kHz
START
35.0MHz 70.0MHz
TPC 16. Single-Tone SFDR @
= 140 MHz (f
f
CLOCK
= 2 MHz)
OUT1
STOP
–85.0
START
0kHz
35.0MHz 70.0MHz
TPC 17. Single-Tone SFDR @ f
= 140 MHz (f
CLOCK
= 20 MHz)
OUT1
–12–
STOP
–85.0
0kHz
START
35.0MHz 70.0MHz
TPC 18. Dual-Tone SFDR @ f 140 MHz (f
= 13.5 MHz, f
OUT1
14.5 MHz)
STOP
CLOCK
=
OUT2
REV. B
=
Page 13
ADV7123

CIRCUIT DESCRIPTION AND OPERATION

The ADV7123 contains three 10-bit D/A converters, with three input channels, each containing a 10-bit register. Also integrated on board the part is a reference amplifier. CRT control functions BLANK and SYNC are integrated on board the ADV7123.

Digital Inputs

Thirty bits of pixel data (color information) R0–R9, G0–G9, and B0–B9 are latched into the device on the rising edge of each clock cycle. This data is presented to the three 10-bit DACs and then converted to three analog (RGB) output waveforms. See Figure 2.
CLOCK
DIGITAL INPUTS
(R9–R0, G9–G0, B9–B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOG, IOB IOR, IOG, IOB)
DATA
Figure 2. Video Data Input/Output
The ADV7123 has two additional control signals that are latched to the analog video outputs in a similar fashion. BLANK and SYNC are each latched on the rising edge of CLOCK to maintain synchronization with the pixel data stream.
The BLANK and SYNC functions allow for the encoding of these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the BLANK and SYNC digital inputs. Figure 3 shows the analog output, RGB video waveform of the ADV7123. The influence of SYNC and BLANK on the analog video waveform is illustrated.
Table I details the resultant effect on the analog outputs of BLANK and SYNC.
All these digital inputs are specified to accept TTL logic levels.

Clock Input

The CLOCK input of the ADV7123 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate, and thus the required CLOCK frequency, will be determined by the on-screen resolution according to the following equation:
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
Horiz Res =Number of Pixels/Line.
Vert Res =Number of Lines/Frame.
Refresh Rate =Horizontal Scan Rate. This is the rate at
which the screen must be refreshed, typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system.
Retrace Factor =Total Blank Time Factor. This takes into
account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8).
RED, BLUE GREEN
mA V mA V
18.62 0.7 26.67 1.000
100 IRE
008.05 0.3
43 IRE
00
NOTES:
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75⍀ LOAD. = 1.235V, R
2. V
REF
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
SET
= 530⍀.
WHITE LEVEL
BLANK LEVEL
SYNC LEVEL
Figure 3. RGB Video Output Waveform
Table I. Video Output Truth Table (R
= 530 ⍀, R
SET
LOAD
= 37.5 ⍀)
DAC
Description IOG (mA) IOG (mA) IOR/IOB IOR/IOB SYNC BLANK Input Data
WHITE LEVEL 26.67 0 18.62 0 1 1 3FFH VIDEO Video + 8.05 18.62 – Video Video 18.62 – Video 1 1 Data VIDEO to BLANK Video 18.62 – Video Video 18.62 – Video 0 1 Data BLACK LEVEL 8.05 18.62 0 18.62 1 1 000H BLACK to BLANK 0 18.62 0 18.62 0 1 000H
BLANK LEVEL 8.05 18.62 0 18.62 1 0 xxxH SYNC LEVEL 0 18.62 0 18.62 0 0 xxxH
–13–REV. B
Page 14
ADV7123
Therefore, if we have a graphics system with a 1024 × 1024 resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of 0.8, then:
Dot Rate = 1024 × 1024 × 60/0.8
= 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7123 on the rising edge of CLOCK, as described in the Digital Inputs section. It is recommended that the CLOCK input to the ADV7123 be driven by a TTL buffer (e.g., 74F244).

Video Synchronization and Control

The ADV7123 has a single composite sync (SYNC) input con­trol. Many graphics processors and CRT controllers have the ability of generating horizontal sync (HSYNC), vertical sync (VSYNC), and composite SYNC.
In a graphics system that does not automatically generate a composite SYNC signal, the inclusion of some additional logic circuitry will enable the generation of a composite SYNC signal.
The sync current is internally connected directly to the IOG output, thus encoding video synchronization information onto the green video channel. If it is not required to encode sync information onto the ADV7123, the SYNC input should be tied to logic low.

Reference Input

The ADV7123 contains an on-board voltage reference. The
pin is normally terminated to VAA through a 0.1 µF capaci-
V
REF
tor. Alternatively, the part could, if required, be overdriven by an external 1.23 V reference (AD1580).
A resistance R
connected between the R
SET
pin and GND
SET
determines the amplitude of the output video level according to Equations 1 and 2 for the ADV7123:
IOG* (mA) = 11,445 × V
IOR, IOB (mA) = 7,989.6 × V
*Applies to the ADV7123 only when SYNC is being used. If SYNC is not being
encoded onto the green channel, Equation 1 will be similar to Equation 2.
Using a variable value of R
(V)/R
REF
, as shown in Figure 4, allows for
SET
REF
SET
(V)/R
(Ω) (1)
(Ω) (2)
SET
accurate adjustment of the analog output video levels. Use of a fixed 560 Ω R
resistor yields the analog output levels as quoted
SET
in the specification page. These values typically correspond to the RS-343A video waveform values as shown in Figure 3.

D/A Converters

The ADV7123 contains three matched 10-bit D/A converters. The DACs are designed using an advanced, high speed, seg­mented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = “1”) or GND (bit = “0”) by a sophisticated decoding scheme. As all this circuitry is on one monolithic device, matching between the three DACs is optimized. As well as matching, the use of identi­cal current sources in a monolithic design guarantees monoto­nicity and low glitch. The on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations.

Analog Outputs

The ADV7123 has three analog outputs, corresponding to the red, green, and blue video signals.
The red, green, and blue analog outputs of the ADV7123 are high impedance current sources. Each one of these three RGB current outputs is capable of directly driving a 37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable. Figure 4a shows the required configuration for each of the three RGB outputs con­nected into a doubly terminated 75 Ω load. This arrangement will develop RS-343A video output voltage levels across a 75 Ω monitor.
A suggested method of driving RS-170 video levels into a 75 Ω monitor is shown in Figure 4b. The output current levels of the DACs remain unchanged, but the source termination resistance, Z
, on each of the three DACs is increased from 75 Ω to 150 Ω.
S
IOR, IOG, IOB
DACs
Z
= 75⍀
S
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES FOR RED, GREEN, AND BLUE DACs
= 75⍀
Z
O
(CABLE)
Z
= 75⍀
L
(MONITOR)
Figure 4a. Analog Output Termination for RS-343A
IOR, IOG, IOB
DACs
Z
= 150⍀
S
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES FOR RED, GREEN, AND BLUE DACs
= 75⍀
Z
O
(CABLE)
Z
= 75⍀
L
(MONITOR)
Figure 4b. Analog Output Termination for RS-170
More detailed information regarding load terminations for vari­ous output configurations, including RS-343A and RS-170, is available in an Application Note entitled Video Formats & Required Load Terminations available from Analog Devices, pub­lication no. E1228–15–1/89.
Figure 3 shows the video waveforms associated with the three RGB outputs driving the doubly terminated 75 Ω load of Figure 4a. As well as the gray scale levels, Black Level to White Level, the diagram also shows the contributions of SYNC and BLANK for the ADV7123. These control inputs add appropri­ately weighted currents to the analog outputs, producing the specific output level requirements for video applications. Table I details how the SYNC and BLANK inputs modify the output levels.

Gray Scale Operation

The ADV7123 can be used for stand-alone, gray scale (mono­chrome), or composite video applications (i.e., only one channel used for video information). Any one of the three channels, RED, GREEN, or BLUE, can be used to input the digital video data. The two unused video data channels should be tied to logical zero. The unused analog outputs should be terminated with the same load as that for the used channel. In other words, if the red channel is used and IOR is terminated with a doubly terminated 75 Ω load (37.5 Ω), IOB and IOG should be termi­nated with 37.5 Ω resistors. See Figure 5.
–14–
REV. B
Page 15
ADV7123
37.5⍀
37.5⍀
DOUBLY TERMINATED 75⍀ LOAD
VIDEO
INPUT
R0 R9
G0 G9
B0 B9
ADV7123
IOR
IOG
IOB
GND
Figure 5. Input and Output Connections for Stand-Alone Gray Scale or Composite Video

Video Output Buffers

The ADV7123 is specified to drive transmission line loads, as are most monitors rated. The analog output configurations to drive such loads are described in the Analog Interface section and illustrated in Figure 5. However, in some applications it may be required to drive long “transmission line” cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between two and four will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices pro­duces a range of suitable op amps for such applications. These include the AD84x series of monolithic op amps. In very high frequency applications (80 MHz), the AD8061 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain compo­nents of the buffer circuit will result in any desired video level.
Z
2
IOR, IOG, IOB
DACs
Z
= 75⍀
S
(SOURCE
TERMINATION)
+V
AD848
–V
S
Z
1
0.1␮F
S
75⍀
0.1␮F
ZO = 75⍀
(CABLE)
GAIN (G) = 1 +
= 75⍀
Z
L
(MONITOR)
Z
1
Z
2
Figure 6. AD848 As an Output Buffer

PC Board Layout Considerations

The ADV7123 is optimally designed for lowest noise perfor­mance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7123, it is imperative that great care be given to the PC board layout. Figure 7 shows a recommended connection diagram for the ADV7123.
The layout should be optimized for lowest noise on the ADV7123 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of V
and GND pins should be shortened to
AA
minimize inductive ringing.

Ground Planes

The ADV7123, and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 7. This bead should be located as close as possible (within three inches) to the ADV7123.
The analog ground plane should encompass all ADV7123 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces, and any output amplifiers.
The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7123.

Power Planes

The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV7123 (V
) and all
AA
associated analog circuitry. This power plane should be con­nected to the regular PCB power plane (V
) at a single point
CC
through a ferrite bead, as illustrated in Figure 7. This bead should be located within three inches of the ADV7123.
The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7123 power pins, voltage reference circuitry, and any output amplifiers.
The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling.

Supply Decoupling

Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 7).
Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of V
should be individu-
AA
ally decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV7123 contains cir­cuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three terminal voltage regulator.

Digital Signal Interconnect

The digital signal lines to the ADV7123 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the ADV7123 should be avoided to minimize noise pickup.
–15–REV. B
Page 16
ADV7123
Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (V
CC
) and
not the analog power plane.

Analog Signal Interconnect

The ADV7123 should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch.
The video output signals should overlay the ground plane and not the analog power plane, thereby maximizing the high fre­quency power supply rejection.
POWER SUPPLY DECOUPLING (0.1␮F AND 0.01␮F CAPACITOR FOR EACH V
0.1␮F
ANALOG GROUND PLANE
0.1␮F
R
SET
530⍀
75⍀
75⍀ 75⍀
COMPLEMENTARY OUTPUTS
5V (V
VIDEO
DATA
INPUTS
V
R
V
REF
SET
IOR
IOG
IOB
13, 29, 30
AA
0.1␮F
)
AA
39-48
14-23
COMP
R9–R0
1-10
G9–G0
B9–B0
ADV7123
SYNC
BLANK
CLOCK
PSAVE
IOR
IOG
IOB
GND
25, 26
For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7123 to minimize reflections.
Additional information on PCB design is available in an application note entitled, Design and Layout of a Video Graphics System for Reduced EMI. This application note is available from Analog Devices, publication no. E1309–15–10/89.
GROUP)
AA
0.01␮F
5V (VAA)
COAXIAL CABLE
75⍀
CONNECTORS
BNC
V
AA
10␮F
L1
(FERRITE BEAD)
MONITOR
(CRT)
75⍀
75⍀
75⍀
V
CC
33␮F
Figure 7. Typical Connection Diagram
–16–
REV. B
Page 17

OUTLINE DIMENSIONS

48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick (ST-48)
Dimensions shown in millimeters
ADV7123
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
ROTATED 90ⴗ CCW
VIEW A
0.08 MAX COPLANARITY
1.60 MAX
0.75
0.60
0.45
SEATING
PLANE
0.20
0.09
7ⴗ
3.5ⴗ 0ⴗ
COMPLIANT TO JEDEC STANDARDS MS-026BBC
PIN 1
INDICATOR
VIEW A
1
12
0.50
BSC
48
13
9.00 BSC
TOP VIEW
(PINS DOWN)
37
24
36
25
0.27
0.22
0.17
7.00
BSC
–17–REV. B
Page 18
ADV7123

Revision History

Location Page
10/02—Data Sheet changed from REV. A to REV. B.
Change in title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Change to Reference Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Change to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
–18–
REV. B
Page 19
–19–
Page 20
C00215–0–10/02(B)
–20–
PRINTED IN U.S.A.
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