Datasheet ADV3226, ADV3227 Datasheet (ANALOG DEVICES)

750 MHz, 16 × 16

FEATURES

16 × 16 high speed, nonblocking switch array
Pinout and functionally equivalent to the AD8114/AD8115
Complete solution

Buffered inputs
Programmable high impedance outputs
16 output amplifiers, G = +1 (ADV3226), G = +2 (ADV3227)

Drives 150 Ω loads
Operates on ±5 V supplies
Low power: 1.3 W
Excellent ac performance

−3 dB bandwidth
200 mV p-p: 820 MHz (ADV3226), 750 MHz (ADV3227)
2 V p-p: 600 MHz (ADV3226), 750 MHz (ADV3227)

Slew rate: 2150 V/μs (ADV3226), 2950 V/μs (ADV3227)
Serial or parallel programming of switch array
100-lead LFCSP (12 mm × 12 mm)

APPLICATIONS

Routing of high speed signals including

Video (NTSC, PAL, S, SECAM, YUV, RGB)

Compressed video (MPEG, wavelet)

3-level digital video (HDB3)
Data communications
Telecommunications

GENERAL DESCRIPTION

The ADV3226/ADV3227 are high speed 16 × 16 analog crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater
than 750 MHz and channel switch times of less than 20 ns with
1% settling.

The ADV3226/ADV3227 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs to prevent off channels from loading the
output bus. The ADV3226 has a gain of +1 and the ADV3227
has a gain of +2. They both operate on voltage supplies of ±5 V

Analog Crosspoint Switch

ADV3226/ADV3227

FUNCTIONAL BLOCK DIAGRAM

SER/PAR

CLK

DATAIN

UPDATE

CE

RESET

ADV3226/
ADV3227

16

INPUTS

while consuming only 118 mA (ADV3226) and 133 mA
(ADV3227) of idle current. Channel switching is performed via
a serial digital control that can accommodate daisy chaining of
several devices or via a parallel control to allow updating of an
individual output without reprogramming the entire array.

The ADV3226/ADV3227 are available in the 100-lead LFCSP
package over the extended industrial temperature range of

−40°C to +85°C.

D0 D1 D2 D3

80-BIT SHIFT REGISTER

PARALLEL L OADING

PARALLEL L ATCH

DECODE

16 × 5:16 DECODERS

SWITCH
MATRIX

D4

WITH 5-BIT

80

80

256

Figure 1.

SET INDIVIDUAL
OR RESET ALL
OUTPUTS TO OFF

16

OUTPUT
BUFFER

G = +1,

G = +2

A0

A1

A2
A3

DATAOUT

16

OUTPUTS

08653-001

Rev. 0

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rights of third parties that may result from its use. Specifications subject to change without notice. No
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ADV3226/ADV3227

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics (Serial) .................................................. 5

Logic Levels ................................................................................... 5

Timing Characteristics (Parallel) ............................................... 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

Power Dissipation ......................................................................... 7

REVISION HISTORY

4/10—Revision 0: Initial Version

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Truth Table and Logic Diagram ............................................... 10

Typical Performance Characteristics ............................................ 11

Circuit Diagrams ............................................................................ 20

Theory of Operation ...................................................................... 21

Applications Information .......................................................... 21

Power-On Reset .......................................................................... 22

Gain Selection ............................................................................. 22

Creating Larger Crosspoint Arrays .......................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. 0 | Page 2 of 24

ADV3226/ADV3227

SPECIFICATIONS

VS = ±5 V, TA = +25°C, RL = 150 Ω, unless otherwise noted.

Table 1.

ADV3226 ADV3227

Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p 820 750 MHz

2 V p-p 600 750 MHz

Gain Flatness 0.1 dB, 2 V p-p 130 60 MHz

0.5 dB, 2 V p-p, CL = 2.2 pF 400 200 MHz

Propagation Delay 2 V p-p 0.6 0.6 ns

Settling Time 1%, 2 V step 3 3 ns

Slew Rate 2 V step, peak 2150 2950 V/μs

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL 0.04 0.02 %

Differential Phase Error NTSC or PAL 0.01 0.01 Degrees

Crosstalk, All Hostile f = 100 MHz −45 −35 dB

f = 5 MHz −75 −60 dB

Off Isolation, Input to Output f = 100 MHz, one channel −80 −75 dB

IMD2 f = 100 MHz, RL = 100 Ω 47 dBm

f = 500 MHz, RL = 100 Ω 22 dBm

IMD3 f = 100 MHz, RL = 100 Ω 42 dBm

f = 500 MHz, RL = 100 Ω 14 dBm

Output 1 dB Compression Point f = 100 MHz, RL = 100 Ω 18 dBm

f = 500 MHz, RL = 100 Ω 9 dBm

Input Voltage Noise 0.01 MHz to 50 MHz 16 16 nV/√Hz

DC PERFORMANCE

Gain Error 0.1 1.0 0.4 1.5 %

Gain Matching Channel-to-channel 1.0 1.5 %

Gain Temperature Coefficient 0.8 16 ppm/°C

OUTPUT CHARACTERISTICS

Output Resistance DC, enabled 0.2 0.2 Ω

DC, disabled 10 5 MΩ

Output Disabled Capacitance 2.7 2.7 pF

Output Leakage Current Output disabled 1 1 μA

Output Voltage Range No load ±3 ±3 V

R
Short-circuit current 55 55 mA
INPUT CHARACTERISTICS

Input Offset Voltage Worst case (all configurations) ±5 ±5 mV

Input Offset Voltage Drift 8 8 μV/°C

Input Voltage Range No load ±3 ±1.5 V

R

Input Capacitance Any switch configuration 2.1 2.1 pF

Input Resistance 2 2 MΩ

Input Bias Current Any switch configuration 1 1 μA

= 150 Ω ±2.8 ±2.8 V

L

= 150 Ω ±3 ±1.5 V

L

Rev. 0 | Page 3 of 24

ADV3226/ADV3227

ADV3226 ADV3227

Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

SWITCHING CHARACTERISTICS

Enable/Disable Time
Switching Time, 2 V Step
Switching Transient (Glitch) 40 65 mV p-p

POWER SUPPLIES

Supply Current AVCC, outputs enabled, no load 110 130 125 140 mA
AVCC, outputs disabled 25 35 25 35 mA
AVEE, outputs enabled, no load 110 130 125 140 mA
AVEE, outputs disabled 25 35 25 35 mA
DVCC, outputs enabled, no load 8 10 8 10 mA

Supply Voltage Range ±4.5 ±5 ±5.5 ±4.5 ±5 ±5.5 V

PSRR DC to 50 kHz, AVCC, AVEE >60 >60 dB
f = 100 kHz, AVCC, AVEE 55 60 dB
f = 10 MHz, AVCC 45 40 dB
f = 10 MHz, AVEE 35 55 dB
f = 100 kHz, DVCC 90 80 dB
OPERATING TEMPERATURE RANGE

Temperature Range Operating (still air) −40 +85 −40 +85 °C

θJA Operating (still air) 26 26 °C/W

50%
50%

UPDATE
UPDATE

to 1% settling
to 1% settling

20 20 ns
20 20 ns

Rev. 0 | Page 4 of 24

ADV3226/ADV3227

0

T

TIMING CHARACTERISTICS (SERIAL)

Table 2.

Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t1 10 ns
CLK Pulse Width t2 10 ns
Serial Data Hold Time t3 10 ns
CLK Pulse Separation, Serial Mode t4 10 ns

t

CLK to
UPDATE

UPDATE

Delay

Pulse Width

CLK to DATAOUT Valid, Serial Mode t7 50 ns
Propagation Delay,

UPDATE

to Switch On or Off

Data Load Time, CLK = 5 MHz, Serial Mode 1.6 μs
CLK,

RESET

UPDATE

Rise and Fall Times

Time

Timing Diagram—Serial Mode

CLK

DATAIN

1 = LATCHED

UPDATE

= TRANSPAREN

t

1

0

1

0

t1t

OUT07 (D4) O UT07 (D3) OUT00 (D0)

2

3

t

7

t

4

10 ns

5

t

10 ns

6

20 ns

50 ns
30 ns

LOAD DATA INT O

SERIAL REGISTER

ON FALLING EDGE

t

5

TRANSFER DATA F ROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

t

6

DATAOUT

08653-002

Figure 2. Timing Diagram, Serial Mode

LOGIC LEVELS

Table 3. Logic Levels

VIH V

,

/PAR,

SER

RESET
CLK, DATAIN,
CE

,

UPDATE

2.0 V min 0.8 V max 2.4 V min 0.4 V max 2 μA max 2 μA max 2 μA max 300 μA max 3 mA min 1 mA min

V

IL

,

/PAR,

SER

RESET

V

OH

DATAOUT DATAOUT

CLK, DATAIN,
CE

,

UPDATE

I

OL

I

IH

/PAR,

SER
CLK, DATAIN,

,

CE

UPDATE

I

IL

/PAR, CLK,

SER
DATAIN,
UPDATE

CE

IH

RESET

,

I

I

IL

RESET

I

OH

OL

DATAOUT DATAOUT

Rev. 0 | Page 5 of 24

ADV3226/ADV3227

TIMING CHARACTERISTICS (PARALLEL)

Table 4.

Parameter Symbol Min Typ Max Unit

Parallel Data Setup Time t1d 10 ns
Address Setup Time t1a 10 ns
CLK Pulse Width t2 10 ns
Parallel Data Hold Time t3d 10 ns
Address Hold Time t3a 10 ns
CLK Pulse Separation t4 20 ns

t

UPDATE
CLK,
RESET

Pulse Width

UPDATE

Time

Rise and Fall Times

Timing Diagram—Parallel Mode

CLK

A0 TO A3

D0 TO D4

1 = LATCHED

0 = TRANSPARENT

UPDATE

1

0

1

0

1

0

t

1a

10 ns

5

50 ns
30 ns

t

2

t

1d

Figure 3. Timing Diagram, Parallel Mode

t

4

t

3a

t

3d

t

5

08653-003

Rev. 0 | Page 6 of 24

ADV3226/ADV3227

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Supply Voltage (AVCC − AVEE) 11 V
Digital Supply Voltage (DVCC − DGND) 6 V
Supply Potential Difference

±0.5 V

(AVCC − DVCC)

Ground Potential Difference

±0.5 V

(AGND − DGND)

Maximum Potential Difference

6 V

(DVCC − AVEE)
Analog Input Voltage AVEE < VIN < AVCC
Digital Input Voltage DGND < DIN < DVCC
Exposed Paddle Voltage AVEE < VIN < AVCC
Output Voltage (Disabled Analog

AVEE < V

< AVCC

OUT

Output)
Output Short-Circuit

Duration Momentary

Current Internally limited to 55 mA
Temperature

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +85°C

Junction Temperature 150°C

Lead Temperature (Soldering,

300°C

10 sec)

POWER DISSIPATION

The ADV3226/ADV3227 operate with ±5 V supplies and can
drive loads down to 100 Ω, resulting in a wide range of possible
power dissipations. For this reason, extra care must be taken
when derating the operating conditions based on ambient
temperature.

Packaged in the 100-lead LFCSP, the ADV3226/ADV3227
junction-to-ambient thermal impedance (θ
For long-term reliability, the maximum allowed junction
temperature of the die should not exceed 125°C; even
temporarily exceeding this limit can cause a shift in parametric
performance due to a change in stresses exerted on the die by
the package. Exceeding a junction temperature of 150°C for an
extended period can result in device failure. In Figure 4, the
curve shows the range of allowed internal die power dissipation
that meets these conditions over the −40°C to +85°C ambient
temperature range. When using Figure 4, do not include the
external load power in the maximum power calculation, but do
include the load current dropped on the die output transistors.

6

5

) is 26°C/W.

JA

TJ = 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θJC θJB ψJT ψJB Unit

100-Lead LFCSP 26 2.56 9.5 0.2 8.9 °C/W

4

MAXIMUM POWER (W)

3

2

15 25 35 45 55 65 75 85

Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

AMBIENT TEMPERATURE (°C)

ESD CAUTION

08653-004

Rev. 0 | Page 7 of 24

ADV3226/ADV3227

T

O

O

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESETCEDATAOU

CLK

DATAIN

UPDATE

SER/PARNCNCNCNCNCNCNCNCNCA0A1A2A3D0D1D2D3D4

100

99

98

95

97

93

96

94

898887

92

91

90

84

86

85

82

81

83

787776

80

79

1

DVCC

2

DGND

3

AGND

4

IN08

5

AGND

6

IN09

7

AGND

8

IN10

9

AGND

10

IN11

11

AGND

12

IN12

13

AGND

14

IN13

15

AGND

16

IN14

17

AGND

18

IN15

19

AGND

20

AVEE

21

AVCC

22

AVCC

23

UT15

24

AVEE

25

UT14

NOTES

1. NC = NO CONNECT.

2. T HE EXPOSE D METAL PADDL E ON THE BOT TOM O F THE LF CSP PACKAGE MUST BE SOLDERED TO PCB
GROUND FOR PRO PER HEAT DISSIPATIO N AND ALSO FO R NOISE AND MECHANI CAL STRENGT H BENEFITS.

PIN 1

26

AVCC

ADV3226/ADV3227

TOP VIEW

(Not to Scale)

27

28

OUT13

31

29

AVEE

OUT12

33

30

32

AVEE

AVCC

OUT10

OUT11

34

AVCC

37

38

39

42

44

35

36

AVEE

OUT09

OUT08

40

41

AVEE

AVCC

OUT06

OUT07

45

43

AVEE

AVCC

OUT05

48

49

46

AVCC

OUT04

50

47

AVEE

AVCC

OUT03

OUT02

Figure 5. Pin Configuration

75

DVCC

74

DGND

73

AGND

72

IN07

71

AGND

70

IN06

69

AGND

68

IN05

67

AGND

66

IN04

65

AGND

64

IN03

63

AGND

62

IN02

61

AGND

60

IN01

59

AGND

58

IN00

57

AGND

56

AVEE

55

AVCC

54

AVCC

53

OUT00

52

AVEE

51

OUT01

08653-005

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 DVCC Digital Positive Power Supply.
2 DGND Digital Ground.
3 AGND Analog Ground.
4 IN08 Input Number 8.
5 AGND Analog Ground.
6 IN09 Input Number 9.
7 AGND Analog Ground.
8 IN10 Input Number 10.
9 AGND Analog Ground.
10 IN11 Input Nu mbe r 11.
11 AGND Analog Ground.
12 IN12 Input Number 12.
13 AGND Analog Ground.
14 IN13 Input Number 13.
15 AGND Analog Ground.
16 IN14 Input Number 14.

Rev. 0 | Page 8 of 24

Pin No. Mnemonic Description

17 AGND Analog Ground.
18 IN15 Input Number 15.
19 AGND Analog Ground.
20 AVEE Analog Negative Supply.
21 AVCC Analog Positive Supply
22 AVCC Analog Positive Supply.
23 OUT15 Output Number 15.
24 AVEE Analog Negative Supply.
25 OUT14 Output Number 14.
26 AVCC Analog Positive Supply.
27 OUT13 Output Number 13.
28 AVEE Analog Negative Supply.
29 OUT12 Output Number 12.
30 AVCC Analog Positive Supply.
31 OUT11 Output Number 11.
32 AVEE Analog Negative Supply.

ADV3226/ADV3227

Pin No. Mnemonic Description

33 OUT10 Output Number 10.
34 AVCC Analog Positive Supply.
35 OUT09 Output Number 9.
36 AVEE Analog Negative Supply.
37 OUT08 Output Number 8.
38 AVCC Analog Positive Supply.
39 OUT07 Output Number 7.
40 AVEE Analog Negative Supply.
41 OUT06 Output Number 6.
42 AVCC Analog Positive Supply.
43 OUT05 Output Number 5.
44 AVEE Analog Negative Supply.
45 OUT04 Output Number 4.
46 AVCC Analog Positive Supply.
47 OUT03 Output Number 3.
48 AVEE Analog Negative Supply.
49 OUT02 Output Number 2.
50 AVCC Analog Positive Supply.
51 OUT01 Output Number 1.
52 AVEE Analog Negative Supply.
53 OUT00 Output Number 0.
54 AVCC Analog Positive Supply.
55 AVCC Analog Positive Supply.
56 AVEE Analog Negative Supply.
57 AGND Analog Ground.
58 IN00 Input Number 0.
59 AGND Analog Ground.
60 IN01 Input Number 1.
61 AGND Analog Ground.
62 IN02 Input Number 2.
63 AGND Analog Ground.
64 IN03 Input Number 3.
65 AGND Analog Ground.
66 IN04 Input Number 4.
67 AGND Analog Ground.

Pin No. Mnemonic Description

68 IN05 Input Number 5.
69 AGND Analog Ground.
70 IN06 Input Number 6.
71 AGND Analog Ground.
72 IN07 Input Number 7.
73 AGND Analog Ground.
74 DGND Digital Ground.
75 DVCC Digital Positive Power Supply.
76 D4 Parallel Data Input, Output Enable.
77 D3 Parallel Data Input.
78 D2 Parallel Data Input.
79 D1 Parallel Data Input.
80 D0 Parallel Data Input.
81 A3 Parallel Data Input.
82 A2 Parallel Data Input.
83 A1 Parallel Data Input.
84 A0 Parallel Data Input.
85 to 93 NC No Connect.
94

95

/PAR

SER
UPDATE

Serial/Parallel Mode Select (Control Pin).

Second Rank Write Strobe (Control Pin).
96 DATAIN Serial Data In (Control Pin).
97 CLK Serial Data Clock. Parallel 1st rank latch

enable (control pin).
98 DATAOUT Serial Data Out.
99
100

CE
RESET

Chip Enable (Control Pin).

Second Rank Reset (Control Pin).
N/A1 EP Exposed Paddle. The exposed metal

paddle on the bottom of the LFCSP

package must be soldered to the PCB

ground for proper heat dissipation and

for noise and mechanical strength

benefits.

1

N/A means not applicable.

Rev. 0 | Page 9 of 24

ADV3226/ADV3227

TRUTH TABLE AND LOGIC DIAGRAM

Table 8. Operation Truth Table1

UPDATE

CE

1 X X X X X X No change in logic.
0 X

0 X 0 D0…D4 N/A

0 0 X X X 1 X

X X X X X 0 X Asynchronous operation. All outputs are disabled. Second rank

1

X is don’t care.

2

DataI: serial data.

3

N/A means not applicable.

4

DATAOUT remains active in parallel mode and always reflects the state of the MSB of the serial shift register.

PARALLEL

DATA

(OUTPUT

ENABLE)

SER/PAR

DATA IN

(SERIAL)

CLK DATAIN DATAOUT

2

Data

Data

D

CLK

I

S

D1

Q

D

Q

Q

D0

CLK

D0
D1
D2
D3
D4

S

D1

Q

D0

RESET SER

X 0 The data on the serial DATAIN line is loaded into the serial register.

I-80

/PAR

Description

The first bit clocked into the serial register appears at DATAOUT 80
clock cycles later.

3

in

parallel

X 1 The data on the parallel data lines, D0 to D4, are loaded into the

80-bit serial shift register location addressed at A0 to A3.

mode4

Data in the 80-bit shift register transfers into the parallel latches
that control the switch array. Latches are transparent.

latches are cleared. Remainder of logic is unchanged.

S

D1

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

D

Q

Q

D0

CLK

S

D1

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D

Q

D0

CLK

S

D1

D0

DATA

Q

D

Q

OUT

CLK

CLK

CE

UPDATE

OUT0 EN

OUT1 EN

OUT2 EN

OUTPUT

ADDRESS

OUT3 EN

OUT4 EN

A0

OUT5 EN

A1

OUT6 EN

A2

OUT7 EN

A3

OUT8 EN

OUT9 EN

OUT10 EN

4 TO 16 DECODER

OUT11 EN

OUT12 EN

OUT13 EN

OUT14 EN

OUT15 EN

(OUTPUT ENABLE)

RESET

LE

OUT0

D

B0

Q

LE

OUT0

B1

D

Q

LE

OUT0

D

B2

Q

LE

OUT0

B3

D

Q

LE

OUT0

EN

D

QCLR

LE

OUT1

D

B0

Q

LE

OUT14

EN

D

QCLR

LE

OUT15

B0

D

Q

LE

OUT15

B1

D

Q

LE

OUT15

B2

D

Q

LE

OUT15

B3

D

Q

LE

OUT15

EN

D

QCLR

DECODE

256

16

OUTPUT ENABLESWITCH MATRIX

08653-006

Figure 6. Logic Diagram

Rev. 0 | Page 10 of 24

ADV3226/ADV3227

TYPICAL PERFORMANCE CHARACTERISTICS

1

0

–1

–2

–3

–4

–5

GAIN (dB)

–6

–7

–8

RL = 150Ω

–9

V

= 200mV p-p

OUT

–10

110k

10 100 1k

FREQUENCY (MHz )

08653-014

Figure 7. ADV3226 Small Signal Frequency Response

1

0

–1

–2

–3

–4

–5

GAIN (dB)

–6

–7

–8

RL = 150Ω

–9

V

= 2V p-p

OUT

–10

110k10 100 1k

FREQUENCY (MHz )

08653-015

Figure 8. ADV3226 Large Signal Frequency Response

6
5

4

3

2

1

0

–1

–2

–3

GAIN (dB)

–4

–5

–6

–7

–8

RL = 150Ω

–9

V

= 200mV p-p

OUT

–10

1 10 100 1k 10k

10.4pF

1.2pF

0pF

FREQUENCY (MHz )

5.0pF

2.2pF

08653-016

Figure 9. ADV3226 Small Signal Frequency Response with Capacitive Loads

8
7

6
5
4
3
2
1

0
–1
–2

GAIN (dB)

–3
–4
–5
–6
–7

RL = 150Ω

–8

V

–9

–10

= 200mV p-p

OUT

1 10 100 1k 10k

FREQUENCY (MHz )

Figure 10. ADV3227 Small Signal Frequency Response

8

7

6

5

4

3

2

1

0
–1
–2

GAIN (dB)

–3
–4
–5
–6
–7

RL = 150Ω

–8

V

–9

–10

= 2V p-p

OUT

1 10 100 1k 10k

FREQUENCY (MHz )

Figure 11. ADV3227 Large Signal Frequency Response

12

10

8

6

4

2

0

GAIN (dB)

–2

–4

–6

RL = 150Ω

–8

V

= 200mV p-p

OUT

–10

1 10 100 1k 10k

10.4pF

5.0pF

2.2pF

1.2pF

0pF

FREQUENCY (MHz )

Figure 12. ADV3227 Small Signal Frequency Response, RL = 150 Ω

08653-017

08653-018

08653-019

Rev. 0 | Page 11 of 24

ADV3226/ADV3227

4

3

2

1

0

–1

–2

–3

–4

GAIN (dB)

–5

–6

–7

–8

RL = 150Ω

–9

V

= 2V p-p

OUT

–10

1 10 100 1k 10k

Figure 13. ADV3226 Large Signal Frequency Response with Capacitive Loads

0.15

10.4pF

1.2pF

0pF

FREQUENCY (MHz )

5.0pF

2.2pF

3-020
0865

14

12

10

8

6

4

2

0

GAIN (dB)

–2

–4

–6

RL = 150Ω

–8

V

= 2V p-p

OUT

–10

1 10 100 1k 10k

10.4pF

1.2pF
0pF

FREQUENCY (MHz )

5.0pF

2.2pF

08653-023

Figure 16. ADV3227 Large Signal Frequency Response with Capacitive Loads

0.15

0.10

0.05

(V)

0

OUT

V

–0.05

–0.10

–0.15

024681012 20181614

RL = 150Ω
V

= 200mV p-p

OUT

INPUT SIGNAL

TIME (ns)

Figure 14. ADV3226 Small Signal Pulse Response

1.5

1.0

0.5

(V)

0

OUT

V

–0.5

INPUT SIGNAL

OUTPUT SI GNAL

OUTPUT SI GNAL

0.10

0.05

(V)

0

OUT

V

–0.05

–0.10

1

08653-02

–0.15

024681012 20181614

R

= 150Ω

L

V

= 200mV p-p

OUT

INPUT SIGNAL

TIME (ns)

OUTPUT SIGNAL

08653-024

Figure 17. ADV3227 Small Signal Pulse Response

1.5

1.0

0.5

(V)

0

OUT

V

–0.5

INPUT SIGNAL

OUTPUT SIG NAL

–1.0

RL = 150Ω
V

= 2V p-p

OUT

–1.5

024681012 20181614

TIME (ns)

Figure 15. ADV3226 Large Signal Pulse Response

08653-022

Rev. 0 | Page 12 of 24

–1.0

RL = 150Ω
V

= 2V p-p

OUT

–1.5

024681012 20181614

TIME (ns)

Figure 18. ADV3227 Large Signal Pulse Response

08653-025

ADV3226/ADV3227

2.0

SLEW RATE

1.5

1.0

0.5

(V)

0

OUT

V

–0.5

–1.0

PULSE: RISING EDGE

3000

2500

2000

1500

1000

500

0

SLEW RATE (V/µs)

2.0

1.5

1.0

0.5

(V)

0

OUT

V

–0.5

–1.0

SLEW RATE

PULSE: RISING EDGE

3000

2500

2000

1500

1000

500

0

SLEW RATE (V/µs)

–1.5

–2.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TIME (ns)

Figure 19. ADV3226 Rising Edge Slew Rate

2.0

1.5

1.0

0.5

(V)

0

OUT

V

–0.5

–1.0

–1.5

–2.0 –3500

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

SLEW RATE

PULSE: FALLING EDGE

TIME (ns)

Figure 20. ADV3226 Falling Edge Slew Rate

1.5

–500

–1000

500

0

–500

–1000

–1500

–2000

–2500

–3000

40

–1.5

26

08653-0

–2.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TIME (ns)

–500

–1000

08653-122

Figure 22. ADV3227 Rising Edge Slew Rate

2.0

1.5

1.0

0.5

(V)

0

OUT

V

SLEW RATE (V/µs)

08653-120

–0.5

–1.0

–1.5

–2.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

SLEW RATE

PULSE: FALLING EDGE

TIME (ns)

500

0

–500

–1000

–1500

–2000

–2500

–3000

–3500

SLEW RATE (V/µs)

08653-029

Figure 23. ADV3227 Falling Edge Slew Rate

1.5

40

1.0

OUTPUT–I NPUT

0.5

(V)

0

OUT

V

–0.5

–1.0

–1.5 –20

–1.0 –0.5 0 0.5 1.0 1.5 2.0 2. 5 3.0 3.5 4.0

INPUT SIGNAL

OUTPUT SI GNAL

PROPAGATION DELAY NOT SHOWN

TIME (ns)

Figure 21. ADV3226 Settling Time

30

20

10

0

OUTPUT ERROR (%)

–10

Rev. 0 | Page 13

1.0
OUTPUT–INPUT

0.5

(V)

0

OUT

V

–0.5

–1.0

–1.5 –20

–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

08653-027

INPUT SIGNAL

OUTPUT SI GNAL

PROPAGATION DELAY NOT SHOWN

TIME (ns)

30

20

10

0

–10

OUTPUT ERROR (%)

08653-030

Figure 24. ADV3227 Settling Time

of 24

ADV3226/ADV3227

20

10

0

–10

–20

–30

–40

PSR (dB)

–50

–60

–70

–80

–90

0.1 1k110100

Figure 25. ADV3226 Power Supply Rejection

200

180

160

140

120

100

80

60

40

NOISE SPECT RAL DENSITY (nV/ Hz)

20

0

1k 10k 100k 100M10M1M

Figure 26. ADV3226 Output Noise, 100 Ω Load

0

–10

–20

–30

–40

–50

–60

ISOLATION (dB)

–70

–80

–90

–100

110 10k1k100

VEE AGGRESSOR

FREQUENCY (MHz)

FREQUENCY (Hz)

FREQUENCY (MHz)

Figure 27. ADV3226 Off Isolation

VCC AGGRESSOR

20

0

–20

PSR (dB)

–40

–60

8

08653-02

–80

0.1 1k110100

VCC AGGRESSOR

FREQUENCY (MHz)

VEE AGGRESSOR

08653-031

Figure 28. ADV3227 Power Supply Rejection

200

180

160

140

120

100

80

60

40

NOISE SPECT RAL DENSITY (nV/ Hz)

20

2

08653-03

0

1k 10k 100k 100M10M1M

FREQUENCY (Hz)

08653-035

Figure 29. ADV3227 Output Noise, 100 Ω Load

0

–10

–20

–30

–40

–50

ISOLATION (dB)

–60

–70

–80

–90

110 11k100

08653-033

FREQUENCY (MHz)

0k

08653-036

Figure 30. ADV3227 Off Isolation

Rev. 0 | Page 14 of 24

ADV3226/ADV3227

0

IN3–OUT3: ENABLED CHANNEL
IN2 ACTIVATED

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

110100

FREQUENCY (MHz)

Figure 31. ADV3226 Crosstalk, One Adjacent Channel, RTO

0

IN3–OUT3: ENABLED CHANNEL

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

110100

FREQUENCY (MHz)

Figure 32. ADV3226 Crosstalk, All Hostile, RTO

1M

4

1k

08653-03

1k

08653-038

0

IN3–OUT3: ENABLED CHANNEL
IN2 ACTIVATED

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

110 1k100

FREQUENCY (MHz)

Figure 34. ADV3227 Crosstalk, One Adjacent Channel, RTO

20

IN3–OUT3: ENABLED CHANNEL

0

–20

–40

CROSSTALK (dB)

–60

–80

–100

110 1k100

FREQUENCY (MHz)

Figure 35. ADV3227 Crosstalk, All Hostile, RTO

1M

08653-037

08653-041

100k

10k

1k

IMPEDANCE (Ω)

100

10

1

0.01 10k1k1001010.1

FREQUENCY (MHz)

Figure 33. ADV3226 Input Impedance

08653-039

Rev. 0 | Page 15 of

24

100k

10k

1k

IMPEDANCE (Ω)

100

10

1

0.01 10k1k1001010.1

FREQUENCY (MHz)

Figure 36. ADV3227 Input Impedance

08653-042

ADV3226/ADV3227

1M

1M

100k

10k

1k

IMPEDANCE (Ω)

100

10

1

0.1 10k1k100101

FREQUENCY (MHz)

Figure 37. ADV3226 Output Impedance, Disabled

100

10

IMPEDANCE (Ω)

1

100k

10k

1k

IMPEDANCE (Ω)

100

10

0

08653-04

1

0.1 10k1k100101

FREQUENCY (MHz)

08653-043

Figure 40. ADV3227 Output Impedance, Disabled

100

10

IMPEDANCE (Ω)

1

0.1

0.1 1k100101

2.0

UPDATE

1.5

1.0

0.5

(V)

0

OUT

V

–0.5

–1.0

–1.5

–2.0

–10 3020100

FREQUENCY (MHz)

Figure 38. ADV3226 Output Impedance, Enabled

V

RISING EDGE

OUT

V

FALLING EDGE

OUT

TIME (ns)

Figure 39. ADV3226 Switching Time

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

4

08653-04

0.1

0.1 1k100101

FREQUENCY (MHz)

08653-047

Figure 41. ADV3227 Output Impedance, Enabled

2.0

UPDATE

1.5

RISING EDGE

V

1.0

0.5

(V)

0

OUT

UPDATE (V)

08653-045

V

–0.5

–1.0

–1.5

–2.0

–10 3020100

TIME (ns)

OUT

V

FALLING EDGE

OUT

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

UPDATE (V)

08653-142

Figure 42. ADV3227 Switching Time

Rev. 0 | Page 16 of 24

ADV3226/ADV3227

20

50

10

0

–10

(mV)

OUT

–20

V

–30

–40

–50

0545403530252015105

TIME (ns)

0

08653-046

Figure 43. ADV3226 Switching Glitch

40

30

20

(mV)

10

OUT

V

0

–10

–20

–30

05045403530252015105

TIME (ns)

08653-049

Figure 46. ADV3227 Switching Glitch

3

UPDATE

2

V

RISING EDG E

1

(V)

0

OUT

V

–1

–2

OUT

FALLING EDGE

V

OUT

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

UPDATE (V)

2.0

UPDATE

1.5

V

RISING EDGE

1.0

0.5

(V)

0

OUT

V

–0.5

–1.0

–1.5

OUT

V

FALLING EDGE

OUT

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

UPDATE (V)

–3 –0.5

–10 3020100

TIME (ns)

Figure 44. ADV3226 Enable Time

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

DIFFERENT IAL GAIN E RROR (%)

0

–0.005

–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0. 6 0. 8

INPUT DC OFFSET (V)

Figure 45. ADV3226 Differential Gain Error

–2.0

–10 3020100

08653-050

TIME (ns)

–0.5

08653-048

Figure 47. ADV3227 Enable Time

0.025

0.020

0.015

0.010

0.005

DIFFERENT IAL GAIN E RROR (%)

0

–0.005

–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0. 6 0.8

08653-051

INPUT DC OFFSET (V)

08653-054

Figure 48. ADV3227 Differential Gain Error

Rev. 0 | Page 17 of

24

ADV3226/ADV3227

0.0020

0.0015

0.0010

0.0005

0

–0.0005

FFERENTI AL PHASE ERROR (Degrees)
DI

–0.0010

–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8

Figure 49. ADV3226 Differential Phase Error

5

VIN = ±4.55V p- p

4

3

2

1

0

–1

VOLTAGE (V)

–2

–3

–4

–5

0 100908070605040302010

Figure 50. ADV3226 Overdrive Recovery

25

INPUT DC OFFSET (V)

@ VIN = ±4.55V p-p

V

OUT

TIME (ns)

0.008

0.006

0.004

0.002

0

–0.002

–0.004

–0.006

–0.008

DIFFERENT IAL PHASE ERROR (Degrees)

2

08653-05

–0.010

–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8

INPUT DC OFFSET (V)

08653-055

Figure 52. ADV3227 Differential Phase Error

6

VIN = ±4.65V p- p

4

2

0

VOLTAGE (V)

–2

V

@ VIN = ±4.65V p-p

–4

–6

0 100908070605040302010

08653-056

OUT

TIME (ns)

08653-059

Figure 53. ADV3227 Overdrive Recovery

60

20

15

10

5

1dB GAIN COMPRESSION (dBm)

0

10 1k100

INPUT FREQ UENCY (MHz)

Figure 51. ADV3227 1 dB Gain Compression, 100 Ω Load

08653-057

Rev. 0 | Page 18 of

50

40

30

20

THIRD-ORDER INT ERCEPT (dBm)

10

0

10 1k100

INPUT FREQ UENCY (MHz)

Figure 54. ADV3227 Third-Order Intercept, 100 Ω Load

24

08653-060

ADV3226/ADV3227

90

80

70

60

50

40

30

20

SECOND-ORDER INTERCEPT (d Bm)

10

0

10 1k100

INPUT FREQ UENCY (MHz)

Figure 55. ADV3227 Second-Order Intercept, 100 Ω Load

140

120

100

08653-058

20

–30

–40

–50

–60

–70

–80

–90

HARMONIC DI STORTION (dBc)

–100

–110

10 1k100

HD2, 10dBm

HD2, 0dBm

HD3, 0dBm

HD3, 10dBm

INPUT FREQUENCY (MHz)

Figure 57. ADV3227 Harmonic Distortion (Input Referred),100 Ω Load

08653-061

80

60

NUMBER OF HITS

40

20

0

–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30

COUNT

08653-156

Figure 56. ADV3226 and ADV3227, Input VOS Distribution

Rev. 0 | Page 19 –of 24

ADV3226/ADV3227

CIRCUIT DIAGRAMS

INx

2.1pF

Figure 58. Analog Input

Figure 59. Analog Output Enabled

AVCC

A[3:0], CE, CLK,

7

08653-00

D[4:0], DATAI N,
SER/PAR, UPDATE

1kΩ

DGND

08653-008

Figure 61. Logic Input

OUTx

OUTx

2.7pF

08653-010

08653-011

Figure 62. Analog Output Disabled

DVCC

INx, OUTx

AGND

AGND

DGND

Figure 60. ESD Map

CLK, RESET,
SER/PAR, CE,
UPDATE,
DATAIN,
DATAOUT,
A[3:0]. D[4:0]

DVCC

20kΩ

RESET

08653-013

1kΩ

DGND

8653-009

Figure 63. Reset Input

DVCC

DATAOUT

DGND

08653-012

Figure 64. Logic Output

Rev. 0 | Page 20 of 24

ADV3226/ADV3227

THEORY OF OPERATION

The ADV3226 (G = 1) and ADV3227 (G = 2) are crosspoint
arrays with 16 outputs, each of which can be connected to any
one of 16 inputs. Organized by output row, 16 switchable input
transconductance stages are connected to each output buffer to
form 16-to-1 multiplexers. There are 16 of these multiplexers,
each with its inputs wired in parallel, for a total array of 256 trans­conductance stages forming a multicast-capable crosspoint
switch. Each input is buffered and is not loaded by the outputs,
simplifying the construction of larger arrays using the ADV3226
or ADV3227 as a building block.

Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier. A mask programmable feedback
network sets the closed-loop signal gain. For theADV3226, this
gain is 1, and for the ADV3226, this gain is 2.

The output stage of the ADV3226 or ADV3227 is designed for
low differential gain and phase error when driving composite
video signals. It also provides slew current for a fast pulse response
when driving component video signals. Unlike many multiplexer
designs, these requirements are balanced such that large signal
bandwidth is very similar to small signal bandwidth. The design
load is150 Ω, but provisions are made to drive loads as low as
100 Ω when on-chip power dissipation limits are not exceeded.

The outputs of the ADV3226/ADV3227 can be disabled to mini­mize on-chip power dissipation. When disabled, there is no
feedback network loading the output. This high disabled output
impedance allows multiple ICs to be bussed together without
additional buffering. Care must be taken to reduce output capa­citance, which results in more overshoot and frequency domain
peaking.

A series of internal amplifiers drives internal nodes such that a
wideband high impedance is presented at the disabled output,
even while the output bus is under large signal swings. To keep
these internal amplifiers in their linear range of operation when
the outputs are disabled and driven externally, do not allow the
voltage applied to them to exceed the valid output swing range
for the ADV3226/ADV3227. If the disabled outputs are left
floating, they may exhibit high enable glitches. If necessary,
the disabled output can be kept from drifting out of range by
applying an output load resistor to ground.

The connection of the ADV3226/ADV3227 is controlled by a
flexible TTL-compatible logic interface. Either parallel or serial
loading into a first rank of latches preprograms each output. A
global update signal moves the programming data into the second
rank of latches, simultaneously updating all outputs. In serial
mode, a serial out pin allows devices to be daisy-chained together
for single pin programming of multiple ICs. A power-on reset

Rev. 0 | Page 21 of 24

pin is available to avoid bus conflicts by disabling all outputs.
This power-on reset clears the second rank of latches but does
not clear the first rank of latches. In serial mode, preprogramming
individual inputs is not possible and the entire shift register needs
to be flushed.

To easily interface to ground referenced video signals, the
ADV3226/ADV3227 operate on split ±5 V supplies. The logic
inputs and output run on a single +5 V supply, but the logic
inputs switch at approximately 1.6 V for compatibility with a
variety of logic families. The serial output buffer is a rail-to-rail
output stage with 5 mA of drive capability.

APPLICATIONS INFORMATION

The ADV3226/ADV3227 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 80 bits can be provided, which updates the entire
matrix each time the 80-bit word is shifted into the part. The
second option allows for changing the programming of a single
output via a parallel interface. The serial option requires fewer
signals but more time (clock cycles) for changing the program­ming, whereas the parallel programming technique requires
more signals but can change a single output at a time and requires
fewer clock cycles to complete the programming.

Serial Programming

The serial programming mode uses the CE, CLK, DATAIN,

UPDATE

SER

on
the chip must be low to allow data to be clocked into the device.

CE

The

devices are connected in parallel.

UPDATE

The

shifted into the serial port of the device. Although the data still
shifts in when

latches allow the shifting data to reach the matrix, which causes
the matrix to try to update to every intermediate state as defined by
the shifting data.

The data at DATAIN is clocked in at every falling edge of CLK.
A total of 80 bits must be shifted in to complete the programming.
For each of the 16 outputs, there are four bits (D0 to D3) that deter­mine the source of its input. The MSB is shifted in first. A fifth bit
(D4) precedes the four input select bits and determines the enabled
state of the output. If D4 is low (output disabled), the four asso­ciated bits (D0 to D3) do not matter because no input switches
to that output.

The most significant output address data is shifted in first, and
the remaining addresses follow in sequence until the least signifi­cant output address data is shifted in. At this point,

can be taken low, which programs the device according to the

SER

, and

/PAR to enable the serial programming mode. CE for

signal can be used to address an individual device when

/PAR pins. The first step is to assert a low

signal should be high during the time that data is

UPDATE

is low, the transparent, asynchronous

UPDATE

ADV3226/ADV3227

data that was just shifted in. The update registers are asynchronous,
and when

If more than one ADV3226/ADV3227 device is to be serially
programmed in a system, the DATAOUT signal from one
device can be connected to the DATAIN of the next device to
form a serial chain. Connect all of the CLK,

SER

in this section. The serial data is input to the DATAIN pin of
the first device of the chain, and it ripples through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence (80 bits) is multiplied by the number
of devices in the chain.

UPDATE

/PAR pins in parallel and operate them as described previously

Parallel Programming

When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
Parallel programming allows the modification of a single output
at a time. Because this takes only one CLK/

cant time savings can be realized by using parallel programming.

An important consideration in using parallel programming is

RESET

that the

ADV3227. When taken low, the

to the disabled state. This is helpful during power-up to ensure
that two parallel outputs are not active at the same time.

After initial power-up, the internal registers in the device
generally contain random data, even though the

was asserted. If parallel programming is used to program one
output, that output is properly programmed, but the rest of the
device has a random program state depending on the internal
register content at power-up. Therefore, when using parallel
programming, it is essential that all outputs be programmed to
a desired state after power-up to ensure that the programming
matrix is always in a known state. From this point, parallel pro­gramming can be used to modify either a single output or multiple
outputs at one time.

Similarly, if both

power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent programming
the crosspoint into an unknown state, do not apply low logic
levels to both

To eliminate the possibility of programming the matrix to an
unknown state, after initial power-up, program the full shift
register one time to a desired state using either serial or parallel
programming.

To change the programming of an output via parallel program­ming, take the

CE

pin low. The CLK signal should be in the high state. Place

the 4-bit address of the output to be programmed on A0 to A3.

is low (and CE is low), they are transparent.

CE

UPDATE

,

UPDATE

signal does not reset all registers in the ADV3226/

RESET

signal sets each output

RESET

CE

CE

and

SER

UPDATE

and

UPDATE

/PAR and

are taken low after initial

after power is initially applied.

UPDATE

pins high, and take the

, and

cycle, signifi-

signal

The first four data bits (D0 to D3) contain the information that
identifies the input that is programmed to the addressed output.
The fifth data bit (D4) determines the enabled state of the out­put. If D4 is low (output disabled), the data on D0 to D3 does
not matter.

After the address and data signals are established, they can be
latched into the shift register by pulling the CLK signal low;
however, the matrix is not programmed until the

signal is taken low. In this way, it is possible to latch in new data
for several or all of the outputs first via successive negative transi­tions of CLK while

new data take effect when
when programming the device for the first time after power-up
when using parallel programming. In parallel mode, the CLK
pin is level sensitive, whereas in serial mode, it is edge triggered.

UPDATE

UPDATE

is held high and then have all the

goes low. Use this technique

UPDATE

POWER-ON RESET

When powering up the ADV3226/ADV3227, it is usually desirable
to have the outputs come up in the disabled state. When taken

RESET

low, the

However, the

ADV3226/ADV3227. This is important when operating in the
parallel programming mode. Refer to the
section for information about programming internal registers
after power-up. Serial programming programs the entire matrix
each time; therefore, no special considerations apply.

Because the data in the shift register is random after power-up,
it should not be used to program the matrix, or the matrix can
enter unknown states. To prevent the matrix from entering
unknown states, do not apply logic low signals to both

UPDATE

register with the data and then take
the device.

RESET

The

used to create a simple power-up reset circuit. A capacitor from
RESET

to ground holds the

which the rest of the device stabilizes. The low condition causes
all of the outputs to be disabled. The capacitor then charges
through the pull-up resistor to the high state, thereby allowing full
programming capability of the device.

pin causes all outputs to be in the disabled state.

RESET

signal does not reset all registers in the

Parallel Programming

CE

and

initially after power-up. Instead, first load the shift

UPDATE

pin has a 20 k pull-up resistor to DVCC that can be

RESET

pin low for a period during

low to program

GAIN SELECTION

The 16 × 16 crosspoints come in two versions, depending on
the gain of the analog circuit path. The ADV3226 device is unity
gain and can be used for analog logic switching and other
applications where unity gain is desired. The ADV3226 outputs
have very high impedance when their outputs are disabled.

The ADV3227 can be used for devices that drive a terminated
cable with its outputs. This device has a built-in gain-of-2 that
eliminates the need for a gain-of-2 buffer to drive a video line. Its

Rev. 0 | Page 22 of 24

ADV3226/ADV3227

high output disabled impedance minimizes signal degradation
when paralleling additional outputs.

CREATING LARGER CROSSPOINT ARRAYS

The ADV3226/ADV3227 are high density building blocks for
creating crosspoint arrays of dimensions larger than 16 × 16.
Various features, such as output disable, chip enable, and gain­of-1 and gain-of-2 options, are useful for creating larger arrays.
When required for customizing a crosspoint array size, they can
be used with the AD8108 and AD8109, which are a pair of
(unity-gain and gain-of-2) 8 × 8 video crosspoint switches, or
with the AD8110 and AD8111, a pair of (unity-gain and gain-
of-2) 16 × 8 video crosspoint switches.

The first consideration in constructing a larger crosspoint is to
determine the minimum number of required devices that are
required. The 16 × 16 architecture of the ADV3226/ADV3227
contains 256 points, which is a factor of 64 greater than a 4 × 1
crosspoint (or multiplexer). The benefits realized in PCB area
used, power consumption, and design effort are readily apparent
when compared to using multiples of these smaller 4 × 1 devices.

To obtain the minimum number of required points for a non­blocking crosspoint, multiply the number of inputs by the number
of outputs. Nonblocking requires that the programming of a given
input to one or more outputs does not restrict the availability of
that input to be a source for any other outputs. Some nonblocking
crosspoint architectures require more than this minimum. In
addition, there are blocking architectures that can be constructed
with fewer devices than this minimum. These systems have
connectivity available on a statistical basis that is determined
when designing the overall system.

The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-OR
the outputs together in the vertical direction. The meaning of
horizontal and vertical can best be understood by referring to
Figure 65, which illustrates this concept for a 32 × 32 crosspoint
array that uses four ADV3226 or ADV3227 devices.

IN 00–15

16

ADV3226

OR

ADV3227

16

IN 16–31

16

ADV3226

OR

ADV3227

16

Figure 65. A 32 × 32 Nonblocking Crosspoint Switch Array

R

R

16

TERM

16

TERM

16

16

ADV3226

OR

ADV3227

16

ADV3226

OR

ADV3227

16

Each input is uniquely assigned to each of the 32 inputs of the two
devices and terminated appropriately. The outputs are wired-OR’ed
together in pairs. Enable the output from only one wire-OR’ed
pair at any given time. The device programming software must
be properly written to prevent multiple connected outputs from
being enabled at the same time.

For a complete 32 × 32 array in a single device, refer to the AD8117
and AD8118 for high bandwidth or the ADV3200 and

ADV3201 for lower bandwidth. Also available are 32 × 16 arrays in

a single package: AD8104, AD8105, ADV3202, and ADV3203.

08653-062

Rev. 0 | Page 23 of 24

ADV3226/ADV3227

A

X

OUTLINE DIMENSIONS

PIN 1

INDICATOR

12.00

BSC SQ

11.7 5

BSC SQ

0.60 MAX

0.40

BSC

0.60 M

0.25

0.20

0.15

PIN 1

75

76

EXPOSED PAD

(BOTTOM VIEW)

1

100

INDICATOR

7.00

6.90 SQ

6.80

26

25

0.20 MIN

FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

06-11-2008-B

0.90

0.85

0.80

SEATING

PLANE

12° MAX

TOP VIEW

50

51

0.50

0.05 MAX

0.01 NOM

0.20 REF

0.40

0.30

9.60 REF

0.70

0.65

0.60

COMPLIANT TO JEDEC STANDARDS MO-220-VRRE.

Figure 66. 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

12 mm × 12 mm Body, Very Thin Quad

(CP-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADV3226ACPZ −40°C to +85°C 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-100-1
ADV3227ACPZ −40°C to +85°C 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-100-1
ADV3226-EVALZ Evaluation Board
ADV3227-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08653-0-4/10(0)

Rev. 0 | Page 24 of 24