Datasheet ADV212 Datasheet (ANALOG DEVICES)

www.BDTIC.com/ADI

JPEG 2000 Video Codec

FEATURES

Complete single-chip JPEG 2000 compression and

decompression solution for video and still images

Identical in pinout and footprint to the ADV202 and

supports all the functionality of the ADV202
Power reduction of at least 30% compared with ADV202
JTAG/boundary scan support
Patented SURF® (spatial ultraefficient recursive filtering)

technology enables low power, low cost wavelet-based

compression
Supports both 9/7 and 5/3 wavelet transforms with up to

6 levels of transform
Video interface directly supporting ITU-R BT.656,

SMPTE 125M PAL/NTSC, SMPTE 274M, SMPTE 293M

(525p), and ITU-R BT.1358 (625p), or any video format with

a maximum input rate of 65 MSPS for irreversible mode or

40 MSPS for reversible mode
Programmable tile/image size with widths up to 4096 pixels

in single-component mode; maximum tile/image height:

4096 pixels
2 or more ADV212s can be combined to support full-frame

SMPTE 274M HDTV (1080i) or SMPTE 296M (720p)
Flexible, asynchronous SRAM-style host interface allows glue-

less connection to most 16-/32-bit microcontrollers and ASICs

2.5 V or 3.3 V input/output and 1.5 V core supply
12 mm × 12 mm, 121-ball CSPBGA with a speed grade of

115 MHz, or 13 mm × 13 mm, 144-ball CSPBGA with a

speed grade of 150 MHz

APPLICATIONS

Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders

ADV212

GENERAL DESCRIPTION

The ADV212 is a single-chip JPEG 2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and features provided by
the JPEG 2000 (J2K)—ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG 2000 image compression standard and
provides fully compliant code-stream generation for most
applications.

The dedicated video port of the ADV212 provides glueless con­nection to common digital video standards such as ITU-R BT.656,
SMPTE 125M, SMPTE 293M (525p), ITU-R BT.1358 (625p),
SMPTE 274M (1080i), or SMPTE 296M (720p). A variety of
other high speed, synchronous pixel and video formats can also
be supported by using the programmable framing and
validation signals.

The ADV212 is an upgrade version of the ADV202 that is
identical in pinout and footprint. It supports all the functionality
of the ADV202 and has the following additional options:

• JTAG/boundary scan support

• Power reduction of at least 30% compared with the

ADV202

FUNCTIONAL BLOCK DIAGRAM

PIXEL I/F

HOST I/F

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

PIXEL I/F

EXTERNAL
DMA CTRL

PIXEL FIFO
CODE FIF O
ATTR FIFO

ADV212

WAVELET

ENGINE

INTERNAL BUS AND DMA ENGINE

EMBEDDED

RISC

PROCESSOR

SYSTEM

Figure 1.

EC1 EC2 EC3

RAM ROM

06389-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADV212

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

JPEG 2000 Feature Support......................................................... 3

Specificatons...................................................................................... 4

Supply Voltages and Current ...................................................... 4

Input/Output Specifications........................................................ 4

Clock and

Normal Host Mode—Write Operation ..................................... 6

Normal Host Mode—Read Operation ...................................... 7

DREQ

DREQ

External DMA Mode—FIFO Write, Burst Mode .................. 12

External DMA Mode—FIFO Read, Burst Mode ................... 13

Streaming Mode (JDATA)—FIFO Read/Write...................... 14

VDATA Mode Timing............................................................... 15

Raw Pixel Mode Timing............................................................ 17

JTAG Timing............................................................................... 18

Absolute Maximum Ratings.......................................................... 19

Thermal Resistance .................................................................... 19

ESD Caution................................................................................ 19

Pin Configurations and Function Descriptions ......................... 20

Theory of Operation ...................................................................... 25

Wavelet Engine ........................................................................... 25

Entropy Codecs........................................................................... 25

Embedded Processor System.................................................... 25

RESET

Specifications................................................ 5

DACK

/

DMA Mode—Single FIFO Write Operation .. 8

DACK

/

DMA Mode—Single FIFO Read Operation. 10

Memory System.......................................................................... 25

Internal DMA Engine................................................................ 25

ADV212 Interface .......................................................................... 26

Video Interface (VDATA Bus).................................................. 26

Host Interface (HDATA Bus) ................................................... 26

Direct and Indirect Registers.................................................... 26

Control Access Registers........................................................... 27

Pin Configuration and Bus Sizes/Modes ................................ 27

Stage Register.............................................................................. 27

JDATA Mode............................................................................... 27

External DMA Engine ............................................................... 27

Internal Registers............................................................................ 28

Direct Registers........................................................................... 28

Indirect Registers........................................................................ 29

PLL ............................................................................................... 30

Hardware Boot............................................................................ 31

Video Input Formats ...................................................................... 32

Applications..................................................................................... 34

Encode—Multichip Mode......................................................... 34

Decode—Multichip Master/Slave ............................................ 35

Digital Still Camera/Camcorder .............................................. 36

Encode/Decode SDTV Video Application............................. 37

32-Bit Host Application............................................................. 38

HIPI (Host Interface—Pixel Interface) ................................... 39

JDATA Interface ......................................................................... 40

Outline Dimensions....................................................................... 41

Ordering Guide .......................................................................... 42

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

ADV212

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The ADV212 can process images at a rate of 40 MSPS in reversible
mode and at higher rates when used in irreversible mode. The
ADV212 contains a dedicated wavelet transform engine, three
entropy codecs, an on-board memory system, and an embedded
reduced instruction set computer (RISC) processor that can
provide a complete JPEG 2000 compression/decompression
solution.

The wavelet processor supports the 9/7 irreversible wavelet
transform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy codecs support all features in
the JPEG 2000 Part 1 specification, except maximum shift
region of interest (ROI).

The ADV212 operates on a rectangular array of pixel samples
called a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV212’s maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while maintaining a single, fully compliant JPEG 2000
code stream for the entire image.

JPEG 2000 FEATURE SUPPORT

The ADV212 supports a broad set of features that are included
in Part 1 of the JPEG 2000 standard (ISO/IEC 15444). See

ADV212 User’s Guide f

that the ADV212 currently supports.

Depending on the particular application requirements, the
ADV212 can provide varying levels of JPEG 2000 compression
support. It can provide raw code block and attribute data output,
which allows the host software to have complete control over
the generation of the JPEG 2000 code stream and other aspects
of the compression process such as bit-rate control. Otherwise,
the ADV212 can create a complete, fully compliant JPEG 2000
code stream (J2C) and enhanced file formats such as JP2.

or information on the JPEG 2000 features

Rev. 0 | Page 3 of 44

ADV212

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SPECIFICATONS

Specifications apply to IOVDD = 2.5 V or 3.3 V over operating temperature range, unless otherwise specified.

SUPPLY VOLTAGES AND CURRENT

Table 1.

Parameter Mnemonic Min Typ Max Unit

DC Supply Voltage, Core VDD 1.425 1.5 1.575 V
DC Supply Voltage, Input/Output IOVDD 2.375 2.5 2.625 V
DC Supply Voltage, Input/Output IOVDD 3.135 3.3 3.465 V
Input Range VIN −0.3 V
Operating Ambient Temperature Range in Free Air T −40 +25 +85 °C
Static Current1 IDD 15 30 mA
Dynamic Current, Core (JCLK Frequency = 150 MHz)2 380 440 mA
Dynamic Current, Core (JCLK Frequency = 108 MHz) 280 320 mA
Dynamic Current, Core (JCLK Frequency = 81 MHz) 210 290 mA
Dynamic Current, Input/Output 40 50 mA

1

No clock or input/output activity.

2

ADV212-150 only.

INPUT/OUTPUT SPECIFICATIONS

+ 0.3 V

DDI/O

Table 2.

Parameter Mnemonic Min Typ Max Unit Test Conditions

High Level Input Voltage V
High Level Input Voltage V
Low Level Input Voltage V
High Level Output Voltage V
High Level Output Voltage V
Low Level Output Voltage V
High Level Input Current IIH 1.0 μA VDD = maximum, VIN = VDD
Low Level Input Current IIL 1.0 μA VDD = maximum, VIN = 0 V
High Level Three-State Leakage Current I
Low Level Three-State Leakage Current I
Input Pin Capacitance CI 8 pF
Output Pin Capacitance CO 8 pF

2.2 V VDD = maximum

IH (3.3 V)

1.9 V VDD = maximum

IH (2.5 V)

IL (3.3 V, 2.5 V )

OH (3.3 V)

OH (2.5 V)

OL (3.3 V, 2.5 V )

OZH

OZL

0.6 V VDD = minimum

2.4 V VDD = minimum, IOH = −0.5 mA

2.0 V VDD = minimum, IOH = −0.5 mA

0.4 V VDD = minimum, IOL = +2 mA

1.0 μA VDD = maximum, VIN = VDD

1.0 μA VDD = maximum, VIN = 0V

Rev. 0 | Page 4 of 44

ADV212

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CLOCK AND RESET SPECIFICATIONS

Table 3.

Parameter Mnemonic Min Typ Max Unit

MCLK Period t
MCLK Frequency f
MCLK Width Low t
MCLK Width High t
VCLK Period t
VCLK Frequency f
VCLK Width Low t
VCLK Width High t
RESET Width Low

1

For a definition of MCLK, see Figure 32.

MCLK

13.3 100 ns

MCLK

10 75.18 MHz

MCLK

6 ns

MCLKL

6 ns

MCLKH

13.4 50 ns

VCLK

20 74.60 MHz

VCLK

5 ns

VCLKL

5 ns

VCLKH

t

5 MCLK cycles1

RESET

t

MCLK

VCLK

t

MCLKH

t

VCLKH

t

MCLKL

t

VCLKL

t

VCLK

Figure 2. Input Clock

06389-010

Rev. 0 | Page 5 of 44

ADV212

A

www.BDTIC.com/ADI

NORMAL HOST MODE—WRITE OPERATION

Table 4.

Parameter Mnemonic Min Typ Max Unit

t

WE to ACK, Direct Registers and FIFO Accesses

WE to ACK, Indirect Registers

Data Setup tSD 3.0 ns
Data Hold tHD 1.5 ns
Address Setup tSA 2 ns
Address Hold t
CS to WE Setup

CS Hold
Write Inactive Pulse Width (Minimum Time Until Next WE Pulse)
Write Active Pulse Width tWL 2.5 JCLK ns
Write Cycle Time t

1

For a definition of JCLK, see Figure 32.

t

SA

ADDR

(direct) 5 1.5 × JCLK + 7.0 ns

ACK

t

(indirect) 5 2.5 × JCLK + 7.0 ns

ACK

2 ns

HA

t

0 ns

SC

t

0 ns

HC

t

2.5 JCLK1 ns

WH

5 JCLK ns

WCYC

t

HA

ACK

HDAT

CS

WE

t

SC

t

WL

t

ACK

t

SD

VALID

t

HC

t

WCYC

t

WH

t

HD

06389-012

Figure 3. Normal Host Mode—Write Operation

Rev. 0 | Page 6 of 44

ADV212

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NORMAL HOST MODE—READ OPERATION

Table 5.

Parameter Mnemonic Min Typ Max Unit

RD to ACK, Direct Registers and FIFO Accesses

RD to ACK, Indirect Registers

Read Access Time, Direct Registers t
Read Access Time, Indirect Registers t
Data Hold t
CS to RD Setup

t

ACK

t

ACK

DRD

DRD

HZRD

t

0 ns

SC

Address Setup tSA 2 ns

t

CS Hold
Address Hold t

0 ns

HC

2 ns

HA

Read Inactive Pulse Width tRH 2.5 JCLK 2 ns
Read Active Pulse Width tRL 2.5 JCLK ns
Read Cycle Time, Direct Registers t

1

Timing relationship between

minimum of three JCLK cycles is recommended between

2

For a definition of JCLK, see Figure 32.

ACK

falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to RD rising transition. A

ACK

assert and RD deassert.

RCYC

t

SA

ADDR

1

(direct)

(indirect)

1

5 1.5 × JCLK + 7.0 ns

10.5 × JCLK 15.5 × JCLK + 7.0 ns

(direct) 5 1.5 × JCLK + 7.0 ns
(indirect) 10.5 × JCLK 15.5 × JCLK + 7.0 ns

2 8.5 ns

5.0 JCLK ns

t

HA

CS

RD

ACK

HDATA

t

SC

t

RL

t

ACK

t

DRD

VALID

t

HC

t

RCYC

t

RH

t

HZRD

06389-011

Figure 4. Normal Host Mode—Read Operation

Rev. 0 | Page 7 of 44

ADV212

A

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DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION

Table 6.

Parameter Mnemonic Min Typ Max Unit

DREQ Pulse Width DREQ
DACK Assert to Subsequent DREQ Delay

WE to DACK Setup

Data to DACK Deassert Setup
Data to DACK Deassert Hold

t

DREQ

t

WE

t

SU

t

HD

PULSE

2.5 JCLK 3.5 × JCLK + 8.5 ns

0 ns

SU

2 ns

2 ns
DACK Assert Pulse Width DACKLO
DACK Deassert Pulse Width DACKHI

t

WE Hold After DACK Deassert

0 ns

WE

HD

WE Assert to FSRQ Deassert (FIFO Full) WFSRQ

t

DACK to DREQ Deassert (DR × PULS = 0)

1

For a definition of JCLK, see Figure 32.

2.5 JCLK 3.5 × JCLK + 9.0 ns

DREQ

RTN

DREQ

DREQ

DACK

HDAT

WE

PULSE

t

WESU

Figure 5. Single Write for

DACK

t

DREQ

DACK

HI

LO

t

HD

t

SU

DACK

DREQ

/

DMA Mode for Assigned DMA Channel

(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)

t

DREQRTN

DREQ

DACK

HI

t

HD

0 1 2

DACK

DREQ

/

DMA Mode for Assigned DMA Channel

DACK

HDAT

WE

DACK

LO

t

WESU

t

SU

Figure 6. Single Write for

(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)

1

1 JCLK

15 JCLK ns

2 JCLK ns
2 JCLK ns

1.5 JCLK 2.5 × JCLK + 7.5 ns

t

WEHD

t

WEHD

3210

6389-013

06389-014

Rev. 0 | Page 8 of 44

ADV212

A

A

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DREQ

DREQ

DACK

WEFB

HDAT

t

WESU

PULSE

t

DREQ

DACK

DACK

LO

t

SU

HI

t

HD

0 1 2

t

WEHD

06389-015

Figure 7. Single Write Cycle for Fly-By DMA Mode

DREQ

(

Pulse Width Is Programmable)

FCS0

RD

WFSRQ

0

SUtHD

1 2

Figure 8. Single Write Access for DCS DMA Mode

FIFO FULL

NOT WRITTEN TO FIFO

6389-021

FSRQ0

HDAT

FIFO NOT FULL

t

Rev. 0 | Page 9 of 44

ADV212

A

A

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DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION

Table 7.

Parameter Mnemonic Min Typ Max Unit

DREQ Pulse Width DREQ
DACK Assert to Subsequent DREQ Delay

RD to DACK Setup

DACK to Data Valid

t

t

t

DREQ

RD

RD

PULSE

2.5 JCLK 3.5 × JCLK + 9.0 ns

0 ns

SU

2.5 11 ns

Data Hold tHD 1.5 ns
DACK Assert Pulse Width DACKLO
DACK Deassert Pulse Width DACKHI

t

RD Hold after DACK Deassert

0 ns

RD

HD

RD Assert to FSRQ Deassert (FIFO Empty) RDFSRQ

t

DACK to DREQ Deassert (DR × PULS = 0)

1

For a definition of JCLK, see Figure 32.

2.5 JCLK

DREQ

RTN

DREQ

PULSE

DREQ

DACK

t

DREQ

LO

DACK

HI

1

1 JCLK

15 JCLK ns

2 JCLK ns
2 JCLK ns

1.5 JCLK

2.5 × JCLK + 9.0

3.5 × JCLK + 9.0

ns
ns

DACK

HDAT

RD

t

RDSU

t

RD

0 1 2

Figure 9. Single Read for

t

HD

DREQ

DACK

/

DMA Mode for Assigned DMA Channel

t

RDHD

6389-018

(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)

t

DREQRTN

DREQ

DACK

HI

t

HD

0 1 2

DACK

DREQ

/

DMA Mode for Assigned DMA Channel

t

RDHD

06389-019

DACK

HDAT

RD

DACK

LO

t

RDSU

t

RD

Figure 10. Single Read for

(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)

Rev. 0 | Page 10 of 44

ADV212

A

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DREQ

DACK

RDFB

HDAT

DREQ

t

RDSU

PULSE

t

DREQ

DACK

DACK

LO

t

RD

HI

t

HD

0 1 2

t

RDHD

6389-020

Figure 11. Single Read Cycle for Fly-By DMA Mode

DREQ

(

Pulse Width Is Programmable)

FCS0

RD

RDFSRQ

FSRQ0

FIFO NOT EMPTY

t

RD

FIFO EMPTY

t

HD

HDATA

0

Figure 12. Single Read Access for DCS DMA Mode

1

6389-090

Rev. 0 | Page 11 of 44

ADV212

A

A

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EXTERNAL DMA MODE—FIFO WRITE, BURST MODE

Table 8.

Parameter Mnemonic Min Typ Max Unit

DREQ Pulse Width1 DREQ
WE to DREQ Deassert (DR × PULS = 0)

DACK to WE Setup

t

t

DREQ

DACK

PULSE

2.5 JCLK 3.5 × JCLK + 7.5 ns

RTN

0 ns

SU

Data Setup tSU 2.5 ns
Data Hold tHD 2 ns
WE Assert Pulse Width WELO

WE Deassert Pulse Width WEHI

t

WEDeassert to Next DREQ

WE Deassert to DACK Deassert

1

Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.

2

For a definition of JCLK, see Figure 32.

2.5 JCLK 4.5 × JCLK + 9.0 ns

DREQ

WAIT

t

WE_DACK

DREQ

PULSE

DREQ

DACK

2

1 JCLK

15 JCLK ns

1.5 JCLK ns

1.5 JCLK ns

0 ns

t

DREQWAIT

t

WE_DACK

WE

HDATA

DREQ

DACK

WE

HDAT

DREQ

DACK

WEFB

HDAT

t

DACKSU

t

HD

t

SU

01 13

Figure 13. Burst Write Cycle for

WE

DREQ

/DMA Mode for Assigned DMA Channel

LO

WE

HI

14 15

(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)

t

DREQRTN

t

WE_DACK

t

DACKSU

t

HD

t

SU

0 1 13 14 15

Figure 14. Burst Write Cycle for

WE

LO

DREQ

/DMA Mode for Assigned DMA Channel

WE

HI

(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)

t

DREQRTN

t

WE_DACK

t

DACKSU

t

HD

t

SU

0 1 13 14 15

WE

LO

WE

HI

Figure 15. Burst Write Cycle for Fly-By DMA Mode

t

DREQWAIT

t

DREQWAIT

06389-022

06389-023

6389-024

Rev. 0 | Page 12 of 44

ADV212

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EXTERNAL DMA MODE—FIFO READ, BURST MODE

Table 9.

Parameter Mnemonic Min Typ Max Unit

DREQ Pulse Width1 DREQ
RD to DREQ Deassert (DR × PULS = 0)

DACK to RD Setup

RD to Data Valid

t

DREQ

t

DACK

t

RD

PULSE

2.5 JCLK 3.5 × JCLK + 7.5 ns

RTN

0 ns

SU

2.5 9.7 ns

Data Hold tHD 2.5 ns
RD Assert Pulse Width

RD Deassert Pulse Width
RD Deassert to Next DREQ

RD Deassert to DACK Deassert

1

Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.

2

For a definition of JCLK, see Figure 32.

RD

LO

RD

HI

t

2.5 JCLK 3.5 × JCLK + 7.5 ns

DREQ

WAIT

t

RD_DACK

t

DREQPULSE

DREQ

DACK

2

1 JCLK

15 JCLK ns

1.5 JCLK ns

1.5 JCLK ns

0 ns

t

DREQWAIT

t

RD_DACK

HDAT

DREQ

DACK

HDAT

DREQ

DACK

RD

RD

t

DACKSU

t

HD

0 1 13 14 15

t

RD

Figure 16. Burst Read Cycle for

(EMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0

t

DREQRTN

t

DACKSU

t

HD

0 1 13 14 15

t

RD

Figure 17. Burst Read Cycle for

(EMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)

t

DREQRTN

t

DACKSU

DREQ

DREQ

RD

LO

DACK

/

DMA Mode for Assigned DMA Channel

RD

LO

DACK

/

DMA Mode for Assigned DMA Channel

RD

HI

t

RD_DACK

RD

t

RD_DACK

HI

t

DREQWAIT

t

DREQWAIT

06389-025

06389-026

RDFB

t

HD

HDAT

0 1 13 14 15

t

RD

RD

Figure 18. Burst Read Cycle for Fly-By DMA Mode

Rev. 0 | Page 13 of 44

06389-027

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STREAMING MODE (JDATA)—FIFO READ/WRITE

Table 10.

Parameter Mnemonic Min Typ Max Unit

MCLK to JDATA Valid JDATATD 1.5 JCLK1 2.5 × JCLK + 9.5 ns
MCLK to VALID Assert/Deassert VALIDTD 1.5 JCLK 2.5 × JCLK + 8.0 ns
HOLD Setup to Rising MCLK HOLDSU 3 ns
HOLD Hold from Rising MCLK HOLDHD 3 ns
JDATA Setup to Rising MCLK JDATASU 3 ns
JDATA Hold from Rising MCLK JDATAHD 3 ns

1

For a definition of JCLK, see Figure 32.

MCLK

JDATA

JDATA

HD

SU

JDAT

VALID

JDATA

VALID

TD

TD

HOLD

HD

06389-028

HOLD

HOLD

SU

Figure 19. Streaming Mode Timing—Encode Mode JDATA Output

MCLK

JDATA

HD

HOLD

HOLD

SU

HD

06389-029

JDAT

VALID

HOLD

JDATA

VALID

SU

TD

Figure 20. Streaming Mode Timing—Decode Mode JDATA Input

Rev. 0 | Page 14 of 44

ADV212

V

V

C

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VDATA MODE TIMING

Table 11.

Parameter Mnemonic Min Typ Max Unit

VCLK to VDATA Valid Delay (VDATA Output) VDATATD 12 ns
VDATA Setup to Rising VCLK (VDATA Input) VDATASU 4 ns
VDATA Hold from Rising VCLK (VDATA Input) VDATAHD 4 ns
HSYNC Setup to Rising VCLK HSYNCSU 3 ns
HSYNC Hold from Rising VCLK HSYNC
VCLK to HSYNC Valid Delay HSYNCTD 12 ns
VSYNC Setup to Rising VCLK VSYNC
VSYNC Hold from Rising VCLK VSYNCHD 4 ns
VCLK to VSYNC Valid Delay VSYNCTD 12 ns
FIELD Setup to Rising VCLK FIELD
FIELD Hold from Rising VCLK FIELDHD 3 ns
VCLK to FIELD Valid FIELDTD 12
Decode Slave Data Sync Delay

SYNC DELAY 8

(HSYNC Low to First 0xFF of EAV/SAV Code)

Decode Slave Data Sync Delay

10

(HSYNC Low to First Data for HVF Mode)

1

The sync delay value varies according to the application. Refer to the ADV212 User Guide for more information.

4 ns

HD

3 ns

SU

4 ns

SU

1

VCLK cycles

1

VCLK cycles

HSYNC

DATA (IN)

VCLK

SYN

FIELD

VDATA (IN)

VCLK

VCLK

VDATA

SU

Cr Y Cb YFF EAV FF SAV Cb Y Cr

VDATA

HD

00 00 00 00

Figure 21. Encode Video Mode Timing—CCIR 656 Mode

HSYNC

SU

Cb YCbY Cr Y

Cr Y

HSYNC

HD

Figure 22. Encode Video Mode Timing—HVF Mode (HSYNC Timing)

(HSYNC Programmed for Negative Polarity)

VSYNC

HD

FIELD

HD

FIELD

VSYNC

SU

SU

Figure 23. Encode Video Mode Timing—HVF Mode (VSYNC and FIELD Timing)

(VSYNC and FIELD Programmed for Negative Polarity)

06389-091

6389-092

06389-093

Rev. 0 | Page 15 of 44

ADV212

V

V

www.BDTIC.com/ADI

VCLK

VDATA

TD

DATA (OUT)

HSYNC (IN)

VSYNC (IN)

FIELD (IN)

VCLK

DATA (OUT)

HSYNC (IN)

VSYNC (IN)

FIELD (IN)

VDATA

FIELD

SU

VSYNC

00 00

HSYNC

SU

HD

VSYNC

SU

SYNC DELAY

HSYNC

HD

YCbEAVFF

06389-094

Figure 24. Decode Video Mode Timing—CCIR 656 Mode, Decode Slave

(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)

TD

YCr YCbYCb

HSYNC

FIELD

SU

VSYNC

HD

SU

VSYNC

SU

SYNC DELAY

HSYNC

HD

06389-095

Figure 25. Decode Video Mode Timing—HVF Mode, Decode Slave

(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)

VCLK

HSYNC (OUT)

VSYNC (OUT)

FIELD (OUT)

VCLK

VDATA (OUT)

HSYNC (OUT)

VSYNC (OUT)

FIELD (OUT)

FIELD

FIELD

VDATA

TD

Cb

HSYNC

VSYNC

TD

TD

FF

TD

00

00

SAV

Cb

CrVDATA (OUT)

Y

06389-096

Figure 26. Decode Video Mode Timing—CCIR 656 Mode, Decode Master

(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)

VDATA

TD

Cb Y

VSYNC

TD

TD

Cr Y Cb Y

Cb Y Cr

06389-097

Figure 27. Decode Video Mode Timing—HVF Mode, Decode Master

(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)

Rev. 0 | Page 16 of 44

ADV212

www.BDTIC.com/ADI

RAW PIXEL MODE TIMING

Table 12.

Parameter Mnemonic Min Typ Max Unit

VCLK to PIXELDATA Valid Delay (PIXELDATA Output) VDATATD 12 ns
PIXELDATA Setup to Rising VCLK (PIXELDATA Input) VDATASU 4 ns
PIXELDATA Hold from Rising VCLK (PIXELDATA Input) VDATAHD 4 ns
VCLK to VRDY Valid Delay VRDY
VFRM Setup to Rising VCLK (VFRAME Input) VFRMSU 3 ns
VFRM Hold from Rising VCLK (VFRAME Input) VFRMHD 4 ns
VCLK to VFRM Valid Delay (VFRAME Output) VFRM
VSTRB Setup to Rising VCLK VSTRB
VSTRB Hold from Rising VCLK VSTRBHD 3 ns

VCLK

VDATA

VDATA

SU

HD

12 ns

TD

12 ns

TD

4 ns

SU

PIXEL DATA (IN)

VFRM (IN)

VRDY (OUT)

VSTRB (IN)

VCLK

PIXELDATA (OUT)

VFRM (OUT )

VRDY (OUT)

VSTRB

VSTRB

PIXEL 1 PIXEL 2 PIXEL 3

VFRM

SU

VFRM

HD

VRDY

TD

VSTRB

VSTRB

HD

HD

SU

RAW PIXEL MODE—ENCO DE

VDATA

TD

PIXEL 1 PIXEL 2

VFRM

TD

VRDY

TD

SU

PIXEL 3

VSTRB (IN)

RAW PIXEL MODE—DECODE

Figure 28. Raw Pixel Modes

Rev. 0 | Page 17 of 44

06389-031

ADV212

www.BDTIC.com/ADI

JTAG TIMING

Table 13.

Parameter Mnemonic Min Typ Max Unit

TCK Period TCK 134 ns
TDI or TMS Setup Time TDISU 4.0 ns
TDI or TMS Hold Time TDIHD 4.0 ns
TDO Hold Time TDOHD 0.0 ns
TDO Valid TDO
TRST Hold Time TRSTHD 4.0 ns
TRST Setup Time TRSTSU 4.0 ns
TRST Pulse Width Low TRSTLO 4 TCK cycles

TCK

TDO

TDI

TMS

TRST

SU

TRST

10.0 ns

VALI D

TDO

TDI

TDI

SU

TRST

Figure 29. JTAG Timing

VALID

HD

HD

TDO

HD

06389-032

Rev. 0 | Page 18 of 44

ADV212

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 14.

Parameter Rating

VDD − Supply Voltage, Core −0.3 V to +1.65 V
IOVDD − Supply Voltage,

Input/Output
Storage Temperature [TS] −65°C to +150°C
Reflow Soldering

Pb-Free, 121-Ball 260°C [20 sec to 40 sec]

Pb-Free, 144-Ball 260°C [20 sec to 40 sec]

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−0.3 V to 3.63 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 15. Thermal Resistance

Package Type θJA θ

144-Ball ADV212BBCZ 22.5 3.8 °C/W
121-Ball ADV212BBCZ 32.8 7.92 °C/W

Unit

JC

ESD CAUTION

Rev. 0 | Page 19 of 44

ADV212

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

10 876

BOTTOM VIEW

(Not to S cale)

2195411

3

A
B
C
D
E
F
G
H
J
K

L

Figure 30.121-Ball Pin Configuration

6389-035

121110 876

9

BOTTOM VIEW

(Not to S cale)

Figure 31. 144-Ball Pin Configuration

4

321

5

A
B
C
D
E
F
G
H
J
K
L
M

06389-036

Rev. 0 | Page 20 of 44

ADV212

www.BDTIC.com/ADI

Table 16. Pin Function Descriptions

121-Ball Package 144-Ball Package

Pins

Pin No. Location Pin No. Location Mnemonic

119 L9 132 L12 MCLK 1 I System Input Clock. See the PLL section.
117 L7 131 L11

37 to 34,
27 to 25,
16, 15, 24,
14 to 12,
2, 6, 5

88, 107,
87, 97

96 J8 95 H11

95 J7 94 H10

86 H9 84 G12

85 H8 83 G11

76 G10 82 G10

D4 to D1,
C5 to C3,
B5, B4, C2,
B3 to B1,
A2, A6, A5

H11, K8,
H10, J9

64, 49 to 51,
37 to 39, 25
to 27, 13 to
15, 2 to 4

108 to 106,
96

F4, E1 to E3,
D1 to D3,
C1 to C3,
B1 to B3,
A2 to A4

J12, J11,
J10, H12

RESET

HDATA
[15:0]

ADDR [3:0]

CS

1

WE

2

RDFB

1

RD

3

WEFB

ACK

IRQ

Used Type Description

1 I

16 I/O

Reset. Causes the ADV212 to immediately reset.
CS, RD, WE, DACK0, DACK1, DREQ0, and DREQ1
must be held high when a RESET

Host Data Bus. With HDATA [23:16],
HDATA [27:24], and HDATA [31:28], these pins
make up the 32-bit wide host data bus. The
async host interface is interfaced together
with ADDR[3:0], CS

Unused HDATA pins should be pulled down
via a 10 kΩ resistor.

, WE, RD, and ACK.

is applied.

4 I Address Bus for the Host Interface.

1 I

1 I Write Enable Used with the Host Interface.

1 I Read Enable Used with the Host Interface.

1 O

1 O

Chip Select. This signal is used to qualify
addressed read and write access to the
ADV212 using the host interface.

Read Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of WE
activates the HDATA bus, even if the DMA
channels are disabled.

Write Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of RD and DACK low
activates the HDATA bus, even if the DMA
channels are disabled.

Acknowledge. Used for direct register accesses.
This signal indicates that the last register access
was successful. Due to synchronization issues,
control and status register accesses might incur
an additional delay; therefore, the host software
should wait for acknowledgment from the
ADV212 before attempting another register
access.

Accesses to the FIFOs (external DMA modes),
on the other hand, are guaranteed to occur
immediately, provided that space is available;
therefore, the host software does not need to
wait for ACK
access, provided that the timing constraints
are observed.

If ACK
should be connected to a pull-up resistor (10 kΩ)

and the PLL_HI register, Bit 4, must be set to 1.
Interrupt. This pin indicates that the ADV212

requires the attention of the host processor.
This pin can be programmed to indicate the
status of the internal interrupt conditions
within the ADV212. The interrupt sources are
enabled via the bits in register EIRQIE.

before attempting another register

is shared with more than one device, ACK

and DACK low

Rev. 0 | Page 21 of 44

ADV212

www.BDTIC.com/ADI

121-Ball Package 144-Ball Package

Pins

Pin No. Location Pin No. Location Mnemonic

63 F8 72 F12

CFG1 I

64 F9 71 F11

65 F10 70 F10

CFG2 I

75 G9 69 F9

90 to 92, 78 J2 to J4, H1 111,97 to 99 K3, J1 to J3

JDATA [7:4] I/O JDATA Bus (JDATA Mode).
79 to 81, 70 H2 to H4, G4 100, 85 to 87 J4, H1 to H3

JDATA [3:0] I/O JDATA Bus (JDATA Mode).

DREQ0

FSRQ0

VALID

DACK0

HOLD

FCS0

DREQ1

FSRQ1

DACK1

FCS1

HDATA
[31:28]

HDATA
[27:24]

Used

1 O

O

O

1 I

I

I

1 O

O

1 I

I

4 I/O Host Expansion Bus.

4 I/O Host Expansion Bus.

Type Description

Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 0.

FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 0 (asynchronous mode).

Valid Indication for JDATA Input/Output Stream.
Polarity of this pin is programmable in the
EDMOD0 register. VALID is always an output.

Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.

Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ0
acknowledged and that the data transfer can
proceed. This pin must be held high at all
times if the DMA interface is not used, even if
the DMA channels are disabled.

External Hold Indication for JDATA Input/Output
Stream. Polarity is programmable in the
EDMOD0 register. This pin is always an input.

FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 0
(asynchronous mode).

Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 1.

FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 1 (asynchronous mode).

Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.

Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ1
acknowledged and data transfer can proceed.
This pin must be held high at all times unless a
DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA
interface is not used, even if the DMA channels
are disabled.

FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 1
(asynchronous mode).

) has been

) has been

Rev. 0 | Page 22 of 44

ADV212

www.BDTIC.com/ADI

121-Ball Package 144-Ball Package

Pins

Pin No. Location Pin No. Location Mnemonic

69, 68,
59, 58

57, 46 to 48

112 L2 134 M2 SCOMM7 8 I/O

113 L3 135 M3 SCOMM6 I/O

114 L4 136 M4 SCOMM5 I/O

100 K1 121 L1 SCOMM4 O

101 K2 122 L2 SCOMM3 I

115 L5 123 L3 SCOMM2 O

103 K4 109 K1 SCOMM1 I

102 K3 110 K2 SCOMM0 O

53 E9 60 E12 VCLK 1 I

44, 43, 29,
31, 32, 18 to
20, 22, 21, 7,
10

41 D8 58 E10 VSYNC 1 I/O Vertical Sync for Video Mode.
VFRM

42 D9 59 E11 HSYNC 1 I/O Horizontal Sync for Video Mode.
VRDY O Raw Pixel Mode Ready Signal.
54 E10 57 E9 FIELD 1 I/O Field Sync for Video Mode.
VSTRB I Raw Pixel Mode Transfer Strobe.
94 J6 120 K12 TCK 1 I

108 K9 119 K11 TRS 1 I

G3, G2,
F4, F3

F2, E2, E3,
E4

D11, D10,
C7, C9, C10,
B7, B8, B9,
B11, B10,
A7, A10

88,73 to 75 H4, G1 to G3

76, 61 to 63 G4, F1 to F3

46 to 48,
34 to 36,
22 to 24,
9 to 11

D10 to D12,
C10 to C12,
B10 to B12,
A9 to A11

HDATA
[23:20]

HDATA
[19:16]

VDATA
[15:12]

VDATA
[11:0]

Used

4 I/O Host Expansion Bus.

4 I/O Host Expansion Bus.

I/O

12 I/O

Type Description

Video Data. Only used for raw pixel video
mode. Unused pins should be pulled down via
a 10 kΩ resistor.

Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.

Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.

Serial Communication. This pin must be used
in multiple chip mode to align the outputs of
two or more ADV212s. For details, see the
Applications section and the AN-796

Applic

ation Note. When not used, this pin

should be tied low via a 10 kΩ resistor.
LCODE Output in Encode Mode. When LCODE

is enabled, the output on this pin indicates on
a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit
interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled
by default.

Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.

Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.

Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.

Serial Communication. This pin should be tied
low via a10 kΩ resistor.

Video Data Clock. This pin must be supplied if
video data is input/output on the VDATA bus.

Video Data. Unused pins should be pulled
down via a 10 kΩ resistor.

Raw Pixel Mode Framing Signal. When this pin
is asserted high, it indicates the first sample of
a tile.

JTAG Clock. If not used, this pin should be
connected to ground via a pull-down resistor.

JTAG Reset. If the JTAG is used, this pin must
be toggled low to high. If JTAG is not used, this
pin must be held low.

Rev. 0 | Page 23 of 44

ADV212

www.BDTIC.com/ADI

121-Ball Package 144-Ball Package

Pins

Pin No. Location Pin No. Location Mnemonic

98 J10 118 K10 TMS 1 I

116 L6 141 M9 TDI 1 I

109 K10 130 L10 TDO 1 O

3, 8, 40, 84,
120

1, 4, 9,11,
23, 33, 39,
45, 49 to 51,
55, 56, 60 to
62, 66, 67,
71 to 73, 77,
83, 89,99,
110, 111,
118, 121

17, 28, 30,
38, 52, 74,
82, 93, 104
to 106

1

In fly-by mode DMA, the function of the RD and WE signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV212

with the use of a single strobe.

2

In encode mode with fly-by DMA, the host can use the

3

In decode mode with fly-by DMA, the host can use the

A3, A8, D7,
H7, L10

A1, A4, A9,
A11, C1,
C11, D6, E1,
E5 to E7,
E11, F1, F5
to F7, F11,
G1, G5 to
G7, G11, H6,
J1, J11, K11,
L1, L8, L11

B6, C6, C8,
D5, E8, G8,
H5, J5, K5 to
K7

18, 19, 30,
31, 42, 43,
102, 103,
114, 115,
126, 127,
142

1, 5 to 8, 12,
17, 20, 29,
32, 41, 44,
52 to 56, 65
to 68, 77 to
81, 89 to 93,
101, 104,
105, 113,
116, 125,
128, 133,
137 to 140,
143, 144

16, 21, 28,
33, 40, 45,
112, 117,
124, 129

B6, B7, C6,
C7, D6, D7,
J6, J7, K6,
K7, L6, L7,
M10

A1, A5 to
A8, A12, B5,
B8, C5, C8,
D5, D8, E4
to E8, F5 to
F8, G5 to
G9, H5 to
H9, J5, J8,
J9, K5, K8,
L5, L8, M1,
M5 to M8,
M11, M12

B4, B9, C4,
C9, D4, D9,
K4, K9, L4,
L9

RDFB

signal (WE pin) to simultaneously read from the ADV212 and write to an external device like memory.

WEFB

signal (RD pin) to simultaneously read from the external device and write to the ADV212.

VDD V Positive Supply for Core.

DGND GND Ground.

IOVDD V Positive Supply for Input/Output.

Used

Type Description

JTAG Mode Select. If JTAG is used, connect
10 kΩ pull-up resistor to this pin. If not used,
this pin should be connected to ground via a
pull-down resistor.

JTAG Serial Data Input. If JTAG is used, connect
a 10 kΩ pull-up resistor to this pin. If JTAG is
not used, this pin should be connected to
ground via a pull-down resistor.

JTAG Serial Data Output. If this pin is not used,
do not connect it.

Rev. 0 | Page 24 of 44

ADV212

www.BDTIC.com/ADI

THEORY OF OPERATION

The input video or pixel data is passed on to the ADV212’s pixel
interface, and samples are deinterleaved and passed on to the
wavelet engine, which decomposes each tile or frame into
subbands using the 5/3 or 9/7 filters. The resultant wavelet
coefficients are then written to the internal memory. The
entropy codecs code the image data so that it conforms to the
JPEG 2000 standard. An internal DMA provides high
bandwidth memory-to-memory transfers, as well as high
performance transfers between functional blocks and memory.

WAVELET ENGINE

The ADV212 provides a dedicated wavelet transform processor
based on the Analog Devices proven and patented SURF
technology. This processor can perform up to six wavelet
decomposition levels on a tile. In encode mode, the wavelet
transform processor takes in uncompressed samples, performs
the wavelet transform and quantization, and writes the wavelet
coefficients in all frequency subbands to the internal memory.
Each of these subbands is further broken down into code
blocks. The code-block dimensions can be user defined and are
used by the wavelet transform processor to organize the wavelet
coefficients into code blocks when writing to the internal
memory. Each completed code block is then entropy coded by
one of the entropy codecs.

In decode mode, wavelet coefficients are read from internal
memory and recomposed into uncompressed samples.

ENTROPY CODECS

The entropy codec block performs context modeling and
arithmetic coding on a code block of the wavelet coefficients.
Additionally, this block also performs the distortion metric
calculations during compression that are required for optimal
rate and distortion performance. Because the entropy coding
process is the most computationally intensive operation in the
JPEG 2000 compression process, three dedicated hardware
entropy codecs are provided on the ADV212.

EMBEDDED PROCESSOR SYSTEM

The ADV212 incorporates an embedded 32-bit RISC processor.
This processor is used for configuration, control, and manage­ment of the dedicated hardware functions, as well as for parsing
and generation of the JPEG 2000 code stream. The processor
system includes memory for both the program and data
memory, the interrupt controller, the standard bus interfaces,
and other hardware functions such as timers and counters.

MEMORY SYSTEM

The main function of the memory system is to manage wavelet
coefficient data, interim code-block attribute data, and
temporary workspace for creating, parsing, and storing the
JPEG 2000 code stream. The memory system can also be used
for the program and data memory for the embedded processor.

INTERNAL DMA ENGINE

The internal DMA engine provides high bandwidth memory­to-memory transfers, as well as high performance transfers
between memory and functional blocks. This function is critical
for high speed generation and parsing of the code stream.

Rev. 0 | Page 25 of 44

ADV212

www.BDTIC.com/ADI

ADV212 INTERFACE

There are several possible modes to interface to the ADV212 using
the VDATA bus and t he HDATA bus or the HDATA bus alone.

VIDEO INTERFACE (VDATA BUS)

The video interface can be used in applications in which
uncompressed pixel data is on a separate bus from compressed
data. For example, it is possible to use the VDATA bus to input
uncompressed video while using the HDATA bus to output the
compressed data. This interface is ideal for applications
requiring very high throughput, such as live video capture.

Optionally, the ADV212 interlaces ITU-R BT.656 resolution
video on the fly prior to wavelet processing, which yields
significantly better compression performance for temporally
coherent frame-based video sources. Additionally, high
definition digital video such as SMPTE 274M (1080i) is
supported using two or more ADV212 devices.

The video interface can support video data or still image data
input/output in 8-/10-/12-bit formats, in YCbCr format, or in
single input mode. YCbCr data must be in 4:2:2 format.

Video data can be input/output in several different modes on
the VDATA bus, as described in Table 17. In all these modes,
the pixel clock must be input on the VCLK pin.

Table 17. Video Input/Output Modes

Mode Description

EAV/SAV

HVF

Raw Video

Accepts video with embedded EAV/SAV codes, where
the YCbCr data is interleaved onto a single bus.

Accepts video data accompanied with separate H,
V, and F signals, where YCbCr data is interleaved
onto a single bus.

Used for still picture data and nonstandard video.
VFRM, VSTRB, and VRDY are used to program the
dimensions of the image.

HOST INTERFACE (HDATA BUS)

The ADV212 can connect directly to a wide variety of host
processors and ASICs using an asynchronous SRAM-style
interface, DMA accesses, or streaming mode (JDATA) interface.
The ADV212 supports 16- and 32-bit buses for control and
8-/16-/32-bit buses for data transfer.

The control and data channel bus widths can be specified
independently, which allows the ADV212 to support
applications that require control and data buses of different
widths.

The host interface is used for configuration, control, and status
functions, as well as for transferring compressed data streams. It
can be used for uncompressed data transfers in certain modes.
The host interface can be shared by as many as three concurrent
data streams in addition to control and status communications.
The data streams are

• Uncompressed tile data (for example, still image data)

• Fully encoded JPEG 2000 code stream (or unpackaged

code blocks)

• Code-block attributes

The ADV212 uses big endian byte alignment for 16- and 32-bit
transfers. All data is left-justified (MSB).

Pixel Input on the Host Interface

Pixel input on the host interface supports 8-/10-/12-/14-/16-bit
raw pixel data formats. It can be used for pixel (still image)
input/output or compressed video output. Because there are no
timing codes or sync signals associated with the input data on
the host interface, dimension registers and internal counters are
used and must be programmed to indicate the start and end of
the frame. Refer to the
information about using the ADV212 in this mode.

ADV202 in HIPI Mode te

chnical note for

Host Bus Configuration

For maximum flexibility, the host interface provides several
configurations to meet particular system requirements. The
default bus mode uses the same pins to transfer control, status,
and data to and from the ADV212. In this mode, the ADV212
can support 16- and 32-bit control transfers and 8-/16-/32-bit
data transfers. The size of these buses can be selected
independently, allowing, for example, a 16-bit microcontroller
to configure and control the ADV212 while still providing
32-bit data transfers to an ASIC or external memory system.

DIRECT AND INDIRECT REGISTERS

To minimize pin count and cost, the number of address pins
is limited to four, which yields a total direct address space of
16 locations. These locations are most commonly used by the
external controller and are, therefore, accessible directly. All
other registers in the ADV212 can be accessed indirectly
through the IADDR and IDATA registers.

Rev. 0 | Page 26 of 44

ADV212

www.BDTIC.com/ADI

CONTROL ACCESS REGISTERS

With the exception of the indirect address and data registers
(IADDR and IDATA), all control/status registers in the
ADV212 are 16 bits wide and are half-word (16-bit) addressable
only. When 32-bit host mode is enabled, the upper 16 bits of the
HDATA bus are ignored on writes and return all zeros on reads
of 16-bit registers.

PIN CONFIGURATION AND BUS SIZES/MODES

The ADV212 provides a wide variety of control and data
configurations, which allows it to be used in many applications
with little or no glue logic. The modes described in this section
are configured using the BUSMODE register. In this section,
host refers to normal addressed accesses (
and data refers to external DMA accesses (

CS

/RD/WE/ADDR)

DREQ

DACK

/

).

32-Bit Host/32-Bit Data

In this mode, the HDATA<31:0> pins provide full 32-bit wide
data access to PIXEL, CODE, ATTR FIFOs.

16-Bit Host/32-Bit Data

This mode allows a 16-bit host to configure and communicate
with the ADV212 while allowing 32-bit accesses to the PIXEL,
CODE, ATTR FIFOs using the external DMA capability.

All addressed host accesses are 16 bits and, therefore, use only
the HDATA<15:0> pins. The HDATA<31:16> pins provide the
additional 16 bits necessary to support the 32-bit external DMA
transfers to and from the FIFOs only.

16-Bit Host/16-Bit Data

This mode uses 16-bit transfers if used for host or external
DMA data transfers.

16-Bit Host/8-Bit Data (JDATA Bus Mode)

This mode provides separate data input/output and host
control interface pins. Host control accesses are 16 bits and use
HDATA<15:0>, whereas the dedicated data bus uses JDATA<7:0>.

JDATA uses a valid/hold synchronous transfer protocol. The
direction of the JDATA bus is determined by the mode of the
ADV212. If the ADV212 is encoding (compression),
JDATA<7:0> is an output. If the ADV212 is decoding
(decompression), JDATA<7:0> is an input. Host control
accesses remain asynchronous. See also JDATA section below.

STAGE REGISTER

Because the ADV212 contains both 16-bit and 32-bit registers
and its internal memory is mapped as 32-bit data, a mechanism

has been provided to allow 16-bit hosts to access these registers
and memory locations using the stage register (STAGE). STAGE
is accessed as a 16-bit register using HDATA [15:0]. Prior to
writing to the desired register, the stage register must be written
with the upper (most significant) half-word.

When the host subsequently writes the lower half-word to the
desired control register, HDATA is combined with the
previously staged value to create the required 32-bit value that is
written. When a register is read, the upper (most significant)
half-word is returned immediately on HDATA and the lower
half-word can be retrieved by reading the stage register on a
subsequent access. For details on using the stage register, see the

ADV212 User’s Guide.

ote that the stage register does not apply to the three data

N
channels (PIXEL, CODE, ATTR). These channels are always
accessed at the specified data width and do not require the use
of the stage register.

JDATA MODE

JDATA mode is typically used only when the dedicated video
interface (VDATA) is also enabled. This mode allows code
stream data (compressed data compliant with JPEG 2000) to be
input or output on a single dedicated 8-bit bus (JDATA<7:0>).
The bus is always an output during compression operations,
and is an input during decompression.

A 2-pin handshake is used to transfer data over this
synchronous interface. VALID is used to indicate that the
ADV212 is ready to provide or accept data and is always an
output. HOLD is always an input and is asserted by the host if it
cannot accept/provide data. For example, JDATA mode allows
real-time applications, in which pixel data is input over the
VDATA bus while the compressed data stream is output over
the JDATA bus.

EXTERNAL DMA ENGINE

The external DMA interface is provided to enable high
bandwidth data input/output between an external DMA
controller and the ADV212 data FIFOs. Two independent DMA
channels can each be assigned to any one of the three data
stream FIFOs (PIXEL, CODE, ATTR).

The controller supports asynchronous DMA using a

DREQ

data-request/data-acknowledge (
either single or burst access modes. Additional functionality is
provided for single address compatibility (fly-by) and dedicated
chip select (DCS) modes.

DACK

/

) protocol in

Rev. 0 | Page 27 of 44

ADV212

www.BDTIC.com/ADI

INTERNAL REGISTERS

This section describes the internal registers of the ADV212.

DIRECT REGISTERS

The ADV212 has 16 direct registers, as listed in Table 18. The
direct registers are accessed over the ADDR [3:0], HDATA [31:0],
CS

, RD, WE, and

ACK

pins.

The host must first initialize the direct registers before any
application-specific operation can be implemented.

For additional information on accessing and configuring these
registers, see the

ADV212 User’s Guide.

Table 18. Direct

Address Name Description

0x00 PIXEL Pixel FIFO access register
0x01 CODE Compressed code stream access register
0x02 ATTR Attribute FIFO access register
0x03 Reserved Reserved
0x04 CMDSTA Command stack
0x05 EIRQIE External interrupt enabled
0x06 EIRQFLG External interrupt flags
0x07 SWFLAG Software flag register
0x08 BUSMODE Bus mode configuration register
0x09 MMODE Miscellaneous mode register
0x0A STAGE Staging register
0x0B IADDR Indirect address register
0x0C IDATA Indirect data register
0x0D BOOT Boot mode register
0x0E PLL_HI PLL control register—high byte
0x0F PLL_LO PLL control register—low byte

Registers

Rev. 0 | Page 28 of 44

ADV212

www.BDTIC.com/ADI

INDIRECT REGISTERS

In certain modes, such as custom-specific input format or HIPI
mode, indirect registers must be accessed by the user through
the use of the IADDR and IDATA registers. The indirect
register address space starts at Internal Address 0xFFFF0000.

Table

19. Indirect Registers

Address Name Description

0xFFFF0400 PMODE1 Pixel/video format
0xFFFF0404 COMP_CNT_STATUS Horizontal count
0xFFFF0408 LINE_CNT_STATUS Vertical count
0xFFFF040C XTOT Total samples per line
0xFFFF0410 YTOT Total lines per frame
0xFFFF0414 F0_START Start line of Field 0 [F0]
0xFFFF0418 F1_START Start line of Field 1 [F1]
0xFFFF041C V0_START Start of active video Field 0 [F0]
0xFFFF0420 V1_START Start of active video Field 1 [F1]
0xFFFF0424 V0_END End of active video Field 0 [F0]
0xFFFF0428 V1_END End of active video Field 1 [F1]
0xFFFF042C PIXEL_START Horizontal start of active video
0xFFFF0430 PIXEL_END Horizontal end of active video
0xFFFF0440 MS_CNT_DEL Master/slave delay
0xFFFF0444 Reserved Reserved
0xFFFF0448 PMODE2 Pixel Mode 2
0xFFFF044C VMODE Video mode
0xFFFF1408 EDMOD0 External DMA Mode Register 0
0xFFFF140C EDMOD1 External DMA Mode Register 1
0xFFFF1410 FFTHRP FIFO threshold for pixel FIFO
0xFFFF1414 Reserved Reserved
0xFFFF1418 Reserved Reserved
0xFFFF141C FFTHRC FIFO threshold for code FIFO
0xFFFF1420 FFTHRA FIFO threshold for ATTR FIFO
0xFFFF1424 to 0xFFFF14FC Reserved Reserved

Both 32-bit and 16-bit hosts can access the indirect registers.
32-bit hosts use the IADDR and IDATA registers, and the 16-bit
hosts use the IADDR, the IDATA, and the stage register.

For additional information on accessing and configuring these
registers, see the

ADV212 User’s Guide.

Rev. 0 | Page 29 of 44

ADV212

www.BDTIC.com/ADI

PLL

The ADV212 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 μs before reading from or writing
to another register. If this delay is not implemented, erratic
behavior might result.

MCLK is the input clock to the ADV212 PLL and is used to
generate the internal JCLK (JPEG 2000 processor clock) and
HCLK (embedded CPU clock).

The PLL can be programmed to have any possible final
multiplier value as long as

• JCLK > 50 MHz and < 150 MHz (144-pin version).

• JCLK > 50 MHz and < 115 MHz (121-pin version).

• HCLK < 81 MHz (121-pin version), or HCLK < 108 MHz

(144-pin version).

• JCLK ≥ 2 × VCLK for single-component input.

• JCLK ≥ 2 × VCLK for YCbCr [4:2:2] input.

• In JDATA mode (JDATA), JCLK must be 4 × MCLK

or higher.

• The maximum burst frequency for external DMA modes is

≤ 0.36 JCLK.

• For MCLK frequencies greater than 50 MHz, the input clock

divider must be enabled, that is, IPD must be set to 1.

• IPD cannot be enabled for MCLK frequencies below 20 MHz.

• Deinterlace modes require JCLK ≥ 4 × MCLK.

• It is not recommended to use an LLC output from a video

decoder as a clock source for MCLK.

To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR 656
input. The PLL circuit is recommended to have a multiplier of 3.
This sets JCLK and HCLK to 81 MHz.

MCLK

IPD

÷2

Figure 32. PLL Architecture and Control Functions

PHASE

DETECT

LFB

BYPASS

LPF

÷PLLMULT÷2

VCO

÷2

÷2

HCLKD

JCLK

HCLK

÷2

06389-009

Table 20. Recommended PLL Register Settings

IPD LFB PLLMULT HCLKD HCLK JCLK

0 0 N 0 N × MCLK N × MCLK
0 0 N 1 N × MCLK/2 N × MCLK
0 1 N 0 2 × N × MCLK 2 × N × MCLK
0 1 N 1 N × MCLK 2 × N × MCLK
1 0 N 0 N × MCLK/2 N × MCLK/2
1 0 N 1 N × MCLK/4 N × MCLK/2
1 1 N 0 N × MCLK N × MCLK
1 1 N 1 N × MCLK/2 N × MCLK

Table 21. Recommended Values for PLL_HI and PLL_LO Registers

Video Standard CLKIN Frequency on MCLK PLL_HI PLL_LO

SMPTE 125M or ITU-R BT.656 (NTSC or PAL) 27 MHz 0x0008 0x0004
SMPTE 293M (525p) 27 MHz 0x0008 0x0004
ITU-R BT.1358 (625p) 27 MHz 0x0008 0x0004
SMPTE 274M (1080i) 74.25 MHz 0x0008 0x0084

Rev. 0 | Page 30 of 44

ADV212

www.BDTIC.com/ADI

HARDWARE BOOT

The boot mode can be configured via hardware using the CFG pins or via software. The first boot mode after power-up is set by the CFG pins.

Table 22. Hardware Boot Modes

Boot Mode Settings Description

Hardware Boot Mode 2 CFG<1> tied high, CFG<2> tied low

Hardware Boot Mode 4 CFG<1> tied low, CFG<2> tied high Reserved.
Hardware Boot Mode 6 CFG<1> and CFG<2> tied high Reserved.

No boot host mode. ADV212 does not boot, but all internal registers and
memory are accessible through normal host input/output operations.

Rev. 0 | Page 31 of 44

ADV212

www.BDTIC.com/ADI

VIDEO INPUT FORMATS

The ADV212 supports a wide variety of formats for
uncompressed video and still image data. The actual interface
and bus modes selected for transferring uncompressed data
dictates the allowed size of the input data and the number of
samples transferred with each access.

The host interface can support 8-/10-/12-/14-/16-bit data
formats. The video interface can support video data or still
image data input/output. Supported formats are 8-/10-/12-bit

Table 23. Maximum Pixel Data Input Rates (144-Ball Package)

Input Rate Limit
Active Resolution

Interface Compression Mode Input Format

HDATA Irreversible 8-bit data 45 130 200
Irreversible 10-bit data 45 130 200
Irreversible 12-bit data 45 130 200
Irreversible 16-bit data 45 130 200
Reversible 8-bit data 40 130 200
Reversible 10-bit data 32 130 200
Reversible 12-bit data 27 130 200
Reversible 14-bit data 23 130 200
VDATA Irreversible 8-bit data 65 130 200
Irreversible 10-bit data 65 130 200
Irreversible 12-bit data 65 130 200
Reversible 8-bit data 40 130 200
Reversible 10-bit data 32 130 200
Reversible 12-bit data 27 130 200

1

Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings.

2

Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate].

3

Maximum peak output rate; an output rate above this value is not possible.

(MSPS)1

YCbCr formats or single component format. See the

ADV212

User’s Guide for details. All formats can support less precision

than provided by specifying the actual data width/precision in
the PMODE register.

The maximum allowable data input rate is limited by using
irreversible or reversible compression modes and the data width
(or precision) of the input samples. Refer to Table 23 and
Table 25 to determine the maximum data input rate.

Approx Min Output Rate,
Compressed Data2
(Mbps)

Approx Max Output Rate,
Compressed Data3
(Mbps)

Table 24. Maximum Pixel Data Input Rates (121-Ball Package)

Input Rate Limit
Active Resolution

1

Interface Compression Mode Input Format

HDATA Irreversible 8-bit data 34 98 150
Irreversible 10-bit data 34 98 150
Irreversible 12-bit data 34 98 150
Irreversible 16-bit data 34 98 150
Reversible 8-bit data 30 98 150
Reversible 10-bit data 24 98 150
Reversible 12-bit data 20 98 150
Reversible 14-bit data 17 98 150
VDATA Irreversible 8-bit data 48 98 150
Irreversible 10-bit data 48 98 150
Irreversible 12-bit data 48 98 150
Reversible 8-bit data 30 98 150
Reversible 10-bit data 24 98 150
Reversible 12-bit data 20 98 150

1

Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings.

2

Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate].

3

Maximum peak output rate; an output rate above this value is not possible.

(MSPS)

Rev. 0 | Page 32 of 44

Approx Min Output Rate,
Compressed Data2
(Mbps)

Approx Max Output Rate,
Compressed Data3
(Mbps)

ADV212

www.BDTIC.com/ADI

Table 25. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses

Compression Mode Input Format Tile/Precinct Maximum Width

9/7i Single-component 2048
9/7i Two-component 1024 each
9/7i Three-component 1024 (Y)
5/3i Single-component 4096
5/3i Two-component 2048 (each)
5/3i Three-component 2048 (Y)
5/3r Single-component 4096
5/3r Two-component 2048
5/3r Three-component 1024

Rev. 0 | Page 33 of 44

ADV212

www.BDTIC.com/ADI

APPLICATIONS

This section describes typical video applications for the
ADV212 JPEG 2000 video processor.

ENCODE—MULTICHIP MODE

Due to the data input rate limitation (see Table 23), an 1080i
application requires at least two ADV212s to encode or decode
full-resolution 1080i video. In encode mode, the ADV212
accepts Y and CbCr data on separate buses. An encode example
is shown in Figure 33.

32-BIT HOST CPU

DATA[31:0] HDATA[31:0]

ADDR[3:0] ADDR[3:0]

CS CS

RD RD

ACK ACK

WR WE

IRQ

DREQ DREQ
DACK DACK

G I/O SCOMM[5]

ADV212_1_SLAVE

VDATA[11:2]

IRQ

VCLK

MCLK

FIELD
VSYNC
HSYNC

In decode mode, a master/slave configuration (as shown in
Figure 34) or a slave/slave configuration can be used to
synchronize the outputs of the two ADV212s. See the

A

pplication Note for details on how to configure the ADV212s

AN-796

in a multichip application.

Applications that have two separate VDATA outputs sent to an
FPGA or buffer before they are sent to an encoder do not
require synchronization at the ADV212 outputs.

74.25MHz
OSC

Y

CbCr

ADV7402

10-BIT SD/ HD

VIDEO

DECODER

LLC

Y[9:0]

C[9:0]

1080i
VIDEO IN

ADV212_2_SLAVE

VCLK

MCLK

HSYNC
VSYNC

FIELD

VDATA[11:2]

CbCr

6389-002

CS

RD

WR

ACK

IRQ

DREQ
DACK

HDATA[31:0]
ADDR[3:0]

CS
RD
WE
ACK
IRQ

DREQ
DACK
SCOMM[5]

Figure 33. Encode—Multichip Application

Rev. 0 | Page 34 of 44

ADV212

www.BDTIC.com/ADI

DECODE—MULTICHIP MASTER/SLAVE

In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM[5] pin is connected to the same GPIO on the host.

32-BIT HOST CPU

DATA[31:0] HDATA[31:0]

ADDR[3:0] ADDR[3:0]

CS CS
RD RD

WR WE

ACK ACK

IRQ

DREQ DREQ
DACK DACK

G I/O SCOMM[5]

CS
RD

WR

ACK

IRQ

DREQ
DACK

ADV212_1_MASTER

VDATA[11:2]

IRQ

ADV212_2_SLAVE

HDATA[31:0]
ADDR[3:0]

CS
RD
WE
ACK
IRQ

VDATA[11:2]

DREQ
DACK
SCOMM[5]

Figure 34. Decode—Multichip Master/Slave Application

VCLK

MCLK

FIELD

VSYNC

HSYNC

VCLK

MCLK

HSYNC

VSYNC

FIELD

In a slave/slave configuration, the common HVF for both
ADV212s is generated by an external house sync and each
SCOMM[5] is connected to the same GPIO output on the host.

SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.

74.25MHz
OSC

YY

CbCr

CbCr

ADV7321A

10-BIT SD/ HD

VIDEO

ENCODER

CLKIN

Y[9:0]

C[9:0]

1080i
VIDEO OUT

6389-003

Rev. 0 | Page 35 of 44

ADV212

www.BDTIC.com/ADI

DIGITAL STILL CAMERA/CAMCORDER

Figure 35 is a typical configuration for a digital camera or camcorder.

AD9843A

10

D[9:0]

SDATA SERIAL DAT A

SCK SERIAL CLK

SL SERIAL EN

FPGA

DATA INPUTS[9:0]

MCLK
VCLK

VFRM
VRDY
VSTRB

VDATA[15:6]PIXEL OUT[9:0]

ADV212

DATA[15:0]HDATA[15:0]
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK
IRQIRQ

16-BIT

HOST CPU

Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode

06389-004

Rev. 0 | Page 36 of 44

ADV212

www.BDTIC.com/ADI

ENCODE/DECODE SDTV VIDEO APPLICATION

Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode.

ENCODE MODE

32-BIT

HOST CPU

DECODE MODE

32-BIT

HOST CPU

HDATA[31:0]DATA[31:0]
IRQINTR
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK

HDATA[31:0]DATA[31:0]
IRQINTR
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK

ADV212

ADV212

VCLK

MCLK

MCLK

27MHz

OSC

27MHz

OSC

P[19:10]VDATA[11:2]

LLC1

ADV7301A

P[9:0]VDATA[11:2]
CLKINVCLK

ADV7189

10-BIT
VIDEO

DECODER

10-BIT
VIDEO

ENCODER

Figure 36. Encode/Decode—SDTV Video Application

VIDEO IN

VIDEO OUT

06389-005

Rev. 0 | Page 37 of 44

ADV212

www.BDTIC.com/ADI

32-BIT HOST APPLICATION

Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode.

FPGA

32-BIT

HOST CPU

DATA[31:0]

FPGA

31-BIT

HOST CPU

DATA[31:0]

DREQ0DREQ0
DACK0DACK0

HDATA[31:0]DATA[31:0]

IRQIRQ
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK

DREQ0DREQ0
DACK0DACK0

HDATA[31:0]DATA[31:0]

IRQIRQ
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK

ADV212

VDATA[11:2]

ADV212

VCLK

MCLK

MCLK

27MHz

OSC

27MHz

OSC

P[19:10]

LLC1

ADV730xA

P[9:0]VDATA[11:2]
CLKINVCLK

ADV7189

10-BIT
VIDEO

DECODER

10-BIT
VIDEO

ENCODER

VIDEO IN

ENCODE MODE

VIDEO OUT

DECODE MODE

06389-006

Figure 37. Encode/Decode 32-Bit Host Application

Rev. 0 | Page 38 of 44

ADV212

www.BDTIC.com/ADI

HIPI (HOST INTERFACE—PIXEL INTERFACE)

Figure 38 is a typical configuration using HIPI mode.

ADV212

HDATA<31>Y0/G0<MSB>
HDATA<30>Y0/G0<6>
HDATA<29>Y0/G0<5>
HDATA<28>Y0/G0<4>
HDATA<27>Y0/G0<3>
HDATA<26>Y0/G0<2>
HDATA<25>Y0/G0<1>
HDATA<24>Y0/G0<0>
HDATA<23>Cb0/G1<MSB>
HDATA<22>Cb0/G1<6>
HDATA<21>Cb0/G1<5>
HDATA<20>Cb0/G1<4>
HDATA<19>Cb0/G1<3>
HDATA<18>Cb0/G1<2>
HDATA<17>Cb0/G1<1>
HDATA<16>Cb0/G1<0>
HDATA<15>Y1/G2<MSB>
HDATA<14>Y1/G2<6>
HDATA<13>Y1/G2<5>
HDATA<12>Y1/G2<4>
HDATA<11>Y1/G2<3>
HDATA<10>Y1/G2<2>
HDATA<9>Y1/G2<1>
HDATA<8>Y1/G2<0>
HDATA<7>Cr0/G3<MSB>
HDATA<6>Cr0/G3<6>
HDATA<5>Cr0/G3<5>
HDATA<4>Cr0/G3<4>
HDATA<3>Cr0/G3<3>
HDATA<2>Cr0/G3<2>
HDATA<1>Cr0/G3<1>

32-BIT HOS T

DATA<31:0>

CS

RD RD

WR WE

ACK ACK

IRQ IRQ

DREQ DREQ0
DACK DACK0

DREQ DREQ1
DACK DACK1

74.25MHz

Figure 38. Host Interface—Pixel Interface Mode

HDATA<0>Cr0/G3<0>

CS

MCLK

COMPRESSED
DATA PATH

RAW PIXEL
DATA PATH

06389-007

Rev. 0 | Page 39 of 44

ADV212

www.BDTIC.com/ADI

JDATA INTERFACE

Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656.

FPGA

16-BIT

HOST CPU

ADV212

JDATA[7:0]
HOLD
VALID

HDATA[15:0]DATA[15:0]
IRQIRQ
ADDR[3:0]ADDR[3:0]
CSCS
RDRD
WEWE
ACKACK

HSYNC

VCLK

MCLK

YCrCb

27MHz

OSC

P[19:10]VDATA[11:2]
FIELDFIELD

VSVSYNC
HS

LLC1

ADV7189

VIDEO IN

06389-008

Figure 39. JDATA Application

Rev. 0 | Page 40 of 44

ADV212

A

R

*

A

R

*

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

12.20

12.00 SQ

11.80

BALL A1
CORNER

TOP VIEW

10.00

BSC SQ

1.00

BSC

9

1087

11

BOTTOM VIEW

1 CORNE

INDEX AREA

63

5

21

4

A
B
C
D
E
F
G
H
J
K
L

1.85

1.71

1.40

1.85

MAX

DETAIL A

DETAILA

0.50 NOM

0.30 MIN

0.70

0.60

0.50

BALL DIAMET ER

*COMPLIANT WITH JEDE C STANDARDS MO-192-ABD- 1 WITH

EXCEPTIO N TO PACKAGE HEI GHT AND THICKNES S .

SEATING
PLANE

Figure 40. 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-121-1)

Dimensions shown in millimeters

1 CORNE

13 .00

BSC SQ

BALL A1
INDICATOR

TOP VIEW

DETAIL A

11.00

BCS SQ

1.00 BSC

0.53

0.43

BALL DIAMET ER

12

0.70

0.60

0.50

11

10 876

INDEX AREA

9

5

BOTTOM VIEW

DETAILA

SEATING
PLANE

4

321

*

1.31

1.21

1.11

0.20
COPLANARITY

A
B
C
D
E
F
G
H
J
K
L
M

*

1.32

1.21

1.11

COPLANARITY

0.20 MAX

082406-A

*

COMPLIANT WITH JEDEC STANDARDS MO- 192-AAD- 1 WITH

EXCEPTION TO PACKAGE HEIGHT AND THI CKNE S S.

Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Dimensions shown in millimeters

Rev. 0 | Page 41 of 44

(BC-144-3)

021506-A

ADV212

www.BDTIC.com/ADI

ORDERING GUIDE

Temperature

Model

ADV212BBCZ-1151 −40°C to +85°C 115 MHz

ADV212BBCZRL-1151 −40°C to +85°C 115 MHz

ADV212BBCZ-1501 −40°C to +85°C 150 MHz

ADV212BBCZRL-1501 −40°C to +85°C 150 MHz

1

Z = Pb-free part.

Range

Speed
Grade Operating Voltage Package Description

1.5 V Internal,

2.5 V or 3.3 V I/O

1.5 V Internal,

2.5 V or 3.3 V I/O

1.5 V Internal,

2.5 V or 3.3 V I/O

1.5 V Internal,

2.5 V or 3.3 V I/O

121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-121-1

121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-121-1

144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-3

144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-3

Package
Option

Rev. 0 | Page 42 of 44

ADV212

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 43 of 44

ADV212

www.BDTIC.com/ADI

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06389-0-10/06(0)

Rev. 0 | Page 44 of 44