Page 1
CMOS
a
FEATURES
80 MHz Pipelined Operation
Triple 8-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
40-Pin DIP or 44-Pin PLCC Package
Plug-In Replacement for BT101
Power Dissipation: 400 mW
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Desktop Publishing
SPEED GRADES
80 MHz
50 MHz
30 MHz
GENERAL DESCRIPTION
The ADV101 is a digital-to-analog video converter on a single
monolithic chip. The part is specifically designed for high resolution color graphics and video systems. It consists of three,
high speed, 8-bit, video D/A converters (RGB); a standard TTL
input interface and high impedance, analog output, current
sources.
The ADV101 has three separate, 8-bit, pixel input ports, one
each for red, green and blue video data. Additional video input
controls on the part include sync, blank and reference white. A
single +5 V supply, an external 1.23 V reference and pixel clock
input are all that are required to make the part operational.
The ADV101 is capable of generating RGB video output signals, which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV101 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low
power dissipation. The part is packaged in both a 0.6", 40-pin
plastic DIP and a 44-pin plastic leaded (J-lead) chip carrier,
PLCC.
80 MHz, Triple 8-Bit Video DAC
ADV101*
FUNCTIONAL BLOCK DIAGRAM
V
AA
ADV101
CLOCK
PIXEL
INPUT
PORT
REF WHITE
BLANK
R0
R7
G0
G7
B0
B7
SYNC
8
8
8
GND
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 80 MHz.
2. Compatible with a wide variety of high resolution color
graphics video systems.
3. Guaranteed monotonic with a maximum differential nonlinearity of ±0.5 LSB. Integral nonlinearity is guaranteed to be
a maximum of ±1 LSB.
FS
ADJUST
RED
REGISTER
GREEN
REGISTER
BLUE
REGISTER
CONTROL
REGISTER
V
REF
REFERENCE
AMPLIFIER
8
8
8
DAC
DAC
DAC
SYNC
CONTROL
COMP
IOR
IOG
IOB
I
SYNC
*ADV is a registered trademark of Analog Devices Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
ADV101–SPECIFICA TIONS
(VAA = +5 V 6 5%; V
connected to IOG. All Specifications T
= +1.235 V; RL = 37.5 V, CL = 10 pF; R
REF
MIN
1
to T
unless otherwise noted.)
MAX
SET
Parameter All Versions Units Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits
Accuracy (Each DAC)
Integral Nonlinearity, INL ±1 LSB max
Differential Nonlinearity, DNL ±0.5 LSB max Guaranteed Monotonic
Gray Scale Error ±5 % Gray Scale max Max Gray Scale Current: IOG = (V
Max Gray Scale Current: IOR, IOB = (V
* 12,082/R
REF
REF
Coding Binary
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
INL
IN
IN
INH
2
2 V min
0.8 V max
±1 µA max VIN = 0.4 V or 2.4 V
10 pF max
ANALOG OUTPUTS
Gray Scale Current Range 15 mA min
22 mA max
Output Current
White Level Relative to Blank 17.69 mA min Typically 19.05 mA
20.40 mA max
White Level Relative to Black 16.74 mA min Typically 17.62 mA
18.50 mA max
Black Level Relative to Blank 0.95 mA min Typically 1.44 mA
1.90 mA max
Blank Level on IOR, IOB 0 µA min Typically 5 µA
50 µA max
Blank Level on IOG 6.29 mA min Typically 7.62 mA
9.5 mA max
Sync Level on IOG 0 µA min Typically 5 µA
50 µA max
LSB Size 69.1 µA typ
DAC to DAC Matching 2 % typ
Output Compliance, V
Output Impedance, R
OC
OUT
Output Capacitance, C
OUT
2
2
–1 V min
+1.4 V max
100 kΩ typ
30 pF max I
OUT
= 0 mA
VOLTAGE REFERENCE
Voltage Reference Range, V
Input Current, I
VREF
REF
1.14/1.26 V min/V max V
+10 µA typ
= 1.235 V for Specified Performance
REF
POWER REQUIREMENTS
V
AA
I
AA
5 V nom
125 mA max Typically 80 mA: 80 MHz Parts
100 mA max Typically 70 mA: 50 MHz & 35 MHz Parts
Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: f = 1 kHz, COMP = 0.1 µF
Power Dissipation 625 mW max Typically 400 mW: 80 MHz Parts
500 mW max Typically 350 mW: 50 MHz & 30 MHz Parts
= 560 V. I
SET
* 8,627/R
SYNC
) mA
SET
) mA
DYNAMIC PERFORMANCE
Glitch Impulse
DAC Noise
2, 3, 4
2, 3
50 pV secs typ
200 pV secs typ
Analog Output Skew 2 ns max Typically 1 ns
NOTES
1
Temperature Range (T
2
Sample tested at +25°C to ensure compliance.
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
4
This includes effects due to clock and data feedthrough as well as RGB analog crosstalk.
Specifications subject to change without notice.
MIN
to T
MAX
); 0°C to +70°C.
–2–
REV. B
Page 3
ADV101
TIMING CHARACTERISTICS
(VAA = +5 V 6 5%; V
1
I
connected to IOG. All Specifications T
SYNC
= +1.235 V; RL = 37.5 V, CL = 10 pF; R
REF
MIN
2
to T
unless otherwise noted.)
MAX
= 560 V.
SET
Parameter 80 MHz Version 50 MHz Version 30 MHz Version Units Conditions/Comments
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
80 50 30 MHz max Clock Rate
3 6 8 ns min Data & Control Setup Time
2 2 2 ns min Data & Control Hold Time
12.5 20 33.3 ns min Clock Cycle Time
4 7 9 ns min Clock Pulse Width High Time
4 7 9 ns min Clock Pulse Width Low Time
30 30 30 ns max Analog Output Delay
20 20 20 ns typ
t
7
3
t
8
NOTES
1
TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1.
2
Temperature range (T
3
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
3 3 3 ns max Analog Output Rise/Fall Time
12 15 15 ns typ Analog Output Transition Time
to T
MIN
): 0°C to +70°C.
MAX
CLOCK
t
3
t
4t5
t
1
DIGITAL INPUTS
(R0–R7, G0–G7, B0–B7;
SYNC, BLANK,
REF WHITE)
ANALOG OUTPUTS
(IOR, IOG, IOB, I
NOTES
1. OUTPUT DELAY (
CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. TRANSITION TIME (
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
3. OUTPUT RISE/FALL TIME (
OF FULL TRANSITION.
SYNC
)
t
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF
6
t
) MEASURED FROM THE 50% POINT OF FULL-SCALE
8
t
) MEASURED BETWEEN THE 10% AND 90% POINTS
7
DATA
Figure 1. Video Input/Output Timing
t
2
t
t
6
8
t
7
REV. B
–3–
Page 4
ADV101
WARNING!
ESD SENSITIVE DEVICE
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units
Power Supply V
AA
4.75 5.00 5.25 Volts
Ambient Operating
Temperature T
Output Load R
Reference Voltage V
ORDERING GUIDE
Package
2
Option
80 MHz 50 MHz 30 MHz
A
L
REF
0 +70 °C
37.5 Ω
1.14 1.235 1.26 Volts
1
Speed
Plastic DIP
(N-40A) ADV101KN80 ADV101KN50 ADV101KN30
3
PLCC
(P-44A) ADV101KP80 ADV101KP50 ADV101KP30
NOTES
1
All devices are specified for 0°C to +70°C operation.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier.
3
PLCC: Plastic Leaded Chip Carrier (J-lead).
ABSOLUTE MAXIMUM RATINGS
1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to V
Ambient Operating Temperature (T
Storage Temperature (T
Junction Temperature (T
) . . . . . . . . . . . . . . –65°C to +150°C
S
) . . . . . . . . . . . . . . . . . . . . +150°C
J
) . . . . . . . . 0°C to +70°C
A
+ 0.5 V
AA
Soldering Temperature (10 secs) . . . . . . . . . . . . . . . . . .300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . .220°C
IOR, IOB, IOG, I
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
to GND2 . . . . . . . . . . . . . . 0 V to V
SYNC
AA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV101 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
PLCC
B0
B2
B1
432156 44 43 42 41 40
GND
GND
FS ADJUST
1
G4
2
R7
3
R6
4
R5
5
R4
B7
6
B6
7
B5
8
B4
9
10
V
AA
11
GND
12
B0
13
B1
14
B2
15
B3
16
CLOCK
17
R0
R1
18
R2
19
R3
20 21
ADV101
TOP VIEW
(NOT TO SCALE)
DIP
G5
40
G6
39
G7
38
BLANK
37
SYNC
36
GND
35
IOB
34
IOR
33
IOG
32
31
I
30
V
GND
29
FS ADJUST
28
27
V
26
COMP
25
REF WHITE
24
G3
23
G2
22
G1
G0
SYNC
AA
REF
CLOCK
REF WHITE
COMP
B3
7
R0
8
R1
9
R2
10
R3
11
12
G0
G1
13
G2
14
G3
15
16
17
18 19 20 21 22 23 24 25
REF
V
GND
GND
ADV101
TOP VIEW
(Not to Scale)
AA
AA
V
V
I
AA
V
SYNC
V
IOG
AA
B5
B6
B4
39
B7
38
R4
37
R5
36
R6
35
R7
34
G4
33
G5
32
G6
31
G7
30
BLANK
29
SYNC
282726
IOR
IOB
GND
–4–
REV. B
Page 5
ADV101
PIN FUNCTION DESCRIPTION
Pin
Mnemonic Function
BLANK Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. The
BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are ignored.
SYNC Composite sync control input (TTL compatible). A logical zero on the SYNC input; switches off a 40 IRE cur-
rent source on the I
output. SYNC does not override any other control or data input, therefore, it should
SYNC
only be asserted during the blanking interval.
CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated TTL buffer.
REF WHITE Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB out-
puts to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7) REF WHITE is latched
on the rising edge of clock.
R0–R7, Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0–G7, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular
B0–B7 PCB power or ground plane.
IOR, IOG, IOB Red, green and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not
they are all being used.
I
SYNC
Sync current output. This high impedance current source can be directly connected to the IOG output. This allows sync information to be encoded onto the green channel. I
at logical zero. The amount of current output at I
I
(mA) = 3,455 × V
SYNC
If sync information is not required on the green channel, I
FS ADJUST Full-scale adjust control. A resistor (R
SET
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between R
and the full-scale output current on IOG (assuming I
SET
is given by:
R
(Ω) = 12,082 × V
SET
The relationship between R
and the full-scale output current on IOR and IOB is given by:
SET
IOR, IOB (mA) = 8,628 × V
COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor
must be connected between COMP and V
V
REF
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected
between V
V
AA
Analog power supply (5 V ± 5%). All VAA pins on the ADV101 must be connected.
and VAA.
REF
GND Ground. All GND pins must be connected.
BLANK signal is latched on the rising edge of CLOCK. While
SYNC is latched on the rising edge of CLOCK.
SYNC,
does not output any current while SYNC is
SYNC
should be connected to AGND.
SYNC
REF
(V)/R
while SYNC is at logical one is given by:
SYNC
(Ω)
SET
) connected between this pin and GND, controls the magnitude of the
is connected to IOG)
SYNC
(V)/IOG (mA)
REF
AA
.
REF
(V)/ R
SET
(Ω)
REV. B
–5–
Page 6
ADV101
TERMINOLOGY
Blanking Level
The level separating the
SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture.
Color Video (RGB)
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels, while a 6-bit DAC contains 64.
CIRCUIT DESCRIPTION AND OPERATION
The ADV101 contains three 8-bit D/A converters, with three
input channels, each containing an 8-bit register. Also integrated on board the part is a reference amplifier and CRT control functions
Digital Inputs
BLANK, SYNC and REF WHITE.
24-bits of pixel data (color information) R0–R7, G0–G7 and
B0–B7 are latched into the device on the rising edge of each
clock cycle. This data is presented to the three 8-bit DACs and
is then converted to three analog (RGB) output waveforms.
(See Figure 2.)
Three other digital control signals are latched to the analog
video outputs in a similar fashion.
BLANK, SYNC and REF
WHITE are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.
The
BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV101. The influence of
SYNC and BLANK on the analog video waveform is illustrated.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the SYNC signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion which may be
visually observed.
The REF WHITE control input drives the RGB video outputs
to the white level. This function could be used to overlay a cursor or crosshair onto the RGB video output.
Table I details the resultant effect on the analog outputs of
BLANK, SYNC and REF WHITE.
All these digital inputs are specified to accept TTL logic levels
Clock Input
The CLOCK input of the ADV101 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following equation.
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
Dot Rate = (Retrace Factor)
Horiz Res = Number of pixels/line
Vert Res = Number of lines/frame
Refresh Rate = Horizontal Scan Rate. This is the rate at
which the screen must be refreshed, typically 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
Retrace Factor = Total blank time factor. This takes into ac-
count that the display is blanked for a certain
fraction of the total duration of each frame
(e.g., 0.8).
CLOCK
DIGITAL INPUTS
(R0–R7, G0–G7, B0–B7;
SYNC, BLANK,
REFWHITE)
ANALOG OUTPUTS
(IOR, IOG, IOB, I )
SYNC
DATA
Figure 2. Video Data Input/Output
–6–
REV. B
Page 7
ADV101
If we, therefore, have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate = 1024 × 1024 × 60/0.8
Dot Rate = 78.6 MHz
RED, BLUE GREEN
mA V mA V
19.05 0.714 26.67 1.000
92.5 IRE
1.44 0.054 9.05 0.340
0 0 7.62 0.286
00
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. V = 1.235V, R = 560Ω, I CONNECTED TO IOG.
REF SET SYNC
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
7.5 IRE
40 IRE
Figure 3. RGB Video Output Waveform
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV101
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV101 be driven by a TTL buffer (e.g., 74F244).
WHITE LEVEL
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
Table I. Video Output Truth Table
IOG IOR, IOB REF DAC
Description (mA)
1
(mA) WHITE SYNC BLANK Input Data
WHITE LEVEL 26.67 19.05 1 1 1 xxH
WHITE LEVEL 26.67 19.05 0 1 1 FFH
VIDEO video + 9.05 video + 1.44 0 1 1 data
VIDEO to BLANK video + 1.44 video + 1.44 0 0 1 data
BLACK LEVEL 9.05 1.44 0 1 1 00H
BLACK to BLANK 1.44 1.44 0 0 1 00H
BLANK LEVEL 7.62 0 0 1 0 xxH
SYNC LEVEL 0 0 0 0 0 xxH
NOTE
1
Typical with full-scale IOG = 26.67 mA. V
= 1.235 V, R
REF
= 560 Ω, I
SET
Video Synchronization and Control
The ADV101 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite
SYNC.
In a graphics system which does not automatically generate a
composite
circuitry will enable the generation of a composite
The I
SYNC signal, the inclusion of some additional logic
SYNC signal.
current output is typically connected directly to the
SYNC
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV101, the
to logic low and I
should be connected to analog GND.
SYNC
SYNC input should be tied
connected to IOG.
SYNC
Reference Input
An external 1.23 V voltage reference is required to drive the
ADV101. The AD589 from Analog Devices is an ideal choice of
reference. It is a two-terminal, low cost, temperature compensated bandgap voltage reference which provides a fixed 1.23 V
output voltage for input currents between 50 µA and 5 mA. Fig-
ure 4 shows a typical reference circuit connection diagram. The
voltage reference gets its current drive from the ADV101’s V
through an external 1 kΩ resistor to the V
pin. A 0.1 µF ce-
REF
ramic capacitor is required between the COMP and V
. This is
AA
AA
necessary so as to provide compensation for the internal reference amplifier.
REV. B
–7–
Page 8
ADV101
A resistance R
connected between FS ADJUST and GND
SET
determines the amplitude of the output video level according to
the following equations:
IOG (mA) = 12,082 × V
IOR, IOB (mA) = 8,628 × V
SYNC is not being encoded onto the green channel, then
If
REF
(V)/R
(V)/R
REF
(Ω) (1)
SET
(Ω) (2)
SET
Equation 1 will be similar to Equation 2.
Using a variable value of R
, as shown in Figure 4, allows for
SET
accurate adjustment of the analog output video levels. Use of a
fixed 560 Ω R
resistor yields the analog output levels as
SET
quoted in the specification page. These values also correspond
to the RS-343A video waveform values as shown in Figure 3.
ANALOG POWER PLANE
COMP
TO DACs
*ADDITIONAL CIRCUITRY, INCLUDING
DECOUPLING COMPONENTS,
EXCLUDED FOR CLARITY
0.1µF
ADV101*
V
AA
1kΩ
V
REF
FS ADJUST
GND
R
560Ω
+
5V
~
4mAI
~
REF
AD589
500Ω
SET
100Ω
(1.235V
VOLTAGE
REFERENCE)
Figure 4. Reference Circuit
D/A Converters
The ADV101 contains three matched 8-bit D/A converters. The
DACs are designed using an advanced, high speed, segmented
architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = “1”) or GND
(bit = “0”) by a sophisticated decoding scheme. As all this circuitry is on one monolithic device, matching between the three
DACs is optimized. As well as matching, the use of identical
current sources in a monolithic design guarantees monotonicity
and low glitch. The onboard operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
Analog Outputs
The ADV101 has three analog outputs, corresponding to the
red, green and blue video signals. A fourth analog output
(I
) can be used if it is required to encode video synchroni-
SYNC
zation information onto the green signal. In this case, I
SYNC
is
connected to IOG. (See “Video Synchronization and Control”
section.)
The red, green and blue analog outputs of the ADV101 are high
impedance current sources. Each one of these three RGB current outputs is capable of directly driving a 37.5 Ω load, such as
a doubly terminated 75 Ω coaxial cable. Figure 5a shows the
IOR, IOG, IOB
DACs
Z = 75Ω
S
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
Z = 75Ω
O
(CABLE)
Z = 75Ω
L
(MONITOR)
Figure 5a. Analog Output Termination for RS-343A
IOR, IOG, IOB
DACs
Z = 150Ω
S
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
Z = 75Ω
O
(CABLE)
Z = 75Ω
L
(MONITOR)
Figure 5b. Analog Output Termination for RS-170
required configuration for each of the three RGB outputs connected into a doubly terminated 75 Ω load. This arrangement
will develop RS-343A video output voltage levels across a 75 Ω
monitor.
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 5b. The output current levels of the
DACs remain unchanged, but the source termination resistance,
Z
, on each of the three DACs is increased from 75 Ω to 150 Ω.
S
More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is
available in an application note entitled “Video Formats &
Required Load Terminations” available from Analog Devices,
publication number E1228-15-1/89.
Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of Figure
5a. As well as the gray scale levels, black level to white level, the
diagram also shows the contributions of
SYNC and BLANK.
These control inputs add appropriately weighted currents to the
analog outputs, producing the specific output level requirements
for video applications. Table I details how the
SYNC and
BLANK inputs modify the output levels.
Gray Scale Operation
The ADV101 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels, red,
green or blue can be used to input the digital video data. The
two unused video data channels should be tied to logical zero.
–8–
REV. B
Page 9
ADV101
The unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red
channel is used and IOR is terminated with a doubly terminated 75 Ω load (37.5 Ω), IOB and IOG should be terminated
with 37.5 Ω resistors. (See Figure 6.)
37.5Ω
37.5Ω
DOUBLY
TERMINATED
75Ω LOAD
VIDEO
INPUT
R0
R7
G0
G7
B0
B7
IOR
IOG
IOB
ADV101
GND
Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video
Z
2
IOR, IOG, IOB
DACs
Z = 75Ω
S
(SOURCE
TERMINATION)
2
AD848
3
Z
1
0.1µF
+
V
S
7
6
4
0.1µF
–
V
S
75Ω
GAIN (G) = 1
Video Output Buffers
The ADV101 is specified to drive transmission line loads, which
is what most monitors are rated as. The analog output configurations to drive such loads are described in the Analog Interface
section and illustrated in Figure 5. However, in some applications it may be required to drive long “transmission line” cable
lengths. Cable lengths greater than 10 meters can attenuate and
distort high frequency analog output pulses. The inclusion of
output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between 2 and 4
will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing.
Analog Devices produces a range of suitable op amps for such
applications. These include the AD84X series of monolithic op
amps. In very high frequency applications (80 MHz), the
AD9617 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired video
level.
Z = 75Ω
O
(CABLE)
Z
1
+
Z
2
Z = 75Ω
L
(MONITOR)
Figure 7. AD848 As an Output Buffer
REV. B
–9–
Page 10
ADV101
PC BOARD LAYOUT CONSIDERATIONS
The ADV101 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV101, it is imperative
that great care be given to the PC board layout. Figure 8 shows
a recommended connection diagram for the ADV101.
The layout should be optimized for lowest noise on the
ADV101 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling. The
lead length between groups of V
and GND pins should by
AA
minimized so as to minimize inductive ringing.
COMP
C6
0.1µF
ANALOG POWER PLANE
C3
0.1µF
R
SET
R1
560Ω
75ΩR275Ω
C4
0.1µF
VIDEO
DATA
INPUTS
R0
R7
G0
G7
B0
B7
ADV101
V
GND
V
AA
REF
Ground Planes
The ADV101, and associated analog circuitry, should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 8. This bead should be located as close as possible
(within 3 inches) to the ADV101.
The analog ground plane should encompass all ADV101
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces and any output amplifiers.
The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV101.
C5
R4
0.1µF
1kΩ
Z1 (AD589)
ANALOG GROUND PLANE
R3
75Ω
L1 (FERRITE BEAD)
C2
10µF
L2 (FERRITE BEAD)
C1
33µF
5V (V+)
CC
GROUND
VIDEO
CONTROL
INPUTS
SYNC
R1, R2, R3
FS ADJUST
IOR
IOG
I
SYNC
IOB
DESCRIPTION
33µF TANTALUM CAPACITOR
C1
10µF TANTALUM CAPACITOR
C2
0.1µF CERAMIC CAPACITOR
FERRITE BEAD
L1, L2
75Ω 1% METAL FILM RESISTOR
1kΩ 1% METAL FILM RESISTOR
R4
R
SET
560Ω 1% METAL FILM RESISTOR
1.235V VOLTAGE REFERENCE
Z1
VENDOR PART NUMBER
FAIR-RITE 27430011 OR MURATA BL01/02/03
DALE CMF-55C
DALE CMF-55C
DALE CMF-55C
ANALOG DEVICES AD589JH
CLOCK
REF WHITE
BLANK
COMPONENT
C3, C4, C5, C6
Figure 8. Typical Connection Diagram and Component List
RGB
VIDEO
OUTPUT
–10–
REV. B
Page 11
ADV101
Power Planes
The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV101 (V
) and all asso-
AA
ciated analog circuitry. This power plane should be connected
to the regular PCB power plane (V
) at a single point through
CC
a ferrite bead, as illustrated in Figure 8. This bead should be located within three inches of the ADV101.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV101 power pins, voltage reference circuitry and
any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors. (See Figure 8.)
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of V
should be individually
AA
decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV101 contains circuitry
to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three-terminal voltage regulator.
Digital Signal Interconnect
The digital signal lines to the ADV101 should be isolated as
much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power
plane.
Due to the high clock rates used, long clock lines to the
ADV101 should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (V
CC
), and
not the analog power plane.
Analog Signal Interconnect
The ADV101 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high frequency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
should be a s close as possible to the ADV101 so as to minimize
reflections.
Additional information on PCB design is available in an application note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” This application note is available from
Analog Devices, publication number E1309–15–10/89.
REV. B
–11–
Page 12
ADV101
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Terminal Plastic Leaded Chip Carrier
(P-44A)
C1380–24–4/90
40-Pin Plastic DIP
(N-40A)
PRINTED IN U.S.A.
–12–
REV. B
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