Datasheet ADUM7510 Datasheet (ANALOG DEVICES)

5-Channel, 1 kV

Data Sheet

FEATURES

RoHS-compliant, 16-lead, QSOP package Low power operation: 5 V

1.2 mA per channel maximum @ 0 Mbps to 2 Mbps

2.8 mA per channel maximum @ 10 Mbps High temperature operation: 105°C Up to 10 Mbps data rate (NRZ) Low default output state 1000 V rms isolation rating

Safety and regulatory approvals (pending)

UL recognition

1000 V rms for 1 minute per UL 1577

APPLICATIONS

General-purpose, unidirectional, multichannel isolation

GENERAL DESCRIPTION

The ADuM75101 is a unidirectional 5-channel isolator based on the Analog Devices, Inc., iCoupler® technology. In contrast to the ADuM1510, the ADuM7510 has a lower isolation rating, offering a reduced cost option for applications that can accept a 1 kV ac isolation. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices eliminate the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital

Unidirectional Digital Isolator

ADuM7510

FUNCTIONAL BLOCK DIAGRAM

DD1

ADuM7510

GND

V V

V V V

GND

ENCODE DECODE

Figure 1.

interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices run at one-tenth to one-sixth the power consumption of optocouplers at comparable signal data rates.

The ADuM7510 isolator provides five independent isolation channels supporting data rates up to 10 Mbps. Each side operates with the supply voltage of 4.5 V to 5.5 V. Unlike other optocoupler alternatives, the ADuM7510 isolator has a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

DD2

GND

07632-001

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuM7510 Data Sheet

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Package Characteristics ............................................................... 4

Insulation and Safety-Related Specifications ............................ 4

Recommended Operating Conditions ...................................... 4

Regulatory Information ............................................................... 4

REVISION HISTORY

2/12—Rev. A to Rev. B

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to Printed Circuit Board (PCB) Layout Section ............ 8

1/10—Revision A: Initial Version

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Applications Information .................................................................8

Printed Circuit Board (PCB) Layout ..........................................8

Propagation Delay-Related Parameters ......................................8

DC Correctness and Magnetic Field Immunity..............................8

Power Consumption .....................................................................9

Power-Up/Power-Down Considerations ...................................9

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. B | Page 2 of 12

Data Sheet ADuM7510

Input Quiescent Supply Current per Channel

DDI (Q)

0.4

0.7

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

OEH

OCL

ODL

OEL

SWITCHING SPECIFICATIONS

PHL

PLH

PHL

PSK

PSKCD

Logic High Output7

transient magnitude = 800 V

DDI (D)

DDO (D)

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C, V

DD1

= V

DD2

= 5 V.

Output Quiescent Supply Current per Channel I

0.3 0.5 mA

Total Supply Current, Five Channels1

Supply Current, Quiescent I

Supply Current, 10 Mbps Data Rate I

Supply Current, 10 Mbps Data Rate I Input Currents IIA, IIB, IIC, IID, I Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

2.0 3.5 mA VIA = VIB = VIC = VID = VIE = 0 V

1.5 2.5 mA VIA = VIB = VIC = VID = VIE = 0 V

7.7 10 mA 5 MHz logic signal frequency

3.3 4.0 mA 5 MHz logic signal frequency

−10 +1 +10 µA VIA, VIB, VIC, VID, VIE ≥ 0 V V V

, V

OAH

OBH

, V

OCH

ODH

, V

OAL

OBL

, V

2.0 V

0.8 V

− 0.4 4.8 V IOx = −4 mA, VIx = VIH

DD2

0.2 0.4 V IOx = +4 mA, VIx = VIL

, V

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse-Width Distortion, |t

− t

, t

20 27 40 ns CL = 15 pF, CMOS signal levels

PWD 5 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching6 t

30 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

|CMH| 10 15 kV/µs VIx = V

DD1/VDD2

, VCM = 1000 V,

Common-Mode Transient Immunity at

Logic Low Output

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8 I

Supply current values are for all five channels combined, running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel, operating at a given data rate, can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total I

and I

DD1

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Operation below the minimum pulse width is not

recommended.

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component.

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V × V

rate that can be sustained while maintaining V transient magnitude is the range over which the common mode is slewed.

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for infor-

mation on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

supply currents as a function of the data rate for the ADuM7510.

DD2

|CML| 10 15 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.14 mA/Mbps

0.045 mA/Mbps

propagation delay is

signal to the 50% level of the rising edge of the VOx signal.

and/or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The

that is measured between units at the same operating temperature, supply voltages, and output

PLH

. CML is the maximum common-mode voltage slew

DD2

Rev. B | Page 3 of 12

PLH

ADuM7510 Data Sheet

Resistance (Input-to-Output)1

I-O

1012 Ω

I-O

Rated Dielectric Insulation Voltage

1000

V rms

1 minute duration

DD1

DD2

PACKAGE CHARACTERISTICS

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Capacitance (Input-to-Output)

2.2 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction-to-Ambient Thermal Resistance, QSOP θJA 76 °C/W Thermocouple located at center of

package underside

The device is considered a 2-terminal device. Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

Input capacitance is from any input data pin to ground.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 3.

Parameter Symbol Value Unit Test Conditions/Comments

Minimum External Air Gap QSOP Package (Clearance) L(I01) 3.8 min mm Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking QSOP Package (Creepage) L(I02) 3.8 min mm Measured from input terminals to output terminals,

shortest distance path along body Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1) Maximum Working Voltage Compatible with 50 Years

354 V peak Continuous peak voltage across the isolation barrier

IORM

Service Life

RECOMMENDED OPERATING CONDITIONS

All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.

Table 4.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C Supply Voltages V

, V

4.5 5.5 V

Input Signal Rise and Fall Times 1.0 ms

REGULATORY INFORMATION

The ADuM7510 is approved by the organization listed in Table 5.

Table 5.

UL (Pending)

Recognized under UL 1577 component recognition program1 Single/basic insulation, 1000 V rms isolation voltage File E214100

In accordance with UL 1577, each ADuM7510 is proof tested by applying an insulation test voltage of 1200 V rms for 1 sec (current leakage detection limit = 5 µA).

Rev. B | Page 4 of 12

Data Sheet ADuM7510

DD1

DD2

ABSOLUTE MAXIMUM RATINGS

Ambient temperature TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

Storage Temperature (TST) Range −65°C to +150°C Ambient Operating Temperature (TA)

−40°C to +105°C

Range Supply Voltages1 (V Input Voltages1

, VIB, VIC, VID, VIE)

Output Voltages1

, VOB, VOC, VOD, VOE)

, V

) −0.5 V to +7.0 V

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current per Pin2

Side 1 (IO1) −10 mA to +10 mA

Side 2 (IO2) −10 mA to +10 mA Common-Mode Transients3 −100 kV/μs to +100 kV/μs

All voltages are relative to their respective ground.

See Figure 3 for maximum rated current values for various temperatures.

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latchup or permanent damage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 5 of 12

ADuM7510 Data Sheet

DD1

GND

DD2

GND

ADuM7510

TOP VIEW

(Not to S cale)

*PIN 2 AND PIN 8 ARE INTERNALLY CO NNE CTED. CONNECTING BOTH

TO GND

IS RECOMM E NDE D. PIN 9 AND PIN 15 ARE INTERNALL Y

CONNECTED. CONNECTING BOTH TO GND

IS RECOMMENDED.

07632-002

DD1

to GND1 is recommended.

Logic Input A.

DD2

Supply Voltage for Isolator Side 2 (4.5 V to 5.5 V).

DD2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 GND

Supply Voltage for Isolator Side 1 (4.5 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both

4 VIB Logic Input B. 5 VIC Logic Input C. 6 V 7 V

Logic Input D. Logic Input E.

8 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both

to GND

is recommended.

9 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both

10 V 11 V

to GND Logic Output E. Logic Output D.

is recommended.

12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both

to GND

is recommended.

Table 8. Truth Table (Positive Logic)

1, 2

DD1

State

DD2

State

VOx Output

Input

High Powered Powered High Normal operation, data is high. Low Powered Powered Low Normal operation, data is low. X Unpowered Powered Low Input unpowered. Outputs return to input state within 1 µs of V

X Powered Unpowered High-Z Output unpowered. Output pins are in high impedance state. Outputs return to input

VIX and VOX refer to the input and output signals of a given channel (A, B, C, D, or E).

X = don’t care.

Description

See the Power-Up/Power-Down Considerations section for more details.

state within 1 µs of V

Rev. B | Page 6 of 12

power restoration.

DD1

Data Sheet ADuM7510

07632-003

100

150

200

250

300

350

0 25 50 75 100 125 150 175

MAXIMUM CURRENT (mA)

AMBIENT TEMPERATURE (°C)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0 2 4 6 8 10

DATA RATE (Mbps)

DD1

CURRENT/CHANNEL ( mA)

07632-004

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0 2 4 6 8 10

DATA RATE (Mbps)

DD2

CURRENT/CHANNEL ( mA)

07632-005

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0 2 4 6 8 10

DATA RATE (Mbps)

DD2

CURRENT/CHANNEL 15pF LOAD (mA)

07632-006

0 2 4 6 8 10

DATA RATE (Mbps)

DD1

CURRENT (mA)

07632-007

0 2 4 6 8 10

DATA RATE (Mbps)

DD2

CURRENT 15pF LOAD (mA)

07632-008

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

Figure 4. Typical I

Supply Current per Channel vs. Data Rate

DD1

Figure 6. Typical I

Figure 7. Typical Total I

Supply Current per Channel vs. Data Rate

DD2

(15 pF Output Load)

Supply Current vs. Data Rate

DD1

Figure 5. Typical I

Supply Current per Channel vs. Data Rate

DD2

(No Output Load)

Figure 8. Typical Total I

Supply Current vs. Data Rate

DD2

(15 pF Output Load)

Rev. B | Page 7 of 12

ADuM7510 Data Sheet

APPLICATIONS INFORMATION

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM7510 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 9). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V

and between Pin 15 and Pin 16 for V

DD1

DD2

. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 10 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.

GND

DD1

ADuM7510

Figure 9. Recommended PCB Layout

DD2

GND V

GND

7632-009

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output.

INPUT (

OUTPUT (V

)

PLH

)

PHL

50%

Figure 10. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM7510 component.

Propagation delay skew refers to the maximum amount the propagation delay differs among multiple ADuM7510 components operated under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output.

07632-010

If the decoder receives no pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit (see Table 8).

The limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines such conditions. The ADuM7510 is examined in a 4.5 V operating condition because it represents the most susceptible mode of operation of this product.

The pulses at the transformer output have an amplitude greater than 1.5 V. The decoder has a sensing threshold of about 1.0 V, thereby establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)∑∏r

; n = 1, 2, …, N

where:

β is the magnetic flux density. r

is the radius of the nth turn in the receiving coil.

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM7510 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 11.

1000

100

(kgauss)

0.1

0.01

MAXIMUM ALL OWABLE MAG NE TIC FLUX

0.001 1k 10k 100k 1M 10M 100M

MAGNETIC FIELD FREQUENCY (Hz)

07632-011

Figure 11. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. If such an event occurs with the worst-case polarity during a transmitted pulse, it reduces the received pulse from >1.0 V to

0.75 V, still well above the 0.5 V sensing threshold of the decoder.

Rev. B | Page 8 of 12

Data Sheet ADuM7510

The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM7510 transformers. Figure 12 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADuM7510 is very insensitive to external fields. Only extremely large, high frequency currents, very close to the component can potentially be a concern. For the 1 MHz example noted, a 1.2 kA current must be placed 5 mm away from the ADuM7510 to affect component operation.

1000

100

DISTANCE = 5mm

0.1

MAXIMUM ALLOWABLE CURRENT (kA)

0.01 1k 10k 100k 1M 10M 100M

DISTANCE = 100mm DISTANCE = 1m

MAGNETIC FIELD FREQUENCY (Hz)

Figure 12. Maximum Allowable Current for

Various Current to ADuM7510 Spacings

07632-012

Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Take care to avoid PCB structures that form loops.

POWER CONSUMPTION

The supply current at a given channel of the ADuM7510 isolator is a function of the supply voltage, the channel data rate, and the channel output load.

For each input channel, the supply current is given by

= I

DDI

DDI (Q)

DDI

= I

× (2f − fr) + I

DDI (D)

DDI (Q)

f ≤ 0.5fr

f > 0.5fr

For each output channel, the supply current is given by

DDO

= I

= (I

f ≤ 0.5fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

DDO (Q)

f ≤ 0.5fr

where:

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

is the output load capacitance (pF).

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

is the input stage refresh rate (Mbps).

, I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

To calculate the total I

DD1

and I

supply current, the supply

DD2

currents for each input and output channel corresponding to I

DD1

and I

are calculated and totaled. Figure 4 and Figure 5

DD2

provide per-channel supply currents as a function of the data rate for an unloaded output condition. Figure 6 provides perchannel supply current as a function of the data rate for a 15 pF output condition. Figure 7 and Figure 8 provide total I I

supply current as a function of the data rate for ADuM7510

DD2

DD1

and

products.

POWER-UP/POWER-DOWN CONSIDERATIONS

The ADuM7510 behaves as specified in Table 8 during powerup and power-down operations. However, the part can transfer incorrect data when the power supplies are below the minimum operating voltage but the internal circuits are not completely off.

Power-up/power-down errors can occur at V the operating threshold of 1.9 V. The encoder generates data pulses at low amplitude. The detector can miss data pulses that are near the detection threshold. If the transferring state is a logic high, the encoder generates a pair of pulses; the decoder can reject one of the pulses for low amplitude. A single pulse is interpreted as a logic low, and the output can be placed in the wrong logic state for that refresh cycle.

Glitch-free operation is possible by following these recommendations.

voltage near

DDx

 Slew the power on or off as quickly as possible.  Use the default low operating mode by holding the inputs

low until power is stable.

Rev. B | Page 9 of 12

ADuM7510 Data Sheet

COMPLIANT TO JEDEC STANDARDS MO-137-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

SEATING PLANE

0.010(0.25)

0.004(0.10)

0.012 (0.30)

0.008 (0.20)

0.025(0.64) BSC

0.041(1.04) REF

0.010 (0.25)

0.006 (0.15)

0.050 (1.27)

0.016 (0.41)

0.020 (0.51)

0.010 (0.25)

8° 0°

COPLANARITY

0.004 (0.10)

0.065(1.65)

0.049(1.25)

0.069(1.75)

0.053(1.35)

0.197 (5.00)

0.193 (4.90)

0.189 (4.80)

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

01-28-2008-A

DD1

DD2

OUTLINE DIMENSIONS

Figure 13. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Number

1, 2

Model

ADuM7510BRQZ

of Inputs,

Side

5 0 10 Mbps 40 ns 5 ns

ADuM7510BRQZ-RL7 5 0 10 Mbps 40 ns 5 ns

Z = RoHS Compliant Part.

RL7 = 7” tape and reel option.

Number of Inputs,

Side

Maximum Data Rate

Maximum Propagation Delay, 5 V

Maximum Pulse Width Distortion

Temperature Range

−40°C to +105°C

Package Description

Package Option

16-Lead QSOP RQ-16 16-Lead QSOP RQ-16

Rev. B | Page 10 of 12

Data Sheet ADuM7510

NOTES

Rev. B | Page 11 of 12

ADuM7510 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D07632-0-2/12(B)

Rev. B | Page 12 of 12

Datasheet ADUM7510 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

PACKAGE CHARACTERISTICS

INSULATION AND SAFETY-RELATED SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

REGULATORY INFORMATION

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PRINTED CIRCUIT BOARD (PCB) LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

POWER-UP/POWER-DOWN CONSIDERATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE