Datasheet ADUM7440 Datasheet (ANALOG DEVICES)

V

1 kV RMS Quad-Channel Digital Isolators

Data Sheet

FEATURES

Small, 16-lead QSOP 1000 V rms isolation rating

Safety and regulatory approvals

UL recognition

UL 1577: 1000 V rms for 1 minute

CSA Component Acceptance Notice #5A (pending)

Low power operation

5 V operation

2.25 mA per channel maximum @ 0 Mbps to 1 Mbps

11.5 mA per channel maximum @ 25 Mbps

3.3 V operation

1.5 mA per channel maximum @ 0 Mbps to 1 Mbps

8.25 mA per channel maximum @ 25 Mbps Bidirectional communication Up to 25 Mbps data rate (NRZ) 3 V/5 V level translation High temperature operation: 105°C High common-mode transient immunity: >15 kV/μs

APPLICATIONS

General-purpose, multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation

ADuM7440/ADuM7441/ADuM7442

GENERAL DESCRIPTION

The ADuM744x1 are 4-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to the alternatives, such as optocoupler devices and other integrated couplers.

The ADuM744x family of quad 1 kV digital isolation devices is packaged in a small 16-lead QSOP. While most 4-channel isolators come in 16-lead wide SOIC packages, the ADuM744x frees almost 70% of board space and yet can still withstand high isolation voltage and meet regulatory requirements such as UL and CSA standards (pending). In addition to the space savings, the ADuM744x offers a lower price than 2.5 kV or 5 kV isolators where only functional isolation is needed.

This family, like many Analog Devices isolators, offers very low power consumption, consuming one-tenth to one-sixth the power of comparable isolators at comparable data rates up to 25 Mbps. Despite the low power consumption, all models of the ADuM744x provide low pulse width distortion (< 5 ns for C grade). In addition, every model has an input glitch filter to protect against extraneous noise disturbances.

The ADuM744x isolators provide four independent isolation channels in a variety of channel configurations and two data rates (see the Ordering Guide) up to 25 Mbps. All models operate with the supply voltage on either side ranging from

3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have an output default high logic state in the absence of the input power.

1

Protected by U.S. Patents 5,952,849, 6,873,065 and 7,075,329. Other patents

pending.

FUNCTIONAL BLOCK DIAGRAMS

V

GND

V

GND

DD1A

V

V V

DD1B

1

ADuM7440

2

1

3

ENCODE DECODE

V

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

ENCODE DECODE

ID

7 8

1

Figure 1. ADuM7440

16

V

DD2A

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

DD2B

9

GND

2

08340-001

DD1A

GND

DD1B

GND

V V

V

OD

1

ADuM7441

2

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

7 8

1

Figure 2. ADuM7441

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

16

V

DD2A

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

DD2B

9

GND

2

08340-002

DD1A

GND

DD1B

GND

V V

V

OC

V

OD

1

ADuM7442

2

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

6

DECODE ENCODE

7 8

1

16

V

DD2A

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

DD2B

9

GND

2

Figure 3. ADuM7442

08340-003

ADuM7440/ADuM7441/ADuM7442 Data Sheet

REVISION HISTORY

2/12—Rev. B to Rev. C

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 14

2/11—Rev. A to Rev. B

Changes to Figure 7 ........................................................................ 11

8/10—Rev. 0 to Rev. A

Change Features ................................................................................ 1

Changes to Table 1 ............................................................................ 3

Added Note 1, Table 1 ...................................................................... 3

Changes to Table 4 ................................

Added Note 1, Table 4 ...................................................................... 4

Changes to Table 7 ............................................................................ 5

Added Note 1, Table 7 ...................................................................... 5

Changes to Table 10 .......................................................................... 6

Added Note 1, Table 10 .................................................................... 6

Changes to Table 14 .......................................................................... 7

10/09—Revision 0: Initial Version

............................................ 4

Recommended Operating Conditions .......................................7

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions ............................9

Typical Performance Characteristics ........................................... 12

Applications Information .............................................................. 14

PC Board Layout ........................................................................ 14

Propagation Delay-Related Parameters ................................... 14

DC Correctness and Magnetic Field Immunity........................... 14

Power Consumption .................................................................. 15

Insulation Lifetime ..................................................................... 15

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. C | Page 2 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

A Grade

C Grade

Min

Typ

Max

Min

Typ

Max

PHL

PLH

PHL

Pulse Width

PW

250

40

ns

Within PWD limit

1

PSK

PSKCD

PSKOD

1 Mbps—A Grade

25 Mbps—C Grade

Min

Typ

Max

Min

Typ

Max

DD1

DDx

IxH

DDx

IxH

IxL

DDx

DDI(Q)

DDO(Q)

Dynamic Input Supply Current

I

DDI(D)

0.26 mA/Mbps

DDO(D)

Output Rise/Fall Time

tR/tF 2.0 ns

10% to 90%

1

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at TA = 25°C, V operation range of 4.5 V ≤ V are tested with C

= 15 pF, and CMOS signal levels, unless otherwise noted.

L

≤ 5.5 V, 4.5 V ≤ V

DD1

Table 1.

DD1

= V

= 5 V. Minimum/maximum specifications apply over the entire recommended

DD2

≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications

DD2

Parameter Symbol

Unit Test Conditions

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t Pulse Width Distortion PWD 10 25 2 5 ns |t

, t

50 75 29 40 50 ns 50% input to 50% output

− t

|

Change vs. Temperature 5 3 ps/°C

Propagation Delay Skew

t

20 10 ns

Channel Matching

Codirectional t Opposing-Direction t

25 2 4 ns 30 3 6 ns

Jitter 2 2 ns

1

t

is the magnitude of the worst-case difference in t

PSK

recommended operating conditions.

or t

that is measured between units a t the same operating temperature, supply voltages, and output load within the

PHL

PLH

Table 2.

Parameter Symbol

SUPPLY CURRENT

ADuM7440 I I ADuM7441 I I ADuM7442 I

I

4.3 5.4 28 35 mA

2.5 3.6 6.0 11 mA

DD2

4.1 4.9 18 26 mA

3.6 4.7 8.5 14 mA

DD2

3.2 4.0 15 20 mA

3.2 4.0 12 17 mA

DD2

Unit Test Conditions

Table 3. For All Models

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages VOH V V

V

− 0.1 5.0 V IOx = −20 µA, VIx = V

− 0.4 4.8 V IOx = −4 mA, VIx = V

Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ V Supply Current per Channel

Quiescent Input Supply Current I Quiescent Output Supply Current I

0.76 0.95 mA

0.57 0.73 mA

Dynamic Output Supply Current I

AC SPECIFICATIONS

Common-Mode Transient Immunity

Refresh Rate fr 1.2 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining V

common-mode voltage edges.

0.05 mA/Mbps

|CM| 15 25 kV/µs VIx = V

, VCM = 1000 V,

DDx

transient magnitude = 800 V

> 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling

Rev. C | Page 3 of 20

O

ADuM7440/ADuM7441/ADuM7442 Data Sheet

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at TA = 25°C, V operation range of 3.0 V ≤ V are tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

L

≤ 3.6 V, 3.0 V ≤ V

DD1

Table 4.

A Grade C Grade Parameter Symbol

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t

PHL

Pulse Width Distortion PWD 10 25 2 5 ns |t

Change vs. Temperature 5 3 ps/°C Pulse Width PW 250 40 ns Within PWD limit Propagation Delay Skew

1

t

PSK

Channel Matching

Codirectional t

Opposing-Direction t

PSKCD

PSKOD

Jitter 2 2 ns

1

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

Table 5.

1 Mbps—A, C Grades 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

SUPPLY CURRENT

ADuM7440 I I ADuM7441 I I ADuM7442 I

I

3.0 3.8 20 28 mA

DD1

1.8 2.3 4.0 5.0 mA

DD2

2.8 3.5 14 20 mA

DD1

2.5 3.3 5.5 7.5 mA

DD2

2.2 2.7 10 13 mA

DD1

2.2 2.8 8.4 11 mA

DD2

= V

DD1

, t

60 85 37 51 66 ns 50% input to 50% output

PLH

= 3.3 V. Minimum/maximum specifications apply over the entire recommended

DD2

≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications

DD2

Min Typ Max Min

Typ Max

Unit Test Conditions

− t

|

PLH

PHL

20 10 ns

25 3 5 ns

30 4 7 ns

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

Table 6. For All Models

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages VOH V V Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V Input Current per Channel II −10 +0.01 +10 μA 0 V ≤ VIx ≤ V

DDx

− 0.2 3.3 V IOx = −20 μA, VIx = V

DDx

− 0.4 3.1 V IOx = −4 mA, VIx = V

DDx

V

DDx

V

DDx

IxH

IxL

Supply Current per Channel

Quiescent Input Supply Current I

Quiescent Output Supply Current I

Dynamic Input Supply Current I

Dynamic Output Supply Current I

0.50 mA

DDI(Q)

0.41 mA

DDO(Q)

0.18 mA/Mbps

DDI(D)

0.02 mA/Mbps

DDO(D)

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.8 ns 10% to 90% Common-Mode Transient Immunity1 |CM| 15 20 kV/μs

= V

Ix

DDx

, VCM = 1000 V,

V

transient magnitude = 800 V

Refresh Rate fr 1.1 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both

rising and falling common-mode voltage edges.

Rev. C | Page 4 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION

All typical specifications are at TA = 25°C, V

mended operation range of 4.5 V ≤ V

specifications are tested with C

DD1

= 15 pF and CMOS signal levels, unless otherwise noted.

L

Table 7.

A Grade C Grade

Parameter Symbol

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t

PHL

Pulse Width Distortion PWD 10 25 2 5 ns |t

Change vs. Temperature 5 3 ps/°C Pulse Width PW 250 40 ns Within PWD limit Propagation Delay Skew

1

t

PSK

Channel Matching

Codirectional t

Opposing-Direction t

PSKCD

PSKOD

Jitter 2 2 ns

1

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

Table 8.

Parameter

Symbol

SUPPLY CURRENT

ADuM7440 I I ADuM7441 I I ADuM7442 I

I

4.4 5.5 28 35 mA

DD1

1.6 2.1 3.5 4.5 mA

DD2

3.7 5.0 19 27 mA

DD1

2.2 2.8 5.2 7.0 mA

DD2

3.2 3.9 15 20 mA

DD1

2.0 2.6 7.8 12 mA

DD2

= 5 V, V

DD1

≤ 5.5 V, 3.0 V ≤ V

Min Typ Max Min Typ Max

, t

55 80 30 42 55 ns 50% input to 50% output

PLH

= 3.3 V. Minimum/maximum specifications apply over the entire recom-

DD2

≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching

DD2

Unit Test Conditions

− t

PHL

|

PLH

20 10 ns

25 2 5 ns

30 3 6 ns

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

1 Mbps—A, C Grades 25 Mbps—C Grade

Min Typ Max Min Typ Max

Unit

Test Conditions

Table 9. For All Models

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages VOH V V Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V Input Current per Channel II −10 +0.01 +10 μA 0 V ≤ VIx ≤ V

DDx

− 0.1 V

DDx

− 0.4 V

DDx

V IOx = −20 μA, VIx = V

DDx

− 0.2 V IOx = −4 mA, VIx = V

DDx

V

DDx

V

DDx

IxH

IxL

Supply Current per Channel

Quiescent Input Supply Current I

Quiescent Output Supply Current I

Dynamic Input Supply Current I

Dynamic Output Supply Current I

0.77 mA

DDI(Q)

0.40 mA

DDO(Q)

0.26 mA/Mbps

DDI(D)

0.02 mA/Mbps

DDO(D)

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient Immunity

1

|CM| 15 20 kV/μs

= V

Ix

DDx

, VCM = 1000 V,

V

transient magnitude = 800 V

Refresh Rate fr 1.2 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both

rising and falling common-mode voltage edges.

Rev. C | Page 5 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet

ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION

All typical specifications are at TA = 25°C, V mended operation range of 3.0 V ≤ V specifications are tested with C

DD1

= 15 pF and CMOS signal levels, unless otherwise noted.

L

Table 10.

A Grade C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t

PHL

Pulse Width Distortion PWD 10 25 2 5 ns |t

Change vs. Temperature 5 3 ps/°C Pulse Width PW 250 40 ns Within PWD limit Propagation Delay Skew

1

t

PSK

Channel Matching

Codirectional t

Opposing-Direction t

PSKCD

PSKOD

Jitter 2 2 ns

1

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

Table 11.

1 Mbps—A, C Grades 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

SUPPLY CURRENT

ADuM7440 I I ADuM7441 I I ADuM7442 I

I

DD1

DD2

DD1

DD2

DD1

DD2

= 3.3 V, V

DD1

≤ 3.6 V, 4.5 V ≤ V

, t

55 80 31 46 60 ns 50% input to 50% output

PLH

= 5 V. Minimum/maximum specifications apply over the entire recom-

DD2

≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching

DD2

− t

|

PLH

PHL

20 10 ns

25 2 5 ns

30 3 7 ns

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

2.7 3.3 18 24

2.5 3.3 5.7 8.0

2.5 3.3 12 20

3.6 4.6 8.0 11

2.0 2.4 8.9 13

3.2 4.0 12 15

mA mA mA mA mA mA

Table 12. For All Models

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages VOH V V Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V Input Current per Channel II −10 +0.01 +10 μA 0 V ≤ VIx ≤ V

DDx

− 0.1 V

DDx

− 0.4 V

DDx

V IOx = −20 μA, VIx = V

DDx

− 0.2 V IOx = −4 mA, VIx = V

DDx

V

DDx

V

DDx

IxH

IxL

Supply Current per Channel

Quiescent Input Supply Current I

Quiescent Output Supply Current I

Dynamic Input Supply Current I

Dynamic Output Supply Current I

0.50 0.60 mA

DDI(Q)

0.61 0.73 mA

DDO(Q)

0.17 mA/Mbps

DDI(D)

0.03 mA/Mbps

DDO(D)

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient Immunity1 |CM| 15 20 kV/μs

= V

Ix

DDx

, VCM = 1000 V,

V

transient magnitude = 800 V

Refresh Rate fr 1.1 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both

rising and falling common-mode voltage edges.

Rev. C | Page 6 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

Resistance (Input-to-Output)1

R

I-O

10

13

Ω

1

I-O

Isolation Group

IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

CASE TEMPERATURE (°C)

SAFETY-L IMIT ING CURRENT ( mA)

0

350

300

250

200

150

100

50

50 100 150 200

08340-007

DD1

DD2

PACKAGE CHARACTERISTICS

Table 13.

Parameter Symbol Min Typ Max Unit Test Conditions

Capacitance (Input-to-Output)

C

2 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction-to-Ambient Thermal

Resistance

1

The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

θJA 76 °C/W Thermocouple located at center of package

underside

REGULATORY INFORMATION

The ADuM744x is approved by the organizations listed in Tabl e 14. See Table 18 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 14.

UL CSA (Pending)

Recognized under UL 1577 Component Recognition Program

1

Single Protection, 1000 V rms Isolation Voltage

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1, 148 V rms (210 V peak) maximum working voltage

File E274400 File 205078

1

In accordance with UL 1577, each ADuM744x is proof tested by applying an insulation test voltage ≥1200 V rms for 1 sec (current leakage detection limit = 5 µA).

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 15.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 1000 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 3.8 mm min Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage) L(I02) 2.8 mm min Measured from input terminals to output terminals,

shortest distance path along body Minimum Internal Gap (Internal Clearance) 2.6 μm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

RECOMMENDED OPERATING CONDITIONS

Table 16.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C Supply Voltages1 V Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground. See the DC Correctness

and Magneti c Field Immunity section for information on immunity to external magnetic fields.

Rev. C | Page 7 of 20

, V

3.0 5.5 V

ADuM7440/ADuM7441/ADuM7442 Data Sheet

DD1

DD2

1, 2

DDI

DDO

Side 1 (IO1)

−10 mA to +10 mA

DDI

DDO

L

Powered

L

Normal operation; data is low.

X

Unpowered

Powered

H

Input unpowered. Outputs are in the default high state. Outputs return to

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 17.

Parameter Rating

Storage Temperature (TST) Range −65°C to +150°C Ambient Operating Temperature (TA) −40°C to +105°C Supply Voltages (V Input Voltages ( VIA, VIB, VIC, VID) Output Voltages (VOA, VOB, VOC, VOD)

, V

) −0.5 V to +7.0 V

−0.5 V to V

1, 2

−0.5 V to V

+ 0.5 V

Average Output Current per Pin3

Side 2 (IO2) −10 mA to +10 mA

Common-Mode Transients3 −100 kV/µs to +100 kV/µs

1

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

2

See Figure 4 for maximum rated current values for various temperatures.

3

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.

Table 18. Maximum Continuous Working Voltage

refer to the supply voltages on the input and output sides of a

DDO

1

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 420 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform

Basic Insulation 420 V peak 50-year minimum lifetime

DC Voltage

Basic Insulation 420 V peak 50-year minimum lifetime

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Table 19. Truth Table (Positive Logic)

VIx Input1 V

State2 V

State3 VOx Output1 Description

H Powered Powered H Normal operation; data is high.

input state within 1 µs of V descriptions (

Table 20 through Table 22) for more details.

power restoration. See the pin function

DDI

X Powered Unpowered Z Output unpowered. Output pins are in high impedance state. Outputs

return to input state within 1 µs of V

power restoration. See the pin function

DDO

descriptions (Tab le 20 through Table 22) for more details.

1

VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).

2

V

refers to the power supply on the input side of a given channel (A, B, C, or D).

DDI

3

V

refers to the power supply on the output side of a given channel (A, B, C, or D).

DDO

Rev. C | Page 8 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

V

DD1A

1

GND

1

*

2

V

IA

3

V

IB

4

V

DD2A

16

GND2*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

ID

6

V

OD

11

V

DD1B

7

V

DD2B

10

GND1*

8

GND2*

9

ADuM7440

TOP VIEW

(Not to Scal e)

*PI N 2 AND PIN 8 ARE INT ERNALLY CO NNECTED. CO NNECTING BO TH

TO GND

1

IS RECOMME NDED. PIN 9 AND PI N 15 ARE INTERNAL LY

CONNECTED. CO NNECTING BOTH TO GND

2

IS RECOMMENDED.

08340-004

DD1A

IA

ID

DD1B

Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic

DD2B

OD

DD2A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADuM7440 Pin Configuration

Table 20. ADuM7440 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1A

2 GND

1

Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 1) and GND1 (Pin 2).

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended.

3 V

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V 7 V

Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic

DD1B

Logic Input D.

bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 7) and GND1 (Pin 8).

8 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended. 9 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is

recommended. 10 V

11 V

DD2B

bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 10) and GND2 (Pin 9).

Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is

recommended. 16 V

Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a

DD2A

ceramic bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 16) and GND2 (Pin 15).

Rev. C | Page 9 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet

V

DD1A

1

GND1*

2

V

IA

3

V

IB

4

V

DD2A

16

GND2*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

OD

6

V

ID

11

V

DD1B

7

V

DD2B

10

GND1*

8

GND2*

9

ADuM7441

TOP VIEW

(Not to Scal e)

*PI N 2 AND PIN 8 ARE INT ERNALLY CO NNECTED. CO NNECTING BO TH

TO GND

1

IS RECOMME NDED. PIN 9 AND PI N 15 ARE INTERNAL LY

CONNECTED. CO NNECTING BOTH TO GND

2

IS RECOMMENDED.

08340-005

DD1A

IA

OD

DD1B

Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic

DD2B

ID

DD2A

Figure 6. ADuM7441 Pin Configuration

Table 21. ADuM7441 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1A

2 GND

1

Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 1) and GND1 (Pin 2).

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended.

3 V

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V 7 V

Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic

DD1B

Logic Output D.

bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 7) and GND1 (Pin 8).

8 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended. 9 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is

recommended. 10 V

11 V

Supply

DD2B

bypass capacitor of value 0.01 µF to 0.1 µF between V

Logic Input D.

(Pin 10) and GND2 (Pin 9).

12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is

recommended. 16 V

Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a

DD2A

ceramic bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 16) and GND2 (Pin 15).

Rev. C | Page 10 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

V

DD1A

1

GND

1

*

2

V

IA

3

V

IB

4

V

DD2A

16

GND

2

*

15

V

OA

14

V

OB

13

V

OC

5

V

IC

12

V

OD

6

V

ID

11

V

DD1B

7

V

DD2B

10

GND

1

*

8

GND

2

*

9

ADuM7442

TOP VIEW

(Not to Scale)

*PI N 2 AND PIN 8 ARE INT ERNALLY CO NNECTED. CO NNECTING BO TH

TO GND

1

IS RECOMMENDED. PIN 9 AND PI N 15 ARE INTERNAL LY

CONNECTED. CONNECTING BOTH TO GND

2

IS RECOMMENDED.

08340-006

DD1A

IA

OD

DD1B

10

V

Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic

DD2B

ID

15

GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is

DD2A

Figure 7. ADuM7442 Pin Configuration

Table 22. ADuM7442 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1A

2 GND

1

Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 1) and GND1 (Pin 2).

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended.

3 V

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 V 7 V

Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic

DD1B

Logic Output D.

bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 7) and GND1 (Pin 8).

8 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended. 9 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is

recommended.

DD2B

11 V

bypass capacitor of value 0.01 µF to 0.1 µF between V

Logic Input D.

(Pin 10) and GND2 (Pin 9).

12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A.

recommended. 16 V

Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a

DD2A

ceramic bypass capacitor of value 0.01 µF to 0.1 µF between V

(Pin 16) and GND2 (Pin 15).

Rev. C | Page 11 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet

08340-015

0 5 10 15 20 25 30

D

ATA RATE (Mbps)

3V

5V

10

8

6

4

2

0

CURRENT (mA)

08340-016

CURRENT (mA)

0

1

2

3

4

0 5 10 15 20 25 30

DATA RATE (Mbps)

5V

3V

08340-017

CURRENT (mA)

0

1

2

3

4

0 5 10 15 20 25 30

DATA RATE (Mbps)

5V

3V

08340-018

CURRENT (mA)

0

5

10

15

20

25

30

35

0 5 10 15 20 25 30

DATA RATE (Mbps)

5V

3V

08340-019

CURRENT (mA)

0 5 10 15 20 25 30

DATA RATE (Mbps)

0

2

4

6

8

10

5V

3V

08340-020

CURRENT (mA)

0 5 10 15 20 25 30

DATA RATE (Mbps)

5V

3V

0

5

10

15

20

25

30

35

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Typical Supply Current per Input Channel vs. Data Rate

for 5 V and 3 V Operation

Figure 9. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

Figure 11. Typical ADuM7440 V

for 5 V and 3 V Operation

Figure 12. Typical ADuM7440 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD1

Supply Current vs. Data Rate

DD2

Figure 10. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

Figure 13. Typical ADuM7441 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD1

Rev. C | Page 12 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

08340-021

CURRENT (mA)

0 5 10 15 20 25 30

DATA RATE (Mbps)

0

2

4

6

8

10

5V

3V

08340-022

CURRENT (mA)

0 5 10 15 20 25 30

DATA RATE (Mbps)

0

5

10

15

20

25

5V

3V

Figure 14. Typical ADuM7441 V

Supply Current vs. Data Rate

for 5 V and 3 V Operation

DD2

Figure 15. Typical ADuM7442 V

or V

DD1

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD2

Rev. C | Page 13 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet

V

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM744x digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). A total of four bypass capacitors should be connected between Pin 1 and Pin 2 for V and Pin 8 for V between Pin 15 and Pin 16 for V V

Pin 7 should be connected together and supply V

DD1B

Pin 10 and V

, between Pin 9 and Pin 10 for V

DD1B

. Supply V

DD2A

Pin 16 should be connected together. The

DD2A

, between Pin 7

DD1A

Pin 1 and

DD1A

DD2B

, and

DD2B

capacitor values should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the power supply pin should not exceed 20 mm.

V

DD1A

GND

1

V

IA

V

IB IC/VOC ID/VOD

V

DD1B

GND

1

Figure 16. Recommended Printed Circuit Board Layout

V

DD2A

GND V

OA

V

OB

V

OC/VIC

V

OD/VID

V

DD2B

GND

2

08340-014

In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition.

INPUT (

)

Ix

OUTPUT (V

t

PLH

)

Ox

t

PHL

Figure 17. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved.

50%

08340-008

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM744x component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM744x components operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default high state by the watchdog timer circuit.

The magnetic field immunity of the ADuM744x is determined by the changing magnetic field, which induces a voltage in the transformer’s receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM744x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ / dt) ∑ π r

where:

β is magnetic flux density (gauss). r

is the radius of the nth turn in the receiving coil (cm).

n

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM744x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18.

2

; n = 1, 2, … , N

n

Rev. C | Page 14 of 20

1000

100

10

1

0.1

0.01

0.001 1k

100M10k

MAXIMUM ALL OWABLE MAGNETI C FLUX (kgauss)

100k 1M

10M

MAGNETIC FIELD FREQUENCY (Hz)

08340-009

1000

100

10

1

0.1

0.01

1k

100M10k

MAXIMUM ALL OWABLE CURRENT (kA)

100k 1M

10M

MAGNETIC FIELD FREQUENCY (Hz)

DISTANCE = 5mm

DISTANCE = 100mm

DISTANCE = 1m

08340-010

Data Sheet ADuM7440/ADuM7441/ADuM7442

POWER CONSUMPTION

The supply current at a given channel of the ADuM744x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

= I

I

DDI

× (2f − fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

Figure 18. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM744x transformers. Figure 19 shows these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM744x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted previously, a 1.2 kA current would have to be placed 5 mm away from the ADuM744x to affect the operation of the component.

= I

DDO

= (I

I

DDO

where:

I

, I

DDI (D)

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz); it is half the input

data rate, expressed in units of Mbps.

f

is the input stage refresh rate (Mbps).

r

I

, I

DDI (Q)

DDO (Q)

supply currents (mA).

To calculate the total V currents for each input and output channel corresponding to V

and V

DD1

show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 shows the per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 show the total V V

supply current as a function of data rate for ADuM7440/

DD2

ADuM7441/ADuM7442 channel configurations.

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

are the input and output dynamic supply currents

are the specified input and output quiescent

and V

DD1

are calculated and totaled. Figure 8 and Figure 9

DD2

supply current, the supply

DD2

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM744x.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to

Figure 19. Maximum Allowable Current for Various

Note that at combinations of strong magnetic field and high

Current-to-ADuM744x Spacings

frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

failure at the actual working voltage. The values shown in Table 18 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

f ≤ 0.5 fr

f > 0.5 fr

DDO (Q)

f > 0.5 fr

and

DD1

Rev. C | Page 15 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet

0V

RATED PEAK VOL TAGE

08340-011

0V

RATED PEAK VOL TAGE

08340-012

0V

RATED PEAK VOL TAGE

08340-013

The insulation lifetime of the ADuM744x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Tab l e 18 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 21 or Figure 22 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 18.

Note that the voltage presented in Figure 21 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

Figure 20. Bipolar AC Waveform

Figure 21. Unipolar AC Waveform

Figure 22. DC Waveform

Rev. C | Page 16 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

COMPLIANT TO JEDEC STANDARDS MO-137-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

16

9

8

1

SEATING PLANE

0.010 (0.25)

0.004 (0.10)

0.012 (0.30)

0.008 (0.20)

0.025 (0.64) BSC

0.041 (1.04) REF

0.010 (0.25)

0.006 (0.15)

0.050 (1.27)

0.016 (0.41)

0.020 (0.51)

0.010 (0.25)

8° 0°

COPLANARITY

0.004 (0.10)

0.065 (1.65)

0.049 (1.25)

0.069 (1.75)

0.053 (1.35)

0.197 (5.00)

0.193 (4.90)

0.189 (4.80)

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

01-28-2008-A

Number

DD1

Number

DD2

Maximum

ADuM7440CRQZ

4 0 25 Mbps

50 ns

5

−40°C to +105°C

16-Lead QSOP

RQ-16

ADuM7441CRQZ

3 1 25 Mbps

50 ns

5

−40°C to +105°C

16-Lead QSOP

RQ-16

OUTLINE DIMENSIONS

Figure 23. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

of Inputs,

Model1

ADuM7440ARQZ

V

4 0 1 Mbps 75 ns 25 −40°C to +105°C 16-Lead QSOP RQ-16

ADuM7440ARQZ-RL7 4 0 1 Mbps 75 ns 25 −40°C to +105°C 16-L ea d QS O P,

ADuM7440CRQZ-RL7 4 0 25 Mbps 50 ns 5 −40°C to +105°C 16-Lead QS O P,

ADuM7441ARQZ

3 1 1 Mbps 75 ns 25 −40°C to +105°C 16-Lead QSOP RQ-16

ADuM7441ARQZ-RL7 3 1 1 Mbps 75 ns 25 −40°C to +105°C 16-L ea d QS O P,

ADuM7441CRQZ-RL7 3 1 25 Mbps 50 ns 5 −40°C to +105°C 16-Le a d QS O P,

ADuM7442ARQZ

2 2 1 Mbps 75 ns 25 −40°C to +105°C 16-Lead QSOP RQ-16

ADuM7442ARQZ-RL7 2 2 1 Mbps 75 ns 25 −40°C to +105°C 16-L ea d QS O P,

ADuM7442CRQZ

2 2 25 Mbps 50 ns 5 −40°C to +105°C 16-Lead QSOP RQ-16

ADuM7442CRQZ-RL7 2 2 25 Mbps 50 ns 5 −40°C to +105°C 16-Le a d QS O P,

1

Z = RoHS Compliant Part.

Side

of Inputs, V

Side

Maximum Data Rate

Propagation Delay, 5 V

Pulse Width Distortion (ns)

Temperature Range

Package Description

7” Tape and Reel

Package Option

RQ-16

Rev. C | Page 17 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet

NOTES

Rev. C | Page 18 of 20

Data Sheet ADuM7440/ADuM7441/ADuM7442

NOTES

Rev. C | Page 19 of 20

ADuM7440/ADuM7441/ADuM7442 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D08340-0-2/12(C)

Rev. C | Page 20 of 20

Datasheet ADUM7440 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE