Datasheet ADuM6200 Datasheet (ANALOG DEVICES)

Dual-Channel, 5 kV Isolators with

Data Sheet

Integrated DC-to-DC Converter

ADuM6200/ADuM6201/ADuM6202

FEATURES

isoPower integrated, isolated dc-to-dc converter
Regulated 5 V or 3.3 V output
Up to 400 mW output power
Dual dc-to-25 Mbps (NRZ) signal isolation channels
16-lead SOIC wide body package version
16-lead SOIC wide body enhanced creepage version
High temperature operation: 105°C maximum
Safety and regulatory approvals

UL recognition

5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A (Pending)

IEC 60601-1: 250 V rms, 8 mm package (RI-16-1)
IEC 60950-1: 400 V rms, 8 mm package (RI-16-1)

VDE Certificate of Conformity (RW-16) (Pending)

IEC 60747-5-2 (VDE 0884 Part 2):2003-01
V

= 846 V peak

IORM

VDE Certificate of Conformity, 8 mm package (RI-16-1)

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V

= 846 V peak

IORM

APPLICATIONS

RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Isolated sensor interfaces
Industrial PLCs

V

DD1

GND

VIA/V

VIB/V

RC

RC

SEL

VE1/NC

GND

NC = NO CONNECT

GENERAL DESCRIPTION

The ADuM6200/ADuM6201/ADuM62021 are dual-channel
digital isolators with isoPower®, an integrated, isolated dc-to-dc
converter. Based on the Analog Devices, Inc., iCoupler® technology,
the dc-to-dc converter provides up to 400 mW of regulated, iso­lated power at either 5.0 V or 3.3 V from a 5.0 V input supply, or
at 3.3 V from a 3.3 V supply at the power levels shown in Tab l e 1.
These devices eliminate the need for a separate, isolated dc-to-dc
converter in low power, isolated designs. The iCoupler chip scale
transformer technology is used to isolate the logic signals and for
the magnetic components of the dc-to-dc converter. The result
is a small form factor, total isolation solution.

The ADuM6200/ADuM6201/ADuM6202 isolators provide two
independent isolation channels in a variety of channel configura­tions and data rates (see the Ordering Guide for more information).

isoPower uses high frequency switching elements to transfer power
through its transformer. Special care must be taken during printed
circuit board (PCB) layout to meet emissions standards. See the

AN-0971 Application Note for board layout recommendations.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329; other patents are pending.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Table 1. Power Levels

Input Voltage (V) Output Voltage (V) Output Power (mW)

5.0 5.0 400

5.0 3.3 330

3.3 3.3 132

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010–2011 Analog Devices, Inc. All rights reserved.

FUNCTIONAL BLOCK DIAGRAMS

OA

OB

1

IN

1

1

2

3

4

5

6

7

8

OSCILLATOR

2-CHANNEL iCOUPLER CORE

V

IA

V

IB

V

IA

V

OB

V

OA

V

OB

RECTIFIER

ADuM6200/
ADuM6201/

ADuM6202

Figure 1.

3

14

ADuM6200

4

13

Figure 2. ADuM6200

3

14

ADuM6201

4

13

Figure 3. ADuM6201

3

14

ADuM6202

4

13

Figure 4. ADuM6202

REGULATOR

V

OA

V

OB

V

OA

V

IB

V

IA

V

IB

16

V

ISO

15

GND

ISO

14

VIA/V

OA

13

VIB/V

OB

12

NC

V

11

SEL

VE2/NC

10

GND

9

ISO

08775-001

08775-002

08775-003

08775-004

ADuM6200/ADuM6201/ADuM6202 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Primary Input Supply/5 V

Secondary Isolated Supply .......................................................... 3

Electrical Characteristics—3.3 V Primary Input Supply/3.3 V

Secondary Isolated Supply .......................................................... 4

Electrical Characteristics—5 V Primary Input Supply/3.3 V

Secondary Isolated Supply .......................................................... 6

Package Characteristics ............................................................... 7

Regulatory Information............................................................... 8

Insulation and Safety-Related Specifications............................ 8

IEC 60747-5-2 (VDE 0884 Part 2):2003-01 Insulation

Characteristics .............................................................................. 9

Recommended Operating Conditions ...................................... 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10









Pin Configurations and Function Descriptions......................... 11

Truth Table.................................................................................. 13

Typical Performance Characteristics........................................... 14

Terminology.................................................................................... 17

Applications Information.............................................................. 18

PCB Layout ................................................................................. 18

Start-Up Behavior....................................................................... 18

EMI Considerations................................................................... 19

Propagation Delay Parameters ................................................. 19

DC Correctness and Magnetic Field Immunity..................... 19

Power Consumption .................................................................. 20

Current Limit and Thermal Overload Protection ................. 21

Power Considerations................................................................ 21

Thermal Analysis ....................................................................... 22

Increasing Available Power ....................................................... 22

Insulation Lifetime..................................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 25

REVISION HISTORY

8/11—Rev. A to Rev. B

Change to Features Section............................................................. 1

Changes to Table 15.......................................................................... 8

8/11—Rev. 0 to Rev. A

Added 16-Lead SOIC (RI-16-1) Package........................Universal

Changes to Features Section............................................................ 1

Changes to Table 15 and Table 16 .................................................. 8

Changes to Table 20........................................................................ 10

10/10—Revision 0: Initial Version

Rev. B | Page 2 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY

Typical specifications are at TA = 25°C, V
operation range, which is 4.5 V ≤ V
tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

L

DD1

Table 2. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC-TO-DC CONVERTER SUPPLY

Setpoint V
Line Regulation V
Load Regulation V
Output Ripple V
Output Noise V
Switching Frequency f
PWM Frequency f
Output Supply Current I
Efficiency at I
I

, No V

DD1

I

DD1

, Full V

ISO

ISO

32 % I

ISO(MAX)

Load I

Load I

ISO

ISO(LINE)

ISO(LOAD)

ISO(RIP)

ISO(NOISE)

OSC

PWM

ISO(MAX)

DD1(Q)

DD1(MAX)

= V

= V

DD1

SEL

, V

, V

≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are

SEL

ISO

4.7 5.0 5.4 V I
1 mV/V I

1 5 % I

= 5 V. Minimum/maximum specifications apply over the entire recommended

ISO

= 0 mA

ISO

= 40 mA, V

ISO

= 8 mA to 72 mA

ISO

= 4.5 V to 5.5 V

DD1

75 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, I

200 mV p-p CBO = 0.1 μF||10 μF, I

= 72 mA

ISO

180 MHz

625 kHz

80 mA V

> 4.5 V

ISO

= 80 mA

ISO

10 26 mA

290 mA

= 72 mA

ISO

Table 3. DC-to-DC Converter Dynamic Specifications

1 Mbps—A or C Grade 25 Mbps—C Grade

Parameter Symbol

Min Typ Max Min Typ Max

Unit

Test Conditions/
Comments

SUPPLY CURRENT

Input I

ADuM6200 9 34 mA No V
ADuM6201 10 38 mA No V
ADuM6202 11 41 mA No V

Available to Load I

ADuM6200

DD1(D)

ISO(LOAD)

80 74 mA

ISO

ISO

ISO

load
load
load

ADuM6201 80 72 mA
ADuM6202 80 70 mA

Table 4. Switching Specifications

A Grade C Grade

Parameter Symbol

Min Typ Max Min Typ Max

Unit

Test Conditions/
Comments

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit
Propagation Delay t
Pulse Width Distortion PWD 40 6 ns |t

, t

55 100 45 60 ns 50% input to 50% output

PHL

PLH

− t

PHL

|

PLH

Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew t

50 15 ns Between any two units

PSK

Channel Matching

Codirectional1 t

Opposing Directional2 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the

isolation barrier.

50 6 ns

PSKCD

50 15 ns

PSKOD

Rev. B | Page 3 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

Table 5. Input and Output Characteristics

Test Conditions/

Parameter Symbol Min Typ Max Unit

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages VOH V
V

− 0.3 or V

DD1

− 0.5 or V

DD1

or 0.7 × V

ISO

V

DD1

or 0.3 × V

ISO

− 0.3 5.0 V IOx = −20 μA, VIx = V

ISO

− 0.5 4.8 V IOx = −4 mA, VIx = V

ISO

V

DD1

Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V
Undervoltage Lockout UVLO V

Positive-Going Threshold V
Negative-Going Threshold V
Hysteresis V

UV+

UV−

UVH

2.7 V

2.4 V

0.3 V

Input Currents per Channel II −20 +0.01 +20 μA 0 V ≤ VIx ≤ V

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient

Immunity

1

|CM| 25 35 kV/μs

Refresh Rate fr 1.0 Mbps

1

|CM | is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

or 0.7 × V

DD1

for a high input or VO < 0.3 × V

ISO

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

Typical specifications are at TA = 25°C, V
recommended operation range, which is 3.0 V ≤ V
specifications are tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

L

DD1

= V

= 3.3 V, V

ISO

, V

DD1

= GND

SEL

, V

≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching

SEL

ISO

. Minimum/maximum specifications apply over the entire

ISO

Comments

IxH

IxH

IxL

IxL

, V

supplies

DD1

ISO

DDx

= V

or V

V

Ix

DD1

, VCM = 1000 V,

ISO

transient magnitude = 800 V

or 0.3 × V

DD1

for a low

ISO

Table 6. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC-TO-DC CONVERTER SUPPLY

Setpoint V
Line Regulation V
Load Regulation V
Output Ripple V
Output Noise V
Switching Frequency f
PWM Frequency f
Output Supply Current I
Efficiency at I
I

, No V

DD1

I

DD1

, Full V

ISO

ISO

29 % I

ISO(MAX)

Load I

Load I

3.0 3.3 3.6 V I

ISO

1 mV/V I

ISO(LINE)

1 5 % I

ISO(LOAD)

50 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, I

ISO(RIP)

130 mV p-p CBO = 0.1 μF||10 μF, I

ISO(NOISE)

180 MHz

OSC

625 kHz

PWM

40 mA V

ISO(MAX)

10 17 mA

DD1(Q)

175 mA

DD1(MAX)

= 0 mA

ISO

= 20 mA, V

ISO

= 4 mA to 36 mA

ISO

> 3 V

ISO

= 40 mA

ISO

DD1

= 3.0 V to 3.6 V

= 36 mA

ISO

= 36 mA

ISO

Rev. B | Page 4 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

Table 7. DC-to-DC Converter Dynamic Specifications

1 Mbps—A or C Grade 25 Mbps—C Grade

Parameter Symbol

Min Typ Max Min Typ Max

Unit

SUPPLY CURRENT

Input I

DD1(D)

ADuM6200 6 23 mA No V

ADuM6201 7 25 mA No V

ADuM6202 8 27 mA No V
Available to Load I

ADuM6200

ISO(LOAD)

40 36 mA
ADuM6201 40 35 mA
ADuM6202 40 34 mA

Table 8. Switching Specifications

A Grade C Grade

Parameter Symbol

Min Typ Max Min Typ Max

Unit

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit
Propagation Delay t

, t

60 100 45 65 ns 50% input to 50% output

PHL

PLH

Pulse Width Distortion PWD 40 6 ns |t

Change vs. Temperature 5 ps/°C

Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew t

50 45 ns Between any two units

PSK

Channel Matching

Codirectional1 t
Opposing Directional2 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the

isolation barrier.

50 6 ns

PSKCD

50 15 ns

PSKOD

Test Conditions/
Comments

load

ISO

load

ISO

load

ISO

Test Conditions/
Comments

− t

PHL

|

PLH

Table 9. Input and Output Characteristics

Test Conditions/

Parameter Symbol Min Typ Max Unit

Comments

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages VOH V
V

− 0.3 or V

DD1

− 0.5 or V

DD1

or 0.7 × V

ISO

V

DD1

or 0.3 × V

ISO

− 0.3 3.3 V IOx = −20 μA, VIx = V

ISO

− 0.5 3.1 V IOx = −4 mA, VIx = V

ISO

V

DD1

Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.0 0.4 V IOx = 4 mA, VIx = V
Undervoltage Lockout UVLO V

Positive-Going Threshold V
Negative-Going Threshold V
Hysteresis V

UV+

UV−

UVH

2.7 V

2.4 V

0.3 V

DD1

, V

ISO

supplies

Input Currents per Channel II −20 +0.01 +20 μA 0 V ≤ VIx ≤ V

DDx

IxL

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient

Immunity

1

|CM| 25 35 kV/μs

V

Ix

transient magnitude = 800 V

= V

DD1

or V

ISO

, VCM = 1000 V,

Refresh Rate fr 1.0 Mbps

1

|CM | is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. B | Page 5 of 28

or 0.7 × V

DD1

for a high input or VO < 0.3 × V

ISO

or 0.3 × V

DD1

IxH

IxH

IxL

for a low

ISO

ADuM6200/ADuM6201/ADuM6202 Data Sheet

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

Typical specifications are at TA = 25°C, V
recommended operation range, which is 4.5 V ≤ V
Switching specifications are tested with C

Table 10. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC-TO-DC CONVERTER SUPPLY

Setpoint V
Line Regulation V
Load Regulation V
Output Ripple V
Output Noise V
Switching Frequency f
PWM Frequency f
Output Supply Current I
Efficiency at I
I

, No V

DD1

I

DD1

, Full V

ISO

ISO

25 % I

ISO(MAX)

Load I

Load I

ISO

ISO(LINE)

ISO(LOAD)

ISO(RIP)

ISO(NOISE)

OSC

PWM

ISO(MAX)

DD1(Q)

DD1(MAX)

Table 11. DC-to-DC Converter Dynamic Specifications

Parameter Symbol

SUPPLY CURRENT

Input I

DD1(D)

ADuM6200 6 22 mA No V
ADuM6201 6 23 mA No V
ADuM6202 6 24 mA No V

Available to Load I

ADuM6200

ISO(LOAD)

ADuM6201 100 95 mA
ADuM6202 100 94 mA

= 5.0 V, V

DD1

= 15 pF and CMOS signal levels, unless otherwise noted.

L

3.0 3.3 3.6 V I
1 mV/V I

1 5 % I

= 3.3 V, V

ISO

≤ 5.5 V, 3.0 V ≤ V

DD1

= GND

SEL

. Minimum/maximum specifications apply over the entire

ISO

≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted.

ISO

= 0 mA

ISO

= 50 mA, V

ISO

= 6 mA to 54 mA

ISO

= 3.0 V to 3.6 V

DD1

50 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, I

130 mV p-p CBO = 0.1 μF||10 μF, I

= 90 mA

ISO

180 MHz

625 kHz

100 mA V

> 3 V

ISO

= 100 mA

ISO

7 13 mA

230 mA

1 Mbps—A or C Grade 25 Mbps—C Grade

Min Typ Max Min Typ Max

Unit

Test Conditions/
Comments

ISO

ISO

ISO

100 96 mA

load
load
load

= 90 mA

ISO

Table 12. Switching Specifications

A Grade C Grade

Parameter Symbol

Min Typ Max Min Typ Max

Unit

Test Conditions/
Comments

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit
Propagation Delay t
Pulse Width Distortion PWD 40 6 ns |t

, t

60 100 45 65 ns 50% input to 50% output

PHL

PLH

− t

PHL

|

PLH

Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew t

50 15 ns Between any two units

PSK

Channel Matching

Codirectional1 t

Opposing Directional2 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the

isolation barrier.

50 6 ns

PSKCD

50 15 ns

PSKOD

Rev. B | Page 6 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

Table 13. Input and Output Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions/ Comments

DC SPECIFICATIONS

Logic High Input Threshold VIH

0.7 × V

0.7 × V

ISO

DD1

or

Logic Low Input Threshold VIL

Logic High Output Voltages VOH

V

DD1

V

ISO

V

DD1

V

ISO

− 0.3 or

− 0.3

− 0.5 or

− 0.5

Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.0 0.4 V IOx = 4 mA, VIx = V
Undervoltage Lockout UVLO V

Positive-Going Threshold V
Negative-Going Threshold V
Hysteresis V

UV+

UV−

UVH

2.7 V

2.4 V

0.3 V

Input Currents per Channel II −20 +0.01 +20 μA 0 V ≤ VIx ≤ V

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient

Immunity

1

|CM| 25 35 kV/μs

Refresh Rate fr 1.0 Mbps

1

|CM | is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

V

V

for a high input or VO < 0.3 × V

ISO

V

DD1

V

DD1

V

ISO

ISO

DD1

or

0.3 × V

0.3 × V

or V

V IOx = −20 μA, VIx = V

ISO

− 0.2 or

V I

− 0.2

or 0.7 × V

DD1

IxH

= −4 mA, VIx = V

Ox

, V

supplies

DD1

ISO

DDx

= V

V

or V

Ix

DD1

IxH

IxL

IxL

, VCM = 1000 V,

ISO

transient magnitude = 800 V

or 0.3 × V

DD1

for a low

ISO

PACKAGE CHARACTERISTICS

Table 14.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

RESISTANCE AND CAPACITANCE

Resistance (Input-to-Output)1 R
Capacitance (Input-to-Output)1 C
Input Capacitance2 C
IC Junction-to-Ambient Thermal

Resistance

THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD 150 °C TJ rising
Thermal Shutdown Hysteresis TS

1

This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

3

Refer to the section for thermal model definitions. Thermal Analysis

1012 Ω

I-O

2.2 pF f = 1 MHz

I-O

4.0 pF

I

45 °C/W

θ

JA

Thermocouple is located at the center of
the package underside; test conducted
on a 4-layer board with thin traces

20 °C

SD-HYS

3

Rev. B | Page 7 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

REGULATORY INFORMATION

The ADuM6200/ADuM6201/ADuM6202 are approved by the organizations listed in Tab l e 1 5 . Refer to Tabl e 20 and the Insulation Lifetime
section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels.

Table 15.

UL1 CSA VDE2

Recognized under UL 1577 component
recognition program

Single protection, 5000 V rms isolation
voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM6200/ADuM6201/ADuM6202 is proof-tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec (current leakage

detection limit = 15 μA).

2

In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM6200/ADuM6201/ADuM6202 is proof-tested by applying an insulation test voltage ≥ 1590 V peak

for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval.

3

In accordance with DIN V VDE V 0884-10, each ADuM6200/ADuM6201/ADuM6202 is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 sec

(partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-07 and IEC 60950-1,
600 V rms (848 V peak) maximum working voltage

RW-16 package: reinforced insulation per CSA 60950-1-07
and IEC 60950-1, 380 V rms (537 V peak) maximum working
voltage, reinforced insulation per IEC 60601-1 125 V rms
(176 V peak) maximum working voltage

(Pending) RI-16-1 package: reinforced insulation per
CSA 60950-1-07 and IEC 60950-1, 400 V rms (565 V peak)
maximum working voltage, reinforced insulation per IEC
60601-1 250 V rms (353 V peak) maximum working voltage

RI-16-1 package: certified
according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-123;
reinforced insulation, 846 V peak

(Pending) RW-16 package:
certified according to IEC 60747-5-2

(VDE 0884 Part 2):2003-01, basic
insulation, 846 V peak

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 16.

Parameter Symbol Value Unit Test Conditions/Comments

Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 8.0 mm

Minimum External Tracking (Creepage),

L (I02) 7.6 mm

RW-16 Package

Minimum External Tracking (Creepage),

L (I02) 8.3 min mm

RI-16-1 Package

Minimum Internal Distance (Internal Clearance) 0.017 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1
Material Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Measured from input terminals to output terminals,
shortest distance through air

Measured from input terminals to output terminals,
shortest distance path along body

Measured from input terminals to output terminals,
shortest distance path along body

Rev. B | Page 8 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

IEC 60747-5-2 (VDE 0884 PART 2):2003-01 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking branded on the components designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval.

Table 17.

Description Test Conditions/Comments Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 450 V rms I to II

For Rated Mains Voltage ≤ 600 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage V
Input-to-Output Test Voltage

Method b1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Method a VPR

After Environmental Tests Subgroup 1 V
After Input and/or Safety Test

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 1375 V peak

IORM

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak

V

IORM

Subgroup 2 and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec V
Safety-Limiting Values

Maximum value allowed in the event of a failure

(see Figure 5)
Case Temperature TS 150 °C
Side 1 Current (I

Insulation Resistance at TS V

) IS1 555 mA

DD1

= 500 V RS >109 Ω

IO

846 V peak

IORM

1590 V peak

V

PR

6000 V peak

IOTM

Thermal Derating Curve

600

500

400

CURRENT (mA)

DD1

300

200

100

SAFE OPERATING V

0

0501001502

Figure 5. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN EN 60747-5-2

AMBIENT TEM P E RATURE (°C)

00

08775-107

RECOMMENDED OPERATING CONDITIONS

Table 18.

Parameter Symbol Min Max Unit Test Conditions/Comments

TEMPERATURE

Operating Temperature TA −40 +105 °C

SUPPLY VOLTAGES Each voltage is relative to its respective ground

V

@ V

DD1

V

DD1

= 0 V V

SEL

@ V

= V

V

SEL

ISO

3.0 5.5 V

DD1

4.5 5.5 V

DD1

Operation at 105°C requires reduction of the
maximum load current as specified in Table 19

Rev. B | Page 9 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 19.

Parameter Rating

Storage Temperature (TST) −55°C to +150°C
Ambient Operating Temperature (TA) −40°C to +105°C
Supply Voltages (V
Input Voltage (VIA, VIB, VE1, VE2, V

RC

IN

, RC

1, 2

)

SEL

Output Voltage (VOA, VOB)

, V

)1 −0.5 V to +7.0 V

DD1

ISO

−0.5 V to V

,

SEL

+ 0.5 V

DDI

1, 2

−0.5 V to V

DDO

+ 0.5 V
Average Output Current per Pin3 −10 mA to +10 mA
Common-Mode Transients4 −100 kV/μs to +100 kV/μs

1

Each voltage is relative to its respective ground.

2

V

and V

DDI

a given channel, respectively. See the PCB Layout section.

3

See Figure 5 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the isolation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.

refer to the supply voltages on the input and output sides of

DDO

Table 20. Maximum Continuous Working Voltage

1

Parameter Max Unit Applicable Certification

AC Voltage, Bipolar Waveform 424 V peak All certifications, 50-year operation
AC Voltage, Unipolar Waveform

Basic Insulation 600 V peak
Reinforced Insulation 565 V peak Working voltage per IEC 60950-1

DC Voltage

Basic Insulation 600 V peak
Reinforced Insulation 565 V peak Working voltage per IEC 60950-1

1

Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 10 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

RC

GND

V

RC

DD1

V
V

SEL

NC

1
2

1

3

IA

4

IB

5

IN

6
7
8

1

ADuM6200

TOP VIEW

(Not to S cal e)

V

16

ISO

15

GND

ISO

14

V

OA

V

13

OB

NC

12
11

V

SEL

10

V

E2

GND

9

ISO

Table 21. ADuM6200 Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2, 8 GND1

Primary Supply Voltage, 3.0 V to 5.5 V.

DD1

Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other,

and it is recommended that both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 RCIN

Regulation Control Input. This pin must be connected to the RC

This pin must not be tied high if RC

of the isolator, damaging the ADuM6200 and possibly the devices that it powers.
6 RC

SEL

Control Input. Determines self-regulation mode (RC

regulation. This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
7, 12 NC No Internal Connection.
9, 15 GND

ISO

Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each

other, and it is recommended that both pins be connected to a common ground.
10 VE2

Data Enable Input. When this pin is high or not connected, the secondary outputs are active; when this pin is

low, the outputs are in a high-Z state.
11 V

SEL

Output Voltage Selection. When V

In slave regulation mode, this pin has no function.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 V

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

ISO

NC = NO CONNECT

Figure 6. ADuM6200 Pin Configuration

is low; this combination causes excessive voltage on the secondary side

SEL

high) or slave mode (RC

SEL

= V

, the V

SEL

ISO

setpoint is 5.0 V. When V

ISO

08775-006

pin of a master isoPower device or tied low.

OUT

low), allowing external

SEL

= GND

SEL

ISO

, the V

setpoint is 3.3 V.

ISO

Rev. B | Page 11 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

RC

V

GND

V

RC

V

GND

DD1

V

SEL

1

IA

OB

IN

E1

1

1
2
3

ADuM6201

4

TOP VIEW

(Not to S cal e)

5
6
7
8

V

16

ISO

15

GND

ISO

14

V

OA

V

13

IB

NC

12
11

V

SEL

10

V

E2

GND

9

ISO

Table 22. ADuM6201 Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2, 8 GND1

Primary Supply Voltage, 3.0 V to 5.5 V.

DD1

Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other,

and it is recommended that both pins be connected to a common ground.
3 VIA Logic Input A.
4 VOB Logic Output B.
5 RCIN

Regulation Control Input. This pin must be connected to the RC

This pin must not be tied high if RC

of the isolator, damaging the ADuM6201 and possibly the devices that it powers.
6 RC

SEL

Control Input. Determines self-regulation mode (RC

regulation. This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
7 VE1

Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low,

the output is in a high-Z state.
9, 15 GND

ISO

Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each

other, and it is recommended that both pins be connected to a common ground.
10 VE2

Data Enable Input. When this pin is high or not connected, the secondary output is active; when this pin is low,

the output is in a high-Z state.
11 V

SEL

Output Voltage Selection. When V

In slave regulation mode, this pin has no function.
12 NC No Internal Connection.
13 VIB Logic Input B.
14 VOA Logic Output A.
16 V

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

ISO

NC = NO CONNECT

Figure 7. ADuM6201 Pin Configuration

is low; this combination causes excessive voltage on the secondary side

SEL

high) or slave mode (RC

SEL

= V

, the V

SEL

ISO

setpoint is 5.0 V. When V

ISO

08775-007

pin of a master isoPower device or tied low.

OUT

low), allowing external

SEL

= GND

SEL

ISO

, the V

setpoint is 3.3 V.

ISO

Rev. B | Page 12 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

GND

RC

GND

V

RC

DD1

V
V

SEL

V

1
OA
OB

IN

E1

1

1
2
3

ADuM6202

4

TOP VIEW

(Not to S cale)

5
6
7
8

V

16

ISO

GND

15

ISO

14

V

IA

13

V

IB

NC

12

V

11

SEL

10

NC
GND

9

ISO

Table 23. ADuM6202 Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2, 8 GND1

Primary Supply Voltage, 3.0 V to 5.5 V.

DD1

Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other,

and it is recommended that both pins be connected to a common ground.
3 VOA Logic Output A.
4 VOB Logic Output B.
5 RCIN

Regulation Control Input. This pin must be connected to the RC

This pin must not be tied high if RC

of the isolator, damaging the ADuM6202 and possibly the devices that it powers.
6 RC

SEL

Control Input. Determines self-regulation mode (RC

regulation. This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
7 VE1

Data Enable Input. When this pin is high or not connected, the primary outputs are active; when this pin is low,

the outputs are in a high-Z state.
9, 15 GND

ISO

Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each

other, and it is recommended that both pins be connected to a common ground.
10, 12 NC No Internal Connection.
11 V

SEL

Output Voltage Selection. When V

In slave regulation mode, this pin has no function.
13 VIB Logic Input B.
14 VIA Logic Input A.
16 V

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

ISO

NC = NO CONNECT

Figure 8. ADuM6202 Pin Configuration

is low; this combination causes excessive voltage on the secondary side

SEL

high) or slave mode (RC

SEL

= V

, the V

SEL

ISO

setpoint is 5.0 V. When V

ISO

08775-008

pin of a master isoPower device or tied low.

OUT

low), allowing external

SEL

= GND

SEL

ISO

, the V

setpoint is 3.3 V.

ISO

TRUTH TABLE

Table 24. Power Control Truth Table (Positive Logic)

RC

SEL

Input

RCIN
Input

V

SEL

Input

V

DD1

Input

H X H 5 V 5 V Self-regulation mode, normal operation
H X L 5 V 3.3 V Self-regulation mode, normal operation
H X L 3.3 V 3.3 V Self-regulation mode, normal operation
H X H 3.3 V 5 V This supply configuration is not recommended due to extremely poor efficiency
L H X X X Part runs at maximum open-loop voltage; damage can occur
L L X X 0 V Power supply disabled
L RC

1

V

must be common between all isoPower devices being regulated by a master isoPower part.

DD1

OUT(EXT)

X X1 X

V

1

ISO

Output

Operation

Slave mode; RC

supplied by a master isoPower device

OUT(EXT)

Rev. B | Page 13 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

A

R

TYPICAL PERFORMANCE CHARACTERISTICS

35

4.0

4.0

30

25

20

15

EFFICIENCY (%)

10

5

0

5.0V INPUT /5.0V OUTPUT

5.0V INPUT /3.3V OUTPUT

3.3V INPUT /3.3V OUTPUT

0 20406080100120

I

CURRENT (mA)

ISO

Figure 9. Typical Power Supply Efficiency

in All Supported Power Configurations

120

100

80

60

CURRENT (mA)

40

ISO

I

20

0

0 50 100 150 200 250 300

5.0V INPUT/5.0V O UTPUT

5.0V INPUT/3.3V O UTPUT

3.3V INPUT/3.3V O UTPUT

I

CURRENT (mA)

DD1

Figure 10. Typical Isolated Output Supply Current vs. Input Current

in All Supported Power Configurations

3.5

3.0

2.5

ENT (A)

2.0

1.5

INPUT CUR

1.0

0.5

0

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6 .5

08775-124

INPUT SUPPLYVOLTAGE (V)

POWER

I

DD1

3.0

2.0

1.0

3.5

2.5

1.5

0.5

0

POWER (W)

8775-036

Figure 12. Typical Short-Circuit Input Current and Power

Supply Voltage

vs. V

DD1

5.4

5.2

(V)

5.0

ISO

V

4.8

4.6

40

20

(mA)

10% LOAD

ISO

I

0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

8775-125

Figure 13. Typical V

90% LOAD

10% LOAD

TIME (ms)

Transient Load Response, 5 V Output,

ISO

08775-127

10% to 90% Load Step

1200

1000

800

TION (mW)

600

400

5.0V INPUT /5.0V OUTPUT

TOTAL POWER D ISSIP

200

0

0 20406080100120

5.0V INPUT /3.3V OUTPUT

3.3V INPUT /3.3V OUTPUT

I

CURRENT (mA)

ISO

Figure 11. Typical Total Power Dissipation vs. Isolated Output Supply

Current in All Supported Power Configurations

8775-126

3.7

3.5

(V)

ISO

3.3

V

3.1

60

40

20

(mA)

10% LOAD

ISO

I

0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Figure 14. Typical V

90% LOAD

10% LOAD

TIME (ms)

Transient Load Response, 3.3 V Output,

ISO

10% to 90% Load Step

08775-128

Rev. B | Page 14 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

5.02

5.00

4.98

(V)

4.96

ISO

V

4.94

4.92

4.90

5.0

2.5

RC

SIGNAL (V)

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

TIME (µs)

Figure 15. Typical Output Voltage Ripple at 90% Load, V

ISO

= 5 V

8775-129

5

4

3

(V)

ISO

V

2

1

0
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0

90% LOAD
10% LOAD

Time (ms)

Figure 18. Typical Output Voltage Start-Up Transient

at 10% and 90% Load, V

= 3.3 V

ISO

08775-132

3.34

3.32

3.30

(V)

ISO

V

3.28

3.26

3.24
4

2

RC

SIGNAL (V)

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

TIME (µs)

Figure 16. Typical Output Voltage Ripple at 90% Load, V

7

6

5

4

(V)

ISO

V

3

2

1

90% LOAD
10% LOAD

= 3.3 V

ISO

20

16

12

SUPPLY CURRENT ( mA)

08775-130

Figure 19. Typical I

5.0V INPUT/5.0V O UTPUT

5.0V INPUT/3.3V O UTPUT

3.3V INPUT/3.3V O UTPUT

8

4

0

051015

DATA RATE (Mbps)

Supply Current per Forward Data Channel

CHn

20 25

08775-041

(15 pF Output Load)

20

16

12

SUPPLY CURRENT (mA)

5.0V INPUT/5.0V O UTPUT

5.0V INPUT/3.3V O UTPUT

3.3V INPUT/3.3V O UTPUT

8

4

0
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0

TIME (ms)

Figure 17. Typical Output Voltage Start-Up Transient

at 10% and 90% Load, V

ISO

= 5 V

08775-131

Rev. B | Page 15 of 28

0

051015

Figure 20. Typical I

DATA RATE (Mbps)

Supply Current per Reverse Data Channel

CHn

(15 pF Output Load)

20 25

08775-042

ADuM6200/ADuM6201/ADuM6202 Data Sheet

5

3.0

4

3

5V

2

SUPPLY CURRENT (mA)

1

0

051015

Figure 21. Typical I

ISO(D)

3.3V

DATA RATE (Mbps)

Dynamic Supply Current per Input

20 25

08775-043

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

051015

Figure 22. Typical I

5V

3.3V

DATA RATE (Mbps)

Dynamic Supply Current per Output

ISO(D)

20 25

08775-044

(15 pF Output Load)

Rev. B | Page 16 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

TERMINOLOGY

I

DD1(Q)

I

is the minimum operating current drawn at the V

DD1(Q)

pin when there is no external load at V

and the I/O pins are

ISO

DD1

operating below 2 Mbps, requiring no additional dynamic
supply current. I

reflects the minimum current operating

DD1(Q)

condition.

I

DD1(D)

I

is the typical input supply current with all channels

DD1(D)

simultaneously driven at a maximum data rate of 25 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Resistive loads on the outputs should be
treated separately from the dynamic load.

I

I

DD1(MAX)

is the input current under full dynamic and V

DD1(MAX)

ISO

load

conditions.

I

ISO(LOAD)

I

t

The t
the falling edge of the V
edge of the V

is the current available to the load.

ISO(LOAD)

Propagation Delay

PHL

propagation delay is measured from the 50% level of

PHL

signal to the 50% level of the falling

Ix

signal.

Ox

Propagation Delay

t

PLH

The t

propagation delay is measured from the 50% level of

PLH

the rising edge of the V
edge of the V

signal.

Ox

Propagation Delay Skew (t

t

is the magnitude of the worst-case difference in t

PSK

that is measured between units at the same operating

or t

PLH

signal to the 50% level of the rising

Ix

)

PSK

and/

PHL

temperature, supply voltages, and output load within the
recommended operating conditions.

Channel-to-Channel Matching (t

PSKCD/tPSKOD

)

Channel-to-channel matching is the absolute value of the
difference in propagation delays between two channels when
operated with identical loads.

Minimum Pulse Width

The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.

Maximum Data Rate

The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.

Rev. B | Page 17 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

APPLICATIONS INFORMATION

The dc-to-dc converter section of the ADuM620x works on
principles that are common to most switching power supplies. It
has a secondary side controller architecture with isolated pulse­width modulation (PWM) feedback. V

power is supplied to

DD1

an oscillating circuit that switches current into a chip scale air
core transformer. Power transferred to the secondary side is
rectified and regulated to either 3.3 V or 5 V. The secondary
(V

) side controller regulates the output by creating a PWM

ISO

control signal that is sent to the primary (V

) side by a dedicated

DD1

iCoupler data channel. The PWM modulates the oscillator
circuit to control the power being sent to the secondary side.
Feedback allows for significantly higher power and efficiency.

The ADuM620x implements undervoltage lockout (UVLO)
with hysteresis on the V

power input. This feature ensures

DD1

that the converter does not enter oscillation due to noisy input
power or slow power-on ramp rates.

The ADuM620x can accept an external regulation control
signal (RC

) that can be connected to other isoPower devices.

IN

This feature allows a single regulator to control multiple power
modules without contention. When accepting control from a
master power module, the V

pins can be connected together,

ISO

adding their power. Because there is only one feedback control
path, the supplies work together seamlessly. The ADuM620x
can only regulate itself or accept regulation (slave device) from
another device in this product line; it cannot provide a
regulation signal to other devices.

PCB LAYOUT

The ADuM620x digital isolators with 0.4 W isoPower integrated
dc-to-dc converter require no external interface circuitry for the
logic interfaces. Power supply bypassing is required at the input
and output supply pins (see Figure 23). Note that low ESR bypass
capacitors are required between Pin 1 and Pin 2 and between
Pin 15 and Pin 16, as close to the chip pads as possible.

The power supply section of the ADuM620x uses a 180 MHz
oscillator frequency to pass power efficiently through its chip
scale transformers. In addition, the normal operation of the data
section of the iCoupler introduces switching transients on the
power supply pins. Bypass capacitors are required for several
operating frequencies. Noise suppression requires a low induc­tance, high frequency capacitor, whereas ripple suppression and
proper regulation require a large value capacitor. These capacitors
are most conveniently connected between Pin 1 and Pin 2 for
V

, and between Pin 15 and Pin 16 for V

DD1

To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 μF and 10 μF for V

DD1

and V
capacitor must have a low ESR; for example, use of a ceramic
capacitor is advised.

.

ISO

. The smaller

ISO

The total lead length between the ends of the low ESR capacitor
and the input power supply pin must not exceed 2 mm. Installing
the bypass capacitor with traces more than 2 mm in length may
result in data corruption. Consider bypassing between Pin 1
and Pin 8 and between Pin 9 and Pin 16 unless both common
ground pins are connected together close to the package.

BYPASS < 2mm

V

DD1

GND

1

VIA/V

OA

VIB/V

OB

RC

IN

RC

SEL

VE1/NC VE2/NC

GND

1

Figure 23. Recommended PCB Layout

V

ISO

GND
VOA/V
VOB/V
NC
V

SEL

GND

ISO

ISO

IA
IB

08775-020

In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
as specified in Ta ble 1 9, thereby leading to latch-up and/or
permanent damage.

The ADuM620x is a power device that dissipates approximately
1 W of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipation into
the PCB through the GND pins. If the device is used at high
ambient temperatures, provide a thermal path from the GND
pins to the PCB ground plane. The board layout in Figure 23
shows enlarged pads for Pin 8 (GND

) and Pin 9 (GND

1

ISO

).
Multiple vias should be implemented from the pad to the
ground plane to significantly reduce the temperature inside the
chip. The dimensions of the expanded pads are at the discretion
of the designer and depend on the available board space.

START-UP BEHAVIOR

The ADuM620x devices do not contain a soft start circuit.
Therefore, the start-up current and voltage behavior must be
taken into account when designing with this device.

When power is applied to V
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and the time
required to reach regulation voltage depends on the load and
the V

With a fast V
up to 100 mA/V of V

slew rate.

DD1

slew rate (200 μs or less), the peak current draws

DD1

DD1

the output can turn on, so the peak current is proportional to
the maximum input voltage.

, the input switching circuit begins

DD1

. The input voltage goes high faster than

Rev. B | Page 18 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

V

With a slow V
voltage is not changing quickly when V
minimum voltage. The current surge is approximately 300 mA
because V
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 12.

When starting the device for V
the current available to the V
The ADuM620x devices may not be able to drive the output to
the regulation point if a current-limiting device clamps the V
voltage during startup. As a result, the ADuM620x devices can
draw large amounts of current at low voltage for extended
periods of time.

The output voltage of the ADuM620x devices exhibits V
overshoot during startup. If this overshoot could potentially
damage components attached to V
such as a Zener diode can be used to clamp the voltage. Typical
behavior is shown in Figure 17 and Figure 18.

EMI CONSIDERATIONS

The dc-to-dc converter section of the ADuM620x devices must
operate at 180 MHz to allow efficient power transfer through the
small transformers. This creates high frequency currents that can
propagate in circuit board ground and power planes, causing
edge emissions and dipole radiation between the primary and
secondary ground planes. Grounded enclosures are recommended
for applications that use these devices. If grounded enclosures
are not possible, follow good RF design practices in the layout
of the PCB. See the AN-0971 Application Note for board layout
recommendations.

PROPAGATION DELAY PARAMETERS

Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high output.

INPUT (

IX

OUTPUT (V

Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM620x component.

Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM620x
components operating under the same conditions.

slew rate (in the millisecond range), the input

DD1

reaches the UVLO

DD1

is nearly constant at the 2.7 V UVLO voltage. The

DD1

= 5 V operation, do not limit

ISO

power pin to less than 300 mA.

DD1

, a voltage-limiting device

ISO

)

t

PLH

)

OX

Figure 24. Propagation Delay Parameters

t

PHL

50%

50%

ISO

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than approximately 5 μs, the

DD1

08775-118

input side is assumed to be unpowered or nonfunctional, and
the isolator output is forced to a default state by the watchdog
timer circuit.

The limitation on the magnetic field immunity of the ADuM620x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this may occur. The 3.3 V operating condition of the
ADuM620x is examined because it represents the most suscept­ible mode of operation.

The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately

0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by

V = (−dβ/dt)

2

∑ πr

; n = 1, 2, … , N

n

where:
β is the magnetic flux density (gauss).

r

is the radius of the nth turn in the receiving coil (cm).

n

N is the total number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM620x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 25.

100

10

1

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETI C F L UX

0.001
1k 10k 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 25. Maximum Allowable External Magnetic Flux Density

1M

100M100k

08775-119

Rev. B | Page 19 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approxi­mately 50% of the sensing threshold and does not cause a faulty
output transition. Similarly, if such an event occurs during a
transmitted pulse (and is of the worst-case polarity), it reduces
the received pulse from >1.0 V to 0.75 V—still well above the

0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM620x transformers. Figure 26 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 26, the ADuM620x is extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example noted, a 0.5 kA current placed 5 mm away from
the ADuM620x is required to affect the operation of the device.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALLOWABLE CURRENT (kA)

0.01
1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 26. Maximum Allowable Current

for Various Current-to-ADuM620x Spacings

8775-120

Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.

POWER CONSUMPTION

The V
channels as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
and secondary input/output channels cannot be determined
separately. All of these quiescent power demands are combined
into the I
current is the sum of the quiescent operating current, the dynamic
current I
I

ISO

power supply input provides power to the iCoupler data

DD1

current shown in Figure 27. The total I

DD1(Q)

demanded by the I/O channels, and any external

DD1(D)

load.

supply

DD1

I

DD1(Q)

I

DD1(D)

CONVERTER

PRIMARY

I

DDP(D)

PRIMARY

DATA I/O

2-CHANNEL

Figure 27. Power Consumption Within the ADuM620x

Both dynamic input and output current is consumed only
when operating at channel speeds higher than the refresh
rate, f

. Each channel has a dynamic current determined by

r

its data rate. Figure 19 shows the current for a channel in the
forward direction, which means that the input is on the primary
side of the part. Figure 20 shows the current for a channel in the
reverse direction, which means that the input is on the secondary
side of the part. Both figures assume a typical 15 pF load. The
following relationship allows the total I

I

= (I

× V

DD1

ISO

)/(E × V

ISO

where:

is the total supply input current.

I

DD1

I

is the current drawn by the secondary side external loads.

ISO

E is the power supply efficiency at the maximum load from

Figure 9 at the V

I

is the current drawn by a single channel, determined from

CHn

ISO

and V

Figure 19 or Figure 20, depending on channel direction.

Calculate the maximum external load by subtracting the
dynamic output load from the maximum allowable load.

I

ISO(LOAD)

= I

ISO(MAX)

− ∑ I

where:

I

is the current available to supply an external secondary

ISO(LOAD)

side load.

I

is the maximum external secondary side load current

ISO(MAX)

available at V

I

is the dynamic load current drawn from V

ISO(D)n

ISO

.

or output channel, as shown in Figure 19 and Figure 20 for a
typical 15 pF load.

This analysis assumes a 15 pF capacitive load on each data output.
If the capacitive load is larger than 15 pF, the additional current
must be included in the analysis of I

To d e te r mi n e I

in Equation 1, additional primary side

DD1

dynamic output current (I
Additional secondary side dynamic output current (I
is added to I

on a per-channel basis.

ISO

E

CONVERTER
SECONDARY

I

ISO(D)

SECONDARY

DATA I/O

2-CHANNEL

current to be calculated:

DD1

) + ∑ I

DD1

condition of interest.

DD1

; n = 1 to 4 (2)

ISO(D)n

) is added directly to I

AOD

; n = 1 to 4 (1)

CHn

ISO

and I

DD1

ISO(LOAD)

I

ISO

08775-021

by an input

.

.

DD1

)

AOD

Rev. B | Page 20 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

To d e te r mi n e I
side output current (I

in Equation 2, additional secondary

ISO(LOAD)

) is subtracted from I

AOD

ISO(MAX)

on a

per-channel basis.

For each output channel with C

greater than 15 pF, the

L

additional capacitive supply current is given by

I

= 0.5 × 10−3 × ((CL − 15) × V

AOD

) × (2f − fr); f > 0.5 fr (3)

ISO

where:

C

is the output load capacitance (pF).

L

is the output supply voltage (V).

V

ISO

f is the input logic signal frequency (MHz); it is half the input

data rate expressed in units of Mbps.

f

is the input channel refresh rate (Mbps).

r

CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION

The ADuM620x is protected against damage due to excessive
power dissipation by thermal overload protection circuits.
Thermal overload protection limits the junction temperature to
a maximum of 150°C (typical). Under extreme conditions (that
is, high ambient temperature and power dissipation), when the
junction temperature starts to rise above 150°C, the PWM is
turned off, turning off the output current. When the junction
temperature drops below 130°C (typical), the PWM turns on
again, restoring the output current to its nominal value.

Consider the case where a hard short from V

to ground occurs.

ISO

At first, the ADuM620x reaches its maximum current, which is
proportional to the voltage applied at V

. Power dissipates on

DD1

the primary side of the converter (see Figure 12). If self-heating
of the junction becomes great enough to cause its temperature
to rise above 150°C, thermal shutdown is activated, turning off
the PWM and turning off the output current. As the junction
temperature cools and drops below 130°C, the PWM turns on
and power dissipates again on the primary side of the converter,
causing the junction temperature to rise to 150°C again. This
thermal oscillation between 130°C and 150°C causes the part
to cycle on and off as long as the short remains at the output.

Thermal limit protections are intended to protect the device
against accidental overload conditions. For reliable operation,
externally limit device power dissipation to prevent junction
temperatures from exceeding 130°C.

POWER CONSIDERATIONS

The ADuM6200/ADuM6201/ADuM6202 power input, data
input channels on the primary side, and data input channels on
the secondary side are all protected from premature operation
by undervoltage lockout (UVLO) circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive,
and all input channel drivers and refresh circuits are idle. Outputs
remain in a high impedance state to prevent transmission of
undefined states during power-up and power-down operations.

During application of power to V

, the primary side circuitry

DD1

is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.

When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because no
data comes from the secondary side inputs until secondary side
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.

The secondary V

voltage is below its UVLO limit at this point;

ISO

the regulation control signal from the secondary side is not being
generated. The primary side power oscillator is allowed to free
run under these conditions, supplying the maximum amount of
power to the secondary side.

As the secondary side voltage rises to its regulation setpoint,
a large inrush current transient is present at V

. When the

DD1

regulation point is reached, the regulation control circuit pro­duces the regulation control signal that modulates the oscillator
on the primary side. The V

current is then reduced and is

DD1

proportional to the load current. The inrush current is less than
the short-circuit current shown in Figure 12. The duration of
the inrush current depends on the V
on the current and voltage available at the V

loading conditions and

ISO

pin.

DD1

As the secondary side converter begins to accept power from
the primary, the V

voltage starts to rise. When the secondary

ISO

side UVLO is reached, the secondary side outputs are initialized
to their default low state until data is received from the corre­sponding primary side input. It can take up to 1 μs after the
secondary side is initialized for the state of the output to
correlate to the primary side input.

Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.

Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care that the design allows the con­verter sufficient time to stabilize before valid data is required.

When power is removed from V

, the primary side converter

DD1

and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.

The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is reached
and the outputs are placed in their high impedance state, or the
outputs detect a lack of activity from the primary side inputs
and the outputs are set to their default low value before the
secondary power reaches UVLO.

Rev. B | Page 21 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

THERMAL ANALYSIS

The ADuM620x devices consist of four internal silicon die
attached to a split lead frame with two die attach paddles. For
the purposes of thermal analysis, the device is treated as a thermal
unit with the highest junction temperature reflected in the θ
value from Tabl e 14 . The value of θ

is based on measurements

JA

JA

taken with the part mounted on a JEDEC standard 4-layer board
with fine width traces and still air. Under normal operating
conditions, the ADuM620x operates at full load across the full
temperature range without derating the output current. How­ever, following the recommendations in the PCB Layout section
decreases the thermal resistance to the PCB, allowing increased
thermal margin at high ambient temperatures.

INCREASING AVAILABLE POWER

The ADuM620x devices are designed to work in combination
with the ADuM6000 in a master/slave configuration. The RC
and RC
from an ADuM6000 through its RC
that control signal. The RC

pins allow the ADuM620x to receive a PWM signal

SEL

pin and to act as a slave to

IN

pin chooses whether the part acts

SEL

as a standalone, self-regulated device or as a slave device.

IN

When the ADuM620x acts as a slave, its power is regulated by a
PWM signal from a master device. This allows multiple isoPower
parts to be combined in parallel while sharing the load equally.
When the ADuM620x is configured as a standalone unit, it
generates its own PWM feedback signal to regulate itself.

The ADuM620x devices can function as slave or standalone
devices. All devices in the ADuM5xxx and ADuM6xxx family
can function as standalone devices. Some of these devices also
function as master devices or slave devices, but not both (see
Tabl e 2 5 ).

Table 25. Function of isoPower Parts

Functio n

Part No.

ADuM6000 Yes Ye s Yes
ADuM620x No Yes Yes
ADuM640x No No Yes
ADuM5000 Yes Ye s Yes
ADuM520x No Yes Yes
ADuM5400 No No Yes
ADuM5401 to

ADuM5404

Master Slave Standalone

Yes N o Ye s

Tabl e 2 6 illustrates how isoPower devices can provide many
combinations of data channel count and multiples of the single­unit power.

Table 26. Configurations for Power and Data Channels

Power Units

1-Unit Power

2-Unit Power

3-Unit Power

0 Channels 2 Channels 4 Channels

ADuM6000 or ADuM5000 (standalone) ADuM620x or ADuM520x (standalone)

ADuM6000 or ADuM5000 (master)
ADuM6000 or ADuM5000 (slave)

ADuM6000 or ADuM5000 (slave)
ADuM6000 or ADuM5000 (master) ADuM6000 or ADuM5000 (master) ADuM6000 or ADuM5000 (master)
ADuM6000 or ADuM5000 (slave) ADuM6000 or ADuM5000 (slave) ADuM620x or ADuM520x (slave)
ADuM6000 or ADuM5000 (slave) ADuM620x or ADuM520x (slave) ADuM620x or ADuM520x (slave)

Number of Data Channels

ADuM6000 or ADuM5000 (master)
ADuM620x or ADuM520x (slave)

ADuM5401, ADuM5402, ADuM5403,
ADuM5404, or ADuM640x (standalone)

ADuM5401, ADuM5402, ADuM5403,
ADuM5404 (master)

Rev. B | Page 22 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

INSULATION LIFETIME

All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insu­lation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the life­time of the insulation structure within the ADuM620x devices.

Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel­eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Tab l e 2 0 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working vol­tages. In many cases, the approved working voltage is higher than
the 50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM620x devices depends on
the voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 28, Figure 29, and Figure 30 illustrate these
different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices.

In the case of unipolar ac or dc voltage, the stress on the insu­lation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life.
The working voltages listed in Tab l e 20 can be applied while
maintaining the 50-year minimum lifetime, provided that the
voltage conforms to either the unipolar ac or dc voltage cases.

Any cross-insulation voltage waveform that does not conform
to Figure 29 or Figure 30 should be treated as a bipolar ac wave­form and its peak voltage limited to the 50-year lifetime voltage
value listed in Table 2 0. The voltage presented in Figure 29 is
shown as sinusoidal for illustration purposes only. It is meant to
represent any voltage waveform varying between 0 V and some
limiting value. The limiting value can be positive or negative,
but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 28. Bipolar AC Waveform

RATED PEAK VOL TAGE

0V

Figure 29. Unipolar AC Waveform

RATED PEAK VOL TAGE

0V

Figure 30. DC Waveform

08775-121

08775-122

08775-123

Rev. B | Page 23 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

0
0

.

7

5

.

2

(

0

(

5

0

)

.

0

2

9

5

9

8

)

.

0

0

1.27 (0.0500)

0.40 (0.0157)

45°

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

13.00 (0.5118)

12.60 (0.4961)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0

.

(

7

5

0

.

0

2

9

5

)

2.65 (0.1043)

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

1.27

(0.0500)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.51 (0.0201)

0.31 (0.0122)

BSC

COMPLIANT TO JEDEC STANDARDS MS-013-AC

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

Figure 32. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]

0

.

2

5

(

0

.

0

0

9

1.27 (0.0500)

0.40 (0.0157)

45°

8

)

10-12-2010-A

Wide Body (RI-16-1)

Dimension shown in millimeters and (inches)

Rev. B | Page 24 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

ORDERING GUIDE

Number
of Inputs,
V

Side

ISO

Model

1, 2

Number
of Inputs,

Side

V

DD1

ADuM6200ARWZ 2 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6200CRWZ 2 0 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6200ARIZ 2 0 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6200CRIZ 2 0 25 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6201ARWZ 1 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6201CRWZ 1 1 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6201ARIZ 1 1 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6201CRIZ 1 1 25 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6202ARWZ 0 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6202CRWZ 0 2 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6202ARIZ 0 2 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6202CRIZ 0 2 25 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1

1

Z = RoHS Compliant Part.

2

Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option.

Maximum
Data Rate
(Mbps)

Maximum
Propagation
Delay, 5 V (ns)

Maximum
Pulse Width
Distortion (ns)

Temperature
Range

Package
Description

Package
Option

Rev. B | Page 25 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

NOTES

Rev. B | Page 26 of 28

Data Sheet ADuM6200/ADuM6201/ADuM6202

NOTES

Rev. B | Page 27 of 28

ADuM6200/ADuM6201/ADuM6202 Data Sheet

NOTES

©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08775-0-9/11(B)

Rev. B | Page 28 of 28