Datasheet ADUM6132 Datasheet (ANALOG DEVICES)

Isolated Half-Bridge Gate Driver with

V

Integrated Isolated High-Side Supply

FEATURES

isoPower integrated isolated high-side supply
275 mW isolated dc-to-dc converter
200 mA output sink current, 200 mA output source current
High common-mode transient immunity: >50 kV/μs
Wide-body 16-lead SOIC package
Safety and regulatory approvals (pending)

UL recognition

3750 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

CSA/IEC 60950-1, 400 V rms

VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V

= 560 V peak

IORM

APPLICATIONS

MOSFET/IGBT gate drivers
Motor drives
Solar panel inverters
Power supplies

ADuM6132

GENERAL DESCRIPTION

The ADuM61321 is an isolated half-bridge gate driver that
employs the Analog Devices, Inc., iCoupler® technology to
provide an isolated high-side driver with an integrated 275 mW
high-side supply. This supply, provided by an internal isolated
dc-to-dc converter, powers not only the ADuM6132 high-side
output but also any external buffer circuitry that is commonly
used with the ADuM6132. This functionality eliminates the
cost, space, and performance issues associated with external
supply configurations such as a bootstrap circuit.

The architecture of the ADuM6132 isolates the high-side
channel and the high-side power from the control and low­side interface circuitry. Care has been taken to ensure close
matching between the high-side and low-side driver timing
characteristics to reduce the need for a dead time margin.

In comparison to gate drivers that employ high voltage level
translation methodologies, the ADuM6132 offers the benefit
of true, galvanic isolation. The differential voltage between
high-side and low-side channels can be as high as 800 V with
good insulation lifetime (see Tab l e 12).

isoPower® uses high frequency switching elements to transfer
power through its transformer. Special care must be taken
during printed circuit board (PCB) layout to meet emissions
standards. Refer to the AN-0971 Application Note for details on
board layout considerations.

FUNCTIONAL BLOCK DIAGRAM

1

V

DD

2

GND

3

V

DDL

4

V

IA

V

5

IB

V

6

OB

7

DDB

8

GND

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; 7,075,329; and other pending patents

Rev. 0

Information furnished by Analog Devices is believed to be acc
responsibility is assumed by Analog Devices for its use, nor for any
rights of third parties that may result from its use. Specifications subj
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

urate and reliable. However, no

infringements of patents or other

ect to change without notice. No

ENCODE

SHIFT

LEVEL-

ISOLATED
DC-TO-DC

CONVERTER

Figure 1.

LEVEL-SHIFT

DECODE AND

ADuM6132

One Technology Way, P
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

16

V

ISO

GND

15

ISO

14

GND

A

13

V

DDA

V

12

OA

11

NC

10

NC

GND

9

ISO

07393-001

.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

ADuM6132

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Package Characteristics ............................................................... 4

Regulatory Information ............................................................... 4

Insulation and Safety Related Specifications ............................ 4

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 5

Recommended Operating Conditions ...................................... 5

Absolute Maximum Ratings ............................................................ 6

REVISION HISTORY

7/08—Revision 0: Initial Version



ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Terminology .................................................................................... 10

Applications Information .............................................................. 11

Typical Application Usage ......................................................... 11

PCB Layout ................................................................................. 11

Thermal Analysis ....................................................................... 12

Undervoltage Lockout ............................................................... 12

Propagation Delay-Related Parameters ................................... 13

Magnetic Field Immunity .......................................................... 13

Insulation Lifetime ..................................................................... 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

ADuM6132

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

All voltages are relative to their respective ground; 4.5 V ≤ VDD = V
specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T
V

= V

DD

= 5.0 V, V

DDL

= 15 V, V

DDB

DDA

= V

ISO

.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Isolated Power Supply

Input Current, Quiescent I

280 mA I

DD(Q)

Input Current, Loaded IDD 350 mA I
Maximum Output Current
Output Voltage V

1

I

22 mA 12.5 V ≤ V

ISO(MAX)

12.5 15 17 V 0 mA ≤ I

ISO

Logic Supply

Input Current I

Output Supplies, Channel A or Channel B

Supply Current, Quiescent I
Supply Current, fIN = 20 kHz I
Supply Current, fIN = 100 kHz I
Supply Current, fIN = 1000 kHz I

1.8 3.0 mA

DDL

2

, I

DDA(Q)

DDA(20)

DDA(100)

DDA(1000)

1.0 2.0 mA

DDB(Q)

, I

1.1 2.1 mA CL = 200 pF

DDB(20)

, I

DDB(100)

, I

DDB(1000)

Logic Inputs, Channel A or Channel B

Input Current IIA, I
Logic High Input Voltage V
Logic Low Input Voltage V

IB

, V

0.7 × V

IAH

IBH

, V

IAL

IBL

Outputs, Channel A or Channel B

Channel A High Level Output Voltage V
Channel B High Level Output Voltage V
Low Level Output Voltages V

or V

3

3

I

Supply

DDB

High Level Output Current, Peak
Low Level Output Current, Peak

Undervoltage Lockout, V

DDA

Positive Going Threshold V
Negative Going Threshold V
Hysteresis V

Undervoltage Lockout, V

DDL

Supply

4

Positive Going Threshold V
Negative Going Threshold V
Hysteresis V

4

V

OAH

V

OBH

0.1 V I

OAL,VOBL

I

, I

200 mA

OAH

OBH

, I

200 mA

OAL

OBL

DDAUV+, VDDBUV+

DDAUV−, VDDBUV−

, V

DDAUVH

DDBUVH

DDLUV+

DDLUV−

DDLUVH

SWITCHING SPECIFICATIONS

Minimum Pulse Width
Maximum Switching Frequency
Propagation Delay

1

PW 50 ns C

1

1

f

1000 kHz CL = 200 pF

IN

t

, t

40 60 100 ns CL = 200 pF

PHL

PLH

Change vs. Temperature 100 ps/°C
Pulse Width Distortion, |t
Channel-to-Channel Matching, Rising or

Falling Matching Edge Polarity
Channel-to-Channel Matching, Rising vs.

Falling Opposite Edge Polarity

PLH

− t

| PWD 10 ns CL = 200 pF

PHL

1

1

tM2 20 ns CL = 200 pF

tM1 20 ns CL = 200 pF

≤ 5.5 V; 12.5 V ≤ V

DDL

≤ 17.0 V; V

DDB

DDA

= V

. All minimum/maximum

ISO

= 0 mA, dc signal inputs

ISO

= I

ISO

ISO(MAX)

ISO

ISO

1.3 2.3 mA CL = 200 pF

4.5 5.5 mA CL = 200 pF

−10 +0.01 +10 µA 0 V ≤ VIA, VIB ≤ 5.5 V

DDL

− 0.1

DDA

− 0.1 V I

DDB

0.3 × V

V I

V

V

DDL

= −1 mA

OAH

= −1 mA

OBH

, I

OAL

OBL

= 1 mA

11.0 11.7 12.3 V

10.0 10.7 11.2 V

1.0 V

3.5 4.2 V

3.1 3.8 V

0.5 V

= 200 pF

L

= 25°C,

A

≤ 17.0 V

≤ 22 mA

Rev. 0 | Page 3 of 16

ADuM6132

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Part-to-Part Matching
Output Rise Time (10% to 90%) tR 15 ns CL = 200 pF
Output Fall Time (10% to 90%) tF 15 ns CL = 200 pF

1

See the section. Terminology

2

I

is supplied by the output of the integrated isolated dc-to-dc power supply. I

DDA

3

Duration less than 1 second. Average output current must conform to the limit shown in the section. Absolute Maximum Ratings

4

Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built

into the detection threshold to prevent oscillations and noise sensitivity.

PACKAGE CHARACTERISTICS

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input Side to High-Side Output)
Capacitance (Input Side to High-Side Output)1 C
Input Capacitance CI 4.0 pF
Junction-to-Ambient Thermal Resistance θJA 45 °C/W 4-layer PCB

1

The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

REGULATORY INFORMATION

The ADuM6132 is pending approval by the organizations listed in Tab l e 3.

1

60 ns CL = 200 pF

is supplied by an external power connection to the V

DDB

1

R

1012 Ω

I-O

2.0 pF

I-O

pin. See Figure . 16

DDB

Table 3.

UL (Pending) CSA (Pending) VDE (Pending)

Recognized under UL 1577
component recognition program

Double/reinforced insulation,
3750 V rms isolation voltage

Approved under CSA Component Acceptance

1

Notice #5A
Basic insulation per CSA 60950-1-03 and IEC 60950-1,

800 V rms (1131 V peak) maximum working voltage

Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12

2

Reinforced insulation, 560 V peak

Reinforced insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms maximum working voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM6132 is proof-tested by applying an insulation test voltage ≥4500 V rms for 1 second (current leakage detection limit = 10 µA).

2

In accordance with DIN V VDE V 0884-10, each ADuM6132 is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection

limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 4.

Parameter Symbol Value Unit Test Conditions/Comments

Rated Dielectric Insulation Voltage 3750 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) >8.0 mm

Minimum External Tracking (Creepage) L(I02) >8.0 mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Measured from input terminals to output
terminals, shortest distance through air

Measured from input terminals to output
terminals, shortest distance path along body

Rev. 0 | Page 4 of 16

ADuM6132

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

The ADuM6132 is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval.

Table 5.

Parameter Test Conditions/Comments Symbol Value Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II

Climatic Classification 40/105/21
Pollution Degree (DIN VDE 0110, Table 1) 2
Maximum Working Insulation Voltage V
Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge <5 pC

Input-to-Output Test Voltage, Method A VPR

After Environmental Tests Subgroup 1 V
After Input and/or Safety Test Subgroup 2

× 1.6 = VPR, tm = 60 sec, partial discharge <5 pC 896 V peak

IORM

× 1.2 = VPR, tm = 60 sec, partial discharge <5 pC 672 V peak

V

IORM

and Subgroup 3

Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 6000 V peak
Safety-Limiting Values

Maximum value allowed in the event of a failure

(see Figure 2)
Case Temperature TS 150 °C
Side 1 Current IS1 555 mA

Insulation Resistance at TS V

= 500 V RS >109 Ω

IO

600

RECOMMENDED OPERATING CONDITIONS

560 V peak

IORM

1050 V peak

V

PR

500

400

CURRENT (mA)

DD

300

200

100

SAFE OPERATING V

0

0 50 100 150 200

AMBIENT TEMPERATURE (°C)

Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Ambient Temperature per DIN V VDE V 0884-10

Table 6.

Parameter Rating

Operating Temperature Range, TA −40°C to +85°C
Input Supply Voltage, VDD and V
Channel A, Channel B Supply Voltage,

and V

V

DDA

DDB

1

1

4.5 V to 5.5 V

DDL

12.5 V to 17 V

Input Signal Rise and Fall Times 1 ms
Common-Mode Transient Immunity,

−50 kV/µs to +50 kV/µs

Input to Output

Minimum Power-On Slew Rate (P

and V

V

DD

1

07393-002

All voltages are relative to their respective ground.

2

The ADuM6132 power supply may fail to properly initialize if VDD and V

applied too slowly. The power supply slew rate must be faster than specified
over the entire turn-on ramp. Power-on should start from a completely
discharged state.

DDL

2

SLEW

1 V/ms

),

are

DDL

Rev. 0 | Page 5 of 16

ADuM6132

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

Storage Temperature Range, TST −55°C to +150°C
Ambient Operating Temperature

Range, T
Input Supply Voltage, V
Channel A, Channel B Supply

Voltage, V
Input Voltage, VIA, V
Output Voltage, V
Output Voltage, V

A

, V

DDL

DD

1

, V

DDA

DDB

1

−0.5 V to V

IB

1

−0.5 V to V

OA

1

−0.5 V to V

OB

Average DC Output Current,

I

, IOB

OA

−40°C to +85°C

1

−0.5 V to +7.0 V

−0.5 V to +27 V

DDL

ISO

DDB

−10 mA to +10 mA

+ 0.5 V

+ 0.5 V

+ 0.5 V

Peak Output Current, IOA, IOB −200 mA to +200 mA
Common-Mode Transients2 −100 kV/µs to +100 kV/µs

1

All voltages are relative to their respective ground.

2

Refers to common-mode transients across any insulation barrier. Common-

mode transients exceeding the absolute maximum ratings can cause latch-up
or permanent damage.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 16

ADuM6132

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

DD

GND

2

V

3

DDL

V

4

IA

5

V

IB

V

6

OB

V

7

DDB

8

GND

NC = NO CONNECT

ADuM6132

TOP VIEW

(Not to Scale)

16

V

ISO

GND

15

ISO

GND

14

A

V

13

DDA

12

V

OA

NC

11

NC

10

9

GND

ISO

07393-003

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD

2, 8 GND
3 V
4 V
5 V
6 V
7 V

DDL

IA

IB

OB

DDB

9, 15 GND

Input Supply Voltage for Logic, 4.5 V to 5.5 V.

Ground Reference for Isolated Power Supply Output.

ISO

Input Supply Voltage for Isolated Power Supply, 4.5 V to 5.5 V.
Ground Reference for Isolated Power Supply Input and Logic Inputs.

Logic Input A.
Logic Input B.
Output B (Nonisolated).
Output B Supply Voltage Input (Nonisolated), 12.5 V to 17 V.

10, 11 NC No Connect.
12 VOA Output A (Isolated).
13 V
14 GNDA Output A Ground Reference. Must be connected externally to GND
16 V

Output A Supply Voltage Input. Must be connected externally to V

DDA

Isolated Power Supply Voltage Output.

ISO

ISO

ISO

Table 9. Truth Table (Positive Logic)

VIA Input VIB Input V

DDL

1

State V

State VOA Output VOB Output Notes

DDB

L L Powered Powered L L
L H Powered Powered L H
H L Powered Powered H L
H H Powered Powered H H
X X Unpowered Powered L L

returns to input state within 1 µs of V

V

OA

power restoration.

X X Powered Unpowered L L

1

L = low; H = high; X = high or low.

(Pin 16).

(Pin 15).

DDL

Rev. 0 | Page 7 of 16

ADuM6132

TYPICAL PERFORMANCE CHARACTERISTICS

All typical performance curves are based on operation at TA = 25°C, unless otherwise noted.

16.0

1.2

15.5

15.0

VDD = 5.0V

ISO

VDD = 5.5V

External Load

(V)

14.5

ISO

V

14.0

13.5

13.0
0 5 10 15 20 25

Figure 4. Typical V

VDD = 4.5V

I

LOAD CURRENT (mA)

ISO

Supply Voltage vs. I

ISO

300

VDD = 4.5V

250

VDD = 5.0V

200

150

100

INPUT CURRENT (mA)

DD

I

50

0

0 5 10 15 20 25

I LOAD CURRENT (mA)

ISO

Figure 5. Typical IDD Supply Current vs. I

VDD = 5.5V

ISO

External Load

30

VDD = 5.5V

25

20

15

EFFICIENCY (%)

10

5

VDD = 4.5V

VDD = 5.0V

1.0

0.8
VDD = 4.5V

0.6

0.4

POWER DISSIPATION (W)

0.2

0

0 5 10 15 20 25

07393-024

VDD = 5.5V

I

LOAD CURRENT (mA)

ISO

Figure 7. Typical Total Power Dissipation vs. I

VDD = 5.0V

External Load

ISO

07393-027

14.8

14.6

14.4

14.2

14.0

13.8

13.6

13.4

AT 22mA LOAD (V)

ISO

13.2

V

13.0

12.8

12.6
–40 –20

07393-025

Figure 8. Typical V

VDD = 5.5V

VDD = 5.0V

VDD = 4.5V

0 20 40 60 80 100 120

AMBIENT TEMPERATURE (°C)

Output Voltage at Maximum Combined Load

ISO

07393-028

over Temperature

2500

VDD = 4.5V

POWER DISSIPATION ( mW)

2000

1500

1000

500

V

= 5.0V

DD

VDD = 5.5V

0

0 5 10 15 20 25

I

LOAD CURRENT (mA)

ISO

Figure 6. Typical V

Supply Efficiency vs. I

ISO

External Load

ISO

07393-026

Rev. 0 | Page 8 of 16

0

1 10 100 1000

V

LOAD IMPE DANCE (Ω)

ISO

Figure 9. Power Dissipation vs. Load Impedance for Fault Conditions

3-029
0739

ADuM6132

6

4

5

4

3

CURRENT (mA)

2

DDA

I

1

0

0 200 400 600 800 1000

VOA DATA FREQUENCY (kHz )

Figure 10. Typical I

V

DDA

Supply Current, CL = 200 pF

DDA

= 15V

V

DDA

V

DDA

6

5

V

= 17V

= 15V

DDB

V

= 12.5V

DDB

CURRENT (mA)

I

DDB

4

3

2

V

DDB

1

= 17V

= 12.5V

3

2

OUTPUT VOLTAGE (V)

OL

1

V

030

07393-

0

50 100 150 200 2500

Figure 13. Typical VOL vs. IOL (VDD = V

IOL (mA)

= 5 V, V

DDL

DDA

= V

DDB

07393-033

= 12 V to 17 V)

70

65

t

CHA

PLH

60

t

CHA

PHL

PROPAGATI ON DELAY (n s)

55

OA

V

) OUTPUT VO LTAGE DRO P (V)

DD

– V

OH

(V

0

0 200 400 600 800 1000

VOB DATA FREQUENCY (kHz )

Figure 11. Typical I

Supply Current, CL = 200 pF

DDB

0

–1

–2

–3

–4

–5

Figure 12. Typical V

50 100 150 200 2500

IOH (mA)

Voltage Drop vs. IOH (VDD = V

OH

= V

V

DDA

= 12 V to 17 V)

DDB

DDL

= 5 V,

031

07393-

50

–50 –25 0 25 50 75 100

TEMPERATURE ( °C)

07393-034

Figure 14. Typical Channel A Propagation Delay vs. Temperature

70

t

CHB

65

60

PROPAGATI ON DELAY (ns)

55

OB

V

50

–50 –25 0 25 50 75 100

07393-032

TEMPERATURE ( °C)

PLH

t

CHB

PHL

035

07393-

Figure 15. Typical Channel B Propagation Delay vs. Temperature

Rev. 0 | Page 9 of 16

ADuM6132

TERMINOLOGY

Channel-to-Channel Matching

Channel-to-channel matching with rising or falling matching
edge polarity is the magnitude of the propagation delay differ­ence between two channels of the same part when the inputs
are both rising edges or both falling edges. The loads on each
channel are equal.

Channel-to-channel matching with rising vs. falling opposite
edge polarity is the magnitude of the propagation delay differ­ence between two channels of the same part when one input is
a rising edge and one input is a falling edge. The loads on each
channel are equal.

Maximum Output Current

The maximum output current is the maximum isolated supply
current that the ADuM6132 can provide. This current supports
external loads as well as the needs of the ADuM6132 Channel A
output circuitry. This is achieved via external connection of the
V

pin to the V

ISO

pin and of the GND

DDA

pin to the GNDA pin

ISO

(see Figure 16). The net current available to power external loads
is the ADuM6132 output current, I
supply current, I

DDA

.

, minus the Channel A

ISO

Maximum Switching Frequency

The maximum switching frequency is the maximum signal
frequency at which the specified timing parameters are guar­anteed. Operation beyond the maximum switching frequency
is not recommended, because high switching rates can cause
droop in the output supply voltage.

Minimum Pulse Width

The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed. Operation
below the minimum pulse width is not recommended.

Part-to-Part Matching

Part-to-part matching is the magnitude of the propagation
delay difference between the same channels of two different
parts. This includes rising vs. rising edges, falling vs. falling
edges, or rising vs. falling edges. The supply voltages, temp­eratures, and loads of each part are equal.

Propagation Delay

The propagation delay is the time that it takes a logic signal to
propagate through a component. The propagation delay to a
logic low output may differ from the propagation delay to a
logic high output.

The t
of the falling edge of the V
the falling edge of the V

propagation delay is measured from the 50% level

PHL

or VIB signal to the 50% level of

IA

or VOB signal. The t

OA

propagation

PLH

delay is measured from the 50% level of the rising edge of the
V

or VIB signal to the 50% level of the rising edge of the VOA

IA

or V

signal.

OB

Capacitive Load (C

)

L

The output capacitive load simulates a typical FET, IGBT, or
buffer for timing or current measurements. This load includes
all discrete and parasitic capacitive loads on the output.

Rev. 0 | Page 10 of 16

ADuM6132

APPLICATIONS INFORMATION

TYPICAL APPLICATION USAGE

The architecture of the ADuM6132 is ideal for motor drive and
inverter applications where the low-side channels are common
to the controller. This arrangement requires only two isolation
regions in a package. All the isolated signals and the isolated
power are grouped on one side of the package to maintain full
package creepage and clearance. The low-side driver, as well as the
control signals, share a common reference and are also grouped.

To maximize the effectiveness of external bypass capacitors, the
isoPower dc-to-dc converter is not internally tied to the data
channels, and should be treated as a completely independent
subsystem, except for a UVLO function (see the Undervoltage
Lockout section). This means that power must be applied to V
to operate the dc-to-dc converter. Power must also be applied to
V

DDL

and V

to operate the data input and the Channel B

DDB

driver output. On the secondary side, the power generated at
the V

pin must be applied as an input power supply to the

ISO

V

pin. GND

DDA

and GNDA must also be connected.

ISO

The ADuM6132 is intended for use in driving low gate
capacitance transistors (200 pF typically). Most high voltage
applications involve larger transistors than this. To accom­modate these applications, users can implement a buffer
configuration with the ADuM6132, as shown in Figure 16. In
many cases, this buffer configuration is the least expensive
option to drive high capacitance devices and provides the
greatest amount of design flexibility. The precise buffer/high

DD

voltage transistor combination can be selected to suit the
requirements of the application.

PCB LAYOUT

The ADuM6132 digital isolator with integrated 275 mW
isoPower dc-to-dc converter requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the input and output supply pins (see Figure 17).
The power supply section of the ADuM6132 uses a very high
oscillator frequency to efficiently pass power through its chip
scale transformers. In addition, the normal operation of the
data section of the iCoupler introduces switching transients
on the power supply pins. Bypass capacitors are required for
several operating frequencies. Noise suppression requires a low
ESR, high frequency capacitor; ripple suppression and proper
regulation require a large value capacitor in parallel (see Ta b le 1 0).
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.

Table 10. Recommended Bypass Capacitors

Supply Pins Bypass Capacitors

VDD 1, 2 0.1 F, 10 F
V

7, 8 0.1 F

DDB

V

2, 3 0.1 F

DDL

V

13, 14 0.1 F

DDA

V

15, 16 0.1 F, 10 F

ISO

+5V

GND

+5V

+15V

10µF

0.1µF

0.1µF

0.1µF

GND

V

V

GND

V

DDL

V

DDB

V

ADuM6132

V

DD

1

2

3

IA

4

7

IB

5

8

ISOLATED

DC-TO-DC

CONVERTER

ISOLATED

GATE

DRIVE

NONISOL ATED

GATE

DRIVE

16

15

9

13

12

14

6

ISO

GND

GND

V

DDA

V

OA

GND

V

OB

0.1µF

ISO

ISO

0.1µF

A

I

I

DDAIAVAIL

C

BUF

R

BUF

C

BUF

R

ISO

+15V

BUF

GND

BUFFER

R

G

BUFFER

R

G

V

DC+

V

DC–

7393-016
0

Figure 16. Typical Application Circuit

Rev. 0 | Page 11 of 16

ADuM6132

In applications involving high common-mode transients, care
should be taken to ensure that board capacitive coupling across
the isolation barrier is minimized. Furthermore, the board
layout should be designed so that any coupling that does occur
affects all pins on a given component side equally. Failure to
ensure this may cause voltage differentials between pins that
exceed the absolute maximum ratings of the device (see Tab le 7 ),
leading to latch-up or permanent damage.

V

DD

GND

V

DDL

V

IA

V

IB

V

OB

V

DDB

GND GND

Figure 17. Recommended PCB Layout

V

ISO

GND
GND
V

DDA

V

OA

NC
NC

ISO

A

ISO

07393-017

The ADuM6132 is a power device that dissipates approximately
1 W of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation
device, the device depends primarily on heat dissipation into
the PCB through the GND pins. If the device will be used at
high ambient temperatures, provide a thermal path from the
GND pins to the PCB ground plane.

The board layout in Figure 17 shows enlarged pads for Pin 8
(GND) and Pin 9 (GND

). Multiple vias should be implem-

ISO

ented from the pad to the ground plane. This layout significantly
reduces the temperatures inside the chip. The dimensions of the
expanded pads are left to the discretion of the designer and the
available board space.

THERMAL ANALYSIS

The ADuM6132 consists of several internal die attached to
two lead frame paddles. For the purposes of thermal analysis,
the part is treated as a thermal unit with the highest junction
temperature determining θ
θ

is based on measurements taken with the part mounted on

JA

a JEDEC standard 4-layer board with fine width traces and still
air. Under normal operating conditions, the ADuM6132 oper­ates at full load across the full temperature range without derating
the output current. However, following the recommendations in
the PCB Layout section decreases the thermal resistance to the
PCB, allowing increased thermal margin at high ambient
temperatures.

Under V

output short-circuit conditions, as shown in

ISO

Figure 9, the package power dissipation quickly exceeds the safe
operating limit of 1.44 W for ambient temperatures up to 85°C.
At low input voltage, the power dissipation can approach 2 W.
Because internal compensation of the PWM makes low V
worst-case condition, input voltage limiting is not an effective
strategy for protecting the ADuM6132 from output load fault
conditions. Therefore, the preferred protection methods, where
required, are either limiting ambient temperature to 60°C or the
use of a fuse.

, as shown in Tabl e 2. The value of

JA

DD

a

UNDERVOLTAGE LOCKOUT

The ADuM6132 has undervoltage lockout (UVLO) circuits on

, V

the V

DDL

DDA

, and V
UVLO circuit monitors the supply voltage and takes a predeter­mined action based on whether the supply voltage is above or
below a given threshold. These thresholds are specified in Tabl e 1.

In the recommended configuration shown in Figure 16, only
two independent supplies are controlled by the user: V
V

DDL/VDD

(V

= VDD in Figure 16). V

DDL

internal dc-to-dc converter via the V
tion. Nevertheless, the V
Tabl e 11 to show how the V
dc-to-dc converter powers on and off.

Table 11. Undervoltage Lockout Functionality

User-Provided
Supplies

V

V

DDL

V

DDB

H H H Normal operation.

H H L Internal dc-to-dc converter is

X L X Internal dc-to-dc converter is

L X X Internal dc-to-dc converter is

1

H: supply voltage > UVLO threshold; L: supply voltage < UVLO threshold;

X: supply voltage level is irrelevant.

When all three supplies are above their respective UVLO
thresholds, the ADuM6132 operates normally. The internal
dc-to-dc converter is active, and both outputs operate as
determined by their respective input logic signals. If either of
the user-provided supplies is below its UVLO threshold, the
ADuM6132 is put into a disabled mode. In this mode, the
internal dc-to-dc converter is turned off and both outputs are
driven low.

The V

output is driven low by either the V

OB

UVLO circuit (whichever is below its threshold). The V
output is driven low when the internal dc-to-dc converter is
turned off. The V
to drop also because V
When V
circuit drives V

is below its UVLO threshold, the V

DDA

OA

supplies. For each supply, the respective

DDB

is supplied by the

DDA

= V

ISO

UVLO functionality is included in

DDA

output behaves when the internal

OA

V

Powered

ISO

Supply

Effect

DDA

external connec-

DDA

1

Internal dc-to-dc converter is
active.

output logic states

V

OA/VOB

match V

active but V

input logic states.

IA/VIB

is below UVLO

ISO

threshold.

output is driven low.

V

OA

output operates normally.

V

OB

DDL

= 0).

ISO

= 0).

ISO

or V

DDA

UVLO

turned off (V

output is driven low.

V

OA

output is driven low.

V

OB

turned off (V

output is driven low.

V

OA

output is driven low.

V

OB

supply voltage drops to 0 V, causing V

ISO

and V

ISO

are externally connected.

DDA

low.

DDB

DDB

OA

and

DDA

Rev. 0 | Page 12 of 16

ADuM6132

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propaga­tion delay to a logic low output may differ from the propagation
delay to a logic high output.

INPUT (VIx)

OUTPUT (V

t

PLH

)

Ox

t

PHL

Figure 18. Propagation Delay Parameters

50%

50%

Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM6132 component.

MAGNETIC FIELD IMMUNITY

The ADuM6132 is extremely immune to external magnetic
fields. The limitation on the ADuM6132 magnetic field immunity
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to falsely set or reset
the decoder. The following analysis defines the conditions
under which this may occur.

The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately

0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by

V = (−dβ/dt) Σπr

where:

β is the magnetic flux density (gauss).

is the radius of the nth turn in the receiving coil (cm).

r

n

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM6132 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic flux density is calculated, as shown in Figure 19.

2

; n = 1, 2, … N

n

100

10

1

0.1

DENSITY (kgauss)

07393-018

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001
1k 10k 10M

MAGNETIC F IELD FREQ UENCY (Hz)

1M

100M100k

07393-019

Figure 19. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic flux density of 0.2 kgauss
induces a voltage of 0.25 V at the receiving coil. This voltage
is approximately 50% of the sensing threshold and does not
cause a faulty output transition. Similarly, if such an event
occurs during a transmitted pulse (with the worst-case polarity),
the received pulse is reduced from >1.0 V to 0.75 V—still well
above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM6132 transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 20, the ADuM6132 is extremely
immune and can be affected only by extremely large currents
operated at high frequency and very close to the component.
For example, at a magnetic field frequency of 1 MHz, a 0.5 kA
current would need to be placed 5 mm away from the ADuM6132
to affect the operation of the component.

1000

DISTANCE = 1m

100

CURRENT (kA)

10

DISTANCE = 100mm

1

DISTANCE = 5mm

Rev. 0 | Page 13 of 16

0.1

MAXIMUM ALL OWABLE

0.01
1k 10k 100M100k 1M 10M

MAGNETIC F IELD FREQ UENCY (Hz)

Figure 20. Maximum Allowable Current for Various

Current-to-ADuM6132 Spacings

07393-020

ADuM6132

Note that in the presence of strong magnetic fields and high
frequencies, any loops formed by PCB traces may induce
sufficiently large error voltages to trigger the threshold of
succeeding circuitry. Care should be taken in the layout of such
traces to avoid this possibility.

INSULATION LIFETIME

All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insul­ation degradation depends on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices conducts
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM6132.

Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel­eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. Ta ble 1 2 summarizes the recommended peak
working voltages for 50 years and 15 years of service life for
various operating conditions evaluated by Analog Devices. In
many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM6132 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 21, Figure 22, and Figure 23 illustrate these
different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices.

In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower, which allows operation at
higher working voltages while still achieving a 50-year service
life. The working voltages listed in Tab le 1 2 can be applied while
maintaining the 50-year minimum lifetime, provided that the
voltage conforms to either the unipolar ac or dc voltage cases.

Any cross-insulation voltage waveform that does not conform to
Figure 22 or Figure 23 should be treated as a bipolar ac waveform,
and its peak voltage should be limited to the 50-year lifetime
voltage value listed in Ta b le 1 2 . Note that the voltage shown in
Figure 22 is sinusoidal for illustration purposes only. It is meant
to represent any voltage waveform varying between 0 V and
some limiting value. The limiting value can be positive or
negative, but the voltage cannot cross 0 V.

RATED PEAK VOLTAGE

0V

Figure 21. Bipolar AC Waveform

07393-021

RATED PEAK VOLTAGE

0V

Figure 22. Unipolar AC Waveform

07393-022

RATED PEAK VOLTAGE

0V

Figure 23. DC Waveform

07393-023

Table 12. Maximum Continuous Working Voltage1

Parameter Peak Voltage Lifetime

AC Voltage, Bipolar Waveform 424 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform

Basic Insulation 800 V peak 15-year minimum lifetime
Basic Insulation 660 V peak 50-year minimum lifetime

DC Voltage Waveform

Basic Insulation 800 V peak 15-year minimum lifetime
Basic Insulation 660 V peak 50-year minimum lifetime

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Rev. 0 | Page 14 of 16

ADuM6132

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

ORDERING GUIDE

Model

ADuM6132ARWZ
ADuM6132ARWZ-RL

1

Z = RoHS Compliant Part.

1

1

2 0.2 15 −40°C to +85°C

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

0
0

.

7

.

2

5

(

0

5

(

0

.

0

2

9

5

)

0

0

9

8

)

.

1.27 (0.0500)

0.40 (0.0157)

45°

032707-B

0.30 (0.0 118)

0.10 (0.0039)

COPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENSIONS ARE IN MILLIM ETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013- AA

Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters (inches)

No. of
Channels

Output Peak
Current (A)

Output
Voltage (V) Temperature Range Package Description

Package
Option

2 0.2 15 −40°C to +85°C 16-Lead SOIC_W RW-16

16-Lead SOIC_W, 13-inch Tape

RW-16

and Reel Option (1,000 Units)

Rev. 0 | Page 15 of 16

ADuM6132

NOTES

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07393-0-7/08(0)

Rev. 0 | Page 16 of 16