Datasheet ADUM5401 Datasheet (ANALOG DEVICES)

Quad-Channel, 2.5 kV Isolators with

V

Data Sheet

ADuM5401/ADuM5402/ADuM5403/ADuM5404

Integrated DC-to-DC Converter

FEATURES

isoPower integrated, isolated dc-to-dc converter Regulated 3.3 V or 5.0 V output Up to 500 mW output power Quad dc-to-25 Mbps (NRZ) signal isolation channels 16-lead SOIC package with 7.6 mm creepage High temperature operation: 105°C maximum High common-mode transient immunity: >25 kV/μs

GND VIA/V VIB/V VIC/V

Safety and regulatory approvals

UL recognition

2500 V rms for 1 minute per UL 1577

RC

GND

CSA Component Acceptance Notice #5A VDE certificate of conformity (pending)

IEC 60747-5-2 (VDE 0884, Part 2) V

= 560 V peak

IORM

APPLICATIONS

RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Power supply start-up bias and gate drives Isolated sensor interfaces Industrial PLCs

GENERAL DESCRIPTION

The ADuM5401/ADuM5402/ADuM5403/ADuM54041 are quad-channel digital isolators with isoPower®, an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler® technology, the dc-to-dc converter provides up to 500 mW of regulated, isolated power at either 5.0 V or 3.3 V from a 5.0 V input supply, or at 3.3 V from a 3.3 V supply at the power levels shown in Table 1. These devices eliminate the need for a separate, isolated dc-to-dc converter in low power, isolated designs. The iCoupler chip scale transformer technology is used to isolate the logic signals and for the power and feedback paths in the dc-to-dc converter. The result is a small form factor, total isolation solution.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for more information).

isoPower uses high frequency switching elements to transfer power through its transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. See the AN-0971 Application Note for board layout recommendations.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Table 1. Power Levels

Input Voltage (V) Output Voltage (V) Output Power (mW)

5.0 5.0 500

5.0 3.3 330

3.3 3.3 200

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

1

3

OA

4

OB

5

OC

V

6

OD

7

OUT

8

1

OSC

4 CHANNEL iCOUPLER CORE

ADuM5401/ADuM5402/

ADuM5403/ADuM5404

IA

3

ADuM5401

V

IB

4

V

IC

5

V

OD

6

Figure 2. ADuM5401

IA

3

ADuM5402

V

IB

4

V

OC

5

V

OD

6

Figure 3. ADuM5402

IA

3

ADuM5403

V

OB

4

V

OC

5

V

OD

6

Figure 4. ADuM5403

OA

3

ADuM5404

V

OB

4

V

OC

5

V

OD

6

Figure 5. ADuM5404

Figure 1.

RECT

14

13

12

11

14

13

12

11

14

13

12

11

14

13

12

11

OA

V

OB

V

OC

V

ID

OA

V

OB

V

IC

V

ID

OA

V

IB

V

IC

V

ID

IA

V

IB

V

IC

V

ID

REG

16

V

ISO

15

GND

ISO

VOA/V

14

IA

VOB/V

13

IB

VOC/V

12

IC

V

11

ID

10

V

SEL

GND

9

ISO

06577-001

06577-100

06577-101

06577-102

06577-103

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

REVISION HISTORY

6/12—Rev. B to Rev. C

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Updated Outline Dimensions ........................................................ 26

9/11—Rev. A to Rev. B

Changes to Product Title, Features Section, and General

Description Section ........................................................................... 1

Added Table 1; Renumbered Sequentially ..................................... 1

Changes to Specifications Section ................................................... 3

Changes to Table 19 and Table 20 ................................................. 11

Changes to Table 21 ........................................................................ 12

Changes to Table 22 ........................................................................ 13

Changes to Table 23 ........................................................................ 14

Changes to Table 24 and Table 25 ................................................. 15

Changes to Figure 11 to Figure 13 ................................................ 16

Changes to Figure 11, Figure 12 Caption, Figure 14 Caption,

and Figure 16 Caption .................................................................... 16

Added Figure 19 and Figure 20; Renumbered Sequentially ...... 17

Changes to Figure 21 and Figure 22 ............................................. 17

Changes to Terminology Section .................................................. 19

Changes to Applications Information Section ............................ 20

Deleted Increasing Available Power, Figure 15, and Figure 16;

Renumbered Sequentially .............................................................. 20

Changes to PCB Layout Section .................................................... 20

Added Start-Up Behavior Section ................................................. 21

Moved and Changes to EMI Considerations Section ................ 21

Changes to DC Correctness and Magnetic Field Immunity

Section .............................................................................................. 21

Changes to Power Consumption Section and Figure 29 ........... 22

Changes to Power Considerations ................................................ 23

Added Increasing Available Power Section and Table 26 .......... 23

Added Table 27 ................................................................................ 24

Changes to Insulation Lifetime Section ....................................... 24

11/08—Rev. 0 to Rev. A

Changes to Figure 1 and General Description Section ................ 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 5

Changes to Table 4 ............................................................................ 7

Changes to Table 6 and Table 7 ....................................................... 8

Changes to Table 8 and Table 9 ....................................................... 9

Changes to Figure 7 and Table 10 ................................................. 10

Changes to Figure 8 and Table 11 ................................................. 11

Changes to Figure 9 and Table 12 ................................................. 12

Changes to Figure 10 and Table 13 ............................................... 13

Moved Truth Table Section ............................................................ 13

Changes to Applications Information Section and PCB Layout

Section .............................................................................................. 17

Changes to DC Correctness and Magnetic Field Immunity

Section .............................................................................................. 18

Changes to Power Considerations Section .................................. 20

Added Increasing Available Power Section, Table 15,

and Table 16 ..................................................................................... 20

5/08—Revision 0: Initial Version

Rev. C | Page 3 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

ISO

ISO (LINE)

ISO

DD1

ISO (LOAD )

ISO

ISO (RIP)

ISO

ISO (NOISE)

ISO

OSC

PWM

ISO (MAX)

ISO

ISO (MAX)

ISO

DD1

ISO

DD1 (Q)

DD1

ISO

DD1 (MAX)

1 Mbps—A Grade, C Grade

25 Mbps—C Grade

DD1

ISO

ISO (LOAD)

ADuM5401

100

87 mA

PHL

PLH

Pulse Width Distortion

PWD

40 6 ns

|t

PLH

− t

PHL

|

PSK

PSKCD

PSKOD

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY

Typical specifications are at TA = 25°C, V operation range which is 4.5 V ≤ V tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

L

DD1

Table 2. DC-to-DC Converter Static Specifications

DC-TO-DC CONVERTER SUPPLY

Setpoint V Line Regulation V Load Regulation V Output Ripple V Output Noise V Switching Frequency f PWM Frequency f Output Supply Current I Efficiency at I I

, No V

I

, Full V

Load I

34 % I

Load I

= V

= 5 V. Minimum/maximum specifications apply over the entire recommended

ISO

, V

DD1

SEL

, V

≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are

SEL

ISO

4.7 5.0 5.4 V I 1 mV/V I

1 5 % I

75 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µ F, I

200 mV p-p CBO = 0.1 µF||10 µ F, I

180 MHz

625 kHz

100 mA V

19 30 mA 290 mA

= 0 mA = 50 mA, V

= 4.5 V to 5.5 V

= 10 mA to 90 mA

> 4.5 V

= 100 mA

= 90 mA

Table 3. DC-to-DC Converter Dynamic Specifications

Parameter Symbol

Unit Test Conditions/Comments Min Typ Max Min Typ Max

SUPPLY CURRENT

Input I

ADuM5401 19 68 mA No V ADuM5402 19 71 mA No V ADuM5403 19 75 mA No V ADuM5404 19 78 mA No V

Available to Load I

load load load load

ADuM5402 100 85 mA ADuM5403 100 83 mA ADuM5404 100 81 mA

Table 4. Switching Specifications

A Grade C Grade

Parameter Symbol

Unit Test Conditions/Comments Min Typ Max Min Typ Max

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t

, t

55 100 45 60 ns 50% input to 50% output

Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t

50 15 ns Between any two units

Channel Matching

Codirectional1 t

Opposing Directional2 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the

isolation barrier.

50 6 ns 50 15 ns

Rev. C | Page 4 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

Table 5. Input and Output Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 × V Logic Low Input Threshold VIL

Logic High Output Voltages VOH V V Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V Undervoltage Lockout UVLO V

Positive Going Threshold V Negative Going Threshold V Hysteresis V

2.7 V

UV+

2.4 V

UV−

0.3 V

UVH

Input Currents per Channel II −20 +0.01 +20 μA 0 V ≤ VIx ≤ V

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient

Immunity

1

|CM| 25 35 kV/μs

Refresh Rate fr 1.0 Mbps

1

|CM | is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

− 0.3 or V

DD1

− 0.5 or V

DD1

or 0.7 × V

ISO

V

DD1

V

, V

DD1

= V

V

Ix

DDL

DD1

, V

or V

ISO

DDx

DD1

or 0.3 ×

ISO

0.3 × V V

− 0.3 5.0 V IOx = −20 μA, VIx = V

ISO

− 0.5 4.8 V IOx = −4 mA, VIx = V

ISO

transient magnitude = 800 V

or 0.7 × V

DD1

for a high output or VO < 0.3 × V

ISO

DD1

IxH

IxL

supplies

, VCM = 1000 V,

ISO

or 0.3 × V

ISO

for a

Rev. C | Page 5 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

ISO

ISO (LINE)

ISO

DD1

ISO (LOAD)

ISO

ISO (RIP)

ISO

ISO (NOISE)

ISO

OSC

PWM

ISO (MAX)

ISO

Efficiency at I

ISO (MAX)

33 %

I

ISO

= 60 mA

DD1

ISO

DD1 (Q)

DD1

ISO

DD1 (M AX)

DD1

ISO

ISO (LOAD)

PHL

PLH

PHL

PSK

PSKCD

Opposing Directional2

t

PSKOD

50

15

ns

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

Typical specifications are at TA = 25°C, V recommended operation range which is 3.0 V ≤ V specifications are tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

L

Table 6. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC-TO-DC CONVERTER SUPPLY

Setpoint V Line Regulation V Load Regulation V Output Ripple V Output Noise V Switching Frequency f PWM Frequency f Output Supply Current I

I

, No V

Load I

I

, Full V

Load I

Table 7. DC-to-DC Converter Dynamic Specifications

Parameter Symbol

SUPPLY CURRENT

Input I

ADuM5401 14 44 mA No V

ADuM5402 14 46 mA No V

ADuM5403 14 47 mA No V

ADuM5404 14 51 mA No V

Available to Load I

ADuM5401 60 52 mA

ADuM5402 60 51 mA

ADuM5403 60 49 mA

ADuM5404 60 48 mA

= V

DD1

= 3.3 V, V

ISO

, V

DD1

3.0 3.3 3.6 V I 1 mV/V I

1 5 % I

= GND

SEL

, V

≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching

SEL

ISO

. Minimum/maximum specifications apply over the entire

ISO

= 0 mA = 30 mA, V

= 3.0 V to 3.6 V

= 6 mA to 54 mA

50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, I

130 mV p-p CBO = 0.1 µF||10 µF, I

= 54 mA

180 MHz

625 kHz

60 mA V

> 3 V

14 20 mA

175 mA

1 Mbps—A or C Grade 25 Mbps—C Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

load load load load

= 54 mA

Table 8. Switching Specifications

Parameter Symbol

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t Pulse Width Distortion PWD 40 6 ns |t

Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t Channel Matching

Codirectional1 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the

isolation barrier.

A Grade C Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

, t

60 100 45 60 ns 50% input to 50% output

− t

|

50 45 ns Between any two units

50 6 ns

Rev. C | Page 6 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

ISO

DD1

ISO

IxH

DD1

ISO

IxH

IxL

DD1

DDL

ISO

Positive Going Threshold

V

UV+

2.7 V

UV−

UVH

DDx

Table 9. Input and Output Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 × V Logic Low Input Threshold VIL 0.3 × V

Logic High Output Voltages VOH V V Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = V

0.0 0.4 V IOx = 4 mA, VIx = V Undervoltage Lockout UVLO V

or 0.7 × V

− 0.3 or V

− 0.5 or V

V

or 0.3 ×

ISO

V

− 0.3 3.3 V IOx = −20 µA, VIx = V

− 0.5 3.1 V IOx = −4 mA, VIx = V

, V

supplies

Negative Going Threshold V Hysteresis V

2.4 V

0.3 V

Input Currents per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ V

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient

Immunity

1

|CM| 25 35 kV/µs V

= V

Ix

transient magnitude = 800 V

Refresh Rate fr 1.0 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

or 0.7 × V

DD1

for a high output or VO < 0.3 × V

ISO

DD1

or V

ISO

or 0.3 × V

DD1

, VCM = 1000 V,

for a

ISO

Rev. C | Page 7 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

ISO

ISO (LINE)

ISO

DD1

ISO (LOAD )

ISO

ISO (RIP)

ISO

ISO (NOISE)

ISO

OSC

PWM

ISO (MAX)

ISO

Efficiency at I

ISO (MAX)

30 %

I

ISO

= 90 mA

DD1

ISO

DD1 (Q)

DD1

ISO

DD1 (MAX)

DD1

ISO

ADuM5402

9

45 mA

No V

ISO

load

ISO

ISO (LOAD)

A Grade

C Grade

PHL

PLH

PHL

Change vs. Temperature

5

ps/°C

PSK

PSKCD

Opposing Directional2

t

PSKOD

50

15

ns

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

Typical specifications are at TA = 25°C, V recommended operation range which is 4.5 V ≤ V Switching specifications are tested with C

Table 10. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC-TO-DC CONVERTER SUPPLY

Setpoint V Line Regulation V Load Regulation V Output Ripple V Output Noise V Switching Frequency f PWM Frequency f Output Supply Current I

I

, No V

Load I

I

, Full V

Load I

Table 11. DC-to-DC Converter Dynamic Specifications

Parameter Symbol

SUPPLY CURRENT

Input I

ADuM5401 9 44 mA No V

= 5.0 V, V

DD1

= 15 pF and CMOS signal levels, unless otherwise noted.

L

3.0 3.3 3.6 V I 1 mV/V I

1 5 % I

= 3.3 V, V

ISO

≤ 5.5 V, 3.0 V ≤ V

DD1

= GND

SEL

ISO

. Minimum/maximum specifications apply over the entire

ISO

≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted.

= 0 mA = 50 mA, V

= 3.0 V to 3.6 V

= 6 mA to 54 mA

50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, I

130 mV p-p CBO = 0.1 µF||10 µ F, I

= 90 mA

180 MHz

625 kHz

100 mA V

> 3 V

14 20 mA

230 mA

1 Mbps—A or C Grade 25 Mbps—C Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

= 90 mA

load

ADuM5403 9 46 mA No V ADuM5404 9 47 mA No V

Available to Load I

load load

ADuM5401 100 92 mA ADuM5402 100 91 mA ADuM5403 100 89 mA ADuM5404 100 88 mA

Table 12. Switching Specifications

Parameter Symbol

Unit Test Conditions/Comments Min Typ Max Min Typ Max

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t Pulse Width Distortion PWD 40 6 ns |t

, t

60 100 45 60 ns 50% input to 50% output

− t

|

Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t

50 15 ns Between any two units

Channel Matching

Codirectional1 t

1

Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the

isolation barrier.

50 6 ns

Rev. C | Page 8 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

DD1

ISO

DD1

ISO

IxH

ISO

IxL

DD1

DDL

ISO

UV+

UV−

UVH

DDx

Common-Mode Transient

|CM|

25

35 kV/µs

VIx = V

or V

, VCM = 1000 V,

Table 13. Input and Output Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 × V

V

Logic Low Input Threshold VIL 0.3 × V

Logic High Output Voltages VOH V V

V

Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = V

0.0 0.4 V IOx = 4 mA, VIx = V Undervoltage Lockout UVLO V

Positive Going Threshold V Negative Going Threshold V Hysteresis V

2.7 V

2.4 V

0.3 V

Input Currents per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ V

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%

Immunity1

Refresh Rate fr 1.0 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

− 0.2, V

− 0.5 or

DD1

− 0.5

or 0.7 ×

ISO

− 0.2 V

V

DD1

V

or 0.3 ×

ISO

V

or V

V IOx = −20 µA, VIx = V

− 0.2 or

V IOx = −4 mA, VIx = V

− 0.2

or 0.7 × V

DD1

V

for a high output or VO < 0.3 × V

ISO

IxH

, V

supplies

DD1

ISO

transient magnitude = 800 V

or 0.3 × V

DD1

ISO

for a

Rev. C | Page 9 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

RESISTANCE AND CAPACITANCE

I-O

PACKAGE CHARACTERISTICS

Table 14.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input-to-Output)1 R Capacitance (Input-to-Output)1 C

1012 Ω

2.2 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction-to-Ambient Thermal

Resistance

1

This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

3

See the Thermal Analysis section for thermal model definitions.

θJA 45 °C/W Thermocouple located at center of package underside,

test conducted on 4-layer board with thin traces

3

REGULATORY INFORMATION

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are approved by the organizations listed in Table 15. Refer to Ta b l e 20 and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels.

Table 15.

UL1 CSA VDE (Pending)2

Recognized under 1577 component recognition program

1

Single protection, 2500 V rms isolation voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second

(current leakage detection limit = 10 µA).

2

In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥

1590 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval.

Approved under CSA Component Acceptance Notice #5A

Testing was conducted per CSA 60950-1-07 and IEC 60950-1 2

nd

Ed. at 2.5 kV rated voltage Basic insulation at 600 V rms (848 V peak) working voltage Reinforced insulation at 250 V rms (353 V peak) working voltage

Certified according to IEC 60747-5-2 (VDE 0884 Part 2):2003-012

Basic insulation, 560 V peak

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 16. Critical Safety-Related Dimensions and Material Properties

Parameter Symbol Value Unit Test Conditions/Comments

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Distance L(I01) 8.0 mm Measured from input terminals to output

Minimum External Tracking (Creepage) L(I02) 7.6 mm Measured from input terminals to output

Minimum Internal Gap (Internal Clearance) 0.017 min mm Distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1 Material Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

terminals, shortest distance through air

terminals, shortest distance path along body

Rev. C | Page 10 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

IORM

DD1

0

100

200

300

400

500

600

0 50 100 150 200

AMBIENT T E M P E RATURE (°C)

SAFE OPERATING V

DD1

CURRENT (mA)

06577-002

DD1

SEL

DD1

SEL

ISO

IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking branded on the package denotes IEC 60747-5-2 (VDE 0884, Part 2) approval.

Table 17. VDE Characteristics

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method b1 V

× 1.875 = VPR, 100% production test, tm = 1 sec,

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method a VPR

After Environmental Tests Subgroup 1 V

After Input and/or Safety Test Subgroup 2

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 896 V peak

V

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 4000 V peak Safety Limiting Values Maximum value allowed in the event of a failure

(see Figure 6) Case Temperature TS 150 °C Side 1 I

Current IS1 555 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

560 V peak

VPR 1050 V peak

Figure 6. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2

RECOMMENDED OPERATING CONDITIONS

Table 18.

Parameter Symbol Min Max Unit

Operating Temperature1 TA −40 +105 °C Supply Voltages2

V

@ V

= 0 V VDD 3.0 5.5 V

V

@ V

= V

VDD 4.5 5.5 V

1

Operation at 105°C requires reduction of the maximum load current as specified in Table 19.

2

Each voltage is relative to its respective ground.

Rev. C | Page 11 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 19.

Parameter Rating

Storage Temperature Range (TST) −55°C to +150°C Ambient Operating Temperature

Range (T Supply Voltages (V Input Voltage (VIA, VIB, VIC, VID, V

)

A

, V

)1 −0.5 V to +7.0 V

DD1

ISO

SEL

Output Voltage (VOA, VOB, VOC, VOD)

−40°C to +105°C

1, 2

)

−0.5 V to V

1, 2

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current per Pin3 −10 mA to +10 mA Common-Mode Transients4 −100 kV/μs to +100 kV/μs

1

Each voltage is relative to its respective ground.

2

V

and V

DDI

given channel, respectively. See the PCB Layout section.

3

See Figure 6 for maximum rated current values for various temperatures.

4

Common-mode transients exceeding the absolute maximum slew rate may

cause latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime

Parameter Max Unit Applicable Certification

AC Voltage, Bipolar Waveform 424 V peak AC Voltage, Unipolar Waveform

Basic Insulation 600 V peak

Reinforced Insulation 353 V peak Working voltage per IEC 60950-1 DC Voltage

Basic Insulation 600 V peak

Reinforced Insulation 353 V peak Working voltage per IEC 60950-1

1

Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

1

All certifications, 50-year operation

Working voltage per IEC 60950-1

Rev. C | Page 12 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

V

DD1

1

GND

1

2

V

IA

3

V

IB

4

V

ISO

16

GND

ISO

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

OD

6

V

ID

11

RC

OUT

7

V

SEL

10

GND

1

8

GND

ISO

9

ADuM5401

TOP VIEW

(Not to Scale)

06577-004

DD1

Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that

IA

5

VIC

Logic Input C.

OD

iso

SEL

ISO

SEL

ISO

ID

ISO

SEL

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 21. ADuM5401 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2, 8 GND

Primary Supply Voltage, 3.0 V to 5.5 V.

1

both pins be connected to a common ground.

3 V

Logic Input A.

4 VIB Logic Input B.

6 V 7 RC

OUT

Logic Output D. Regulation Control Output. This pin is connected to the RCIN pin of a slave

control the regulation of the slave device.

9, 15 GND

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins

ISO

be connected to a common ground. 10 V 11 V

Output Voltage Selection. When V

Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 V

Secondary Supply Voltage Output for External Loads, 3.3 V (V

Figure 7. ADuM5401 Pin Configuration

= V

, the V

setpoint is 5.0 V. When V

Power device to allow the ADuM5401 to

Low) or 5.0 V (V

= GND

High).

, the V

setpoint is 3.3 V.

Rev. C | Page 13 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

V

DD1

1

GND

1

2

V

IA

3

V

IB

4

V

ISO

16

GND

ISO

15

V

OA

14

V

OB

13

V

OC

5

V

IC

12

V

OD

6

V

ID

11

RC

OUT

7

V

SEL

10

GND

1

8

GND

ISO

9

ADuM5402

TOP VIEW

(Not to S cale)

06577-005

DD1

Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that

IA

6

V

OD

Logic Output D.

7

RC

iso

SEL

ISO

SEL

ISO

ID

ISO

SEL

Table 22. ADuM5402 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2, 8 GND

Primary Supply Voltage, 3.0 V to 5.5 V.

1

both pins be connected to a common ground.

3 V

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C.

OUT

Regulation Control Output. This pin is connected to the RCIN pin of a slave

control the regulation of the slave device. 9, 15 GND

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins

ISO

be connected to a common ground. 10 V 11 V

Output Voltage Selection. When V

Logic Input D. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 V

Secondary Supply Voltage Output for External Loads, 3.3 V (V

Figure 8. ADuM5402 Pin Configuration

= V

, the V

setpoint is 5.0 V. When V

Power device to allow the ADuM5402 to

= GND

Low) or 5.0 V (V

High).

, the V

setpoint is 3.3 V.

Rev. C | Page 14 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

V

DD1

1

GND

1

2

V

IA

3

V

OB

4

V

ISO

16

GND

ISO

15

V

OA

14

V

IB

13

V

OC

5

V

IC

12

V

OD

6

V

ID

11

RC

OUT

7

V

SEL

10

GND

1

8

GND

ISO

9

ADuM5403

TOP VIEW

(Not to S cale)

06577-006

DD1

Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that

IA

6

V

OD

Logic Output D.

7

RC

iso

SEL

ISO

SEL

ISO

ID

ISO

SEL

Table 23. ADuM5403 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2, 8 GND

Primary Supply Voltage, 3.0 V to 5.5 V.

1

both pins be connected to a common ground.

3 V

Logic Input A. 4 VOB Logic Output B. 5 VOC Logic Output C.

OUT

Regulation Control Output. This pin is connected to the RCIN pin of a slave

control the regulation of the slave device. 9, 15 GND

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins

ISO

be connected to a common ground. 10 V 11 V

Output Voltage Selection. When V

Logic Input D. 12 VIC Logic Input C. 13 VIB Logic Input B. 14 VOA Logic Output A. 16 V

Secondary Supply Voltage Output for External Loads, 3.3 V (V

Figure 9. ADuM5403 Pin Configuration

= V

, the V

setpoint is 5.0 V. When V

Power device to allow the ADuM5403 to

Low) or 5.0 V (V

= GND

High).

, the V

setpoint is 3.3 V.

Rev. C | Page 15 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

V

DD1

1

GND

1

2

V

OA

3

V

OB

4

V

ISO

16

GND

ISO

15

V

IA

14

V

IB

13

V

OC

5

V

IC

12

V

OD

6

V

ID

11

RC

OUT

7

V

SEL

10

GND

1

8

GND

ISO

9

ADuM5404

TOP VIEW

(Not to S cale)

06577-007

DD1

6

VOD

Logic Output D.

7

RC

iso

SEL

ISO

SEL

ISO

SEL

1

OUT

2

DD1

ISO

H

PWM

5 5 Master mode, normal operation

Figure 10. ADuM5404 Pin Configuration

Table 24. ADuM5404 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Primary Supply Voltage, 3.0 V to 5.5 V.

2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended

that both pins be connected to a common ground. 3 VOA Logic Output A. 4 VOB Logic Output B. 5 VOC Logic Output C.

OUT

Regulation Control Output. This pin is connected to the RCIN pin of a slave

Power device to allow the ADuM5404

to control the regulation of the slave device. 9, 15 GND

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both

ISO

pins be connected to a common ground. 10 V

Output Voltage Selection. When V

= V

, the V

setpoint is 5.0 V. When V

= GND

, the V

setpoint is 3.3 V. 11 VID Logic Input D. 12 VIC Logic Input C. 13 VIB Logic Input B. 14 VIA Logic Input A. 16 V

Secondary Supply Voltage Output for External Loads, 3.3 V (V

Low) or 5.0 V (V

High).

TRUTH TABLE

Table 25. Truth Table (Positive Logic)

V

RC

L PWM 5 3.3 Master mode, normal operation L PWM 3.3 3.3 Master mode, normal operation H PWM 3.3 5 This supply configuration is not recommended due to extremely poor efficiency

1

H refers to a high logic, and L refers to a low logic.

2

PWM refers to the regulation control signal. This signal is derived from the secondary side regulator and can be used to control other isoPower devices.

V

(V) V

(V) Notes

Rev. C | Page 16 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

0

5

10

15

20

25

30

35

40

0 0.02 0.04 0.06 0.08 0.10 0.12

06577-033

OUTPUT CURRE NT (A)

EFFICIENCY (%)

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT 5V INPUT/ 5V OUTPUT

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 0.02 0.04 0.06 0.08 0.10 0.12

I

ISO

(A)

POWER DISSIPATION (W)

V

DD1

= 5V, V

ISO

= 5V

V

DD1

= 5V, V

ISO

= 3.3V

V

DD1

= 3.3V, V

ISO

= 3.3V

06577-026

0

0.02

0.04

0.06

0.08

0.10

0.12

0 0.05 0.10 0.15 0.20 0.25 0.350.30

INPUT CURRENT ( A)

OUTPUT CURRE NT (A)

06577-027

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT 5V INPUT/ 5V OUTPUT

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

3.0 3.5 4.0 4.5 5.0 5

.5 6.0 6.5

INPUT SUPPLY VOLTAGE (V)

POWER (W)

I

DD

06577-011

INPUT CURRENT (A)

POWER

06577-012

OUTPUT VOLTAGE

(500mV/DIV)

(100µs/DIV)

DYNAMIC LOAD

10% LOAD

90% LOAD

06577-013

OUTPUT VOLTAGE

(500mV/DIV)

(100µs/DIV)

DYNAMIC LOAD

10% LOAD 90% LOAD

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 11. Typical Power Supply Efficiency at 5 V Input/5 V Output

and 3.3 V Input/3.3 V Output

Figure 14. Typical Short-Circuit Input Current and Power

vs. V

Supply Voltage

DD1

Figure 12. Typical Total Power Dissipation vs. Isolated Output Supply Current

in All Supported Power Configurations

Figure 13. Typical Isolated Output Supply Current vs. Input Current

in All Supported Power Configurations

Figure 15. Typical V

Rev. C | Page 17 of 28

Figure 16. Typical V

Transient Load Response, 5 V Output,

ISO

10% to 90% Load Step

Transient Load Response, 3.3 V Output,

ISO

10% to 90% Load Step

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

06577-014

BW = 20MHz (400ns/DIV)

5V OUTPUT RIPPLE (10mV /DIV)

06577-015

BW = 20MHz (400ns/DIV)

3.3V OUTPUT RIPPLE ( 10mV /DIV)

06577-030

TIME (ms)

V

ISO

(V)

7

6

5

4

3

2

1

0

–1 0 1 2 3

90% LOAD

10% LOAD

06577-031

TIME (ms)

V

ISO

(V)

5

4

3

2

1

0

–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0

90% LOAD

10% LOAD

0

4

8

12

16

20

0 5 10 15

DATA RATE (Mbps)

SUPPLY CURRENT (mA)

20 25

06577-028

5V INPUT/ 5V OUTPUT

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT

0

4

8

12

16

20

0 5 10 15

DATA RATE (Mbps)

SUPPLY CURRENT (mA)

20 25

5V INPUT/ 5V OUTPUT

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT

06577-029

Figure 17. Typical V

Figure 18. Typical V

= 5 V Output Voltage Ripple at 90% Load

ISO

= 3.3 V Output Voltage Ripple at 90% Load

ISO

Figure 20. Typical Output Voltage Start-Up Transient

at 10% and 90% Load, V

= 3.3 V

ISO

Figure 21. Typical ICH Supply Current per Forward Data Channel

(15 pF Output Load)

Figure 19. Typical Output Voltage Start-Up Transient

at 10% and 90% Load, V

ISO

= 5 V

Figure 22. Typical ICH Supply Current per Reverse Data Channel

(15 pF Output Load)

Rev. C | Page 18 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

0 5 10 15

DATA RATE (Mbps)

SUPPLY CURRENT (mA)

20 25

5V

3.3V

06577-119

0

2

1

3

4

5

0

1.0

0.5

1.5

2.0

2.5

3.0

0 5 10 15

DATA RATE (Mbps)

SUPPLY CURRENT (mA)

20 25

5V

3.3V

06577-118

Figure 23. Typical I

Dynamic Supply Current per Input

ISO (D)

Figure 24. Typical I

Dynamic Supply Current per Output

ISO (D)

(15 pF Output Load)

Rev. C | Page 19 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

TERMINOLOGY

I

DD1 (Q)

is the minimum operating current drawn at the V

I

DD1 (Q)

pin when there is no external load at V

and the I/O pins are

ISO

DD1

operating below 2 Mbps, requiring no additional dynamic supply current. I

I

DD1 (D)

I

is the typical input supply current with all channels

DD1 (D)

reflects the minimum current operating condition.

DD1 (Q)

simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load.

I

DD1 (MAX)

is the input current under full dynamic and V

DD1 (MAX)

ISO

load

conditions.

I

t

The t the falling edge of the V edge of the V

SO (LOAD)

is the current available to the load.

SO (LOAD)

Propagation Delay

PHL

propagation delay is measured from the 50% level of

PHL

signal to the 50% level of the falling

Ix

signal.

Ox

Propagation Delay

t

PLH

t

propagation delay is measured from the 50% level of the

PLH

rising edge of the V of the V

signal.

Ox

Propagation Delay Skew, t

t

is the magnitude of the worst-case difference in t

PSK

t

that is measured between units at the same operating temper-

PLH

signal to the 50% level of the rising edge

Ix

PSK

and/or

PHL

ature, supply voltages, and output load within the recommended operating conditions.

Channel-to-Channel Matching, (t

PSKCD/tPSKOD

)

Channel-to-channel matching is the absolute value of the difference in propagation delays between two channels when operated with identical loads.

Minimum Pulse Width

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

Maximum Data Rate

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

Rev. C | Page 20 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

V

APPLICATIONS INFORMATION

The dc-to-dc converter section of the ADuM5401/ADuM5402/

ADuM5403/ADuM5404 works on principles that are common to

most switching power supplies. It has a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. V

power is supplied to an oscillating circuit that

DD1

switches current into a chip scale air core transformer. Power transferred to the secondary side is rectified and regulated to either 3.3 V or 5 V. The secondary (V

) side controller regulates

ISO

the output by creating a PWM control signal that is sent to the primary (V

) side by a dedicated iCoupler data channel. The

DD1

PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 implement undervoltage lockout (UVLO) with hysteresis on the V

DD1

power input. This feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates.

PCB LAYOUT

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 digital isolators with 0.5 W isoPower integrated dc-to-dc converter require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 25). Note that low ESR bypass capacitors are required between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as close to the chip pads as possible.

The power supply section of the ADuM5401/ADuM5402/

ADuM5403/ADuM5404 uses a 180 MHz oscillator frequency

to pass power efficiently through its chip scale transformers. In addition, the normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. These are most conveniently connected between Pin 1 and Pin 2 for V

To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0.1 μF and 10 μF for V capacitor must have a low ESR; for example, use of a ceramic capacitor is advised.

The total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. Consider bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both common ground pins are connected together close to the package.

and between Pin 15 and Pin 16 for V

DD1

and V

. The smaller

ISO

.

BYPASS < 2mm

V

GND

IA/VOA IB/VOB IC/VOC

V

RC

OUT

GND

DD1

1

OD

1

Figure 25. Recommended PCB Layout

V

ISO

GND VOA/V VOB/V VOC/V V

ID

V

SEL

GND

ISO

IA IB IC

06577-120

In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur affects all pins equally on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings for the device as specified in Table 19, thereby leading to latch-up and/or permanent damage.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are power devices that dissipate approximately 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the PCB through the GND pins. If the devices are used at high ambient temperatures, provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 25 shows enlarged pads for Pin 8 and Pin 9. Large diameter vias should be implemented from the pad to the ground, and power planes should be used to reduce inductance. Multiple vias should be implemented from the pad to the ground plane to significantly reduce the temperature inside the chip. The dimensions of the expanded pads are at the discretion of the designer and depend on the available board space.

THERMAL ANALYSIS

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 parts consist of four internal die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the die is treated as a thermal unit, with the highest junction temperature reflected in the θ measurements taken with the parts mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the ADuM5401/ADuM5402/ADuM5403/

ADuM5404 devices operate at full load across the full temperature

range without derating the output current. However, following the recommendations in the PCB Layout section decreases thermal resistance to the PCB, allowing increased thermal margins in high ambient temperatures.

from Table 14. The value of θJA is based on

JA

Rev. C | Page 21 of 28

INPUT (V

Ix

)

OUTPUT (V

Ox

)

t

PLH

t

PHL

50%

06577-018

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see Figure 26). The propagation delay to a logic low output may differ from the propagation delay to a logic high.

Figure 26. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single

ADuM5401/ADuM5402/ADuM5403/ADuM5404 component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM5401/

ADuM5402/ADuM5403/ADuM5404 components operating

under the same conditions.

START-UP BEHAVIOR

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 do not contain a soft start circuit. Therefore, the start-up current and voltage behavior must be taken into account when designing with this device.

When power is applied to V to operate and draw current when the UVLO minimum voltage is reached. The switching circuit drives the maximum available power to the output until it reaches the regulation voltage where PWM control begins. The amount of current and the time required to reach regulation voltage depends on the load and the V

With a fast V up to 100 mA/V of V

slew rate.

DD1

slew rate (200 µs or less), the peak current draws

DD1

the output can turn on, so the peak current is proportional to the maximum input voltage.

With a slow V

slew rate (in the millisecond range), the input

DD1

voltage is not changing quickly when V minimum voltage. The current surge is approximately 300 mA because V

is nearly constant at the 2.7 V UVLO voltage. The

DD1

behavior during startup is similar to when the device load is a short circuit; these values are consistent with the short-circuit current shown in Figure 14.

When starting the device for V the current available to the V The ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices may not be able to drive the output to the regulation point if a current-limiting device clamps the V

, the input switching circuit begins

DD1

. The input voltage goes high faster than

reaches the UVLO

DD1

= 5 V operation, do not limit

ISO

power pin to less than 300 mA.

DD1

voltage during startup.

DD1

Rev. C | Page 22 of 28

As a result, the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices can draw large amounts of current at low voltage for extended periods of time.

The output voltage of the ADuM5401/ADuM5402/ADuM5403/

ADuM5404 devices exhibits V

overshoot during startup. If

ISO

this overshoot could potentially damage components attached to V

, a voltage-limiting device such as a Zener diode can be

ISO

used to clamp the voltage. Typical behavior is shown in Figure 19 and Figure 20.

EMI CONSIDERATIONS

The dc-to-dc converter section of the ADuM5401/ADuM5402/

ADuM5403/ADuM5404 devices must operate at 180 MHz to

allow efficient power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole radiation between the primary and secondary ground planes. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, follow good RF design practices in the layout of the PCB. See the

AN-0971 Application Note for board layout recommendations

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 µs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than approximately 5 µs, the input side is assumed to be unpowered or nonfunctional, and the isolator output is forced to a default low state by the watchdog timer circuit. This situation should occur in the ADuM5401/ADuM5402/ADuM5403/

ADuM5404 during power-up and power-down operations.

The limitation on the magnetic field immunity of the

ADuM5401/ADuM5402/ADuM5403/ADuM5404 is set by the

condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3.3 V operating condition of the

ADuM5401/ADuM5402/ADuM5403/ADuM5404 is examined

because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at approximately

0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)∑πr

where:

β is the magnetic flux density (gauss). r

is the radius of the nth turn in the receiving coil (cm).

n

N is the total number of turns in the receiving coil.

2

; n = 1, 2, … , N

n

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

MAGNETI C FIELD FRE QUENCY (Hz)

100

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY ( kgauss)

0.001 1M

10

0.01

1k 10k 10M

0.1

1

100M100k

06577-019

MAGNETI C FIELD FRE QUENCY (Hz)

MAXIMUM AL LOWABLE CURRE NT (kA)

1k

100

10

1

0.1

0.01 1k 10k 100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

06577-020

CONVERTER

PRIMARY

CONVERTER SECONDARY

PRIMARY

DATA

INPUT/OUTPUT

4-CHANNEL

I

DDP(D)

SECONDARY

DATA

INPUT/OUTPUT

4-CHANNEL

I

ISO(D)

I

ISO

I

DD1(Q)

I

DD1(D)

06577-024

Given the geometry of the receiving coil in the ADuM5401/

ADuM5402/ADuM5403/ADuM5404, and an imposed

requirement that the induced voltage be, at most, 50% of the

0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 27.

Note that, at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. Exercise care in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The V channels, as well as to the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary input/output channels cannot be determined separately. All of these quiescent power demands have been combined into the I current is the sum of the quiescent operating current; the dynamic current, I I

ISO

power supply input provides power to the iCoupler data

DD1

current, as shown in Figure 29. The total I

DD1 (Q)

, demanded by the I/O channels; and any external

DD1 (D)

load.

supply

DD1

Figure 27. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This voltage is approximately 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to

0.75 V, still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM5401/

ADuM5402/ADuM5403/ADuM5404 transformers. Figure 28

expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 28, the

ADuM5401/ADuM5402/ADuM5403/ADuM5404 are extremely

immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example, a 0.5 kA current placed 5 mm away from the

ADuM5401/ADuM5402/ADuM5403/ADuM5404 is required

to affect the operation of the device.

Figure 28. Maximum Allowable Current for Various Current-to-

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Spacings

Figure 29. Power Consumption Within the

ADuM5401/ADuM5402/ADuM5403/ADuM5404

Both dynamic input and output current is consumed only when operating at channel speeds higher than the refresh rate, f

. Each channel has a dynamic current determined by its data

r

rate. Figure 21 shows the current for a channel in the forward direction, which means that the input is on the primary side of the part. Figure 22 shows the current for a channel in the reverse direction, which means that the input is on the secondary side of the part. Both figures assume a typical 15 pF load. The following relationship allows the total I

I

= (I

× V

DD1

ISO

)/(E × V

ISO

current to be calculated:

DD1

) + Σ I

; n = 1 to 4 (1)

CHn

where:

I

is the total supply input current.

DD1

I

is the current drawn by a single channel determined from

CHn

Figure 21 or Figure 22, depending on channel direction.

I

is the current drawn by the secondary side external load.

ISO

E is the power supply efficiency at 100 mA load from Figure 11

at the V

ISO

and V

condition of interest.

DD1

Rev. C | Page 23 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

The maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load.

I

ISO (LOAD)

= I

ISO (MAX)

− Σ I

; n = 1 to 4 (2)

ISO (D)n

where:

I

is the current available to supply an external secondary

ISO (LOAD)

side load.

I

is the maximum external secondary side load current

ISO (MAX)

available at V

is the dynamic load current drawn from V

I

ISO (D)n

ISO

.

by an input

ISO

or output channel, as shown in Figure 23 and Figure 24.

The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of I

DD1

and I

ISO (LOAD)

.

POWER CONSIDERATIONS

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 power input, data input channels on the primary side, and data channels on the secondary side are all protected from premature operation by undervoltage lockout (UVLO) circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. Outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations.

During application of power to V is held idle until the UVLO preset voltage is reached. At that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side.

When the primary side is above the UVLO threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. The outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary side power is established. The primary side oscillator also begins to operate, transferring power to the secondary power circuits.

The secondary V

voltage is below its UVLO limit at this

ISO

point; the regulation control signal from the secondary side is not being generated. The primary side power oscillator is allowed to free run under these conditions, supplying the maximum amount of power to the secondary side.

As the secondary side voltage rises to its regulation setpoint, a large inrush current transient is present at V regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. The V

current is then reduced and is propor-

DD1

tional to the load current. The inrush current is less than the short-circuit current shown in Figure 14. The duration of the inrush current depends on the V the current and voltage available at the V

, the primary side circuitry

DD1

. When the

DD1

loading conditions and on

ISO

pin.

DD1

As the secondary side converter begins to accept power from the primary, the V

voltage starts to rise. When the secondary side

ISO

UVLO is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. It can take up to 1 μs after the secondary side is initialized for the state of the output to correlate to the primary side input.

Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid about 1 μs after the secondary side becomes active.

Because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care that the design allows the converter sufficient time to stabilize before valid data is required.

When power is removed from V

, the primary side converter

DD1

and coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge.

The outputs on the secondary side hold the last state that they received from the primary side. Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO.

INCREASING AVAILABLE POWER

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are designed with the capability of running in combination with other compatible isoPower devices. The RC

ADuM5401/ADuM5402/ADuM5403/ADuM5404 to provide its

PWM signal to another device acting as a master to regulate its self and slave devices. Power outputs are combined in parallel while sharing output power equally.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 can only be a master/standalone, and the ADuM5200 can only be a slave/ standalone device. The ADuM5000 can operate as either a master or slave. This means that the ADuM5000, ADuM520x, and

ADuM540x can only be used in the master/slave combinations

listed in Table 26.

Table 26. Allowed Combinations of isoPower Parts

Slave

Master ADuM5000 ADuM520x ADuM540x

ADuM5000 Ye s Ye s No ADuM520x No No No ADuM540x Yes Yes No

The allowed combinations of master and slave configured parts listed in Table 26 is sufficient to make any combination of power and channel count.

pin allows the

OUT

Rev. C | Page 24 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

Table 27 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single unit power.

Table 27. Configurations for Power and Data Channels

Number of Data Channels Power Unit 0 Channels 2 Channels 4 Channels 6 Channels

1-Unit Power ADuM5000 master ADuM520x master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM121x 2-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM520x slave ADuM520x slave ADuM520x slave 3-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM5000 slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM5000 slave

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM5401/ADuM5402/

ADuM5403/ADuM5404 devices.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 20 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM5401/ADuM5402/

ADuM5403/ADuM5404 devices depends on the voltage wave-

form type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30, Figure 31, and Figure 32 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the bipolar ac condition determines the maximum working voltage recommended by Analog Devices.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 20 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage cases.

Any cross-insulation voltage waveform that does not conform to Figure 31 or Figure 32 should be treated as a bipolar ac waveform and its peak voltage limited to the 50-year lifetime voltage value listed in Table 20. The voltage presented in Figure 32 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 30. Bipolar AC Waveform

06577-021

RATED PEAK VOL TAGE

0V

Figure 31. DC Waveform

06577-023

RATED PEAK VOL TAGE

0V

NOTES:

1. THE VOLTAGE IS SHOWN AS SINUS OIDAL FO R ILLUSTRATION PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE WAVEFO RM VARYING BETWEEN 0V AND SOME LIMIT ING VALUE. THE LIMITING V AL UE CAN BE POSITI VE OR NEGATIV E , BUT THE VOLTAGE CANNOT CROS S 0V.

Figure 32. Unipolar AC Waveform

06577-022

Rev. C | Page 25 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

10.50 (0.4134)

10.10 (0.3976)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75 (0.0295)

0.25 (0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING PLANE

8° 0°

16

9

8

1

1.27 (0.0500) BSC

03-27-2007-B

DD1

ISO

OUTLINE DIMENSIONS

Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Inputs,

Side

V

Model

1, 2

ADuM5401ARWZ 3 1 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5401CRWZ 3 1 25 60 6 −40 to +105 16-Lead SOIC_W RW-16 ADuM5402ARWZ 2 2 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5402CRWZ 2 2 25 60 6 −40 to +105 16-Lead SOIC_W RW-16 ADuM5403ARWZ 1 3 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5403CRWZ 1 3 25 60 6 −40 to +105 16-Lead SOIC_W RW-16 ADuM5404ARWZ 0 4 1 100 40 −40 to +105 16-Lead SOIC_W RW-16 ADuM5404CRWZ 0 4 25 60 6 −40 to +105 16-Lead SOIC_W RW-16

1

Z = RoHS Compliant Part.

2

Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option.

Number of Inputs,

Side

V

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse Width Distortion (ns)

Temperature Range (°C)

Package Description

Package Option

Rev. C | Page 26 of 28

Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404

NOTES

Rev. C | Page 27 of 28

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D06577-0-6/12(C)

Rev. C | Page 28 of 28

Datasheet ADUM5401 Datasheet (ANALOG DEVICES)

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TRUTH TABLE

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

APPLICATIONS INFORMATION

PCB LAYOUT

THERMAL ANALYSIS

PROPAGATION DELAY-RELATED PARAMETERS

START-UP BEHAVIOR

EMI CONSIDERATIONS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

POWER CONSIDERATIONS

INCREASING AVAILABLE POWER

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE