Datasheet ADUM5200 Datasheet (ANALOG DEVICES)

Dual-Channel, 2.5 kV Isolators with

V

Data Sheet

FEATURES

isoPower integrated, isolated dc-to-dc converter Regulated 3.3 V or 5 V output Up to 500 mW output power Dual, dc-to-25 Mbps (NRZ) signal isolation channels 16-lead SOIC package with 7.6 mm creepage High temperature operation: 105°C maximum High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals

UL recognition

2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A) VDE certificate of conformity (pending)

IEC 60747-5-2 (VDE 0884, Part 2):2003-01

V

= 560 V

IORM

APPLICATIONS

RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Power supply start-up bias and gate drives Isolated sensor interfaces Industrial PLCs

GENERAL DESCRIPTION

The ADuM5200/ADuM5201/ADuM52021 are dual-channel digital isolators with isoPower®, an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler® technology, the dc-to-dc converter provides up to 500 mW of regulated, isolated power at either 5.0 V or 3.3 V from a 5.0 V input supply, or 3.3 V from a 3.3 V supply at the power levels shown in Table 1. These devices eliminate the need for a separate, isolated dc-to-dc converter in low power isolated designs. The iCoupler chip scale transformer technology is used to isolate the logic signals and for the magnetic components of the dc-to-dc converter. The result is a small form factor, total isolation solution.

The ADuM5200/ADuM5201/ADuM5202 isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for more information).

isoPower uses high frequency switching elements to transfer power through its transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. See the

AN-0971 Application Note for board layout recommendations.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

PEAK

Integrated DC-to-DC Converter

ADuM5200/ADuM5201/ADuM5202

FUNCTIONAL BLOCK DIAGRAMS

OSC

1

V

DD1

2

GND

1

3

IA/VOA

IB/VOB

RC

SEL

VE1/NC

GND

IN

1

2-CHANNEL iCOUPLER CORE

4

5

6

7

8

V

IA

3

ADuM5200

V

IB

4

Figure 2. ADuM5200

V

IA

3

ADuM5201

V

OB

4

Figure 3. ADuM5201

V

OA

3

ADuM5202

V

OB

4

Figure 4. ADuM5202

Table 1. Power Levels

Input Voltage (V) Output Voltage (V) Output Power (mW)

5.0 5.0 500

5.0 3.3 330

3.3 3.3 200

ADuM5200/ ADuM5201/

ADuM5202

Figure 1.

RECT

REG

V

OA

14

V

OB

13

V

OA

14

V

IB

13

V

IA

14

V

IB

13

16

V

ISO

15

GND

ISO

14

VIA/V

OA

13

VIB/V

OB

12

NC

V

11

SEL

VE2/NC

10

GND

9

ISO

07540-001

07540-002

07540-003

07540-004

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuM5200/ADuM5201/ADuM5202 Data Sheet

REVISION HISTORY

5/12—Rev. A to Rev. B

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Updated Outline Dimensions ....................................................... 25

9/11—Rev. 0 to Rev. A

Changes to Product Title, Features Section, and General

Description Section .......................................................................... 1

Added Table 1; Renumbered Sequentially .................................... 1

Changes to Specifications Section .................................................. 3

Changes to Table 19 and Table 20 ................................................ 11

Changes to Pin 5 Description, Table 21 ....................................... 12

Changes to Pin 5 Description, Table 22 ....................................... 13

Changes to Pin 5 Description, Table 23 and Tab l e 24 ............... 14

Changes to Figure 9 to Figure 11 .................................................. 15

Added Figure 17 and Figure 18; Renumbered Sequentially ..... 16

Changes to Figure 19 and Figure 20 ............................................ 16

Changes to Terminology Section ................................................. 18

Changes to Applications Information Section ........................... 19

Added Start-Up Behavior Section ................................................ 19

Changes to EMI Considerations Section .................................... 20

10/08—Revision 0: Initial Version

Rev. B | Page 2 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

ISO

ISO (LINE)

ISO

DD1

ISO (LOAD )

ISO

ISO (RIP)

ISO

ISO (NOISE)

ISO

OSC

PWM

ISO (MAX)

ISO

ISO (MAX)

ISO

DD1

ISO

DD1 (Q)

DD1

ISO

DD1 (MAX)

ISO

DD1

ISO (LOAD)

PHL

PLH

PHL

PSK

PSKCD

PSKOD

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY

All typical specifications are at TA = 25°C, V operation range which is 4.5 V ≤ V tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

L

DD1

Table 2. DC-to-DC Converter Static Specifications

DC-TO-DC CONVERTER SUPPLY

Setpoint V Line Regulation V Load Regulation V Output Ripple V Output Noise V Switching Frequency f PW Modulation Frequency f Output Supply I Efficiency at I I

, No V

Load I

I

, Full V

34 % I

Load I

= V

DD1

SEL

, V

≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are

SEL

ISO

4.7 5.0 5.4 V I 1 mV/V I

1 5 % I

= 5 V. Minimum/maximum specifications apply over the entire recommended

ISO

= 0 mA = 50 mA, V

= 4.5 V to 5.5 V

= 10 mA to 90 mA

75 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, I

200 mV p-p CBO = 0.1 µF||10 µF, I

= 90 mA

180 MHz

625 kHz

100 mA V

> 4.5 V

= 100 mA 8 22 mA 290 mA

= 90 mA

Table 3. DC-to-DC Converter Dynamic Specifications

1 Mbps—A Grade or C Grade 25 Mbps—C Grade

Parameter Symbol

Unit Test Conditions Min Typ Max Min Typ Max

SUPPLY CURRENT

Input No V

ADuM5200 I ADuM5201 I ADuM5202 I

6 34 mA 7 38 mA 7 41 mA

load

Available to Load

ADuM5200 I ADuM5201 I ADuM5202 I

100 94 mA 100 92 mA 100 90 mA

Table 4. Switching Specifications

A Grade C Grade

Parameter Symbol

Unit Test Conditions Min Typ Max Min Typ Max

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t Pulse Width Distortion PWD 40 6 ns |t

, t

55 100 45 60 ns 50% input to 50% output

− t

|

Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t

50 15 ns Between any two units

Channel Matching

Codirectional1 t

Opposing Directional2 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the

isolation barrier.

50 6 ns 50 15 ns

Rev. B | Page 3 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

ISO

DD1

ISO

DD1

ISO

IxH

DD1

ISO

IxH

IxL

DD1

DDL

ISO

UV+

UV−

UVH

DDx

AC SPECIFICATIONS

Table 5. Input and Output Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages VOH V V Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V Undervoltage Lockout V

Positive Going Threshold V Negative Going Threshold V Hysteresis V

2.7 V

2.4 V

0.3 V

Input Currents per Channel II −20 +0.01 +20 µA 0 V ≤ VIx ≤ V

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient

Immunity

1

|CM| 25 35 kV/µs V

Refresh Rate fr 1.0 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

or 0.7 V

− 0.3 or V

− 0.5 or V

V

or 0.3 V

V

− 0.3 5.0 V IOx = −20 µA, VIx = V

− 0.5 4.8 V IOx = −4 mA, VIx = V

, V

supplies

= V

or V

Ix

DD1

, VCM = 1000 V,

ISO

transient magnitude = 800 V

or 0.7 × V

DD1

for a high output or VO < 0.3 × V

ISO

or 0.3 × V

DD1

for a

ISO

Rev. B | Page 4 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

ISO

ISO (LINE)

ISO

DD1

ISO (LOAD )

ISO

ISO (RIP)

ISO

ISO (NOISE)

ISO

OSC

PWM

Output Supply

I

ISO (MAX)

60

mA

V

ISO

> 3 V

ISO (MAX)

ISO

DD1

ISO

DD1 (Q)

DD1

ISO

DD1 (MAX)

ISO

DD1

ISO (LOAD)

SWITCHING SPECIFICATIONS

PHL

PLH

PHL

PSK

PSKCD

PSKOD

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

All typical specifications are at TA = 25°C, V recommended operation range which is 3.0 V ≤ V specifications are tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

L

Table 6. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions

DC-TO-DC CONVERTER SUPPLY

Setpoint V Line Regulation V Load Regulation V Output Ripple V Output Noise V Switching Frequency f PW Modulation Frequency f

= V

DD1

= 3.3 V, V

ISO

, V

DD1

SEL

, V

3.0 3.3 3.6 V I 1 mV/V I

1 5 % I

= GND

SEL

≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching

ISO

. Minimum/maximum specifications apply over the entire

ISO

= 0 mA = 30 mA, V

= 3.0 V to 3.6 V

= 6 mA to 54 mA

50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, I

130 mV p-p CBO = 0.1 µF||10 µF, I

= 54 mA

180 MHz

625 kHz

= 54 mA

Efficiency at I I

, No V

Load I

I

, Full V

34 % I

6 15 mA

Load I

175 mA

= 60 mA

Table 7. DC-to-DC Converter Dynamic Specifications

1 Mbps—A Grade or C Grade 25 Mbps—C Grade

Parameter Symbol

Unit Test Conditions Min Typ Max Min Typ Max

SUPPLY CURRENT

Input No V

ADuM5200 I ADuM5201 I ADuM5202 I

4 23 mA 4 25 mA 5 27 mA

load

Available to Load

ADuM5200 I ADuM5201 I ADuM5202 I

60 56 mA 60 55 mA 60 54 mA

Table 8. Switching Specifications

A Grade C Grade

Parameter Symbol

Unit Test Conditions Min Typ Max Min Typ Max

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t Pulse Width Distortion PWD 40 6 ns |t

, t

60 100 45 60 ns 50% input to 50% output

− t

|

Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew t

50 45 ns Between any two units

Channel Matching

Codirectional1 t

Opposing Directional2 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the

isolation barrier.

50 6 ns 50 15 ns

Rev. B | Page 5 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

ISO

DD1

ISO

DD1

ISO

IxH

DD1

ISO

IxH

IxL

DD1

DDL

ISO

UV+

Negative Going Threshold

V

UV−

2.4 V

UVH

DDx

AC SPECIFICATIONS

Table 9. Input and Output Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages VOH V V Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = V

0.0 0.4 V IOx = 4 mA, VIx = V Undervoltage Lockout V

Positive Going Threshold V

2.7 V

or 0.7 V

− 0.3 or V

− 0.5 or V

V

or 0.3 V

V

− 0.3 3.3 V IOx = −20 µA, VIx = V

− 0.5 3.1 V IOx = −4 mA, VIx = V

, V

supplies

Hysteresis V

0.3 V

Input Currents per Channel II −20 +0.01 +20 µA 0 V ≤ VIx ≤ V

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient

Immunity

1

|CM| 25 35 kV/µs V

= V

Ix

transient magnitude = 800 V

Refresh Rate fr 1.0 Mbps

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

or 0.7 × V

DD1

for a high output or VO < 0.3 × V

ISO

DD1

or V

ISO

or 0.3 × V

DD1

, VCM = 1000 V,

for a

ISO

Rev. B | Page 6 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

ISO

ISO (LINE)

ISO

DD1

ISO (LOAD )

ISO

ISO (RIP)

ISO

ISO (NOISE)

ISO

OSC

PWM

ISO (MAX)

ISO

Efficiency at I

ISO (MAX)

30 %

I

ISO

= 90 mA

DD1

ISO

DD1 (Q)

DD1

ISO

DD1 (MAX)

ISO

DD1

ADuM5201

I

DD1

5

23 mA

DD1

ISO (LOAD)

PHL

PLH

PHL

Propagation Delay Skew

t

PSK

50

15

ns

Between any two units

PSKCD

PSKOD

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

All typical specifications are at TA = 25°C, V entire recommended operation range which is 4.5 V ≤ V noted. Switching specifications are tested with C

Table 10. DC-to-DC Converter Static Specifications

Parameter Symbol Min Typ Max Unit Test Conditions

DC-TO-DC CONVERTER SUPPLY

Setpoint V Line Regulation V Load Regulation V Output Ripple V Output Noise V Switching Frequency f PW Modulation Frequency f Output Supply I

I

, No V

Load I

I

, Full V

Load I

Table 11. DC-to-DC Converter Dynamic Specifications

Parameter Symbol

SUPPLY CURRENT

Input No V

ADuM5200 I

5 22 mA

= 5.0 V, V

DD1

= 15 pF and CMOS signal levels, unless otherwise noted.

L

3.0 3.3 3.6 V I 1 mV/V I

1 5 % I

= 3.3 V, V

ISO

≤ 5.5 V, 3.0 V ≤ V

DD1

= GND

SEL

. Minimum/maximum specifications apply over the

ISO

≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise

ISO

= 0 mA = 50 mA, V

= 3.0 V to 3.6 V

= 6 mA to 54 mA

50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, I

130 mV p-p CBO = 0.1 µF||10 µF, I

= 90 mA

180 MHz

625 kHz

100 mA V

> 3 V

5 15 mA

230 mA

1 Mbps—A Grade or C Grade 25 Mbps—C Grade

Unit Test Conditions Min Typ Max Min Typ Max

= 90 mA

load

ADuM5202 I

5 24 mA

Available to Load

ADuM5200 I ADuM5201 I ADuM5202 I

100 96 mA 100 95 mA 100 94 mA

Table 12. Switching Specifications

A Grade C Grade

Parameter Symbol

Unit Te st Conditions Min Typ Max Min Typ Max

SWITCHING SPECIFICATIONS

Data Rate 1 25 Mbps Within PWD limit Propagation Delay t Pulse Width Distortion PWD 40 6 ns |t

, t

60 100 45 60 ns 50% input to 50% output

− t

|

Change vs. Temperature 5 ps/°C

Pulse Width PW 1000 40 ns Within PWD limit

Channel Matching

Codirectional1 t Opposing Directional2 t

1

7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2

Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

50 6 ns 50 15 ns

Rev. B | Page 7 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

Table 13. Input and Output Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages VOH V

Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = V

0.0 0.4 V IOx = 4 mA, VIx = V Undervoltage Lockout V

Positive Going Threshold V Negative Going Threshold V Hysteresis V

2.7 V

UV+

2.4 V

UV−

0.3 V

UVH

Input Currents per Channel II −20 +0.01 +20 μA 0 V ≤ VIx ≤ V

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient

Immunity

1

|CM| 25 35 kV/μs

Refresh Rate fr 1.0 Mbps

1

|CM | is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × V

low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

DD1

V

DD1

V

ISO

or 0.7 V

ISO

− 0.2, V

− 0.5 or

− 0.5

V

DD1

− 0.2 V

ISO

DD1

V

DD1

V

ISO

or 0.3 V

ISO

or V

V IOx = −20 μA, VIx = V

ISO

− 0.2 or

V IOx = −4 mA, VIx = V

− 0.2

or 0.7 × V

DD1

V

DD1

for a high output or VO < 0.3 × V

ISO

IxH

IxL

, V

DD1

DDL

or V

supplies

ISO

DDx

ISO

, VCM = 1000 V,

DD1

= V

V

Ix

transient magnitude = 800 V

or 0.3 × V

DD1

ISO

for a

Rev. B | Page 8 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

PACKAGE CHARACTERISTICS

Table 14. Thermal and Isolation Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions

RESISTANCE AND CAPACITANCE

Resistance (Input-to-Output)1 R Capacitance (Input-to-Output)

1

Input Capacitance2 C IC Junction to Ambient Thermal Resistance θJA 45 °C/W

THERMAL SHUTDOWN

Threshold TSSD 150 °C TJ rising Hysteresis TS

1

This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

3

Refer to the Power Considerations section for thermal model definitions.

REGULATORY INFORMATION

The ADuM5200/ADuM5201/ADuM5202 are approved by the organizations listed in Table 15. Refer to Table 20 and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels.

102 Ω

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

Thermocouple located at the center of the package underside; test conducted on a 4-layer board with thin traces

20 °C

SD-HYS

3

Table 15.

UL1 CSA VDE (Pending)2

Recognized under UL 1577 component recognition program

1

Single protection, 2500 V rms isolation voltage

Approved under CSA Component Acceptance Notice #5A

Testing was conducted per CSA 60950-1-07 and IEC 60950-1 2 Basic insulation at 600 V rms (848 V

nd

Ed. at 2.5 kV rated voltage

)

PEAK

Certified according to IEC 60747-5-2 (VDE 0884, Part 2):2003-012

Basic insulation, 560 V

PEAK

working voltage Reinforced insulation at 250 V rms (353 V

PEAK

)

working voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM5200/ADuM5201/ADuM5202 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage

detection limit = 10 μA).

2

In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM520x is proof tested by applying an insulation test voltage ≥ 1590 V

discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884, Part 2):2003-01 approval.

for 1 second (partial

PEAK

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 16. Critical Safety-Related Dimensions and Material Properties

Parameter Symbol Value Unit Test Conditions/Comments

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap L(I01) 8.0 mm

Minimum External Tracking (Creepage) L(I02) 7.6 mm

Minimum Internal Distance (Internal Clearance) 0.017 min mm Distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1 Isolation Group IIIa Material group (DIN VDE 0110, 1/89, Table 1)

Distance measured from input terminals to output terminals; shortest distance through air along the PCB mounting plane, as an aid to PC board layout

Measured from input terminals to output terminals, shortest distance path along body

Rev. B | Page 9 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

IORM

PEAK

IOTM

PEAK

Withstand Isolation Voltage

1 minute withstand rating

V

ISO

2500

V

RMS

PEAK

IOSM

PEAK

DD1

Insulation Resistance at TS

VIO = 500 V

RS

>109

Ω

0

100

200

300

400

500

600

0 50 100 150 200

AMBIENT TE M P E RATURE (°C)

SAFE OPERATING V

DD1

CURRENT (mA)

07540-005

DD1

SEL

DD1

SEL

ISO

DD1

IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking branded on the components designates IEC 60747-5-2 (VDE 0884, Part 2):2003-1 approval.

Table 17. VDE Characteristics

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method b1 V

× 1.875 = V

IORM

, 100% production test, t

pd (m)

= tm =

ini

1 sec, partial discharge < 5 pC

Input-to-Output Test Voltage, Method a

After Environmental Tests Subgroup 1 V

× 1.5 = V

IORM

, t

= 60 sec, tm = 10 sec, partial

pd (m)

ini

discharge < 5 pC

After Input and/or Safety Test Subgroup 2

and Subgroup 3

V

× 1.2 = V

IORM

pd (m)

discharge < 5 pC

, t

= 60 sec, tm = 10 sec, partial

ini

Highest Allowable Overvoltage V

560 V

V

1050 V

pd (m)

V

840 V

pd (m)

V

672 V

pd (m)

4000 V

PEAK

Surge Isolation Voltage V

= 6 kV, 1.2 µs rise time, 50 µs, 50% fall time V

Safety Limiting Values Maximum value allowed in the event of a failure

(see Figure 5) Case Temperature TS 150 °C Side 1 I

Current IS1 555 mA

Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2

RECOMMENDED OPERATING CONDITIONS

Table 18.

Parameter Symbol Min Max Unit

Operating Temperature1 TA −40 +105 °C Supply Voltages2

V

@ V

V

1

Operation at 105°C requires reduction of the maximum load current as specified in Table 19.

2

Each voltage is relative to its respective ground.

= 0 V V

@ V

= V

V

3.0 5.5 V

4.5 5.5 V

6000 V

Rev. B | Page 10 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

A

DD1

ISO

SEL

DDI

Output Voltage (VOA, VOB)

−0.5 V to V

DDO

+ 0.5 V

Average Output Current per Pin3

−10 mA to +10 mA

PEAK

AC Voltage, Unipolar Waveform

Basic Insulation

600

V

PEAK

Working voltage, 50-year operation

PEAK

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 19.

Parameter Rating

Storage Temperature Range (TST) −55°C to +150°C Ambient Operating Temperature

Range (T Supply Voltages (V Input Voltage (VIA, VIB, RCIN, RC

)

, V

)1 −0.5 V to +7.0 V

, V

1, 2

−40°C to +105°C

1, 2

)

−0.5 V to V

+ 0.5 V

Common-Mode Transients4 −100 kV/µs to +100 kV/µs

1

Each voltage is relative to its respective ground.

2

V

and V

DDI

given channel, respectively. See the PCB Layout section.

3

See Figure 5 for maximum rated current values for various temperatures.

4

Common-mode transients exceeding the absolute maximum slew rate may

cause latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime

Parameter Max Unit Applicable Certification

AC Voltage, Bipolar Waveform 424 V

All certifications, 50-year operation

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

1

Reinforced Insulation 353 V

Working voltage per IEC 60950-1

DC Voltage

Basic Insulation 600 V Reinforced Insulation 353 V

1

Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.

Working voltage per IEC 60950-1

Working voltage, 50-year operation

Rev. B | Page 11 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

V

DD1

1

GND

1

2

V

IA

3

V

IB

4

V

ISO

16

GND

ISO

15

V

OA

14

V

OB

13

RC

IN

5

NC

12

RC

SEL

6

V

SEL

11

NC

7

V

E2

10

GND

1

8

GND

ISO

9

ADuM5200

TO

P VIEW

(Not to S cale)

07540-006

NC = NO CONNECT

DD1

2, 8

GND1 Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and

IA

iso

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended

ISO

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 6. ADuM5200 Pin Configuration

Table 21. ADuM5200 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Primary Supply Voltage, 3.0 V to 5.5 V.

it is recommended that both pins be connected to a common ground.

3 V

Logic Input A. 4 VIB Logic Input B. 5 RC

6 RC

IN

Control Input. Determines self-regulation mode (RC

SEL

Regulation Control Input. This pin must be connected to the RC

that this pin must not be tied high if RC

damaging the

ADuM5200 and possibly the devices that it powers.

is low; this combination causes excessive voltage on the secondary side,

SEL

high) or slave mode (RC

SEL

pin of a master

OUT

Power device or tied low. Note

low), allowing external regulation.

SEL

This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low. 7, 12 NC No Internal Connection. 9, 15 GND

ISO

that both pins be connected to a common ground. 10 VE2 Data Enable Input. When this pin is high or not connected, the secondary outputs are active; when this pin is low,

the outputs are in a high-Z state. 11 V

Output Voltage Selection. When V

SEL

= V

ISO

, the V

setpoint is 5.0 V. When V

ISO

= GND

SEL

ISO

, the V

setpoint is 3.3 V.

ISO

In slave regulation mode, this pin has no function. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 V

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

Rev. B | Page 12 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

V

DD1

1

GND

1

2

V

IA

3

V

OB

4

V

ISO

16

GND

ISO

15

V

OA

14

V

IB

13

RC

IN

5

NC = NO CONNECT

NC

12

RC

SEL

6

V

SEL

11

V

E1

7

V

E2

10

GND

1

8

GND

ISO

9

ADuM5201

TOP VIEW

(Not to S cale)

07540-007

DD1

IA

iso

9, 15

GND

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended

ISO

Figure 7. ADuM5201 Pin Configuration

Table 22. ADuM5201 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2, 8 GND

Primary Supply Voltage, 3.0 V to 5.5 V. Ground 1. Ground reference for isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and it is

1

recommended that both pins be connected to a common ground.

3 V

Logic Input A. 4 VOB Logic Output B. 5 RC

6 RC

IN

SEL

Regulation Control Input. This pin must be connected to the RC

that this pin must not be tied high if RC

damaging the

ADuM5201 and possibly the devices that it powers.

is low; this combination causes excessive voltage on the secondary side,

SEL

Control Input. Determines self-regulation mode (RC

pin of a master

OUT

high) or slave mode (RC

SEL

Power device or tied low. Note

low), allowing external regulation.

SEL

This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low. 7 VE1 Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low, the

output is in a high-Z state.

ISO

that both pins be connected to a common ground. 10 VE2 Data Enable Input. When this pin is high or not connected, the secondary output is active; when this pin is low, the

output is in a high-Z state. 11 V

Output Voltage Selection. When V

SEL

= V

ISO

, the V

setpoint is 5.0 V. When V

ISO

= GND

SEL

ISO

, the V

setpoint is 3.3 V.

ISO

In slave regulation mode, this pin has no function. 12 NC No Internal Connection. 13 VIB Logic Input B. 14 VOA Logic Output A. 16 V

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

Rev. B | Page 13 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

V

DD1

1

GND

1

2

V

OA

3

V

OB

4

V

ISO

16

GND

ISO

15

V

IA

14

V

IB

13

RC

IN

5

NC

12

RC

SEL

6

V

SEL

11

V

E1

7

NC

10

GND

1

8

GND

ISO

9

ADuM5202

TOP VIEW

(Not to S cale)

07540-008

NC = NO CONNECT

DD1

OA

iso

9, 15

GND

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended

14

VIA

Logic Input A.

ISO

OUT(EXT)

iso

Figure 8. ADuM5202 Pin Configuration

Table 23. ADuM5202 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2, 8 GND

Primary Supply Voltage, 3.0 V to 5.5 V. Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and

1

it is recommended that both pins be connected to a common ground.

3 V

Logic Output A. 4 VOB Logic Output B. 5 RC

6 RC

IN

SEL

Regulation Control Input. This pin must be connected to the RC

that this pin must not be tied high if RC

damaging the

ADuM5202 and possibly the devices that it powers.

is low; this combination causes excessive voltage on the secondary side,

SEL

Control Input. Determines self-regulation mode (RC

pin of a master

OUT

high) or slave mode (RC

SEL

Power device or tied low. Note

low), allowing external regulation.

SEL

This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low. 7 VE1 Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low, the

output is in a high-Z state.

ISO

that both pins be connected to a common ground. 10, 12 NC No Internal Connection. 11 V

Output Voltage Selection. When V

SEL

= V

ISO

, the V

setpoint is 5.0 V. When V

ISO

= GND

SEL

ISO

, the V

setpoint is 3.3 V.

ISO

In slave regulation mode, this pin has no function. 13 VIB Logic Input B.

16 V

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

TRUTH TABLE

Table 24. Power Section Truth Table (Positive Logic)1

SEL

RC

IN

Input

RC Input

H X H 5.0 5.0 Self regulation mode, normal operation. H X L 5.0 3.3 Self regulation mode, normal operation. H X L 3.3 3.3 Self regulation mode, normal operation. H X H 3.3 5.0 This supply configuration is not recommended due to extremely poor efficiency. L H X X X Part runs at maximum open-loop voltage; therefore, damage can occur. L L X X 0 Power supply is disabled. L RC

1

H refers to a high logic, L refers to a low logic, and X is don’t care or unknown.

2

V

must be common between all isoPower devices being regulated by a master isoPower part.

DD1

V Input

SEL

V

DD1

Input (V)

2

V

(V) Operation

X X X Slave mode, RC

Rev. B | Page 14 of 28

supplied by a master

Power device.

Data Sheet ADuM5200/ADuM5201/ADuM5202

0

5

10

15

20

25

30

35

40

0 0.02 0.04 0.06 0.08 0.10 0.12

07540-022

OUTPUT CURRE NT (A)

EFFICIENCY (POW ER IN/PO W ER OUT) (%)

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT 5V INPUT/ 5V OUTPUT

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 0.02 0.04 0.06 0.08 0.10 0.12

I

ISO

(A)

POWER DISSIPATION (W)

V

DD1

= 5V, V

ISO

= 5V

V

DD1

= 5V, V

ISO

= 3.3V

V

DD1

= 3.3V, V

ISO

= 3.3V

07540-023

0

0.02

0.04

0.06

0.08

0.10

0.12

0 0.05 0.10 0.15 0.20 0.25 0.350.30

INPUT CURRENT ( A)

OUTPUT CURRE NT (A)

07540-024

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT 5V INPUT/ 5V OUTPUT

07540-011

0

0.5

1.0

1.5

2.0

3.0

2.5

3.5

3.0 3.5 4.0 4.5 5.0 5.5 6.0 V

DD1

(V)

I

DD1

(A) AND POWE R ( W)

POWER

DISSIPATION

I

DD

07540-012

(100µs/DIV)

OUTPUT VOLTAGE

(500mV/DIV)

DYNAMIC LO AD

10% LOAD

90% LOAD

07540-013

(100µs/DIV)

OUTPUT VOLTAGE

(500mV/DIV)

DYNAMIC LO AD

10% LOAD

90% LOAD

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 9. Typical Power Supply Efficiency

in All Supported Power Configurations

Figure 12. Typical Short-Circuit Input Current and Power

vs. V

Supply Voltage

DD1

Figure 10. Typical Total Power Dissipation vs. Isolated Output Supply Current

in All Supported Power Configurations

Figure 11. Typical Isolated Output Supply Current vs. Input Current

in All Supported Power Configurations

Figure 13. Typical V

Transient Load Response, 5 V Output,

ISO

10% to 90% Load Step

Figure 14. Typical V

Transient Load Response, 3 V Output,

ISO

10% to 90% Load Step

Rev. B | Page 15 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

07540-014

TIME (µs)

0 0.5 1.0

25

20

15

10

5

0

–5

1.5 2.0 2.5 3.0 3.5 4.0

5V OUTPUT RIPPLE (mV)

BW = 20MHz

07540-015

TIME (µs)

0 0.5 1.0

16

14

12

10

8

6

4

2

0

1.5 2.0 2.5 3.0 3.5 4.0

3.3V OUTPUT RIPPLE (mV)

BW = 20MHz

07540-027

TIME (ms)

V

ISO

(V)

7

6

5

4

3

2

1

0

–1 0 1 2 3

90% LOAD

10% LOAD

07540-028

TIME (ms)

V

ISO

(V)

5

4

3

2

1

0

–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0

90% LOAD

10% LOAD

0

4

8

12

16

20

0 5 10 15

DATA RATE (Mbps)

SUPPLY CURRENT (mA)

20 25

07540-025

5V INPUT/ 5V OUTPUT

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT

0

4

8

12

16

20

0 5 10 15

DATA RATE (Mbps)

SUPPLY CURRENT (mA)

20 25

5V INPUT/ 5V OUTPUT

3.3V INPUT /3.3V OUTP UT 5V INPUT/ 3.3V OUTPUT

07540-026

Figure 15. Typical Output Voltage Ripple at 90% Load, V

Figure 16. Typical Output Voltage Ripple at 90% Load, V

= 5 V

ISO

= 3.3 V

ISO

Figure 18. Typical Output Voltage Start-Up Transient

at 10% and 90% Load, V

Figure 19. Typical I

Supply Current per Forward Data Channel

CHn

(15 pF Output Load)

= 3.3 V

ISO

Figure 17. Typical Output Voltage Start-Up Transient

at 10% and 90% Load, V

ISO

= 5 V

Figure 20. Typical I

Supply Current per Reverse Data Channel

CHn

(15 pF Output Load)

Rev. B | Page 16 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

0

1

2

3

4

5

0 5 10

DATA RATE (Mbps)

CURRENT (mA)

15 20 25

3.3V

5V

07540-018

0

1.0

0.5

1.5

2.0

2.5

3.0

0 5 10

DATA RATE (Mbps)

CURRENT (mA)

15 20 25

3.3V

5V

07540-019

Figure 21. Typical I

Dynamic Supply Current per Input

ISO (D)

Figure 22. Typical I

Dynamic Supply Current per Output

ISO (D)

(15 pF Output Load)

Rev. B | Page 17 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

TERMINOLOGY

I

DD1 (Q)

I

is the minimum operating current drawn at the V

DD1 (Q)

pin when there is no external load at V

and the I/O pins are

ISO

DD1

operating below 2 Mbps, requiring no additional dynamic supply current. I

reflects the minimum current operating

DD1 (Q)

condition.

I

DD1 (D)

I

is the typical input supply current with all channels

DD1 (D)

simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load.

I

DD1 (MAX)

is the input current under full dynamic and V

DD1 (MAX)

ISO

load

conditions.

I

SO (L OAD)

I

is the current available to the load.

SO (LOA D)

Propagation Delay

t

PHL

t

propagation delay is measured from the 50% level of the

PHL

falling edge of the V of the V

signal.

Ox

signal to the 50% level of the falling edge

Ix

Propagation Delay

t

PLH

t

propagation delay is measured from the 50% level of the

PLH

rising edge of the V of the V

signal.

Ox

Propagation Delay Skew, t

t

is the magnitude of the worst-case difference in t

PSK

signal to the 50% level of the rising edge

Ix

PSK

and/or t

PHL

PLH

that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.

Channel-to-Channel Matching, t

PSKC D/tPSKOD

Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.

Minimum Pulse Width

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

Maximum Data Rate

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

Rev. B | Page 18 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

APPLICATIONS INFORMATION

The dc-to-dc converter section of the ADuM5200/ADuM5201/

ADuM5202 works on principles that are common to most

switching power supplies. It has a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. V

power is supplied to an oscillating circuit that

DD1

switches current into a chip scale air core transformer. Power transferred to the secondary side is rectified and regulated to either 3.3 V or 5 V. The secondary (V

) side controller regulates

ISO

the output by creating a PWM control signal that is sent to the primary (V

) side by a dedicated iCoupler data channel. The

DD1

PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency.

The ADuM5200/ADuM5201/ADuM5202 implements undervoltage lockout (UVLO) with hysteresis on the V

power input.

DD1

This feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates.

The ADuM5200/ADuM5201/ADuM5202 can accept an external regulation control signal (RC

) that can be connected to other

IN

isoPower devices. This allows a single regulator to control multiple power modules without contention. When accepting control from a master power module, the V

pins can be connected together,

ISO

adding their power. Because there is only one feedback control path, the supplies work together seamlessly. The ADuM5200/

ADuM5201/ADuM5202 can only regulate themselves or accept

regulation (as slave devices) from another device in this product line; they cannot provide a regulation signal to other devices.

PCB LAYOUT

The ADuM5200/ADuM5201/ADuM5202 digital isolators with 0.5 W isoPower, integrated dc-to-dc converter require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 23). Note that low ESR bypass capacitors are required between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as close to the chip pads as possible.

The power supply section of the ADuM5200/ADuM5201/

ADuM5202 uses a 180 MHz oscillator frequency to pass power

efficiently through its chip scale transformers. In addition, the normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor, whereas ripple suppression and proper regulation require a large value capacitor. These capacitors are most conveniently connected between Pin 1 and Pin 2 for V

To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0.1 μF and 10 μF for V have a low ESR; for example, use of a ceramic capacitor is advised.

and between Pin 15 and Pin 16 for V

DD1

. The smaller capacitor must

DD1

ISO

.

Note that the total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. Consider bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both common ground pins are connected together close to the package.

BYPASS < 2mm

V

DD1

GND

1

VIA/V

OA

VIB/V

OB

RC

IN

RC

SEL

VE1/NC VE2/NC

GND

1

Figure 23. Recommended PCB Layout

V

ISO

GND VOA/V VOB/V NC V

SEL

GND

ISO

IA IB

07540-020

In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur affects all pins equally on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings for the device (specified in Table 19), thereby leading to latch-up and/or permanent damage.

The ADuM5200/ADuM5201/ADuM5202 is a power device that dissipates approximately 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the PCB through the GND pins. If the device is used at high ambient temperatures, provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 23 shows enlarged pads for Pin 2, Pin 8, Pin 9, and Pin 15. Multiple vias should be implemented from the pad to the ground plane to significantly reduce the temperature inside the chip. The dimensions of the expanded pads are at the discretion of the designer and depend on the available board space.

START-UP BEHAVIOR

The ADuM5200/ADuM5201/ADuM5202 do not contain a soft start circuit. Take the start-up current and voltage behavior into account when designing with this device.

When power is applied to V to operate and draw current when the UVLO minimum voltage is reached. The switching circuit drives the maximum available power to the output until it reaches the regulation voltage where PWM control begins. The amount of current and time this takes depends on the load and the V

With a fast V

slew rate (200 μs or less), the peak current

DD1

draws up to 100 mA/V of V faster than the output can turn on; therefore, the peak current is proportional to the maximum input voltage.

, the input switching circuit begins

DD1

slew rate.

DD1

. The input voltage goes high

DD1

Rev. B | Page 19 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

V

With a slow V voltage is not changing quickly when V minimum voltage. The current surge is approximately 300 mA because V behavior during startup is similar to when the device load is a short circuit; these values are consistent with the short-circuit current shown in Figure 12.

When starting the device for V the current available to the V The ADuM5200/ADuM5201/ADuM5202 devices may not be able to drive the output to the regulation point if a current-limiting device clamps the V

ADuM5200/ADuM5201/ADuM5202 devices can draw large

amounts of current at low voltage for extended periods of time.

The output voltage of the ADuM5200/ADuM5201/ADuM5202 exhibits V damage components attached to V device, such as a Zener diode, can be used to clamp the voltage. Typical behavior is shown in Figure 17 and Figure 18.

EMI CONSIDERATIONS

The dc-to-dc converter section of the ADuM5200/ADuM5201/

ADuM5202 devices must operate at 180 MHz to allow efficient

power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole radiation between the primary and secondary ground planes. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, follow good RF design practices in the layout of the PCB. See the

AN-0971 Application Note for board layout recommendations.

PROPAGATION DELAY PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high.

slew rate (in the millisecond range), the input

DD1

reaches the UVLO

DD1

is nearly constant at the 2.7 V UVLO voltage. The

DD1

= 5 V operation, do not limit

ISO

power pin to less than 300 mA.

DD1

voltage during startup. As a result, the

DD1

overshoot during startup. If this could potentially

ISO

, then a voltage-limiting

ISO

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 24) by the watchdog timer circuit.

The limitation on the magnetic field immunity of the ADuM5200/

ADuM5201/ADuM5202 is set by the condition in which induced

voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM5200/ADuM5201/ADuM5202 is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)∑πr

where:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. r

is the radius of the nth turn in the receiving coil (cm).

n

Given the geometry of the receiving coil in the ADuM5200/

ADuM5201/ADuM5202 and an imposed requirement that the

induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 25.

100

2

; n = 1, 2, … , N

n

INPUT (

OUTPUT (V

)

IX

t

PLH

)

OX

Figure 24. Propagation Delay Parameters

t

50%

PHL

50%

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single

ADuM5200/ADuM5201/ADuM5202 component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM5200/

ADuM5201/ADuM5202 components operating under the

same conditions.

07540-118

Rev. B | Page 20 of 28

10

1

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FL UX

0.001 1k 10k 10M

Figure 25. Maximum Allowable External Magnetic Flux Density

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

07540-119

Data Sheet ADuM5200/ADuM5201/ADuM5202

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM5200/

ADuM5201/ADuM5202 transformers. Figure 26 expresses

these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM5200/ADuM5201/

ADuM5202 are extremely immune and can be affected only by

extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, a 0.5 kA current placed 5 mm away from the ADuM5200/ADuM5201/ADuM5202 is required to affect the operation of the component.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALL OWABLE CURRENT ( kA)

0.01 1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 26. Maximum Allowable Current for Various Current-to-

ADuM5200/ADuM5201/ADuM5202 Spacings

07540-120

Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Exercise care in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The V channels as well as to the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary input/output channels cannot be determined separately. All of these quiescent power demands have been combined into the I current is the sum of the quiescent operating current, dynamic current I I

ISO

power supply input provides power to the iCoupler data

DD1

current shown in Figure 27. The total I

DD1 (Q)

demanded by the I/O channels, and any external

DD1 (D)

load.

supply

DD1

I

DD1(Q)

I

DD1(D)

Figure 27. Power Consumption Within the ADuM5200/ADuM5201/ADuM5202

CONVERTER

PRIMARY

I

DDP(D)

PRIMARY

DATA I/O

2-CHANNEL

CONVERTER SECONDARY

I

ISO(D)

SECONDARY

DATA I/O

2-CHANNEL

Both dynamic input and output current is consumed only when operating at channel speeds higher than the rate of f each channel has a dynamic current determined by its data rate, Figure 19 shows the current for a channel in the forward direction, which means that the input is on the primary side of the part. Figure 20 shows the current for a channel in the reverse direction, which means that the input is on the secondary side of the part. Both figures assume a typical 15 pF load. The following relationship allows the total I

= (I

× V

I

DD1

ISO

)/(E × V

ISO

current to be calculated:

DD1

) + ∑ I

; n = 1 to 4 (1)

CHn

where:

I

is the total supply input current.

DD1

is the current drawn by a single channel determined from

I

CHn

Figure 19 or Figure 20, depending on channel direction.

I

is the current drawn by the secondary side external loads.

ISO

E is the power supply efficiency at 100 mA load from Figure 9

at the V

ISO

and V

condition of interest.

DD1

Calculate the maximum external load by subtracting the dynamic output load from the maximum allowable load.

I

ISO (LOAD)

= I

ISO (MAX)

− ∑ I

; n = 1 to 4 (2)

ISO (D)n

where:

I

is the current available to supply an external secondary

ISO (LOAD)

side load.

I

is the maximum external secondary side load current

ISO (MAX)

available at V

I

is the dynamic load current drawn from V

ISO (D)n

ISO

.

or output channel, as shown in Figure 19 and Figure 20. Data is presented assuming a typical 15 pF load.

The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of I

To d et e rm in e I dynamic output current (I

in Equation 1, additional primary side

DD1

) is added directly to I

AOD

Additional secondary side dynamic output current (I added to I

To d et e rm in e I side output current (I

on a per-channel basis.

ISO

in Equation 2, additional secondary

ISO (LOAD)

) is subtracted from I

AOD

per-channel basis.

I

ISO

and I

DD1

ISO (MAX)

ISO

07540-021

. Because

r

by an input

ISO (LOAD)

.

DD1

) is

AOD

on a

.

Rev. B | Page 21 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

For each output channel with CL greater than 15 pF, the additional capacitive supply current is given by

I

= 0.5 × 10−3 × ((CL − 15) × V

AOD

) × (2f − fr); f > 0.5 fr (3)

ISO

where: C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

ISO

f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps.

f

is the input channel refresh rate (Mbps).

r

CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION

The ADuM5200/ADuM5201/ADuM5202 are protected against damage due to excessive power dissipation by thermal overload protection circuits. Thermal overload protection limits the junction temperature to a maximum of 150°C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation), when the junction temperature starts to rise above 150°C, the PWM is turned off, reducing the output current to zero. When the junction temperature drops below 130°C (typical), the PWM turns on again, restoring the output current to its nominal value.

Consider the case where a hard short from V

to ground occurs.

ISO

At first, the ADuM5200/ADuM5201/ADuM5202 reach their maximum current, which is proportional to the voltage applied at V

. Power dissipates on the primary side of the converter

DD1

(see Figure 12). If self-heating of the junction becomes great enough to cause its temperature to rise above 150°C, thermal shutdown activates, turning off the PWM, and reducing the output current to zero. As the junction temperature cools and drops below 130°C, the PWM turns on, and power dissipates again on the primary side of the converter, causing the junction temperature to rise to 150°C again. This thermal oscillation between 130°C and 150°C causes the part to cycle on and off as long as the short remains at the output.

Thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, externally limit device power dissipation to prevent junction temperatures from exceeding 130°C.

POWER CONSIDERATIONS

The ADuM5200/ADuM5201/ADuM5202 power input, data input channels on the primary side and data input channels on the secondary side are all protected from premature operation by UVLO circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. Outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations.

Rev. B | Page 22 of 28

During application of power to V

, the primary side circuitry

DD1

is held idle until the UVLO preset voltage is reached. At that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side.

When the primary side is above the UVLO threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. The outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary power is established. The primary side oscillator also begins to operate, transferring power to the secondary power circuits.

The secondary V

voltage is below its UVLO limit at this point;

ISO

the regulation control signal from the secondary is not being generated. The primary side power oscillator is allowed to free run in this circumstance, supplying the maximum amount of power to the secondary, until the secondary voltage rises to its regulation setpoint. This creates a large inrush current transient at V

DD1

.

When the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. The V

current is reduced

DD1

and is then proportional to the load current. The inrush current is less than the short-circuit current shown in Figure 12. The duration of the inrush current depends on the V conditions and the current available at the V

DD1

ISO

pin.

loading

As the secondary side converter begins to accept power from the primary, the V

voltage starts to rise. When the secondary

ISO

side UVLO is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. It can take up to 1 μs after the secondary side is initialized for the state of the output to correlate with the primary side input.

Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid about 1 μs after the secondary side becomes active.

Because the rate of charge of the secondary side power supply is dependent on loading conditions and the input voltage level and the output voltage level selected, take care with the design to allow the converter sufficient time to stabilize before valid data is required.

When power is removed from V

, the primary side converter and

DD1

coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side hold the last state that they received from the primary side. Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO.

Data Sheet ADuM5200/ADuM5201/ADuM5202

1-Unit Power

ADuM5000 master

ADuM520x master

ADuM5401 to ADuM5404 master

THERMAL ANALYSIS

The ADuM5200/ADuM5201/ADuM5202 consist of four internal die, attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, it is treated as a thermal unit with the highest junction temperature reflected in the θ Table 14. The value of θ

is based on measurements taken with

JA

value in

JA

the part mounted on a JEDEC standard 4-layer board with fine width traces and still air. Under normal operating conditions, the

ADuM5200/ADuM5201/ADuM5202 operate at full load across

the full temperature range without derating the output current. However, following the recommendations in the PCB Layout section decreases the thermal resistance to the PCB, allowing increased thermal margin at high ambient temperatures.

INCREASING AVAILABLE POWER

The ADuM5200/ADuM5201/ADuM5202 are designed with the capability of running in combination with other compatible isoPower devices. The RC

ADuM5201/ADuM5202 to receive a PWM signal from another

device through the RC signal. The RC

pin chooses whether the part acts as a stand-

SEL

alone self-regulated device or a slave device. When the

ADuM5200/ADuM5201/ADuM5202 act as a slave, their power

is regulated by a PWM signal coming from a master device. This allows multiple isoPower parts to be combined in parallel while sharing the load equally. When the ADuM5200/ADuM5201/

ADuM5202 are configured as standalone units, they generate

their own PWM feedback signal to regulate themselves.

and RC

IN

pin and act as a slave to that control

IN

pins allow the ADuM5200/

SEL

The ADuM5000 can act as a master or a slave device, the

ADuM5401, ADuM5402, ADuM5403, and ADuM5404 can

only be master/standalone, and the ADuM520x can only be a slave/standalone device. This means that the ADuM5000,

ADuM520x, and ADuM5401 to ADuM5404 can only be used

in certain master/slave combinations as listed in Table 25.

Table 25. Allowed Combinations of isoPower Parts

Slave

ADuM5401 to

Master

ADuM5000 Yes Yes No ADuM520x No No No ADuM5401 to

ADuM5404

ADuM5000 ADuM520x

Yes Yes No

ADuM5404

The allowed combinations of master and slave configured parts listed in Table 25 is sufficient to make any combination of power and channel count.

Table 26 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single un it powe r.

Table 26. Configurations for Power and Data Channels

Power Units

2-Unit Power

3-Unit Power

0 Channels 2 Channels 4 Channels 6 Channels

ADuM121x

ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM520x slave ADuM520x slave ADuM520x slave ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master ADuM5000 slave ADuM5000 slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM5000 slave

Number of Data Channels

Rev. B | Page 23 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM5200/

ADuM5201/ADuM5202.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 20 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than a 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM5200/ADuM5201/

ADuM5202 depends on the voltage waveform type imposed

across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 28, Figure 29, and Figure 30 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the maximum working voltage recommended by Analog Devices.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 20 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases.

Any cross-insulation voltage waveform that does not conform to Figure 29 or Figure 30 should be treated as a bipolar ac waveform and its peak voltage limited to the 50-year lifetime voltage value listed in Table 20. The voltage presented in Figure 29 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 28. Bipolar AC Waveform

07540-121

RATED PEAK VOL TAGE

0V

Figure 29. Unipolar AC Waveform

07540-122

RATED PEAK VOL TAGE

0V

Figure 30. DC Waveform

07540-123

Rev. B | Page 24 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

10.50 (0.4134)

10.10 (0.3976)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75 (0.0295)

0.25 (0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING PLANE

8° 0°

16

9

8

1

1.27 (0.0500) BSC

03-27-2007-B

DD1

DD2

OUTLINE DIMENSIONS

Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Inputs,

Side

V

Model

1, 2

ADuM5200ARWZ 2 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5200CRWZ 2 0 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5201ARWZ 1 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5201CRWZ 1 1 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5202ARWZ 0 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM5202CRWZ 0 2 25 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16

1

Z = RoHS Compliant Part.

2

Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option.

Number of Inputs,

Side

V

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse Width Distortion (ns)

Temperature Range

Package Description

Package Option

Rev. B | Page 25 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

NOTES

Rev. B | Page 26 of 28

Data Sheet ADuM5200/ADuM5201/ADuM5202

NOTES

Rev. B | Page 27 of 28

ADuM5200/ADuM5201/ADuM5202 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D07540-0-5/12(B)

Rev. B | Page 28 of 28

Datasheet ADUM5200 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TRUTH TABLE

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

APPLICATIONS INFORMATION

PCB LAYOUT

START-UP BEHAVIOR

EMI CONSIDERATIONS

PROPAGATION DELAY PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION

POWER CONSIDERATIONS

THERMAL ANALYSIS

INCREASING AVAILABLE POWER

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE