Datasheet ADUM4160 Datasheet (ANALOG DEVICES)

Full/Low Speed 5 kV USB Digital Isolator

Data Sheet

FEATURES

USB 2.0 compatible
Low and full speed data rate: 1.5 Mbps and 12 Mbps
Bidirectional communication

4.5 V to 5.5 V V
7 mA maximum upstream supply current @ 1.5 Mbps
8 mA maximum upstream supply current @ 12 Mbps

2.3 mA maximum upstream idle current

Upstream short-circuit protection
Class 3A contact ESD performance per ANSI/ESD STM5.1-2007
High temperature operation: 105°C
High common-mode transient immunity: >25 kV/μs
16-lead SOIC wide-body package version
16-lead SOIC wide body enhanced creepage version
RoHS compliant

Safety and regulatory approvals (RI-16 package)

UL recognition: 5000 V rms for 1 minute per

UL 1577

CSA Component Acceptance Notice #5A

IEC 60601-1: 250 V rms (reinforced)
IEC 60950-1: 400 V rms (reinforced)

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V

= 846 V peak

IORM

APPLICATIONS

USB peripheral isolation
Isolated USB hub
Medical applications

GENERAL DESCRIPTION

The ADuM41601 is a USB port isolator, based on Analog Devices,
Inc., iCoupler® technology. Combining high speed CMOS and
monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
and are easily integrated with low and full speed USB-compatible
peripheral devices.

operation

BUS

ADuM4160

FUNCTIONAL BLOCK DIAGRAM

1

V

GND

PDEN

GND

BUS1

V

DD1

SPU

UD–
UD+

REG

2

1

3

4
5

6

7

8

1

PU LOGIC

PD LOGIC

Figure 1.

Many microcontrollers implement USB so that it presents only
the D+ and D− lines to external pins. This is desirable in many
cases because it minimizes external components and simplifies
the design; however, this presents particular challenges when
isolation is required. USB lines must automatically switch between
actively driving D+/D−, receiving data, and allowing external
resistors to set the idle state of the bus. The ADuM4160 provides
mechanisms for detecting the direction of data flow and control
over the state of the output buffers. Data direction is determined
on a packet-by-packet basis.

The ADuM4160 uses the edge detection based iCoupler tech­nology in conjunction with internal logic to implement a
transparent, easily configured, upstream facing port isolator.
Isolating an upstream facing port provides several advantages
in simplicity, power management, and robust operation.

The isolator has propagation delay comparable to that of a
standard hub and cable. It operates with the bus voltage on
either side ranging from 4.5 V to 5.5 V, allowing connection
directly to V

by internally regulating the voltage to the signaling

BUS

level. The ADuM4160 provides isolated control of the pull-up
resistor to allow the peripheral to control connection timing.
The device has a low idle current; so a suspend mode is not
required. A 2.5 kV version, the ADuM3160, is also available.

REG

16

V

BUS2

15

GND

2

14

V

DD2

13

SPD

12

PIN

11

DD–

10

DD+

9

GND

2

08171-001

1

Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009–2012 Analog Devices, Inc. All rights reserved.

ADuM4160 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Package Characteristics ............................................................... 4

Regulatory Information............................................................... 4

Insulation and Safety-Related Specifications............................ 5

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 5

Recommended Operating Conditions ...................................... 6



Absolute Maximum Ratings ............................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Applications Information.............................................................. 10

Functional Description.............................................................. 10

Product Usage............................................................................. 10

Compatibility of Upstream Applications ................................ 11

Power Supply Options ............................................................... 11

Printed Circuit Board (PCB) Layout....................................... 11

DC Correctness and Magnetic Field Immunity..................... 11

Insulation Lifetime..................................................................... 12

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

REVISION HISTORY

2/12—Rev. C to Rev. D

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section................................................................. 1

Changes to Table 3............................................................................ 4

Change to Table 4 ............................................................................. 5

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 14

10/10—Rev. B to Rev. C

Changes to Features and General Description Section ............... 1

Changes to Endnote 3 in Table 1 and Table 3............................... 4

Changes to Table 4............................................................................ 5

Changes to Table 7 and Table 8....................................................... 7

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 14

8/10—Rev. A to Rev. B

Change to Data Sheet Title...............................................................1

Changes to Features Section ............................................................1

Changes to Applications Section.....................................................1

Changes to General Description Section .......................................1

Changes to Table 3.............................................................................4

9/09—Rev. 0 to Rev. A

Added USB Logo, Reformatted Page 1...........................................1

7/09—Revision 0: Initial Version

Rev. D | Page 2 of 16

Data Sheet ADuM4160

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

4.5 V ≤ V
the entire recommended operation range, unless otherwise noted; all typical specifications are at T
voltage is relative to its respective ground.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Total Supply Current1

1.5 Mbps

12 Mbps

Idle Current

V

Input Currents

Single-Ended Logic High Input Threshold
Single-Ended Logic Low Input Threshold
Single-Ended Input Hysteresis V
Differential Input Sensitivity VDI 0.2 V |V
Logic High Output Voltages V
Logic Low Output Voltages V
V

DD1

V

BUS1

V

BUS2

Transceiver Capacitance CIN 10 pF UD+, UD−, DD+, DD− to ground
Capacitance Matching 10 %
Full Speed Driver Impedance Z
Impedance Matching 10 %

SWITCHING SPECIFICATIONS, I/O PINS LOW SPEED

Low Speed Data Rate 1.5 Mbps CL = 50 pF
Propagation Delay2 t

Side 1 Output Rise/Fall Time (10% to 90%) Low

Speed
Low Speed Differential Jitter, Next Transition
Low Speed Differential Jitter, Paired Transition |t

SWITCHING SPECIFICATIONS, I/O PINS FULL SPEED

Full Speed Data Rate 12 Mbps CL = 50 pF
Propagation Delay2 t

Output Rise/Fall Time (10% to 90%) Full Speed tRF/tFF 4 20 ns

Full Speed Differential Jitter, Next Transition
Full Speed Differential Jitter, Paired Transition |t

≤ 5.5 V, 4.5 V ≤ V

BUS1

V

or V

DD1

BUS1

V

or V

DD2

BUS2

V

or V

DD1

BUS1

V

or V

DD2

BUS2

or V

DD1

BUS1

and V

Supply Undervoltage Lockout V

DD2

Supply Current I
Supply Current I

Supply Current I
Supply Current I

Idle Current I

≤ 5.5 V; 3.1 V ≤ V

BUS2

Supply Undervoltage Lockout V
Supply Undervoltage Lockout V

≤ 3.6 V, 3.1 V ≤ V

DD1

5 7 mA 750 kHz logic signal rate CL = 450 pF

DD1 (L)

5 7 mA 750 kHz logic signal rate CL = 450 pF

DD2 (L)

6 8 mA 6 MHz logic signal rate CL = 50 pF

DD1 (F)

6 8 mA 6 MHz logic signal rate CL = 50 pF

DD2 (F)

1.7 2.3 mA

DD1 (I)

, I

I

DD−

, I

I

UD+

I

, I

SPD

, I

I

SPU

V

IH

V

IL

0.4 V

HST

OH

OL

UVLO

UVLOB1

UVLOB2

OUTH

, t

PHLL

t

RL/tFL

|t

| 45 ns CL = 50 pF

LJN

| 15 ns CL = 50 pF

LJP

, t

PHLF

|t

| 3 ns CL = 50 pF

FJN

| 1 ns CL = 50 pF

FJP

−1 +0.1 +1 μA

,

DD+

,

UD−

,

PIN

PDEN

2.0 V

0.8 V

2.8 3.6 V RL = 15 kΩ, VL = 0 V
0 0.3 V RL = 1.5 kΩ, VL = 3.6 V

2.4 3.1 V

3.5 4.35 V

3.5 4.4 V

4 20 Ω

325 ns

PLHL

75 300 ns

20 60 70 ns

PLHF

≤ 3.6 V; all minimum/maximum specifications apply over

DD2

= 25°C, V

A

0 V ≤ V
V

SPU

XD+

= 50 pF, SPD = SPU = low,

C

L

V

DD1

= 450 pF, SPD = SPU = low,

C

L

V

DD1

= 50 pF, SPD = SPU = high,

C

L

V

DD1

= 50 pF, SPD = SPU = high,

C

L

V

DD1

, V

, V

, V

, V

, V

PDEN

− V

DD1

DD−

XD−

= 3.3 V

DD2

= 3.3 V

DD2

= 3.3 V

DD2

= 3.3 V

DD2

= V

, V

DD+

≤ 3.0

|

= 3.3 V. Each

DD2

, V

, V

UD+

UD−

, V

SPD

, V

,

PIN

Rev. D | Page 3 of 16

ADuM4160 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Operating Modes

Common-Mode Transient Immunity

At Logic High Output3 |CMH| 25 35 kV/μs

At Logic Low Output

1

The supply current values for the device running at a fixed continuous data rate at 50% duty cycle alternating J and K states. Supply current values are specified with

USB-compliant load present.

2

Propagation delay of the low speed DD+ to UD+ or DD− to UD− in either signal direction is measured from the 50% level of the rising or falling edge to the 50% level

of the rising or falling edge of the corresponding output signal.

3

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.

3

|CML| 25 35 kV/μs

PACKAGE CHARACTERISTICS

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input to Output)1 R
Capacitance (Input to Output)

1

Input Capacitance2 C
IC Junction-to-Ambient Thermal Resistance θJA 45 °C/W

1

Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,

Pin 15, and Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

1012 Ω

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

, V

V

UD+

UD−

V

= 1000 V, transient magnitude =

CM

800 V

, V

V

UD+

UD−

1000 V, transient magnitude = 800 V

. CML is the maximum common-mode voltage slew rate

DDx

Thermocouple located at center
of package underside

, V

, V

DD+

DD+

, V

, V

DD−

DD−

= V

or V

DD1

= 0 V, VCM =

DD2

,

REGULATORY INFORMATION

The ADuM4160 is approved by the organizations listed in Tabl e 3. Refer to Ta b le 8 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 3.

UL CSA VDE

Recognized under 1577 component
recognition program

1

Single Protection
5000 V rms Isolation Voltage

Approved under CSA Component
Acceptance Notice #5A

Basic insulation per CSA 60950-1-07 and IEC 60950-1,
600 V rms (848 V peak) maximum working voltage.

Reinforced insulation per CSA 60950-1-07 and IEC
60950-1, 380 V rms (537 V peak) maximum working
voltage, RW-16 package.

Reinforced insulation per CSA 60950-1-07 and IEC
60950-1, 400 V rms (565 V peak) maximum working
voltage, RI-16 package.

Reinforced insulation per IEC 60601-1 125 V rms (176 V
peak) maximum working voltage, RW-16 package.
Reinforced insulation per IEC 60601-1 250 V rms (353 V
peak) maximum working voltage, RI-16 package.

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM4160 is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec (current leakage detection limit = 10 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM4160 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection

limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-122

Reinforced insulation, 846 V peak

Rev. D | Page 4 of 16

Data Sheet ADuM4160

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 4.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 5000 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 8.0 min mm

Minimum External Tracking (Creepage) RW-16 Package L(I02) 7.7 min mm

Minimum External Tracking (Creepage) RI-16 Package L(I02) 8.3 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval.

Table 5.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II

Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage V
Input-to-Output Test Voltage, Method b1

Input-to-Output Test Voltage, Method a V

After Environmental Tests Subgroup 1 1375 V peak
After Input and/or Safety Test Subgroup 2

and Subgroup 3

Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 6000 V peak
Safety-Limiting Values

Case Temperature TS 150 °C
Side 1 + Side 2 Current IS1 550 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

600

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak

V

IORM

Maximum value allowed in the event of a failure
(see Figure 2)

Measured from input terminals to output terminals,
shortest distance through air

Measured from input terminals to output terminals,
shortest distance path along body

Measured from input terminals to output terminals,
shortest distance path along body

846 V peak

IORM

1590 V peak

V

PR

500

400

CURRENT (mA)

DD1

300

200

100

SAFE OPERATING V

0

0 50 100 150 200

Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10

AMBIENT TEMPERATURE (°C)

Rev. D | Page 5 of 16

8171-002

ADuM4160 Data Sheet

RECOMMENDED OPERATING CONDITIONS

Table 6.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C
Supply Voltages1 V
Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground. See the section for information on immunity to external magnetic

fields.

DC Correctness and Magnetic Field Immunity

BUS1

, V

3.1 5.5 V

BUS2

Rev. D | Page 6 of 16

Data Sheet ADuM4160

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

Storage Temperature (TST) −65°C to +150°C
Ambient Operating Temperature (TA) −40°C to +105°C
Supply Voltages (V

)1

V

DD2

Upstream Input Voltage

UD+,VUD−

, V

(V

Downstream Input Voltage

, V

DD+

DD−

, V

(V

SPU

SPD

, V

BUS1

BUS2

1, 2

)

1, 2

, V

)

PIN

, V

DD1

−0.5 V to +6.5 V

,

−0.5 V to V

−0.5 V to V

+ 0.5 V

DD1

+ 0.5 V

DD2

Average Output Current per Pin3

Side 1 (IO1) −10 mA to +10 mA
Side 2 (IO2) −10 mA to +10 mA

Common-Mode Transients4 −100 kV/μs to +100 kV/μs

1

All voltages are relative to their respective ground.

2

V

, V

, and V

, V

DDI

BUS1

downstream sides of the coupler, respectively.

3

See Figure 2 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.

refer to the supply voltages on the upstream and

DD2

BUS2

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 8. Maximum Continuous Working Voltage

1

Parameter Max Unit Constraint

AC Voltage, Bipolar

Waveform

AC Voltage, Unipolar

565 V peak

50-year minimum
lifetime

Waveform
Basic Insulation 848 V peak

Maximum approved
working voltage per

Reinforced Insulation 846 V peak

IEC 60950-1
Maximum approved

working voltage per
VDE 0884-10

DC Voltage

Basic Insulation 848 V peak

Maximum approved
working voltage per

Reinforced Insulation 846 V peak

IEC 60950-1
Maximum approved

working voltage per

1

Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more information.

VDE 0884-10

ESD CAUTION

Rev. D | Page 7 of 16

ADuM4160 Data Sheet

*

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

BUS1

GND1*

2

V

3

DD1

ADuM4160

4

PDEN

SPU
UD–
UD+

GND1*

PIN 2 AND PIN 8 ARE INTERNALLY CO NNE CTED, AND CONNECTING
BOTH TO GND
CONNECTED, AND CO NNECTING BOT H TO GND

IS RECOMM ENDE D. PIN 9 AND PIN 15 ARE INTERNALLY

1

TOP VIEW

(Not to S cal e)

5
6
7
8

NC = NO CONNECT

16

V

BUS2

GND2*

15

V

14

DD2

13

SPD
PIN

12

DD–

11

DD+

10

GND2*

9

IS RECOMMENDE D.

2

Figure 3. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Direction Description

1 V

BUS1

2 GND
3 V

DD1

1

Power

Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect V

to V

V

BUS1

to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect

BUS1

and to the external 3.3 V power supply. Bypass to GND1 is required.

DD1

Return Ground 1. Ground reference for Isolator Side 1.
Power

Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V
should be used for a bypass capacitor to GND
SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V
V

and to the external 3.3 V power supply. Bypass to GND1 is required.

DD1

4 PDEN Input

Pull-Down Enable. This pin is read when exiting reset. For standard operation, connect this pin to V
When connected to GND

while exiting from reset, the downstream pull-down resistors are

1

disconnected, allowing buffer impedance measurements.

5 SPU Input

Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied
low. This input must be set high via connection to V

match Pin 13.
6 UD− I/O Upstream D−.
7 UD+ I/O Upstream D+.
8 GND1 Return Ground 1. Ground reference for Isolator Side 1.
9 GND2 Return Ground 2. Ground reference for Isolator Side 2.
10 DD+ I/O Downstream D+.
11 DD− I/O Downstream D−.
12 PIN

Input

Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can

be tied to V

for operation on power-up, or tied to an external control signal for applications requiring

DD2

delayed enumeration.
13 SPD Input

Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic

conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied

low. This input must be set high via connection to V

Pin 5.
14 V

Power

DD2

Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V

should be used for a bypass capacitor to GND

tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V

external 3.3 V power supply. Bypass to GND

is required.

2

15 GND2 Return Ground 2. Ground reference for Isolator Side 2.
16 V

Power

BUS2

Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,

connect V

V

to V

BUS2

to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect

BUS2

and to the external 3.3 V power supply. Bypass to GND2 is required.

DD2

08171-003

pin

and to the

DD2

DDI

BUS1

DD1

DD2

pin

. Signal lines that may require pull up, such as PDEN and

1

or set low via connection to GND1 and must

DD1

or low via connection to GND2, and must match

DD2

. Signal lines that may require pull-up, such as SPD, can be

2

BUS2

to V

to

.

Rev. D | Page 8 of 16

Data Sheet ADuM4160

Table 10. Truth Table, Control Signals, and Power (Positive Logic)1

,

V

V

SPU

Input

V

BUS1

State

, V

DD1

UD+

V

UD−

State

V

V

, V

SPD

Input

BUS2

State

DD2

H Powered Active H Powered Active H

L Powered Active L Powered Active H

L Powered Active H Powered Active H

H Powered Active L Powered Active H

X Powered Z X Powered Z L

X Unpowered X X Powered Z X

X Powered Z X Unpowered X X

1

H represents logic high input or output, L represents logic low input or output, X represents the don’t care logic input or output, and Z represents the high impedance

output state.

V

DD+

V

DD−

State

,

V

PIN

Input Notes

Input and output logic set for full speed logic convention
and timing.

Input and output logic set for low speed logic convention
and timing.

Not allowed: V

SPU

and V

must be set to the same value.

SPD

USB host detects communications error.
Not allowed: V

SPU

and V

must be set to the same value.

SPD

USB host detects communications error.
Upstream Side 1 presents a disconnected state to the USB

cable.
When power is not present on V

, the downstream data

DD1

output drivers revert to high-Z within 32 bit times. The
downstream side initializes in high-Z state.

When power is not present on V

, the upstream side

DD2

disconnects the pull-up and disables the upstream drivers
within 32 bit times.

Rev. D | Page 9 of 16

ADuM4160 Data Sheet

APPLICATIONS INFORMATION

FUNCTIONAL DESCRIPTION

USB isolation in the D+/D− lines is challenging for several
reasons. First, access to the output enable signals is normally
required to control a transceiver. Some level of intelligence must
be built into the isolator to interpret the data stream and
determine when to enable and disable its upstream and down­stream output buffers. Second, the signal must be faithfully
reconstructed on the output side of the coupler while retaining
precise timing and not passing transient states such as invalid
SE0 and SE1 states. In addition, the part must meet the low
power requirements of the suspend mode.

The iCoupler technology is based on edge detection, and,
therefore, lends itself well to the USB application. The flow of
data through the device is accomplished by monitoring the
inputs for activity and setting the direction for data transfer
based on a transition from the idle (J) state. When data
direction is established, data is transferred until either an end­of-packet (EOP) or a sufficiently long idle state is encountered.
At this point, the coupler disables its output buffers and
monitors its inputs for the next activity

During the data transfers, the input side of the coupler holds its
output buffers disabled. The output side enables its output buffers
and disables edge detection from the input buffers. This allows
the data to flow in one direction without wrapping back through
the coupler making the iCoupler latch. Logic is included to
eliminate any artifacts due to different input thresholds of the
differential and single-ended buffers. The input state is transferred
across the isolation barrier as one of three valid states, J, K, or
SE0. The signal is reconstructed at the output side with a fixed
time delay from the input side differential input.

The iCoupler does not have a special suspend mode, nor does it
need one because its power supply current is below the suspend
current limit of 2.5 mA when the USB bus is idle.

The ADuM4160 is designed to interface with an upstream
facing low/full speed USB port by isolating the D+/D− lines.
An upstream facing port supports only one speed of operation,
thus, the speed related parameters, J/K logic levels, and D+/D−
slew rate are set to match the speed of the upstream facing
peripheral port (see

A control line on the downstream side of the ADuM4160 activates
a pull-up resistor integrated into the upstream side. This allows
the downstream port to control when the upstream port attaches
to the USB bus. The pin can be tied to the peripheral pull-up, a
control line, or the V
connect is to be performed.

Tabl e 10 ).

pin, depending on when the initial bus

DD2

PRODUCT USAGE

The ADuM4160 is designed to be integrated into a USB
peripheral with an upstream facing USB port as shown in
Figure 4. The key design points are:

1. The USB host provides power for the upstream side of the

ADuM4160 through the cable.

2. The peripheral supply provides power to the downstream

side of the ADuM4160.

3. The DD+/DD− lines of the isolator interface with the

peripheral controller, and the UD+/UD− lines of the
isolator connect to the cable or host.

4. Peripheral devices have a fixed data rate that is set at design

time. The ADuM4160 has configuration pins, SPU and
SPD, that determine the buffer speed and logic convention
for each side. These must be set identically and match the
desired peripheral speed.

5. USB enumeration begins when either the UD+ or UD−

line is pulled high at the peripheral end of the USB cable,
which is the upstream side of the ADuM4160. Control of
the timing of this event is provided by the PIN input on the
downstream side of the coupler.

6. Pull-up and pull-down resistors are implemented inside

the coupler. Only external series resistors and bypass
capacitors are required for operation.

PERIPHERAL

3.3VV

DD2

V

BUS1

DD+

USB

DD–

GND

ADuM4160

1

Figure 4. Typical Application

HOST

Other than the delayed application of pull-up resistors, the
ADuM4160 is transparent to USB traffic, and no modifications
to the peripheral design are required to provide isolation. The
isolator adds propagation delay to the signals comparable to a
hub and cable. Isolated peripherals must be treated as if there
were a built-in hub when determining the maximum number of
hubs in a data chain.

Hubs can be isolated like any other peripheral. Isolated hubs
can be created by placing an ADuM4160 on the upstream port
of a hub chip. This configuration can be made compliant if
counted as two hub delays. The hub chip allows the ADuM4160
to operate at full speed yet maintains compatibility with low
speed devices.

V
DD+

DD–
PIN

BUS2

MICRO-

CONTROLLER

POWER
SUPPLY

08171-004

Rev. D | Page 10 of 16

Data Sheet ADuM4160

COMPATIBILITY OF UPSTREAM APPLICATIONS

The ADuM4160 is designed specifically for isolating a USB
peripheral. However, the chip does have two USB interfaces that
meet the electrical requirements for driving USB cables. This
opens the possibility of implementing isolation in downstream
USB ports such as isolated cables, which have generic connections
to both upstream and downstream devices, as well as isolating
host ports.

In a fully compliant application, a downstream facing port must
be able to detect whether a peripheral is low speed or full speed
based on the application of the upstream pull-up. The buffers and
logic conventions must adjust to match the requested speed.
Because the ADuM4160 sets its speed by hard wiring pins, the
part cannot adjust to different peripherals on the fly.

The practical result of using the ADuM4160 in a host port is
that the port works at a single speed. This behavior is acceptable
in embedded host applications; however, this type of interface is
not fully compliant as a general-purpose USB port.

Isolated cable applications have a similar issue. The cable operates
at the preset speed only; therefore, treat cable assemblies as
custom applications, not general-purpose isolated cables.

POWER SUPPLY OPTIONS

In most USB transceivers, 3.3 V is derived from the 5 V USB bus
through an LDO regulator. The ADuM4160 includes internal
LDO regulators on both the upstream and downstream sides.
The output of the LDO is available on the V
In some cases, especially on the peripheral side of the isolation,
there may not be a 5 V power supply available. The ADuM4160
has the ability to bypass the regulator and run on a 3.3 V supply
directly.

Two power pins are present on each side, V
is supplied to V
the xD+ and xD− drivers. V

, an internal regulator creates 3.3 V to power

BUSx

provides external access to the

DDx

3.3 V supply to allow external bypass as well as bias for external
pull-ups. If only 3.3 V is available, it can be supplied to both
V

BUSx

and V

. This disables the regulator and powers the

DDx

coupler directly from the 3.3 V supply.

Figure 5 shows how to configure a typical application when the
upstream side of the coupler receives power directly from the
USB bus and the downstream side is receiving 3.3 V from the
peripheral power supply. The downstream side can run from a
5 V V
manner as V

power supply as well. It can be connected in the same

BUS2

as shown in Figure 5, if needed.

BUS1

DD1

BUSx

and V

and V

DD2

DDx

pins.

. If 5 V

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM4160 digital isolator requires no external interface
circuitry for the logic interfaces. For full speed operation, the
D+ and D− line on each side of the device requires a 24 Ω ± 1%
series termination resistor. These resistors are not required for
low speed applications. Power supply bypassing is required at
the input and output supply pins (see Figure 5)

acitors between V

cap

BUSx

and V

on each side of the chip. The

DDx

. Install bypass

capacitor value should have a value of 0.1 μF and be of a low
ESR type. The total lead length between both ends of the
capacitor and the power supply pin should not exceed 10 mm.
Bypassing between Pin 2 and Pin 8 and between Pin 9 and
Pin 15 should also be considered, unless the ground pair on
each package side is connected close to the package.

V

= 5.0V INPUT

BUS1

= 3.3V OUT PUT

V

DD1

V

BUS1

GND

1

V

DD1

PDEN

SPU
UD–
UD+

GND

1

Figure 5. Recommended Printed Circuit Board Layout

ADuM4160

V

BUS2

= 3.3V INPU T

V

DD2

= 3.3V INP U T

V
GND
V
SPD
PIN
DD–
DD+

GND

BUS2

DD2

2

2

08171-005

In applications involving high common-mode transients, it
is important to minimize board coupling across the isolation
barrier. Furthermore, design the board layout such that any
coupling that does occur equally affects all pins on a given
component side. Failure to ensure this can cause voltage
differentials between pins exceeding the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than about
12 USB bit times, a periodic set of refresh pulses indicative of
the correct input state are sent to ensure dc correctness at the
output. If the decoder receives no internal pulses for more than
about 36 USB bit times, the input side is assumed to be unpowered
or nonfunctional, in which case the isolator output is forced to a
default state (see Table 1 0) by the watchdog timer circuit.

Rev. D | Page 11 of 16

ADuM4160 Data Sheet

The limitation on the magnetic field immunity of the ADuM4160
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this may occur. The 3 V operating condition of the
ADuM4160 is examined because it represents the most susceptible
mode of operation.

The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold of about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages are tolerated.
The voltage induced across the receiving coil is given by

V = (−dβ/dt)

2

∑∏r

; n = 1, 2, … , N

n

where:

β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).

Given the geometry of the receiving coil in the ADuM4160 and
an imposed requirement that the induced voltage is, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 6.

100

10

1

0.1

DENSITY ( kguass)

0.01

MAXIMUM ALLOWABLE MAGNETI C FLUX

0.001
1k

Figure 6. Maximum Allowable External Magnetic Flux Density

10k 100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

100M

08171-006

For example, at a magnetic field frequency of 1 MHz, the max­imum allowable magnetic field of 0.2 kgauss induces a voltage
of 0.25 V at the receiving coil. This is about 50% of the sensing
threshold and does not cause a faulty output transition. Similarly,
if such an event occurs during a transmitted pulse (and is of the
worst-case polarity), it reduces the received pulse from >1.0 V to

0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM4160
transformers. Figure 7 expresses these allowable current
magnitudes as a function of frequency for selected distances.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANC E = 5mm

0.1

MAXIMUM ALL OWABLE CURRENT (kA)

0.01
1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 7. Maximum Allowable Current

for Various Current-to-ADuM4160 Spacings

08171-007

As shown, the ADuM4160 is extremely immune and can be
affected only by extremely large currents operated at high
frequency very close to the component. For the 1 MHz example
noted, a 0.5 kA current would need to be placed 5 mm away
from the ADuM4160 to affect the operation of the component.

Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
induce error voltages sufficiently large enough to trigger the
thresholds of succeeding circuitry. Take care in the layout of
such traces to avoid this possibility.

INSULATION LIFETIME

All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM4160.

Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accele­ration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Tab l e 8 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition, and the maximum CSA/VDE approved working
voltages. In many cases, the approved working voltage is higher
than 50-year service life voltage. Operation at these high work­ing voltages can lead to shortened insulation life in some cases.

Rev. D | Page 12 of 16

Data Sheet ADuM4160

The insulation lifetime of the ADuM4160 depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8,
Figure 9, and Figure 10 illustrate these different isolation voltage
waveforms.

Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.

In the case of unipolar ac or dc voltage, the stress on the insula­tion is significantly lower. This allows operation at higher working
voltages and still achieves a 50-year service life. The working
voltages listed in Tabl e 8 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases. Treat any cross­insulation voltage waveform that does not conform to Figure 9
or Figure 10 as a bipolar ac waveform and limit its peak voltage
to the 50-year lifetime voltage value listed in Table 8.

Note that the voltage presented in Figure 9 is shown as sinu­soidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 8. Bipolar AC Waveform

08171-008

RATED PEAK VOL TAGE

0V

Figure 9. Unipolar AC Waveform

08171-009

RATED PEAK VOL TAGE

0V

Figure 10. DC Waveform

08171-010

Rev. D | Page 13 of 16

ADuM4160 Data Sheet

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

0
0

.

7

.

2

(

5

0

(

5

0

2

9

5

)

.

0

0

9

8

)

.

0

1.27 (0.0500)

0.40 (0.0157)

45°

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 11. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

13.00 (0.5118)

12.60 (0.4961)

0.51 (0.0201)

0.31 (0.0122)

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

0
0

.

7

5

.

2

5

(

0

.

0

2

9

(

0

.

0

0

9

1.27 (0.0500)

0.40 (0.0157)

5

)

45°

)

8

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

16

1

1.27

(0.0500)

BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTSFOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AC

10-12-2010-A

Figure 12. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]

Wide Body (RI-16-1)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Maximum
Propagation
Delay, 5 V (ns)

Rev. D | Page 14 of 16

Maximum
Jitter (ns) Temperature Range Package Description

Package
Option

Model

1, 2

Number
of Inputs,
V

DD1

Side

Number
of Inputs,
V

Side

DD2

Maximum
Data Rate
(Mbps)

ADuM4160BRWZ 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM4160BRWZ-RL 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM4160BRIZ 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM4160BRIZ-RL 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
EVAL-ADUM4160EBZ Evaluation Board

1

Z = RoHS Compliant Part.

2

For all devices listed, specifications represent full speed buffer configuration.

Data Sheet ADuM4160

NOTES

Rev. D | Page 15 of 16

ADuM4160 Data Sheet

NOTES

©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08171-0-2/12(D)

Rev. D | Page 16 of 16