Datasheet ADuM3401 Datasheet (ANALOG DEVICES)

Quad-Channel, Digital Isolators,

Enhanced System-Level ESD Reliability

Data Sheet

FEATURES

Enhanced system-level ESD performance per IEC 61000-4-x Low power operation

5 V operation

1.4 mA per channel maximum @ 0 Mbps to 2 Mbps

4.3 mA per channel maximum @ 10 Mbps 34 mA per channel maximum @ 90 Mbps

3 V operation

0.9 mA per channel maximum @ 0 Mbps to 2 Mbps

2.4 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body, RoHS-compliant package

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

= 560 V peak

V

IORM

APPLICATIONS

General-purpose multichannel isolation SPI/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

ADuM3400/ADuM3401/ADuM3402

GENERAL DESCRIPTION

The ADuM340x1 are 4-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

iCoupler devices remove the design difficulties commonly associated with optocouplers. Typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM340x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. The ADuM340x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

In comparison to the ADuM140x isolators, the ADuM340x isolators contain various circuit and layout changes to provide increased capability relative to system-level IEC 61000-4-x testing (ESD/burst/surge). The precise capability in these tests for either the ADuM140x or ADuM340x products is strongly determined by the design and layout of the user’s board or module. For more information, see the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products.

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

V

GND

DD1

1 2

1

3

V

IA

V

4

IB

5

V

IC

6

V

ID

7

NC

8

1

ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

05985-001

Figure 1. ADuM3400 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

1

V

DD1

2

GND

1

3

ENCODE DECODE

V

IA

V

4

ENCODE DECODE

IB

5

ENCODE DECODE

V

IC

6

OD

7

V

E1

8

1

DECODE ENCODE

V

GND

Figure 2. ADuM3401 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

E2

9

GND

2

05985-002

V

GND

1

DD1

2

1

3

ENCODE DECODE

V

IA

V

4

ENCODE DECODE

IB

5

OC

6

OD

7

V

E1

8

1

DECODE ENCODE DECODE ENCODE

V V

Figure 3. ADuM3402 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

E2

9

GND

2

05985-003

ADuM3400/ADuM3401/ADuM3402 Data Sheet

REVISION HISTORY

2/12—Rev. A to Rev. B

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 20

6/07—Rev. 0 to Rev. A

Updated VDE Certification Throughout ...................................... 1

Changes to Features, General Description, Note 1, Figure 1,

Figure 2, and Figure 3....................................................................... 1

Changes to Regulatory Information Section .............................. 12

Changes to Table 7 and Figure 4 Caption .................................... 13

Added Table 10; Renumbered Sequentially ................................ 14

Added Insulation Lifetime Section .............................................. 22

Inserted Figure 21, Figure 22, and Figure 23 .............................. 22

Changes to Ordering Guide .......................................................... 23

3/06—R

evision 0: Initial Version

Rev. B | Page 2 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

DDI (Q)

Output Supply Current per Channel, Quiescent

I

DDO (Q)

0.29

0.35

mA

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

V

DD2

Supply Current

I

DD2 (10)

4.4

6.5

mA

5 MHz logic signal freq.

DD1

DD1 (90)

DD2

DD2 (90)

DC to 2 Mbps

DD1

DD2

DD1 (Q)

DD2 (Q)

DD1

DD2

DD1 (10)

DD2 (10)

DD1

DD2

DD1 (90)

DD2 (90)

ID

E2

E1

DD1

DD2

EH

EL

OAH

OBH,

DD1

DD2

IxH

OCH

ODH

DD1

DD2

IxH

OAL

OBL,

IxL

OCL

ODL

IxL

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

ADuM3400, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

V

Supply Current I

90 Mbps (CRW Grade Only)

V

Supply Current I

V

Supply Current I

ADuM3401, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

DD2

= 5 V.

0.57 0.83 mA

2.9 3.5 mA DC to 1 MHz logic signal freq.

1.2 1.9 mA DC to 1 MHz logic signal freq.

9.0 11.6 mA 5 MHz logic signal freq.

3.0 5.5 mA 5 MHz logic signal freq.

72 100 mA 45 MHz logic signal freq. 19 36 mA 45 MHz logic signal freq.

2.5 3.2 mA DC to 1 MHz logic signal freq.

1.6 2.4 mA DC to 1 MHz logic signal freq.

7.4 10.6 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

V

Supply Current I

59 82 mA 45 MHz logic signal freq. 32 46 mA 45 MHz logic signal freq.

ADuM3402, Total Supply Current, Four Channels1

V

or V

Supply Current I

, I

2.0 2.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

or V

Supply Current I

, I

6.0 7.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

or V

Supply Current I

, I

51 62 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V V Logic Low Output Voltages V

V

I

, IE1, I VIH, V VIL, V

, V , V , V , V

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

, VE2 ≤ V

2.0 V

0.8 V

(V

or V

) − 0.1 5.0 V IOx = −20 µA, VIx = V

(V

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

or V

DD1

or V

,

DD2

Rev. B | Page 3 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

Propagation Delay4

t

PHL

, t

PLH

50

65

100

ns

CL = 15 pF, CMOS signal levels

PLH

PHL

4

PSK

PSKCD/OD

PHL

PLH

PHL

4

PSK

Maximum Data Rate3

90

120 Mbps

CL = 15 pF, CMOS signal levels

PHL

PLH

PHL

4

PSK

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM340xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels

Pulse Width Distortion, |t Propagation Delay Skew5 t Channel-to-Channel Matching6 t

− t

|

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

ADuM340xBRW

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

− t

|

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

15 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

ADuM340xCRW

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels

Propagation Delay4 t Pulse Width Distortion, |t

− t

|

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

For All Models

Output Disable Propagation Delay

10 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

(High/Low-to-High Impedance) Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output

7

| 25 35 kV/µs VIx = V

|CM

H

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8 I

0.20 mA/Mbps

0.05 mA/Mbps

Rev. B | Page 4 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DD2

propagation delay is

PLH

Rev. B | Page 5 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

DDI (Q)

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

90 Mbps (CRW Grade Only)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD2

DD1 (Q)

DD2 (Q)

DD1

DD2

DD1 (10)

DD2 (10)

DD1

DD2

DD1 (90)

DD2 (90)

ID

E2

EH

EL

OAH

OBH,

DD1

DD2

IxH

OCH

ODH

DD1

DD2

IxH

OAL

OBL

IxL

OCL

ODL

IxL

PHL

PLH

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM3400, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

V

Supply Current I

90 Mbps (CRW Grade Only)

V

Supply Current I

V

Supply Current I

ADuM3401, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

V

Supply Current I

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.31 0.49 mA

0.19 0.27 mA

1.6 2.1 mA DC to 1 MHz logic signal freq.

0.7 1.2 mA DC to 1 MHz logic signal freq.

4.8 7.1 mA 5 MHz logic signal freq.

1.8 2.3 mA 5 MHz logic signal freq.

37 54 mA 45 MHz logic signal freq. 11 15 mA 45 MHz logic signal freq.

1.4 1.9 mA DC to 1 MHz logic signal freq.

0.9 1.5 mA DC to 1 MHz logic signal freq.

4.1 5.6 mA 5 MHz logic signal freq.

2.5 3.3 mA 5 MHz logic signal freq.

V

Supply Current I

V

Supply Current I

31 44 mA 45 MHz logic signal freq. 17 24 mA 45 MHz logic signal freq.

ADuM3402, Total Supply Current, Four Channels1

DC to 2 Mbps

V

or V

Supply Current I

, I

1.2 1.7 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

or V

Supply Current I

, I

3.3 4.4 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

or V

Supply Current I

, I

24 39 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

I

, IE1, I Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V V Logic Low Output Voltages V

V

VIH, V VIL, V

, V , V , V , V

0.2 0.4 V IOx = 4 mA, VIx = V

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

, VE2 ≤ V

E1

1.6 V

0.4 V

(V

or V

) − 0.1 3.0 V IOx = −20 µA, VIx = V

(V

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

, 0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

DD1

or V

SWITCHING SPECIFICATIONS

ADuM340xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

or V

DD2

,

DD2

DD1

Rev. B | Page 6 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

PLH

PHL

4

PSK

PSKCD/OD

Minimum Pulse Width2

PW

100

ns

CL = 15 pF, CMOS signal levels

PHL

PLH

PHL

PSK

PHL

PLH

PHL

4

PSK

Channel-to-Channel Matching,

t

2

ns

CL = 15 pF, CMOS signal levels

Output Disable Propagation Delay

t

, t

6 8

ns

CL = 15 pF, CMOS signal levels

DDI (D)

Output Dynamic Supply Current per Channel8

I

DDO (D)

0.03 mA/Mbps

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM340xBRW

Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

ADuM340xCRW

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t

Codirectional Channels6 Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I

− t

|

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

− t

4

|

22 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

t

6

− t

|

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

6

7

PSKOD

PHZ

PLH

t

, t

PZH

PZL

|CM

| 25 35 kV/µs VIx = V

H

6 8 ns CL = 15 pF, CMOS signal levels

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.10 mA/Mbps

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

Rev. B | Page 7 of 24

propagation delay is

PLH

ADuM3400/ADuM3401/ADuM3402 Data Sheet

DDI (Q)

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

DD1

DD1 (10)

DD2

DD2 (10)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

3 V/5 V Operation

1.6

2.4

mA

DC to 1 MHz logic signal freq.

DD1

DD1 (10)

DD2

DD2 (10)

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

2.7 V ≤ V unless otherwise noted; all typical specifications are at T

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.57 0.83 mA 3 V/5 V Operation 0.31 0.49 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.29 0.27 mA 3 V/5 V Operation 0.19 0.35 mA

ADuM3400, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I 5 V/3 V Operation 2.9 3.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.6 2.1 mA DC to 1 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

= 5 V, V

DD1

≤ 3.6 V; 3 V/5 V operation:

DD2

= 3.0 V.

DD2

V

Supply Current I 5 V/3 V Operation 9.0 11.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.8 7.1 mA 5 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 1.8 2.3 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 5.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I 5 V/3 V Operation 72 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 37 54 mA 45 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 19 36 mA 45 MHz logic signal freq.

ADuM3401, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I 5 V/3 V Operation 2.5 3.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.4 1.9 mA DC to 1 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I 5 V/3 V Operation 7.4 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.6 mA 5 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 2.5 3.3 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.4 6.5 mA 5 MHz logic signal freq.

Rev. B | Page 8 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 59 82 mA 45 MHz logic signal freq. 3 V/5 V Operation 31 44 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 17 24 mA 45 MHz logic signal freq. 3 V/5 V Operation 32 46 mA 45 MHz logic signal freq.

ADuM3402, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.0 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.7 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.2 1.7 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 2.0 2.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 6.0 7.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.3 4.4 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 3.3 4.4 mA 5 MHz logic signal freq. 3 V/5 V Operation 6.0 7.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 46 62 mA 45 MHz logic signal freq. 3 V/5 V Operation 24 39 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 24 39 mA 45 MHz logic signal freq. 3 V/5 V Operation 46 62 mA 45 MHz logic signal freq.

For All Models

Input Currents

Logic High Input Threshold

5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V

Logic High Output Voltages V

V

Logic Low Output Voltages V

V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM340xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

, IIB, IIC,

I

IA

I

, IE1, I

ID

VIH, V

VIL, V

OAH

−10 +0.01 +10 μA

E2

EH

EL

, V

OBH

,

or V

(V

DD1

DD2

) −

or V

(V

DD1

) V IOx = −20 μA, VIx = V

DD2

0 V ≤ V 0 V ≤ V

IA,VIB

E1,VE2

, VIC,VID ≤ V

≤ V

or V

DD1

or V

DD1

DD2

IxH

0.1

, V

(V

or V

) −

(V

OCH

ODH

DD1

DD2

0.4

, 0.0 0.1 V IOx = 20 μA, VIx = V

OAL, VOBL

, V

0.04 0.1 V IOx = 400 μA, VIx = V

OCL

ODL

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

0.2

DD1

or V

V I

) −

DD2

= −4 mA, VIx = V

Ox

IxH

IxL

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

DD2

,

Rev. B | Page 9 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

PHL

PLH

Pulse Width Distortion, |t

PLH

− t

PHL

|

4

PWD

3

ns

CL = 15 pF, CMOS signal levels

PSK

PHL

PLH

PHL

PSK

at Logic High Output7

transient magnitude = 800 V

Common-Mode Transient Immunity

|CML|

25

35 kV/µs

VIx = 0 V, VCM = 1000 V,

DDI (D)

5 V/3 V Operation

0.20 mA/Mbps

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM340xBRW

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

ADuM340xCRW

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

− t

4

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

14 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

, t

PHZ

t

, t

PZH

|CMH| 25 35 kV/µs VIx = V

6 8 ns CL = 15 pF, CMOS signal levels

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PZL

, VCM = 1000 V,

DD1/VDD2

at Logic Low Output

7

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel8 I

3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel8 I

5 V/3 V Operation 0.03 mA/Mbps

3 V/5 V Operation 0.05 mA/Mbps

Rev. B | Page 10 of 24

transient magnitude = 800 V

Data Sheet ADuM3400/ADuM3401/ADuM3402

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DD2

propagation delay is

PLH

Rev. B | Page 11 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

I-O

1

I-O

JCI

JCO

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Tes t Conditions

Resistance (Input-to-Output)1 R Capacitance (Input-to-Output) Input Capacitance2 CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

1

Device considered a 2-terminal device; Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM340x is approved by the organizations listed in Table 5. Refer to Ta bl e 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.

Table 5.

UL CSA VDE

Recognized under 1577 component recognition program

Double/reinforced insulation, 2500 V rms isolation voltage

Approved under

1

CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and

IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage

Reinforced insulation per CSA 60950-1-03

and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM340x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

2

In accordance with DIN V VDE V 0884-10, each ADuM340x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection

limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals,

Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals,

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

1012 Ω

C

2.2 pF f = 1 MHz

33 °C/W Thermocouple located at

28 °C/W

center of package underside

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122

Reinforced insulation, 560 V peak

approval.

shortest distance through air

shortest distance path along body

Rev. B | Page 12 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

IORM

m

CASE TEMPERATURE (°C)

SAFETY- LIMITING CURRENT (mA)

0

350

300

250

200

150

100

50

50 100 150 200

SIDE #1

SIDE #2

05985-004

DD1

DD2

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV

For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1 V

Input-to-Output Test Voltage, Method A V

× 1.87 5 = VPR, 100% production test,

IORM

= 1 sec, partial discharge < 5 pC

t

× 1.6 = VPR, tm = 60 sec,

IORM

partial discharge < 5 pC After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 and Subgroup 3 V

× 1.2 = VPR, tm = 60 sec,

IORM

partial discharge < 5 pC

Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak Safety-Limiting Values Maximum value allowed in the

event of a failure (see Figure 4) Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

560 V peak

VPR 1050 V peak

VPR

672 V peak

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Rating

Operating Temperature Range (TA) −40°C to +105°C Supply Voltages (V Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground. See the DC Correctness

and Magnetic Field Immunity section for information on immunity to external magnetic fields.

, V

)1 2.7 V to 5.5 V

Rev. B | Page 13 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

DD1

DD2

DD1

DDO

DDI

DDO

DDI

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 9.

Parameter Rating

Storage Temperature Range (TST) −65°C to +150°C Ambient Operating Temperature Range (TA) −40°C to +105°C Supply Voltages (V Input Voltage ( VIA, VIB, VIC, VID, VE1, VE2) Output Voltage (VOA, VOB, VOC, VOD)

, V

)1 −0.5 V to +7.0 V

1, 2

−0.5 V to V

+ 0.5 V

Average Output Current per Pin3

Side 1 (IO1) −18 mA to +18 mA Side 2 (IO2) −22 mA to +22 mA

Common-Mode Transients (CMH, CML)4 −100 kV/µs to

+100 kV/µs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

3

See Figure 4 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the Absolute Maximum Ratings can cause latchup or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

1

Table 10. Maximum Continuous Working Voltage

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

DC Voltage

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Table 11. Truth Table (Positive Logic)

VIx Input1 VEx Input2 V

State1 V

State1 VOX Output1 Notes

H H or NC Powered Powered H L H or NC Powered Powered L x L Powered Powered Z x H or NC Unpowered Powered H Outputs return to the input state within 1 µs of V x L Unpowered Powered Z x x Powered Unpowered Indeterminate Outputs return to the input state within 1 µs of V

1

VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. V

refer to the supply voltages on the input and output sides of the given channel, respectively.

V

DDO

2

In noisy environments, connecting VEx to an external logic high or low is recommended.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

power restoration.

power restoration if VEx state is H or NC. Outputs return to high impedance state within 8 ns of V

power restoration if VEx state is L.

DDO

and

DDI

Rev. B | Page 14 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

V

DD1

1

*GND

1

2

V

IA

3

V

IB

4

V

DD2

16

GND

2

*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

ID

6

V

OD

11

NC

7

V

E2

10

*GND

1

8

GND2*

9

NC = NO CONNECT

ADuM3400

TOP VIEW

(Not to S cale)

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNE CTING BOTH TO GND

1

IS RECOMM E NDE D. PIN 9 AND PIN 15 ARE INTERNALL Y CONNECTED AND

CONNECTING BOTH TO GND

2

IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT E NABLES (PIN 7 FOR ADuM3401/ ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED.

05985-005

Pin No.

Mnemonic

Description

DD1

1

IA

ID

9, 15

GND2

Ground 2. Ground reference for Isolator Side 2.

OD

DD2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADuM3400 Pin Configuration

Table 12. ADuM3400 Pin Function Descriptions

1 V 2, 8 GND 3 V

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V

Logic Input D. 7 NC No Connect.

10 VE2 Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.

VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic

high or low is recommended. 11 V

Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. B | Page 15 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

V

DD1

1

*GND

1

2

V

IA

3

V

IB

4

V

DD2

16

GND2*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

OD

6

V

ID

11

V

E1

7

V

E2

10

*GND

1

8

GND

2

*

9

ADuM3401

TOP VIEW

(Not to S cale)

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNE CTING BOTH TO GND

1

IS RECOMM E NDE D. PIN 9 AND PIN 15 ARE INTERNALL Y CONNECTED AND

CONNECTING BOTH TO GND

2

IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT E NABLES (PIN 7 FOR ADuM3401/ ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED.

05985-006

DD1

1

IA

6

V

OD

Logic Output D.

ID

16

V

DD2

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.

Figure 6. ADuM3401 Pin Configuration

Table 13. ADuM3401 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2, 8 GND 3 V

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C.

7 VE1 Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled when

VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended. 9, 15 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected.

, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high

V

OA

or low is recommended. 11 V

Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A.

Rev. B | Page 16 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

V

DD1

1

*GND

1

2

V

IA

3

V

IB

4

V

DD2

16

GND

2

*

15

V

OA

14

V

OB

13

V

OC

5

V

IC

12

V

OD

6

V

ID

11

V

E1

7

V

E2

10

*GND

1

8

GND2*

9

ADuM3402

TOP VIEW

(Not to S cale)

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNE CTING BOTH TO GND

1

IS RECOMM E NDE D. PIN 9 AND PIN 15 ARE INTERNALL Y CONNECTED AND

CONNECTING BOTH TO GND

2

IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT E NABLES (PIN 7 FOR ADuM3401/ ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED.

05985-007

Pin No.

Mnemonic

Description

DD1

1

IA

OD

ID

DD2

Figure 7. ADuM3402 Pin Configuration

Table 14. ADuM3402 Pin Function Descriptions

1 V 2, 8 GND 3 V

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 V

Logic Output D. 7 VE1 Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected.

VOC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or

low is recommended. 9, 15 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.

V

and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or

OA

low is recommended. 11 V

Logic Input D. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. B | Page 17 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

DATA RATE (Mbps)

CURRENT/CHANNEL ( mA)

0

20

4020 60 80 100

5V

3V

15

10

5

05985-008

DATA RATE (Mbps)

CURRENT/CHANNEL ( mA)

0

20

4020 60 80 100

5V

3V

15

10

5

05985-009

DATA RATE (Mbps)

CURRENT/CHANNEL ( mA)

0

20

4020 60 80 100

5V

3V

15

10

5

05985-010

DATA RATE (Mbps)

CURRENT (mA)

0

80

4020 60 80 100

5V

3V

60

40

20

05985-011

DATA RATE (Mbps)

CURRENT (mA)

0

80

4020 60 80 100

5V

3V

60

40

20

05985-012

DATA RATE (Mbps)

CURRENT (mA)

0

80

4020 60 80 100

5V

3V

60

40

20

05985-013

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Typical Input Supply Current per Channel vs. Data Rate (No Load)

Figure 9. Typical Output Supply Current per Channel vs. Data Rate (No Load)

Figure 11. Typical ADuM3400 V

for 5 V and 3 V Operation

Figure 12. Typical ADuM3400 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD1

Supply Current vs. Data Rate

DD2

Figure 10. Typical Output Supply Current per Channel vs. Data Rate

(15 pF Output Load)

Figure 13. Typical ADuM3401 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD1

Rev. B | Page 18 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

DATA RATE (Mbps)

CURRENT (mA)

0

80

4020 60 80 100

5V

3V

60

40

20

05985-014

DATA RATE (Mbps)

CURRENT (mA)

0

80

4020 60 80 100

5V

3V

60

40

20

05985-015

TEMPERATURE (°C)

PROPAGAT ION DELAY (ns)

–50 –25

25

30

35

40

0 50 7525 100

3V

5V

05985-016

Figure 14. Typical ADuM3401 V

Figure 15. Typical ADuM3402 V

Supply Current vs. Data Rate

DD1

DD2

or V

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

Figure 16. Propagation Delay vs. Temperature, C Grade

Rev. B | Page 19 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

V

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM340x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 17). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V Pin 16 for V

. The capacitor value should be between 0.01 μF

DD2

and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.

V

DD1

GND

1

V

IA

V

IB IC/OC ID/OD

V

E1

GND

1

Figure 17. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the Absolute Maximum Ratings of the device, thereby leading to latch-up or permanent damage.

and between Pin 15 and

DD1

V

DD2

GND V

OA

V

OB

V

OC/IC

V

OD/ID

V

E2

GND

2

5985-017

While the ADuM340x improve system-level ESD reliability, they are no substitute for a robust system-level design. See the

AN-793 application note, ESD/Latch-Up Considerations with

iCoupler Isolation Products for detailed recommendations on board layout and system-level design.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high.

INPUT (

)

Ix

OUTPUT (V

t

PLH

)

Ox

Figure 18. Propagation Delay Parameters

t

PHL

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM340x component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM340x components operating under the same conditions.

50%

05985-018

See the AN-1109 Application Note for board layout guidelines.

SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS

System-level ESD reliability (for example, per IEC 61000-4-x) is highly dependent on system design, which varies widely by application. The ADuM340x incorporate many enhancements to make ESD reliability less dependent on system design. The enhancements include:

 ESD protection cells added to all input/output interfaces.  Key metal trace resistances reduced using wider geometry

and paralleling of lines with vias.

 The SCR effect inherent in CMOS devices minimized by

use of guarding and isolation technique between PMOS and NMOS devices.

 Areas of high electric field concentration eliminated using

45° corners on metal traces.

 Supply pin overvoltage prevented with larger ESD clamps

between each supply pin and its respective ground.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 11) by the watchdog timer circuit.

The limitation on the magnetic field immunity of the ADuM340x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM340x is examined because it represents the most susceptible mode of operation.

Rev. B | Page 20 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

MAGNETI C FIELD FRE QUENCY (Hz)

100

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY ( kgauss)

0.001 1M

10

0.

01

1k 10k 10M

0.1

1

100M100k

05985-019

MAGNETI C FIELD FRE QUENCY (Hz)

MAXIMUM AL LOWABLE CURRE NT (kA)

1000

100

10

1

0.1

0.01 1k 10k 100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

05985-020

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)∑∏r

where:

β is magnetic flux density (gauss).

N is the number of turns in the receiving coil.

r

is the radius of the nth turn in the receiving coil (cm).

n

Given the geometry of the receiving coil in the ADuM340x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19.

2

; N = 1, 2, … , N

n

Figure 20. Maximum Allowable Current

for Various Current-to-ADuM340x Spacings

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

Figure 19. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil, which is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM340x transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM340x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM340x to affect the operation of the component.

POWER CONSUMPTION

The supply current at a given channel of the ADuM340x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

I

DDI

= I

× (2f − fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

where:

, I

I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz); it is half of the input

data rate expressed in units of Mbps.

is the input stage refresh rate (Mbps).

f

r

, I

I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

Rev. B | Page 21 of 24

f ≤ 0.5 fr

f > 0.5 fr

DDO (Q)

f > 0.5 fr

ADuM3400/ADuM3401/ADuM3402 Data Sheet

0V

RATED PEAK VOLTAGE

05985-021

0V

RATED PEAK VOLTAGE

05985-022

0V

RATED PEAK VOLTAGE

05985-023

To calculate the total I

DD1

and I

supply current, the supply

DD2

currents for each input and output channel corresponding to V

DD1

and V

are calculated and totaled. Figure 8 provides the

DD2

per-channel input supply current as a function of the data rate. Figure 9 and Figure 10 provide the per-channel supply output current as a function of the data rate for an unloaded output condition and for a 15 pF output condition, respectively. Figure 11 through Figure 15 provide the total V

DD1

and V

supply current

DD2

as a function of the data rate for ADuM3400/ADuM3401/ ADuM3402 channel configurations.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 22 or Figure 23 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10.

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM340x.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Figure 21 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM340x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these different isolation voltage waveforms.

Note that the voltage presented in Figure 22 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

Figure 21. Bipolar AC Waveform

Figure 22. Unipolar AC Waveform

Figure 23. DC Waveform

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the recommended maximum working voltage of Analog Devices.

Rev. B | Page 22 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

10.50 (0.4134)

10.10 (0.3976)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75 (0.0295)

0.25 (0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING PLANE

8° 0°

16

9

8

1

1.27 (0.0500) BSC

03-27-2007-B

DD1

DD2

OUTLINE DIMENSIONS

Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Inputs, V

Model

1, 2

ADuM3400ARWZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3400BRWZ 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3400CRWZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3401ARWZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3401BRWZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3401CRWZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3402ARWZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3402BRWZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM3402CRWZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

1

Z = RoHS Compliant Part.

2

Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.

Side

Number of Inputs, V

Side

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse Width Distortion (ns)

Temperature Range

Package Description

Package Option

Rev. B | Page 23 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D05985-0-2/12(B)

Rev. B | Page 24 of 24

Datasheet ADuM3401 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE