Datasheet ADUM3300 Datasheet (ANALOG DEVICES)

Triple-Channel, Digital Isolators,

Enhanced System-Level ESD Reliability

Data Sheet

FEATURES

Enhanced system-level ESD performance per IEC 61000-4-x Low power operation

5 V operation

2.0 mA per channel maximum @ 0 Mbps to 2 Mbps

4.1 mA per channel maximum @ 10 Mbps 36 mA per channel maximum @ 90 Mbps

3 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps

2.8 mA per channel maximum @ 10 Mbps

17 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body, RoHS-compliant package

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 V

= 560 V peak

IORM

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation

ADuM3300/ADuM3301

GENERAL DESCRIPTION

The ADuM330x1 are 3-channel digital isolators based on the

Analog Devices, Inc. iCoupler® technology. Combining high

peed

s

CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocoupler devices.

iCoupler devices remove the design difficulties commonly associated with optocouplers. Typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM330x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. The ADuM330x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

In comparison to ADuM130x isolators, ADuM330x isolators contain various circuit and layout changes to provide increased capability relative to system-level IEC 61000-4-x testing (ESD, burst, and surge). The precise capability in these tests for either the ADuM130x or ADuM330x products is strongly determined by the design and layout of the user’s system.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

GND

1

ENCODE DECODE

3

ENCODE DECODE

4

ENCODE DECODE

5

6

7

8

GND

V

IA

V

IB

V

IC

NC

1

Figure 1. ADuM3300 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

16

V

DD2

15

GND

2

V

14

OA

13

V

OB

V

12

OC

11

NC

V

10

E2

9

GND

2

05984-001

V

GND

1

DD1

2

1

V

IA

V

IB

V

OC

NC

V

E1

1

ENCODE DECODE

3

ENCODE DECODE

4

DECODE ENCODE

5

6

7

8

V

16

DD2

GND

15

V

14

OA

13

V

OB

V

12

IC

11

NC

10

V

E2

9

GND

Figure 2. ADuM3301 Functional Block Diagram

2

05984-002

ADuM3300/ADuM3301 Data Sheet

REVISION HISTORY

2/12—Rev. A to Rev. B

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section................................................................. 1

Change to PC Board Layout Section............................................ 17

Updated Outline Dimensions....................................................... 20

6/07—Rev. 0 to Rev. A

Updated VDE Certification Throughout...................................... 1

Changes to Features, General Description, and Note 1............... 1

Changes to Regulatory Information Section .............................. 10

Changes to DIN V VDE V 0884-10 (VDE V 0884-10)

Insulation Characteristics.............................................................. 11

Added Table 10 ............................................................................... 12

Added Insulation Lifetime Section .............................................. 19

3/06—Revision 0: Initial Version

Rev. B | Page 2 of 20

Data Sheet ADuM3300/ADuM3301

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM3300, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM3301, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents

I

I Logic High Input Threshold Logic Low Input Threshold

VIH, V

VIL, V

V

Logic Low Output Voltages

V

SWITCHING SPECIFICATIONS

ADuM330xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching6 t

≤ 5.5 V, 4.5 V ≤ V

DD1

0.66 0.97 mA

DDI (Q)

0.39 0.55 mA

DDO (Q)

2.4 3.3 mA DC to 1 MHz logic signal freq.

DD1 (Q)

1.1 2.1 mA DC to 1 MHz logic signal freq.

DD2 (Q)

7.0 8.1 mA 5 MHz logic signal freq.

DD1 (10)

2.7 3.6 mA 5 MHz logic signal freq.

DD2 (10)

54 77 mA 45 MHz logic signal freq.

DD1 (90)

15 31 mA 45 MHz logic signal freq.

DD2 (90)

2.0 3.1 mA DC to 1 MHz logic signal freq.

DD1 (Q)

1.6 2.3 mA DC to 1 MHz logic signal freq.

DD2 (Q)

5.5 6.9 mA 5 MHz logic signal freq.

DD1 (10)

3.9 5.4 mA 5 MHz logic signal freq.

DD2 (10)

41 57 mA 45 MHz logic signal freq.

DD1 (90)

28 41 mA 45 MHz logic signal freq.

DD2 (90)

, IIB, IIC,

IA

, IE1, I

ID

OAH

OCH

OAL

OCL

−10 +0.01 +10 μA

E2

2.0 V

EH

0.8 V

EL

(V

or

,

DD1

) − 0.1

V

DD2

(V

or

DD1

) − 0.4

V

DD2

0.0 0.1 V IOx = 20 μA, VIx = V

0.04 0.1 V IOx = 400 μA, VIx = V

, V , V

OBH

ODH

OBL

ODL

,

0.2 0.4 V IOx = 4 mA, VIx = V

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

≤ 5.5 V; all minimum/maximum specifications apply

DD2

5.0 V I

4.8 V I

= 25°C, V

A

0 V ≤ V 0 V ≤ V

= −20 μA, VIx = V

Ox

= −4 mA, VIx = V

Ox

= V

DD1

, VIB, VIC, VID ≤ V

IA

, VE2 ≤ V

E1

DD1

IxL

DD2

or V

IxH

IxL

= 5 V.

Logic High Output Voltages

DD1

DD2

or V

DD2

,

Rev. B | Page 3 of 20

ADuM3300/ADuM3301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM330xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

ADuM330xCRWZ

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8 I

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See Figure through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

6

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

DD1

and V

supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.

DD2

or t

PHL

PLH

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

10 ns CL = 15 pF, CMOS signal levels

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

PHZ

t

PZH

|CM

, t

6 8 ns CL = 15 pF, CMOS signal levels

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PZL

| 25 35 kV/μs

H

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/μs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

0.20 mA/Mbps

DDI (D)

0.05 mA/Mbps

DDO (D)

ower Consumption

that is measured between units at the same operating temperature, supply voltages, and output load

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

9

propagation delay is

PLH

Figure 8

Rev. B | Page 4 of 20

Data Sheet ADuM3300/ADuM3301

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM3300, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM3301, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages

SWITCHING SPECIFICATIONS

ADuM330xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

≤ 3.6 V, 2.7 V ≤ V

DD1

0.37 0.57 mA

DDI (Q)

0.25 0.37 mA

DDO (Q)

1.4 1.9 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.7 1.2 mA DC to 1 MHz logic signal freq.

DD2 (Q)

3.8 5.3 mA 5 MHz logic signal freq.

DD1 (10)

1.5 2.1 mA 5 MHz logic signal freq.

DD2 (10)

28 41 mA 45 MHz logic signal freq.

DD1 (90)

8.2 11 mA 45 MHz logic signal freq.

DD2 (90)

1.1 1.6 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.9 1.4 mA DC to 1 MHz logic signal freq.

DD2 (Q)

3.0 4.1 mA 5 MHz logic signal freq.

DD1 (10)

2.2 2.9 mA 5 MHz logic signal freq.

DD2 (10)

22 31 mA 45 MHz logic signal freq.

DD1 (90)

15 21 mA 45 MHz logic signal freq.

DD2 (90)

, IIB, I

I

IA

I

, IE1, I

ID

VIH, V VIL, V V

OAH

V

OCH

V

OAL

V

OCL

−10 +0.01 +10 μA

IC,

E2

1.6 V

EH

0.4 V

EL

(V

, V , V

OBH

ODH

OBL

ODL

or

,

DD1

) − 0.1

V

DD2

(V

or

DD1

) − 0.4

V

DD2

0.0 0.1 V IOx = 20 μA, VIx = V

,

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V I

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

≤ 3.6 V; all minimum/maximum specifications apply

DD2

3.0 V I

2.8 V I

= 25°C, V

A

0 V ≤ V 0 V ≤ V

= −20 μA, VIx = V

Ox

= −4 mA, VIx = V

Ox

= 4 mA, VIx = V

Ox

= V

DD1

, VIB, VIC, VID ≤ V

IA

≤ V

E1,VE2

DD1

IxL

= 3.0 V.

DD2

or V

IxH

IxL

or V

DD1

DD2

Logic High Output Voltages

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

DD2

,

Rev. B | Page 5 of 20

ADuM3300/ADuM3301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM330xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

ADuM330xCRWZ

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance-to-High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8 I

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See Figure through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

6

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

DD1

and V

supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.

DD2

or t

PHL

PLH

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

PHZ

t

PZH

|CM

, t

H

6 8 ns CL = 15 pF, CMOS signal levels

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PZL

| 25 35 kV/μs

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/μs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

0.10 mA/Mbps

DDI (D)

0.03 mA/Mbps

DDO (D)

ower Consumption

that is measured between units at the same operating temperature, supply voltages, and output load

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

9

propagation delay is

PLH

Figure 8

Rev. B | Page 6 of 20

Data Sheet ADuM3300/ADuM3301

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

2.7 V ≤ V

≤ 3.6 V, 4.5 V ≤ V

DD1

unless otherwise noted. All typical specifications are at T

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

DDI (Q)

5 V/3 V Operation 0.66 0.97 mA 3 V/5 V Operation 0.37 0.57 mA

Output Supply Current per Channel, Quiescent I

DDO (Q)

5 V/3 V Operation 0.25 0.37 mA 3 V/5 V Operation 0.39 0.55 mA

ADuM3300, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 2.4 3.3 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.4 1.9 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.1 2.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 7.0 8.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.8 5.3 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 1.5 2.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.7 3.6 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

DD1 (90)

5 V/3 V Operation 54 77 mA 45 MHz logic signal freq. 3 V/5 V Operation 28 41 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (90)

5 V/3 V Operation 8.2 11 mA 45 MHz logic signal freq. 3 V/5 V Operation 15 31 mA 45 MHz logic signal freq.

ADuM3301, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 2.0 3.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.1 1.6 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.6 2.3 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 5.5 6.9 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 4.1 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 2.2 2.9 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.9 5.4 mA 5 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

= 5 V, V

DD1

≤ 3.6 V. 3 V/5 V operation:

DD2

= 3.0 V.

DD2

Rev. B | Page 7 of 20

ADuM3300/ADuM3301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 41 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 22 31 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 15 21 mA 45 MHz logic signal freq. 3 V/5 V Operation 28 41 mA 45 MHz logic signal freq.

For All Models

Input Currents

Logic High Input Threshold

5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V

Logic High Output Voltages

Logic Low Output Voltages

SWITCHING SPECIFICATIONS

ADuM330xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM330xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

ADuM330xCRWZ

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

DD1 (90)

DD2 (90)

, IIB, IIC,

I

IA

, IE1, I

I

ID

VIH, V

VIL, V

V

OAH

V

OCH

V

OAL

V

OCL

PHL

, V , V

, t

−10 +0.01 +10 μA

E2

EH

EL

(V

or V

, V

,

or

(V

OBH

DD1

V

, V

ODH

OBL,

ODL

) − 0.1

DD2

(V

or

DD1

) − 0.4

V

DD2

0.0 0.1 V I

0.04 0.1 V IOx = 400 μA, VIx = V

(V V

DD1

DD2

) V IOx = −20 μA, VIx = V

DD2

or

V I

) − 0.2

0.2 0.4 V IOx = 4 mA, VIx = V

50 70 100 ns CL = 15 pF, CMOS signal levels

PLH

, VIB, VIC, VID ≤ V

0 V ≤ V

IA

0 V ≤ V

, VE2 ≤ V

E1

= −4 mA, VIx = V

Ox

= 20 μA, VIx = V

Ox

DD1

IxL

or V

IxH

IxL

or V

DD1

DD2

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

14 ns CL = 15 pF, CMOS signal levels

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

DD2

,

Rev. B | Page 8 of 20

Data Sheet ADuM3300/ADuM3301

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

, t

Output Disable Propagation Delay

t

PHZ

(High/Low-to-High Impedance)

t

Output Enable Propagation Delay

PZH

, t

(High Impedance-to-High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

|CM

H

|CML| 25 35 kV/μs

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current per Channel8 I

DDI (D)

5 V/3 V Operation 0.20 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current per Channel8 I

DDO (D)

5 V/3 V Operation 0.05 mA/Mbps 3 V/5 V Operation 0.03 mA/Mbps

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3300/ADuM3301/ADuM3302 channel configurations.

DD2

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PZL

= 15 pF, CMOS signal levels

L

| 25 35 kV/μs

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Rev. B | Page 9 of 20

ADuM3300/ADuM3301 Data Sheet

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input to Output)1 R Capacitance (Input to Output)

1

Input Capacitance2 C IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

1

The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM330x is approved by the organizations listed in Tab le 5 . See Tab le 1 0 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 5.

UL CSA VDE

Recognized under UL 1577 Component Recognition Program1

Double/reinforced insulation, 2500 V rms isolation voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL1577, each ADuM330x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM330x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection

limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage

1012 Ω

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

33 °C/W

JCI

28 °C/W

JCO

Thermocouple located at center of package underside

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Reinforced insulation, 560 V peak

2

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

Rev. B | Page 10 of 20

Data Sheet ADuM3300/ADuM3301

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV

For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

After Environmental Tests Subgroup 1 896 V peak

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

After Input and/or Safety Test Subgroup 2

V

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak Safety-Limiting Values

Maximum value allowed in the event of a failure

(see Figure 3) Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

350

300

250

SIDE #2

200

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C Supply Voltages1 V Input Signal Rise and Fall Times 1.0 ms

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

SIDE #1

50 100 150 200

CASE TEMPERAT URE ( °C)

05984-003

1

All voltages are relative to their respective ground. See the

and Magnetic Field Immunity magnetic fields.

section for information on immunity to external

560 V peak

IORM

1050 V peak

V

PR

, V

2.7 5.5 V

DD1

DD2

DC Correctness

Rev. B | Page 11 of 20

ADuM3300/ADuM3301 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature TST −65 +150 °C

Ambient Operating

TA −40 +105 °C

Temperature Supply Voltages1 V Input Voltage

Output Voltage

Average Output

Current per Pin

1, 2

3

, V

−0.5 +7.0 V

DD1

DD2

VIA, VIB, VIC,

, VE1, V

V

ID

VOA, VOB, VOC, V

OD

E2

−0.5 V

+ 0.5 V

DDI

+ 0.5 V

DDO

Side 1 IO1 −23 +23 mA

Side 2 IO2 −30 +30 mA Common-Mode

Transients

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively.

3

See Figure 3 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients e xceeding the Absolute Maximum Rating can cause latch-up or permanent damage.

4

refer to the supply voltages on the input and output sides of a

DDO

CM

, CML −100 +100 kV/μs

H

1

Table 10. Maximum Continuous Working Voltage

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1

Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1

Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Table 11. Truth Table (Positive Logic)

VIX Input1 VEX Input2 V

State1 V

DDI

State1 VOX Output1 Notes

DDO

H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H

Outputs return to the input state within 1 μs of V

restoration X L Unpowered Powered Z X X Powered Unpowered Indeterminate

Outputs return to the input state within 1 μs of V

restoration if V

state is H or NC

EX

Outputs return to high impedance state within 8 ns of V

power restoration if V

1

VIX and VOX refer to the input and output signals of a given channel (A, B, or C). VEX refers to the output enable signal on the same side as the VOX outputs. V

refer to the supply voltages on the input and output sides of the given channel, respectively.

2

In noisy environments, connecting VEX to an external logic high or low is recommended.

state is L

EX

Rev. B | Page 12 of 20

power

DDI

power

DDO

DDI

DDO

and V

DDO

Data Sheet ADuM3300/ADuM3301

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

V

DD1

GND1* 2

V

3

IA

ADuM3300

4

V

IB

TOP VIEW

(Not to S cale)

V

5

IC

NC 6 NC11

7

NC

GND1* 8 GND2**9

NC = NO CONNECT

*PIN 2 AND PIN 8 ARE I NTERNALLY CO NNE CTED, AND

CONNECTING BOTH TO G ND

**PIN 9 AND PIN 15 ARE INTERNALLY CO NNE CTED, AND CONNECTING

BOTH TO GND CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3301 AND PIN 10 FOR ALL MODEL S) TO AN EXTERNAL LOG IC HIGH OR L OW IS RECOMMENDED.

IS RECOMMENDE D. IN NOISY E NV IRONMENTS,

2

IS RECOMMENDED.

1

Figure 4. ADuM3300 Pin Configuration

Table 12. ADuM3300 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2, 8 GND 3 V

IA

1

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground Reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6, 7, 11 NC

No Connect. 9, 15 GND2 Ground 2. Ground Reference for Isolator Side 2. 10 VE2

Output Enable 2. Active high logic input. V

, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic

V

OA

high or low is recommended. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

DD2

16

V

DD2

GND2**15 V

14

OA

13

V

OB

V

12

OC

10

V

E2

05984-004

, VOB, and VOC outputs are enabled when VE2 is high or disconnected.

OA

Rev. B | Page 13 of 20

ADuM3300/ADuM3301 Data Sheet

*

1

V

DD1

*GND

2

1

V

3

IA

ADuM3301

4

V

IB

TOP VIEW

(Not to S cale)

V

5

OC

NC

6

V

7

E1

8

*GND

1

NC = NO CONNECT

*PIN 2 AND PIN 8 ARE INTERNALLY CONNE CTED,

AND CONNECTING BO TH TO GND

*PIN 9 AND PIN 15 ARE INTERNALLY CONNE CTED,

AND CONNECTING BO TH TO GND

IS RECOMMENDE D.

1

IS RECOMMENDED.

2

Figure 5. ADuM3301 Pin Configuration

Table 13. ADuM3301 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2, 8 GND 3 V

IA

1

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6, 11 NC 7 VE1

No Connect.

Output Enable 1. Active high logic input. V

disabled when V

is low. In noisy environments, connecting VE1 to an external logic high or low is

E1

output is enabled when VE1 is high or disconnected. VOC is

OC

recommended. 9, 15 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2

Output Enable 2. Active high logic input. V

and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic

V

OA

and VOB outputs are enabled when VE2 is high or disconnected.

OA

high or low is recommended. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 V

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.

DD2

16 15 14 13 12 11 10

9

V

DD2

GND2** V

OA

V

OB

V

IC

NC V

E2

GND2**

05984-005

Rev. B | Page 14 of 20

Data Sheet ADuM3300/ADuM3301

TYPICAL PERFORMANCE CHARACTERISTICS

20

80

15

5V

10

5

CURRENT/CHANNEL (mA)

0

4020 60 80 100

DATA RATE (Mb ps)

3V

05984-006

Figure 6. Typical Input Supply Current per Channel vs. Data Rate (No Load)

20

15

10

5

CURRENT/CHANNEL (mA)

0

5V

3V

4020 60 80 100

DATA RATE (Mb ps)

05984-007

Figure 7. Typical Output Supply Current per Channel vs. Data Rate (No Load)

60

40

CURRENT (mA)

20

0

DATA RATE (Mb ps)

Figure 9. Typical ADuM3300 V

for 5 V and 3 V Operation

80

60

40

CURRENT (mA)

20

0

DATA RATE (Mb ps)

Figure 10. Typical ADuM3300 V

for 5 V and 3 V Operation

5V

3V

4020 60 80 100

Supply Current vs. Data Rate

DD1

5V

3V

4020 60 80 100

Supply Current vs. Data Rate

DD2

05984-009

05984-010

20

15

10

5V

5

CURRENT/CHANNEL (mA)

3V

0

4020 60 80 100

DATA RATE (Mb ps)

Figure 8. Typical Output Supply Current per Channel vs. Data Rate

(15 pF Output Load)

05984-008

Rev. B | Page 15 of 20

80

60

40

CURRENT (mA)

20

0

DATA RATE (Mb ps)

Figure 11. Typical ADuM3301 V

for 5 V and 3 V Operation

5V

3V

4020 60 80 100

Supply Current vs. Data Rate

DD1

05984-011

ADuM3300/ADuM3301 Data Sheet

80

40

60

40

CURRENT (mA)

20

0

Figure 12. Typical ADuM3301 V

5V

3V

4020 60 80 100

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

35

30

PROPAGATI ON DELAY (n s)

25

–50 –25

05984-012

0507525 100

TEMPERATURE ( °C)

3V

5V

05984-019

Figure 13. Propagation Delay vs. Temperature, C Grade

Rev. B | Page 16 of 20

Data Sheet ADuM3300/ADuM3301

V

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM330x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 14). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V Pin 16 for V

. The capacitor value should be between 0.01 μF

DD2

and between Pin 15 and

DD1

and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should be considered unless the ground pair on each package side is connected close to the package.

V

DD1

GND

1

V

IA

V

IB

V

IC/OC

NC

V

E1

GND

1

Figure 14. Recommended Printed Circuit Board Layout

V

DD2

GND V

OA

V

OB

V

OC/IC

NC V

E2

GND

2

05984-015

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s absolute maximum ratings, thereby leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS

System-level ESD reliability (for example, per IEC 61000-4-x) is highly dependent on system design, which varies widely by application. The ADuM330x incorporate many enhancements to make ESD reliability less dependent on system design. The enhancements include

• ESD protection cells added to all input/output interfaces.

• Key metal trace resistances reduced using wider geometry

and paralleling of lines with vias.

• The SCR effect inherent in CMOS devices minimized by

use of guarding and isolation technique between PMOS and NMOS devices.

• Areas of high electric field concentration eliminated using

45° corners on metal traces.

• Supply pin overvoltage prevented with larger ESD clamps

between each supply pin and its respective ground.

While the ADuM330x improve system-level ESD reliability, they are no substitute for a robust system-level design. See

Application Note AN-793 ESD/Latch-Up Considerations with iCoupler Isolation Products for detailed recommendations on

board layout and system-level design.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high.

INPUT (

OUTPUT (V

)

IX

t

PLH

)

OX

Figure 15. Propagation Delay Parameters

t

PHL

50%

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM330x component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM330x components operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Ta b l e 1 1 ) by the watchdog timer circuit.

The limitation on the ADuM330x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM330x is examined because it represents the most susceptible mode of operation.

05984-016

Rev. B | Page 17 of 20

ADuM3300/ADuM3301 Data Sheet

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)

2

∑π r

; n = 1, 2, … , N

n

where:

β is magnetic flux density (gauss).

is the radius of the nth turn in the receiving coil (cm).

r

n

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM330x and an imposed requirement that the induced voltage is at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 16.

100

10

1

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k 10k 10M

Figure 16. Maximum Allowable External Magnetic Flux Density

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

05984-017

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM330x transformers. Figure 17 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADuM330x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component (see Figure 17). For the 1 MHz example noted, a 0.5 kA current would have to be placed 5 mm away from the ADuM330x to affect the component’s operation.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALLOWABLE CURRENT (kA)

0.01 1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 17. Maximum Allowable Current

for Various Current-to-ADuM330x Spacings

05984-018

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM330x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

= I

I

DDI

× (2f − fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

where:

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz); it is half of the input

data rate expressed in units of Mbps.

f

is the input stage refresh rate (Mbps).

r

, I

I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

To calculate the total I

DD1

and I

supply current, the supply

DD2

currents for each input and output channel corresponding to V

DD1

and V

are calculated and totaled. Figure 6 provides per-

DD2

channel input supply current as a function of data rate. Figure 7 and Figure 8 provide per-channel output supply current as a function of data rate for an unloaded output condition and for a 15 pF output condition, respectively. Figure 9 through Figure 12 provide total V

DD1

and V

supply current as a function of data

DD2

rate for ADuM3300/ADuM3301 channel configurations.

f ≤ 0.5 fr

f > 0.5 fr

DDO (Q)

f > 0.5 fr

Rev. B | Page 18 of 20

Data Sheet ADuM3300/ADuM3301

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices executes an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM330x.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage.

The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life.

The insulation lifetime of the ADuM330x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 18, Figure 19, and Figure 20 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 19 or Figure 20 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10.

Note that the voltage presented in Figure 19 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 18. Bipolar AC Waveform

05984-020

RATED PEAK VOL TAGE

0V

Figure 19. Unipolar AC Waveform

05984-021

RATED PEAK VOL TAGE

0V

Figure 20. DC Waveform

05984-022

Rev. B | Page 19 of 20

ADuM3300/ADuM3301 Data Sheet

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

(

5

0

(

5

0

)

.

0

2

9

5

9

8

)

.

0

1.27 (0.0500)

0.40 (0.0157)

45°

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Inputs, V

Side

DD1

Model

1, 2

Temperature Range (°C)

ADuM3300ARWZ −40 to +105 3 0 1 100 40 RW-16 ADuM3300BRWZ −40 to +105 3 0 10 50 3 RW-16 ADuM3300CRWZ −40 to +105 3 0 90 32 2 RW-16 ADuM3301ARWZ −40 to +105 2 1 1 100 40 RW-16 ADuM3301BRWZ −40 to +105 2 1 10 50 3 RW-16 ADuM3301CRWZ −40 to +105 2 1 90 32 2 RW-16

1

Z = RoHS Compliant Part.

2

Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.

3

RW-16 = 16-lead wide body SOIC.

Number of Inputs, V

Side

DD2

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse Width Distortion (ns)

Package Option3

Rev. B | Page 20 of 20

Datasheet ADUM3300 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION INFORMATION

PC BOARD LAYOUT

SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE