Datasheet ADuM3220 Datasheet (ANALOG DEVICES)

Isolated 4 A Dual-Channel Gate Driver

FEATURES

4 A peak output current
Precise timing characteristics

60 ns maximum isolator and driver propagation delay
5 ns maximum channel-to-channel matching

High junction temperature operation: 125°C

3.3 V to 5 V input logic

4.5 V to 18 V output drive
UVLO at 2.5 V V

ADuM3220A/ADuM3221A UVLO at 4.1 V V

ADuM3220B/ADuM3221B UVLO at 7.0 V V
Thermal shutdown protection at >150°C
Output shoot-through logic protection on ADuM3220
Default low output
High frequency operation: dc to 1 MHz
CMOS input logic levels
High common-mode transient immunity: >25 kV/μs
Enhanced system-level ESD performance per IEC 61000-4-x
UL 1577 2500 V rms input-to-output withstand voltage

(pending)
Small footprint and low profile

Narrow body, RoHS-compliant, 8-lead SOIC

5 mm × 6 mm × 1.6 mm

APPLICATIONS

Isolated synchronous dc/dc converters
MOSFET/IGBT gate drivers

DD1

DD2

DD2

ADuM3220/ADuM3221

GENERAL DESCRIPTION

The ADuM3220/ADuM32211 are 4 A isolated, dual-channel
gate drivers based on the Analog Devices, Inc., iCoupler®
technology. Combining high speed CMOS and monolithic
transformer technology, these isolation components provide
outstanding performance characteristics superior to the alterna­tives, such as the combination of pulse transformers and gate
drivers.

The ADuM3220/ADuM3221 provide digital isolation in two
independent isolation channels. They have a maximum propaga­tion delay of 60 ns and 5 ns channel-to-channel matching. In
comparison to gate drivers employing high voltage level transla­tion methodologies, the ADuM3220/ADuM3221 offer the
benefit of true, galvanic isolation between the input and each
output, enabling voltage translation across the isolation barrier.
The ADuM3220 has shoot-through protection logic, which
prevents both outputs from being on at the same time, whereas
the ADuM3221 allows both outputs to be on at the same time.
They both offer a default output low characteristic as required
for gate drive applications.

The ADuM3220/ADuM3221 operate with an input supply
voltage ranging from 3.0 V to 5.5 V, providing compatibility
with lower voltage systems. The outputs of the ADuM3220A/
ADuM3221A can be operated at supply voltages from 5 V to
18 V. The outputs of the ADuM3220B/ADuM3221B can be
operated at supply voltages from 8 V to 18 V.

The ADuM3220/ADuM3221 specify the junction temperature
from −40°C to +125°C.

FUNCTIONAL BLOCK DIAGRAMS

ADuM3220

1

V

GND

DD1

V

V

2

IA

3

IB

4

1

ENCODE

ENCODE

DECODE

AND

LEVEL

SHIFT

DECODE

AND

LEVEL

SHIFT

Figure 1. Figure 2.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

8

V

DD2

7

V

OA

6

V

OB

5

GND

2

1

V

DD1

2

V

IA

3

V

IB

4

GND

1

08994-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010–2011 Analog Devices, Inc. All rights reserved.

ENCODE

ENCODE

ADuM3221

DECODE

AND

LEVEL

SHIFT

DECODE

AND

LEVEL

SHIFT

8

V

DD2

7

V

OA

6

V

OB

5

GND

2

08994-102

ADuM3220/ADuM3221

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3.3 V Operation............................. 4

Package Characteristics ............................................................... 5

Regulatory Information............................................................... 5

Insulation and Safety-Related Specifications............................ 5

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 6

Recommended Operating Conditions ...................................... 6

REVISION HISTORY

3/11—Rev. A to Rev. B

Added ADuM3220BRZ and ADuM3221BRZ models.. Universal
Changes to Features Section and General Description Section . 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Ordering Guide.......................................................... 14

1/11—Rev. 0 to Rev. A

Added ADuM3221 .............................................................Universal

Changes to Features Section and General Description Section . 1

Added Figure 2; Renumbered Sequentially .................................. 1

Changes to Endnote 3, Endnote 4, and Endnote 5, Table 1 ........ 3

Changes to Endnote 3, Endnote 4, and Endnote 5, Table 2 ........ 4

Changes to Table 8............................................................................ 7

Changes to Figure 4, Table 10, and Table 11 ................................. 8

Added Table 12; Renumbered Sequentially .................................. 8

Added Figure 8.................................................................................. 9

Change to Figure 19 and DC Correctness and Magnetic Field

Immunity Section........................................................................... 12

Changes to Ordering Guide.......................................................... 14

4/10—Revision 0: Initial Version



Absolute Maximum Ratings ............................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Typical Performance Characteristics..............................................9

Applications Information.............................................................. 11

PC Board Layout ........................................................................ 11

Propagation Delay-Related Parameters................................... 11

Thermal Limitations and Switch Load Characteristics......... 11

Output Load Characteristics..................................................... 11

DC Correctness and Magnetic Field Immunity........................... 12

Power Consumption .................................................................. 13

Insulation Lifetime..................................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. B| Page 2 of 16

ADuM3220/ADuM3221

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V
maximum specifications apply over T

= −40°C to 125°C. All typical specifications are at TJ = 25°C, V

J

specifications are tested with CMOS signal levels.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Input Supply Current, Two Channels, Quiescent I

Output Supply Current, Two Channels, Quiescent I

Total Supply Current, Two Channels1

DC to 1 MHz

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents IIA, IIB −10 +0.01 +10 μA 0 ≤ VIA, VIB ≤ V

Logic High Input Threshold VIH 0.7 × V

Logic Low Input Threshold VIL 0.3 × V

Logic High Output Voltages V

Logic Low Output Voltages V

Undervoltage Lockout, V

Supply

DD2

ADuM3220A/ADuM3221A

Positive-Going Threshold V
Negative-Going Threshold V
Hysteresis V

ADuM3220B/ADuM3221B

Positive-Going Threshold V
Negative-Going Threshold V
Hysteresis V

Output Short-Circuit Pulsed Current2 I

SWITCHING SPECIFICATIONS

Pulse Width3 PW 50 ns CL = 2 nF, V

Data Rate4 1 MHz CL = 2 nF, V

Propagation Delay5 t

t
Propagation Delay Skew6 t
Channel-to-Channel Matching7 t

t
Output Rise/Fall Time (10% to 90%) tR/tF 14 20 25 ns CL = 2 nF, V

t
Dynamic Input Supply Current per Channel I
Dynamic Output Supply Current per Channel I
Refresh Rate fr 1.2 Mbps

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total V

2

Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the Absolute Maximum Ratings.

3

The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.

5

t

propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. t

DLH

delay is measured from the input falling logic low threshold, V
delay parameters.

6

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions. See Figure 18 for waveforms of propagation delay parameters.

7

Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

DD1

and V

supply currents as a function of data rate.

DD2

DLH

1.2 1.5 mA

DDI(Q)

4.7 10 mA

DDO(Q)

1.4 1.7 mA DC to 1 MHz logic signal frequency

DD1(Q)

11 17 mA DC to 1 MHz logic signal frequency

DD2(Q)

, V

OAH

OAH

, V

OAL

OBL

4.1 4.4 V

DD2UV+

3.2 3.7 V

DD2UV−

DD2UVH

7.0 7.5 V

DD2UV+

6.0 6.5 V

DD2UV−

DD2UVH

, I

OA(SC)

OB(SC)

DLH, tDHL

DLH, tDHL

12 ns CL = 2 nF, V

PSK

1 5 ns CL = 2 nF, V

PSKCD

1 7 ns CL = 2 nF, V

PSKCD

14 22 28 ns CL = 2 nF, V

R/tF

0.05 ns V

DDI(D)

1.5 ns V

DDO(D)

, to the output falling 90% threshold of the VOx signal. See Figure 18 for waveforms of propagation

IL

and/or t

DHL

≤ 5.5 V, 4.5 V ≤ V

DD1

V

DD1

V

− 0.1 V

DD2

DD2

0.0 0.15 V IOx = +20 mA, VIx = V

≤ 18 V, unless stated otherwise. All minimum/

DD2

V

DD1

= 5 V, V

DD1

= 10 V. Switching

DD2

DD1

V IOx = −20 mA, VIx = V

IxH

IxL

0.4 V

0.5 V

2.0 4.0 A V

35 45 60 ns CL = 2 nF, V

36 50 68 ns CL = 2 nF, V

that is measured between units at the same operating temperature, supply voltages, and output

DD2

DD2

DD2

= 10 V

= 10 V
= 10 V

= 10 V

DD2

= 10 V

DD2

= 10 V; see Figure 18

DD2

= 4.5 V; see Figure 18

DD2

= 10 V; see Figure 18

DD2

= 10 V; see Figure 18

DD2

= 4.5 V; see Figure 18

DD2

= 10 V; see Figure 18

DD2

= 4.5 V; see Figure 18

DD2

propagation

DHL

Rev. B| Page 3 of 16

ADuM3220/ADuM3221

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V
maximum specifications apply over T

= −40°C to 125°C. All typical specifications are at TJ = 25°C, V

J

specifications are tested with CMOS signal levels.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, Two Channels, Quiescent I
Output Supply Current, Two Channels,

Quiescent

Total Supply Current, Two Channels1

DC to 1 MHz

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents IIA, IIB −10 +0.01 +10 μA 0 ≤ VIA, VIB ≤ V
Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages V
Logic Low Output Voltages V
Undervoltage Lockout, V

Supply

DD2

ADuM3220A/ADuM3221A

Positive-Going Threshold V
Negative-Going Threshold V
Hysteresis V

ADuM3220B/ADuM3221B

Positive-Going Threshold V
Negative-Going Threshold V
Hysteresis V

Output Short-Circuit Pulsed Current2 I

SWITCHING SPECIFICATIONS

Pulse Width3 PW 50 ns CL = 2 nF, V
Data Rate4 1 MHz CL = 2 nF, V
Propagation Delay5 t

t
Propagation Delay Skew6 t
Channel-to-Channel Matching7 t

t
Output Rise/Fall Time (10% to 90%) tR/tF 14 20 25 ns CL = 2 nF, V

t
Dynamic Input Supply Current per Channel I
Dynamic Output Supply Current per Channel I
Refresh Rate fr 1.1 Mbps

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total V

2

Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the Absolute Maximum Ratings.

3

The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed

4

The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed

5

t

propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. T

DLH

delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 18 for waveforms of propagation
delay parameters.

6

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions. See Figure 18 for waveforms of propagation delay parameters.

7

Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

DD1

and V

supply currents as a function of data rate.

DD2

0.7 1.0 mA

DDI(Q)

I

4.7 10 mA

DDO(Q)

0.8 1.0 mA DC to 1 MHz logic signal frequency

DD1(Q)

11 17 mA DC to 1 MHz logic signal frequency

DD2(Q)

, V

OAH

OAH

, V

OAL

OBL

4.1 4.4 V

DD2UV+

3.2 3.7 V

DD2UV−

DD2UVH

7.0 7.5 V

DD2UV+

6.0 6.5 V

DD2UV−

DD2UVH

,

OA(SC)

I

OB(SC)

36 48 62 ns CL = 2 nF, V

DLH, tDHL

37 53 72 ns CL = 2 nF, V

DLH, tDHL

12 ns CL = 2 nF, V

PSK

1 5 ns CL = 2 nF, V

PSKCD

1 7 ns CL = 2 nF, V

PSKCD

14 22 28 ns CL = 2 nF, V

R/tF

0.025 mA/Mbps V

DDI(D)

1.5 mA/Mbps V

DDO(D)

and/or t

DLH

DHL

≤ 3.6 V, 4.5 V ≤ V

DD1

V

DD1

V

− 0.1 V

DD2

V IOx = −20 mA, VIx = V

DD2

0.0 0.15 V IOx = +20 mA, VIx = V

≤ 18 V, unless stated otherwise. All minimum/

DD2

V

DD1

= 3.3 V, V

DD1

= 10 V. Switching

DD2

DD1

IxH

IxL

0.4 V

0.5 V

2.0 4.0 A V

that is measured between units at the same operating temperature, supply voltages, and output

= 10 V

DD2

= 10 V

DD2

= 10 V

DD2

= 10 V

DD2

= 10 V

DD2

DD2

DD2

DD2

DD2

DD2

DD2

DD2

= 10 V; see Figure 18
= 4.5 V; see Figure 18
= 10 V; see Figure 18
= 10 V; see Figure 18
= 4.5 V; see Figure 18
= 10 V; see Figure 18
= 4.5 V; see Figure 18

propagation

DHL

Rev. B| Page 4 of 16

ADuM3220/ADuM3221

PACKAGE CHARACTERISTICS

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output)1 R
Capacitance (Input-to-Output)1 C
Input Capacitance CI 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θ

IC Junction-to-Case Thermal Resistance, Side 2 θ

1

The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.

REGULATORY INFORMATION

The ADuM3220/ADuM3221 approval is pending by the organizations listed in Tab l e 4 .

Table 4.

UL CSA VDE

Recognized under UL 1577

Component Recognition
Program1

Single/Basic 2500 V rms

Isolation Voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM3220/ADuM3221 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection

limit = 5 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM3220/ADuM3221 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial

discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1,
400 V rms (566 V peak) maximum working voltage

Functional insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage

1012 Ω

I-O

1.0 pF f = 1 MHz

I-O

46 °C/W

JCI

Thermocouple located at center
of package underside

41 °C/W

JCO

Thermocouple located at center
of package underside

Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-12

Reinforced insulation, 560 V peak

2

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 5.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 4.90 min mm

Minimum External Tracking (Creepage) L(I02) 4.01 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Measured from input terminals to output terminals,
shortest distance through air

Measured from input terminals to output terminals,
shortest distance path along body

Rev. B| Page 5 of 16

ADuM3220/ADuM3221

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V

Table 6.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤150 V rms I to IV
For Rated Mains Voltage ≤300 V rms I to III
For Rated Mains Voltage ≤400 V rms I to II

Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage V
Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

2

IORM

V

PR

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

After Environmental Tests Subgroup 1 896 V peak

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

After Input and/or Safety Test Subgroup 2

V

IORM

and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 4000 V peak
Safety-Limiting Values

Maximum value allowed in the event of a failure

(see Figure 3)
Case Temperature TS 150 °C
Side 1 Current IS1 160 mA
Side 2 Current IS2 47 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

200

180

160

140

120

100

80

60

SIDE 2

40

SAFETY- LIMIT ING CURRENT (mA)

20

0

0

Figure 3. Thermal Derating Curve; Dependence of Safety-Limiting

Values on Case Temperature, per DIN V VDE V 0884-10. Safety-limiting

current is defined as the average current at maximum V

SIDE 1

50 100 150 200

CASE TEMPERATURE (°C)

.

DD

08994-002

RECOMMENDED OPERATING CONDITIONS

Table 7.

Parameter Symbol Min Max Unit

Operating Junction

Temperature

Supply Voltages1 V

V

V

Rise Time T

DD1

Common-Mode Transient

Immunity, Input to Output

Input Signal Rise and Fall Times 1 ms

1

All voltages are relative to their respective ground. See the DC Correctness

and Magnetic Field Immunity section for information on immunity to external
magnetic fields.

peak working voltage.

560 V peak

1050 V peak

−40 +125 °C

T

J

3.0 5.5 V

DD1

4.5 18 V

DD2

1 V/μs

VDD1

−25 +25 kV/μs

Rev. B| Page 6 of 16

ADuM3220/ADuM3221

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 8.

Parameter Symbol Rating

Storage Temperature TST −55°C to +150°C
Operating Temperature TJ −40°C to +150°C
Supply Voltage Ranges1 V
V
Input Voltage Range
Output Voltage Range
Average Output Current,

per Pin

3

1, 2

V

1, 2

VOA, VOB −0.5 V to V

−0.5 V to +7.0 V

DD1

−0.5 V to +27 V

DD2

, VIB −0.5 V to V

IA

I

−23 mA to +23 mA

O

+ 0.5 V

DDI

+ 0.5 V

DDO

Common-Mode Transients4 CMH, CML −100 kV/μs to +100 kV/μs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively.

3

See Figure 3 for information on maximum allowable current for various

temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the Absolute Maximum Rating can cause
latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 9. Maximum Continuous Working Voltage

Parameter Max Unit Constraint

AC Bipolar Voltage2 565 V peak 50-year minimum lifetime
AC Unipolar Voltage3
Functional Insulation 1131 V peak Maximum approved working

voltage per IEC 60950-1

Basic Insulation 560 V peak Maximum approved working

voltage per IEC 60950-1 and

VDE V 0884-10
DC Voltage4
Functional Insulation 1131 V peak Maximum approved working

voltage per IEC 60950-1
Basic Insulation 560 V peak Maximum approved working

voltage per IEC 60950-1 and

VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

2

See Figure 22.

3

See Figure 23.

4

See Figure 24.

ESD CAUTION

1

Rev. B| Page 7 of 16

ADuM3220/ADuM3221

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

GND

DD1

V

V

IA

IB

1

1

ADuM3220/

2

ADuM3221

3

TOP VIEW

(Not to Scale)

4

V

8

DD2

V

7

OA

6

V

OB

5

GND

2

08994-003

Figure 4. Pin Configuration

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.

DD1

2 VIA Logic Input A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground reference for Isolator Side 1.
5 GND2 Ground 2. Ground reference for Isolator Side 2.
6 VOB Logic Output B.
7 VOA Logic Output A.
8 V

Supply Voltage for Isolator Side 2, 4.5 V to 18 V.

DD2

Table 11. Truth Table ADuM3220 (Positive Logic)

VIA Input VIB Input V

State V

DD1

DD2

1

State VOA Output VOB Output Notes

L L Powered Powered L L
L H Powered Powered L H
H L Powered Powered H L
H H Powered Powered L L
X X Unpowered Powered L L

X X Powered Unpowered Indeterminate Indeterminate

1

X = don’t care, L = low, H = high.

Outputs return to the input state within
1 μs of V

power restoration.

DD1

Outputs return to the input state within
1 μs of V

power restoration.

DD2

Table 12. Truth Table ADuM3221 (Positive Logic)1

VIA Input VIB Input V

State V

DD1

State VOA Output VOB Output Notes

DD2

L L Powered Powered L L
L H Powered Powered L H
H L Powered Powered H L
H H Powered Powered H H
X X Unpowered Powered L L

X X Powered Unpowered Indeterminate Indeterminate

1

X = don’t care, L = low, H = high.

Rev. B| Page 8 of 16

Outputs return to the input state within
1 μs of V

power restoration.

DD1

Outputs return to the input state within
1 μs of V

power restoration.

DD2

ADuM3220/ADuM3221

TYPICAL PERFORMANCE CHARACTERISTICS

300

250

CH2 = VO (2V/DIV)

200

150

V

= 15V

DD2

V

= 10V

DD2

V

= 8V

DD2

V

= 5V

DD2

2

1

CH1 5V CH2 2V M40ns 2.5GSPS

CH1 = VI (5V/DIV)

ΩΩ

T 22.2%

10k POINTS

CH2 7.2V

Figure 5. Output Waveform for 2 nF Load with 10 V Output Supply

CH2 = VO (2V/DIV)

2

1

CH1 5V CH2 2V M40ns 2.5GSP S

CH1 = VI (5V/DIV)

ΩΩ

T 21.4%

10k POINTS

CH2 7.2V

Figure 6. Output Waveform for 1 nF Load with 10 V Output Supply

100

GATE CHARGE (nC)

50

0

08994-004

8994-005

0 200 400 600 800 1000

SWITCHI NG FREQ UENCY (kHz)

Figure 8. Typical Maximum Load vs. Switching Frequency (R

2.0

1.5

V

= 5V

1.0

CURRENT (mA)

DD1

I

0.5

0

0 0.25 0.50 0.75 1.00

Figure 9. Typical I

DD1

V

= 3.3V

DD1

FREQUENCY(MHz)

Supply Current vs. Frequency

DD1

= 1 Ω)

G

08994-107

08994-015

CH2 = VO (2V/DIV)

2

1

CH1 5V CH2 2V M40ns 2.5G SPS

CH1 = VI (5V/DIV)

ΩΩ

T 22.1%

10k POINTS

CH2 7.2V

8994-006

Figure 7. Output Waveform for 1 nF Load with 5 Ω Series Resistance and

10 V Output Supply

Rev. B| Page 9 of 16

80

70

60

50

40

CURRENT (mA)

30

DD2

I

20

10

0

0

Figure 10. Typical I

V

= 15V

DD2

= 10V

V

DD2

V

= 5V

DD2

0.25 0.50 0.75 1.00

FREQUENCY(MHz)

Supply Current vs. Frequency with 2 nF Load

DD2

08994-016

ADuM3220/ADuM3221

G
A

A

G
A

A

G
A

A

60

30

50

Y (ns)

40

30

TION DEL

20

PROPA

10

0

–40 –20 0 20 40 60 80 100 120 140

JUNCTION TE MPERATURE (°C)

Figure 11. Typical Propagation Delay vs. Temperature

60

50

40

30

20

PROPAGATI ON DELAY (n s)

10

0

3.0 3.5 4.0 4. 5 5.0 5.5

INPUT SUPPLY VOLTAGE (V)

t

PHL

t

PLH

Figure 12. Typical Propagation Delay vs. Input Supply Voltage, V

DD2

8994-017

08994-018

= 10 V

25

20

15

10

RISE/FALL TIME (ns)

5

0

5 7 9 11131517

FALL TIME

RISE TIME

OUTPUT SUPPLY VOLTAGE (V)

08994-020

Figure 14. Typical Rise/Fall Time Variation vs. Output Supply Voltage

5

4

3

2

MATCHING (n s)

PD MATCH

1

PD MATCH

PROPAGATI ON DELAY CHANNEL- TO-CHANNEL

0

5 7 9 11 13 15 17

OUTPUT SUPPLY VOLTAGE (V)

t

t

DLH

DHL

08994-021

Figure 15. Typical Propagation Delay Channel-to-Channel Matching vs.

Output Supply Voltage

60

t

50

Y (ns)

40

30

TION DEL

20

PROPA

10

0

5 7 9 11 13 15 17

OUTPUT SUPPLY VOLTAGE (V)

PHL

t

PLH

Figure 13. Typical Propagation Delay vs. Output Supply Voltage, V

08994-019

= 5 V

DD1

Rev. B| Page 10 of 16

5

4

3

Y CHANNEL-TO-CHANNE L

2

MATCHING ( ns)

TION DEL

1

PROPA

0

–40 –20 0 20 40 60 80 100 120 140

JUNCTION TEMPERATURE (°C)

PD MATCH t

PD MATCH t

DLH

DHL

08994-022

Figure 16. Typical Propagation Delay Channel-to-Channel Matching vs.

Temperature, V

DD2

= 10 V

ADuM3220/ADuM3221

G

O

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM3220/ADuM3221 digital isolators require no exter­nal interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as
shown in Figure 17. Use a small ceramic capacitor with a value
between 0.01 μF and 0.1 μF to provide a good high frequency
bypass. On the output power supply pin, V

, it is recommended

DD2

to also add a 10 μF capacitor to provide the charge required to
drive the gate capacitance at the ADuM3220/ADuM3221
outputs. On the output supply pin, the bypass capacitor use of
vias should be avoided or multiple vias should be employed to
reduce the inductance in the bypassing. The total lead length
between both ends of the smaller capacitor and the input or
output power supply pin should not exceed 20 mm.

V

DD1

V

IA

V

ND

IB

1

Figure 17. Recommended PCB Layout

V

OA

V

OB

V

DD2

GND

2

08994-023

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output. The ADuM3220/ADuM3221 specify t
(see Figure 18) as the time between the rising input high logic
threshold, V
falling propagation delay, t
the input falling logic low threshold, V

, to the output rising 10% threshold. Likewise, the

IH

, is defined as the time between

DHL

, and the output falling

IL

90% threshold. The rise and fall times are dependent on the
loading conditions and are not included in the propagation
delay, as is the industry standard for gate drivers.

90%

UTPUT

10%

DLH

THERMAL LIMITATIONS AND SWITCH LOAD CHARACTERISTICS

For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the part, and heat is, therefore, dissipated mainly
through the package pins.

Package thermal dissipation limits the performance of switching
frequency vs. output load, as illustrated in Figure 8, for the maxi­mum load capacitance that can be driven with a 1 Ω series gate
resistance for different values of output voltage. For example,
this curve shows that a typical ADuM3220/ADuM3221 can
drive a large MOSFET with 120 nC gate charge at 8 V output
(which is equivalent to a 15 nF load) up to a frequency of about
300 kHz.

OUTPUT LOAD CHARACTERISTICS

The ADuM3220/ADuM3221 output signals depend on the
characteristics of the output load, which is typically an N-channel
MOSFET. The driver output response to an N-channel MOSFET
load can be modeled with a switch output resistance (R
inductance due to the printed circuit board trace (L
gate resistor (R

), and a gate to source capacitance (Cgs), as

GATE

TRACE

shown in Figure 19.

R

is the switch resistance of the internal ADuM3220/ADuM3221

SW

driver output, which is about 1.5 Ω. R

is the intrinsic gate

GATE

resistance of the MOSFET and any external series resistance. A
MOSFET that requires a 4 A gate driver has a typical intrinsic
gate resistance of about 1 Ω and a gate-to-source capacitance,
C

, of between 2 nF and 10 nF. L

GS

is the inductance of the

TRACE

printed circuit board trace, typically a value of 5 nH or less for a
well-designed layout with a very short and wide connection from
the ADuM3220/ADuM3221 output to the gate of the MOSFET.

The following equation defines the Q factor of the RLC circuit,
which indicates how the ADuM3220/ADuM3221 output responds
to a step change. For a well-damped output, Q is less than one.
Adding a series gate resistance dampens the output response.

), an

SW

), a series

V

INPUT

IH

V

IL

t

t

DLH

t

R

Figure 18. Propagation Delay Parameters

DHL

t

F

08994-007

Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3220/ADuM3221 component.

Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3220/
ADuM3221 components operating under the same conditions.

SW

1

RR

+

GATE

Q ×

=

In Figure 5 and Figure 6, the ADuM3220/ADuM3221 output
waveforms for 10 V output are shown for a C
respectively. Note the ringing of the output in Figure 6 with C
of 1 nF and a calculated Q factor of 1.5, where less than one is
desired for good damping.

Output ringing can be reduced by adding a series gate resistance
to dampen the response. For applications using a 1 nF or less
load, it is recommended to add a series gate resistor of about
5 Ω. As shown in Figure 7, R
Q-factor of about 0.3, and illustrates a damped response in
comparison with Figure 6.

L

TRACE

C

)(

GS

GS

is 5 Ω, which yields a calculated

GATE

of 2 nF and 1 nF,

GS

Rev. B| Page 11 of 16

ADuM3220/ADuM3221

V

IA

ADuM3220/

ADuM3221

R

V

OA

R

SW

L

TRACE

GATE

V

O

C

GS

08994-118

Figure 19. RLC Model of the Gate of an N-Channel MOSFET

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions of more than 1 μs at the input, a periodic set of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output.

If the decoder receives no internal pulses for more than about
3 μs, the input side is assumed to be unpowered or nonfunc­tional, in which case, the isolator output is forced to a default
low state by the watchdog timer circuit. In addition, the outputs
are in a low default state while the power is coming up before
the UVLO threshold is crossed.

The ADuM3220/ADuM3221 is immune to external magnetic
fields. The limitation on the ADuM3220/ADuM3221 magnetic
field immunity is set by the condition in which induced voltage
in the transformer receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM3220/ADuM3221 is examined because
it represents the most susceptible mode of operation. The pulses
at the transformer output have an amplitude greater than 1.0 V.
The decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by

2

V = (−dβ/dt) ∑π r

where:

β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.

is the radius of the nth turn in the receiving coil (cm).

r

n

Given the geometry of the receiving coil in the ADuM3220/
ADuM3221 and an imposed requirement that the induced
voltage is at most 50% of the 0.5 V margin at the decoder, a
maximum allowable magnetic field is calculated, as shown in
Figure 20.

, n = 1, 2, ... , N

n

100

10

1

0.1

DENSITY (kg auss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001
1k 10k 10M

MAGNETIC FIELD FREQ UENCY (Hz)

1M

100M100k

08994-009

Figure 20. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maxi­mum allowable magnetic field of 0.2 kgauss induces a voltage
of 0.25 V at the receiving coil. This is about 50% of the sensing
threshold and does not cause a faulty output transition. Simi­larly, if such an event were to occur during a transmitted pulse
(and had the worst-case polarity), the received pulse is reduced
from >1.0 V to 0.75 V, still well above the 0.5 V sensing thresh­old of the decoder.

The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM3220/ADuM3221 transformers. Figure 21 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown, the ADuM3220/ADuM3221
are immune and only can be affected by extremely large currents
operated at a high frequency and very close to the component.
For the 1 MHz example, a 0.5 kA current needs to be placed
5 mm away from the ADuM3220/ADuM3221 to affect the
component’s operation.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALL OWABLE CURRENT (kA)

Rev. B| Page 12 of 16

0.01
1k 10k 100M100k 1M 10M

MAGNETIC F IELD FRE QUENCY (Hz)

Figure 21. Maximum Allowable Current for Various

Current-to-ADuM3220/ADuM3221 Spacings

08994-010

ADuM3220/ADuM3221

POWER CONSUMPTION

The supply current at a given channel of the ADuM3220/
ADuM3221 isolator is a function of the supply voltage,
channel data rate, and channel output load.

For each input channel, the supply current is given by

= I

I

DDI

DDI(Q)

I

DDI

= I

× (2f – fr) + I

DDI(D)

DDI(Q)

f ≤ 0.5fr

f > 0.5fr

For each output channel, the supply current is given by

I

I

DDO

DDO

= I

= (I

f ≤ 0.5fr

DDO(Q)

+ (0.5) × CLV

DDO(D)

) × (2f – fr) + I

DDO

DDO(Q)

f > 0.5fr

where:

, I

I

DDI(D)

are the input and output dynamic supply currents

DDO(D)

per channel (mA/Mbps).

is the output load capacitance (pF).

C

L

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

is the input stage refresh rate (Mbps).

f

r

, I

I

DDI(Q)

are the specified input and output quiescent supply

DDO(Q)

currents (mA).

To calculate the total I

DD1

and I

supply current, the supply

DD2

currents for each input and output channel corresponding to
I

and I

DD1

Figure 9 provides total input I
of data rate for both input channels. Figure 10 provides total I

are calculated and totaled.

DD2

DD1

supply current as a function

DD2

supply current as a function of data rate for both outputs loaded
with 2 nF capacitance.

INSULATION LIFETIME

All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insu­lation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM3220/
ADuM3221.

Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel­eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.

The values shown in Tabl e 9 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM3220/ADuM3221 depends
on the voltage waveform type imposed across the isolation
barrier. The iCoupler insulation structure degrades at different
rates depending on whether the waveform is bipolar ac, unipo­lar ac, or dc. Figure 22, Figure 23, and Figure 24 illustrate these
different isolation voltage waveforms.

A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 50-year operating lifetime that
Analog Devices recommends for maximum working voltage. In
the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. Any cross­insulation voltage waveform that does not conform to Figure 23
or Figure 24 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Tabl e 9.

Note that the voltage presented in Figure 23 is shown as sinu­soidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.

RATED PEAK VOLTAGE

0V

Figure 22. Bipolar AC Waveform

08994-011

RATED PEAK VOLTAGE

0V

Figure 23. Unipolar AC Waveform

08994-012

RATED PEAK VOLTAGE

0V

Figure 24. DC Waveform

08994-013

Rev. B| Page 13 of 16

ADuM3220/ADuM3221

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 25. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Minimum
V

DD2

Operating
Voltage (V)

Model1

No. of
Inputs,
V

Side

DD1

Maximum
Data Rate
(MHz)

Maximum
Propagation
Delay, 5 V (ns)

ADuM3220ARZ 2 1 60 4.5 Yes −40°C to 125°C 8-Lead SOIC_N R-8
ADuM3220ARZ-RL7 2 1 60 4.5 Yes −40°C to 125°C 8-Lead SOIC_N R-8
ADuM3220BRZ 2 1 60 7.6 Yes −40°C to 125°C 8-Lead SOIC_N R-8
ADuM3220BRZ-RL7 2 1 60 7.6 Yes −40°C to 125°C 8-Lead SOIC_N R-8
ADuM3221ARZ 2 1 60 4.5 No −40°C to 125°C 8-Lead SOIC_N R-8
ADuM3221ARZ-RL7 2 1 60 4.5 No −40°C to 125°C 8-Lead SOIC_N R-8
ADuM3221BRZ 2 1 60 7.6 No −40°C to 125°C 8-Lead SOIC_N R-8
ADuM3221BRZ-RL7 2 1 60 7.6 No −40°C to 125°C 8-Lead SOIC_N R-8

1

Z = RoHS Compliant Part.

Output Shoot­Through
Protection
(Yes/No)

Junction
Temperature
Range

Package
Description

Package
Option

Rev. B| Page 14 of 16

ADuM3220/ADuM3221

NOTES

Rev. B| Page 15 of 16

ADuM3220/ADuM3221

NOTES

©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08994-0-3/11(B)

Rev. B| Page 16 of 16