Datasheet ADuM2210 Datasheet (ANALOG DEVICES)

Dual-Channel Digital Isolators, 5 kV

Data Sheet

FEATURES

High isolation voltage: 5000 V rms Enhanced system-level ESD performance per IEC 61000-4-x Low power operation

5 V operation

1.6 mA per channel maximum at 0 Mbps to 2 Mbps

3.7 mA per channel maximum at 10 Mbps

3 V operation

1.4 mA per channel maximum at 0 Mbps to 2 Mbps

2.4 mA per channel maximum at 10 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C Default low output High data rate: dc to 10 Mbps (NRZ) Precise timing characteristics

3 ns maximum pulse width distortion

3 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs 16-lead SOIC wide body package version (RW-16) 16-lead SOIC wide body enhanced creepage version (RI-16)

Safety and regulatory approvals (RI-16 package)

UL recognition: 5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

IEC 60601-1: 250 V rms (reinforced) IEC 60950-1: 400 V rms (reinforced)

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V

= 846 V peak

IORM

APPLICATIONS

General-purpose, high voltage, multichannel isolation Medical equipment Power supplies RS-232/RS-422/RS-485 transceiver isolation

GENERAL DESCRIPTION

The ADuM221x1 are 2-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics that are superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. Typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature

ADuM2210/ADuM2211

FUNCTIONAL BLOCK DIAGRAMS

1

GND

V

GND

NC

DD1

V V

NC

PIN 1

1

INDICATOR

2

3

4

IA

5

IB

6

7

1

8

NC = NO CONNECT

ENCODE

ADuM2210

DECODE

Figure 1. ADuM2210

1

GND

V

GND

NC

DD1

OA

V NC

NC

PIN 1

1

INDICATOR

2

3

4

5

IB

6

7

1

8

NC = NO CONNECT

DECODE

ENCODE

ADuM2211

ENCODE

DECODE

Figure 2. ADuM2211

and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices run at one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM221x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). The ADuM221x models operate with the supply voltage of either side ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. The ADuM221x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

Similar to the ADuM320x isolators, the ADuM221x isolators contain various circuit and layout enhancements to provide increased capability relative to system-level IEC 61000-4-x testing (ESD, burst, and surge). The precise capability in these tests for either the ADuM320x or ADuM221x products is strongly determined by the design and layout of the user’s board or module. For more information, see the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products.

16

GND

2

15

NC

14

V

DD2

13

V

OA

12

V

OB

11

NC

10

NC

9

GND

2

09233-001

16

GND

2

15

NC

14

V

DD2

13

V

IA

12

V

OB

11

NC

10

NC

9

GND

2

09233-002

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents pending.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuM2210/ADuM2211 Data Sheet

REVISION HISTORY

2/12—Rev. A to Rev. B

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section................................................................. 1

Change to PCB Layout Section..................................................... 16

Updated Outline Dimensions....................................................... 19

8/11—Rev. 0 to Rev. A

Added 16-Lead SOIC_IC Package ................................... Universal

Changes to Features Section............................................................ 1

Changes to Table 5 and Table 6..................................................... 10

Changes to Endnote 1, Table 8...................................................... 11

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide.......................................................... 20

9/10—Revision 0: Initial Version

Rev. B | Page 2 of 20

Data Sheet ADuM2210/ADuM2211

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

Output Supply Current, per Channel, Quiescent I

0.4 0.8 mA

DDI (Q)

DDO (Q)

ADuM2210, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (TR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

ADuM2211, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (TR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

For All Models

Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ V Logic High Input Threshold VIH

Logic Low Input Threshold VIL

Logic High Output Voltages V

V

Logic Low Output Voltages V

V

OAH

OBH

0.0 0.1 V IOx = 20 μA, VIx = V

OAL

0.04 0.1 V IOx = 400 μA, VIx = V

OBL

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM221xSR

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

, t

PHL

PLH

100 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications

DD2

= 25°C, V

A

DD1

= V

DD2

= 5 V.

0.5 0.6 mA

1.3 1.7 mA

DC to 1 MHz logic signal frequency

1.0 1.6 mA

DC to 1 MHz logic signal frequency

3.5 4.6 mA 5 MHz logic signal frequency

1.7 2.8 mA 5 MHz logic signal frequency

1.1 1.5 mA

DC to 1 MHz logic signal frequency

1.3 1.8 mA

DC to 1 MHz logic signal frequency

2.6 3.4 mA 5 MHz logic signal frequency

3.1 4.0 mA 5 MHz logic signal frequency

or V

DD2

IxH

0.7 (V or V

(V

DD1

V

DD2

or

) −

V

DD1

)

V

0.3 (V

DD1

)

or V

DD2

5.0 V I

= −20 μA, VIx = V

Ox

DD1

0.1 (V

V

DD2

DD1

or

) −

4.8 V I

= −4 mA, VIx = V

Ox

IxH

0.5

IxL

20 150 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 3 of 20

ADuM2210/ADuM2211 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM221xTR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

For All Models

Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current, per Channel8 I Output Dynamic Supply Current, per Channel8 I

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

and I

DD1

supply currents as a function of data rate for ADuM2210 and ADuM2211 channel configurations.

DD2

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

PHL

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for

information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

, t

20 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

15 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

17 ns CL = 15 pF, CMOS signal levels

PSKOD

| 25 35 kV/μs

|CM

H

= V

V

or V

Ix

DD1

transient magnitude = 800 V

| 25 35 kV/μs

|CM

L

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

0.19 mA/Mbps

DDI (D)

0.05 mA/Mbps

DDO (D)

propagation delay is

PLH

and/or t

that is measured between units at the same operating temperature, supply voltages, and output

PLH

. CML is the maximum common-mode voltage slew rate

DD2

, VCM = 1000 V,

DD2

Rev. B | Page 4 of 20

Data Sheet ADuM2210/ADuM2211

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

Output Supply Current, per Channel, Quiescent I

DDI (Q)

DDO (Q)

ADuM2210, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (TR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

ADuM2211, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (TR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

For All Models

Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ V Logic High Input Threshold VIH

Logic Low Input Threshold VIL

Logic High Output Voltages V

V

Logic Low Output Voltages V

V

OAH

OBH

OAL

OBL

0.2 0.42 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM221xSR

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

, t

PHL

100 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.3 0.5 mA

0.8 1.3 mA

DC to 1 MHz logic signal frequency

0.7 1.0 mA

DC to 1 MHz logic signal frequency

2.0 3.2 mA 5 MHz logic signal frequency

1.1 1.7 mA 5 MHz logic signal frequency

0.7 1.3 mA

DC to 1 MHz logic signal frequency

0.8 1.6 mA

DC to 1 MHz logic signal frequency

1.5 2.1 mA 5 MHz logic signal frequency

1.9 2.4 mA 5 MHz logic signal frequency

or V

DD1

V

0.7 (V

DD1

)

or V

DD2

V

0.3 (V

DD1

)

or V

DD2

(V V

DD2

DD1

) −

3.0 V IOx = −20 μA, VIx = V

or

IxH

0.1 (V

V

DD2

DD1

) −

2.8 V I

or

= −4 mA, VIx = V

Ox

IxH

0.5

0.0 0.1 V IOx = 20 μA, VIx = V

0.04 0.1 V IOx = 400 μA, VIx = V

20 150 ns CL = 15 pF, CMOS signal levels

PLH

IxL

50 ns CL = 15 pF, CMOS signal levels

DD2

Rev. B | Page 5 of 20

ADuM2210/ADuM2211 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM221xTR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

−t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PLH

PHL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels

For All Models

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current, per Channel8 I Output Dynamic Supply Current, per

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See Figure 6 for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.

8

Channel

through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

DD1

Figure 8

and I

supply currents as a function of data rate for ADuM2210 and ADuM2211 channel configurations.

DD2

PHL

, t

20 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

22 ns CL = 15 pF, CMOS signal levels

PSKOD

| 25 35 kV/μs

|CM

H

= V

V

or V

Ix

DD1

DD2

transient magnitude = 800 V

| 25 35 kV/μs

|CM

L

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

0.10 mA/Mbps

DDI (D)

I

0.03 mA/Mbps

DDO (D)

Power Consumption

Figure 9 Figure 11

propagation delay is

PLH

and/or t

that is measured between units at the same operating temperature, supply voltages, and output

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Figure 8

Power Consumption

, VCM = 1000 V,

Rev. B | Page 6 of 20

Data Sheet ADuM2210/ADuM2211

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

≤ 3.6 V, 4.5 V ≤ V

≤ V

DD1

otherwise noted. All typical specifications are at T

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless

DD2

= 25°C; V

A

= 3.0 V, V

DD1

DD2

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

DDI (Q)

5 V/3 V Operation 0.4 0.8 mA 3 V/5 V Operation 0.3 0.5 mA

Output Supply Current, per Channel, Quiescent I

DDO (Q)

5 V/3 V Operation 0.3 0.5 mA 3 V/5 V Operation 0.5 0.6 mA

ADuM2210, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 1.3 1.7 mA

3 V/5 V Operation 0.8 1.3 mA

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.7 1.0 mA

3 V/5 V Operation 1.0 1.6 mA

10 Mbps (TR Grade Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 3.5 4.6 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.0 3.2 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 1.1 1.7 mA 5 MHz logic signal frequency 3 V/5 V Operation 1.7 2.8 mA 5 MHz logic signal frequency

ADuM2211, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 1.1 1.5 mA

3 V/5 V Operation 0.7 1.3 mA

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.8 1.6 mA

3 V/5 V Operation 1.3 1.8 mA

10 Mbps (TR Grade Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 2.6 3.4 mA 5 MHz logic signal frequency 3 V/5 V Operation 1.5 2.1 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 1.9 2.4 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.1 4.0 mA 5 MHz logic signal frequency

≤ 5.5 V, 3.0 V ≤ V

DD1

= 5 V; or V

= 5 V, V

DD1

≤ 3.6 V. 3 V/5 V operation: 3.0 V

DD2

= 3.0 V.

DD2

DC to 1 MHz logic signal frequency

Rev. B | Page 7 of 20

ADuM2210/ADuM2211 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ V Logic High Input Threshold VIH

0.7 (V or V

DD2

Logic Low Input Threshold VIL

Logic High Output Voltages V

Logic Low Output Voltages V

, V

OAH

OAL

OBH

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OBL

(V V

DD1

DD2

DD1

DD2

or

) − 0.1

or

) − 0.5

V

DD1

)

V

)

DD2

V I

(V V

DD1

DD2

DD1

DD2

0.3 (V

DD1

or V V I

or

)

or

) − 0.2

= −20 μA, VIx = V

Ox

= −4 mA, VIx = V

Ox

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.42 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM221xSR

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

, t

15 150 ns CL = 15 pF, CMOS signal levels

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

ADuM221xTR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

, t

15 55 ns CL = 15 pF, CMOS signal levels

PHL

PLH

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing Directional Channels

6

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

22 ns CL = 15 pF, CMOS signal levels

t

PSKOD

Output Rise/Fall Time (10% to 90%) tR/tF

5 V/3 V Operation 3.0 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 2.5 ns CL = 15 pF, CMOS signal levels

5 V/3 V Operation 3.0 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 2.5 ns CL = 15 pF, CMOS signal levels

For All Models

| 25 35 kV/μs

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

|CM

H

| 25 35 kV/μs

|CM

L

= V

V

or V

Ix

DD1

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current,

per Channel

8

I

DDI (D)

5 V/3 V Operation 0.19 mA/Mbps

3 V/5 V Operation 0.10 mA/Mbps

or V

DD1

IxH

IxL

, VCM = 1000 V,

DD2

Rev. B | Page 8 of 20

Data Sheet ADuM2210/ADuM2211

Parameter Symbol Min Typ Max Unit Test Conditions

Output Dynamic Supply Current,

per Channel

8

5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See

through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6 for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.

DD1

Figure 8

and I

supply currents as a function of data rate for ADuM2210 and ADuM2211 channel configurations.

DD2

I

DDO (D)

signal to the 50% level of the rising edge of the VOx signal.

Ix

and/or t

PHL

that is measured between units at the same operating temperature, supply voltages, and output

PLH

Power Consumption

Figure 9 Figure 11

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Figure 8

Rev. B | Page 9 of 20

ADuM2210/ADuM2211 Data Sheet

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output)1 R Capacitance (Input-to-Output)

1

Input Capacitance2 C IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

1

Device considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM221x are approved by the organizations listed in Tabl e 5 . Refer to Ta b le 1 0 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 5.

UL CSA VDE

Recognized under 1577 Component

Recognition Program

1

Single Protection

5000 V rms Isolation Voltage

RW-16 package:

RI-16 package:

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL1577, each ADuM221x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM221x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial discharge detection

limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-07 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage

Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage; reinforced insulation per IEC 60601-1 125 V rms (176 V peak) maximum working voltage

Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage; reinforced insulation per IEC 60601-1 250 V rms (353 V peak) maximum working voltage

1012 Ω

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

33 °C/W

JCI

28 °C/W

JCO

Thermocouple located at center of package underside

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122

Reinforced insulation, 846 V peak

approval.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration Minimum External Air Gap L(I01) 8.0 min mm

Minimum External Tracking (Creepage) RW-16 Package L(I02) 7.7 min mm

Minimum External Tracking (Creepage) RI-16 Package L(I02) 8.3 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. B | Page 10 of 20

Distance measured from input terminals to output terminals, shortest distance through air along the PCB mounting plane, as an aid to PC board layout

Measured from input terminals to output terminals, shortest distance path along body

Data Sheet ADuM2210/ADuM2211

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Note that the asterisk (*) branded on packages denotes DIN V VDE V 0884-10 approval for 846 V peak working voltage.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 300 V rms I to IV For Rated Mains Voltage ≤ 450 V rms I to II

For Rated Mains Voltage ≤ 600 V rms I to II Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A VPR

After Environmental Tests Subgroup 1 V

After Input and/or Safety Test Subgroup 2

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 1375 V peak

IORM

V

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 6000 V peak Safety-Limiting Values

Maximum value allowed in the event of a failure;

see Figure 3 Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

350

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

SIDE 2

SIDE 1

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +125 °C Supply Voltages1 V Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground.

846 V peak

IORM

1590 V peak

V

PR

, V

DD1

3.0 5.5 V

DD2

0

0 50 100 150 200

Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting

Values with Case Temperature per DIN V VDE V 0884-10

CASE TEMPERAT URE ( °C)

09233-003

Rev. B | Page 11 of 20

ADuM2210/ADuM2211 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Rating

Storage Temperature (TST) −65°C to +150°C Ambient Operating Temperature (TA) −40°C to +125°C Supply Voltage (V Input Voltage (VIA, VIB) Output Voltage (VOA, VOB)

, V

)1 −0.5 V to +7.0 V

DD1

DD2

1, 2

−0.5 V to V

1, 2

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current per Pin3

Side 1 (IO1) −18 mA to +18 mA Side 2 (IO2) −22 mA to +22 mA

Common-Mode Transients4 −100 kV/μs to +100 kV/μs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively. See the section. PCB Layout

3

See for maximum rated current values for various temperatures. Figure 3

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the Absolute Maximum Rating can cause latchup or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Table 10. Maximum Continuous Working Voltage

1

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform

Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

DC Voltage

Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the section for more details. Insulation Lifetime

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Table 11. ADuM2210 Truth Table (Positive Logic)

VIA Input VIB Input V

State V

DD1

State VOA Output VOB Output Notes

DD2

H H Powered Powered H H L L Powered Powered L L H L Powered Powered H L L H Powered Powered L H X X Unpowered Powered L L

X X Powered Unpowered Indeterminate Indeterminate

Table 12. ADuM2211 Truth Table (Positive Logic)

VIA Input VIB Input V

State V

DD1

State VOA Output VOB Output Notes

DD2

H H Powered Powered H H L L Powered Powered L L H L Powered Powered H L L H Powered Powered L H X X Unpowered Powered Indeterminate L

X X Powered Unpowered L Indeterminate

Outputs return to the input state within 1 μs of V

power restoration.

DDI

Outputs return to the input state within 1 μs of V

power restoration.

DDO

Outputs return to the input state within 1 μs of V

power restoration.

DDI

Outputs return to the input state within 1 μs of V

power restoration.

DDO

Rev. B | Page 12 of 20

Data Sheet ADuM2210/ADuM2211

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

1

NC

2

V

3

DD1

ADuM2210

4

V

IA

TOP VIEW

(Not to S cale)

V

5

IB

NC

6 7

GND

1

NC

8

NC = NO CONNECT

NOTES:

1. PIN 1 AND PIN 7 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND

. PIN 9 AND PIN 16 ARE INTERNALLY CONNECTED, AND

CONNECTING BOTH TO GND

Figure 4. ADuM2210 Pin Configuration

Table 13. ADuM2210 Pin Function Descriptions

Pin No. Mnemonic Description

1 GND

1

Ground 1. Ground reference for Isolator Side 1. 2 NC No internal connection. 3 V 4 V

DD1

IA

Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.

Logic Input A. 5 VIB Logic Input B. 6 NC No internal connection. 7 GND1 Ground 1. Ground reference for Isolator Side 1. 8 NC No internal connection. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 NC No internal connection. 11 NC No internal connection. 12 VOB Logic Output B. 13 VOA Logic Output A. 14 V

Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.

DD2

15 NC No internal connection. 16 GND2 Ground 2. Ground reference for Isolator Side 2.

GND

16

2

NC

15

V

14

DD2

13

V

OA

V

12

OB

NC

11 10

NC GND

9

2

IS RECOMMENDE D.

1

IS RECOMMENDE D.

2

09233-004

Rev. B | Page 13 of 20

ADuM2210/ADuM2211 Data Sheet

2

GND

1

NC

2

V

3

DD1

ADuM2211

4

V

OA

TOP VIEW

(Not to S cale)

V

5

IB

NC

6 7

GND

1

NC

8

NC = NO CONNECT

NOTES:

1. PIN 1 AND PIN 7 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND

. PIN 9 AND PIN 16 ARE INTERNALLY CONNECTED, AND

CONNECTING BOTH TO GND

Figure 5. ADuM2211 Pin Configuration

Table 14. ADuM2211 Pin Function Descriptions

Pin No. Mnemonic Description

1 GND

1

Ground 1. Ground reference for Isolator Side 1. 2 NC No internal connection. 3 V

DD1

Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. 4 VOA Logic Output A. 5 VIB Logic Input B. 6 NC No internal connection. 7 GND1 Ground 1. Ground reference for Isolator Side 1. 8 NC No internal connection. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 NC No internal connection. 11 NC No internal connection. 12 VOB Logic Output B. 13 V 14 V

IA

Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.

DD2

Logic Input A.

15 NC No internal connection. 16 GND2 Ground 2. Ground reference for Isolator Side 2.

GND

16

2

NC

15

V

14

DD2

13

V

IA

V

12

OB

NC

11 10

NC GND

9

2

IS RECOMMENDE D.

1

IS RECOMMENDE D.

2

09233-005

Rev. B | Page 14 of 20

Data Sheet ADuM2210/ADuM2211

TYPICAL PERFORMANCE CHARACTERISTICS

10

20

8

6

4

CURRENT/CHANNEL (mA)

2

0

5V

3V

10 20 30

DATA RATE (Mb ps)

Figure 6. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

4

3

2

5V

1

CURRENT/CHANNEL (mA)

3V

0

10 20 30

DATA RATE (Mb ps)

Figure 7. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

15

10

CURRENT (mA)

5

0

09233-006

0

10 20 30

DATA RATE (Mb ps)

Figure 9. Typical ADuM2210 V

5V

3V

Supply Current vs. Data Rate

DD1

09233-009

for 5 V and 3 V Operation

4

3

5V

2

CURRENT (mA)

1

0

09233-007

10 20 30

DATA RATE (Mb ps)

Figure 10. Typical ADuM2210 V

3V

Supply Current vs. Data Rate

DD2

09233-010

for 5 V and 3 V Operation

4

3

2

1

CURRENT/CHANNEL (mA)

0

5V

3V

10 20 30

DATA RATE (Mb ps)

Figure 8. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

09233-008

Rev. B | Page 15 of 20

10

8

6

4

CURRENT (mA)

2

0

10 20 30

DATA RATE (Mb ps)

Figure 11. Typical ADuM2211 V

for 5 V and 3 V Operation

5V

3V

09233-011

DD1

or V

Supply Current vs. Data Rate

DD2

ADuM2210/ADuM2211 Data Sheet

APPLICATIONS INFORMATION

PCB LAYOUT

The ADuM221x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 12). Bypass capacitors are most conveniently connected between Pin 1 and Pin 3 for V Pin 16 for V

. The capacitor value should be between 0.01 μF

DD2

and between Pin 14 and

DD1

and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 3 and Pin 7 and between Pin 9 and Pin 14 should be considered unless the ground pair on each package side is connected close to the package.

GND

1

NC

V

DD1

VIA/V

OA

V

IB

NC

GND

1

NC

Figure 12. Recommended Printed Circuit Board Layout

GND NC

V

DD2

VOA/V V

OB

NC NC GND

2

IA

2

09233-012

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to logic high.

INPUT (VIx)

OUTPUT (V

t

PLH

)

Ox

Figure 13. Propagation Delay Parameters

t

PHL

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs among channels within a single ADuM221x component.

Propagation delay skew refers to the maximum amount the propagation delay differs among multiple ADuM221x components operated under the same conditions.

50%

09233-013

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than approximately 5 μs, the input side is assumed to be without power or nonfunctional, in which case, the isolator output is forced to a default state (see Tabl e 1 1 and Tabl e 12) by the watchdog timer circuit.

The limitation on the ADuM221x magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM221x is examined because it represents the most susceptibl

e mode of operation.

The puls than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

where:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. r

Given the geometry of the receiving coil in the ADuM221x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 14.

es at the transformer output have an amplitude greater

V = (−dβ/dt)Σπr

is the radius of the nth turn in the receiving coil (cm).

n

100

10

1

0.1

DENSITY ( kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k 10k 10M

Figure 14. Maximum Allowable External Magnetic Flux Density

2

; n = 1, 2,…, N

n

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

09233-014

Rev. B | Page 16 of 20

Data Sheet ADuM2210/ADuM2211

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM221x transformers. Figure 15 expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM221x is immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted previously, one would have to place a 0.5 kA current 5 mm away from the ADuM221x to affect operation of the component.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

0.1

MAXIMUM ALL OWABLE CURRENT ( kA)

0.01 1k 10k 100M100k 1M 10M

DISTANCE = 5mm

MAGNETIC FIELD FREQUENCY (Hz)

Figure 15. Maximum Allowable Current

for Various Current-to-ADuM221x Spacings

09233-015

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM221x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

I

= I

DDI

I

= I

DDI

For each output channel, the supply current is given by

I

DDO

I

DDO

where:

I

, I

DDI (D)

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

f

is the input stage refresh rate (Mbps).

r

, I

I

DDI (Q)

DDO (Q)

supply currents (mA).

To calculate the total I each input and output channel corresponding to I are calculated and totaled. Figure 6 and Figure 7 provide perchannel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 11 provide total I as a function of data rate for ADuM2210/ADuM2211 channel configurations.

f ≤ 0.5fr

DDI (Q)

× (2f − fr) + I

= I

= (I

DDI (D)

f ≤ 0.5fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

DDI (Q)

) × (2f − fr) + I

DDO

are the input and output dynamic supply currents

are the specified input and output quiescent

DD1

and I

, the supply currents for

DD2

DD1

and I

DD1

f > 0.5fr

DDO (Q)

f > 0.5fr

DD2

and I

DD2

Rev. B | Page 17 of 20

ADuM2210/ADuM2211 Data Sheet

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM221x.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than a 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM221x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 16, Figure 17, and Figure 18 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 17 or Figure 18 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10.

Note that the voltage presented in Figure 17 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 16. Bipolar AC Waveform

09233-016

RATED PEAK VOL TAGE

0V

Figure 17. Unipolar AC Waveform

09233-017

RATED PEAK VOL TAGE

0V

Figure 18. DC Waveform

09233-018

Rev. B | Page 18 of 20

Data Sheet ADuM2210/ADuM2211

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

(

5

0

(

5

0

9

5

)

.

0

2

9

8

)

0

.0

1.27 (0.0500)

0.40 (0.0157)

45°

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE INDESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 19. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

13.00 (0.5118)

12.60 (0.4961)

0.51 (0.0201)

0.31 (0.0122)

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

(

5

0

(

5

0

2

9

5

)

.

9

8

)

0

.0

1.27 (0.0500)

0.40 (0.0157)

45°

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

16

1

1.27

(0.0500)

BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETEREQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AC

10-12-2010-A

Figure 20. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]

Wide Body (RI-16-1)

Dimensions shown in millimeters and (inches)

Rev. B | Page 19 of 20

ADuM2210/ADuM2211 Data Sheet

ORDERING GUIDE

Number

1, 2

Model

ADuM2210SRWZ ADuM2210TRWZ ADuM2210SRIZ ADuM2210TRIZ ADuM2211SRWZ ADuM2211TRWZ ADuM2211SRIZ ADuM2211TRIZ

1

Z = RoHS Compliant Part.

2

Tape and reel is available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.

of Inputs, V

DD1

2 0 1 150 40 2 0 10 50 3 2 0 1 150 40 2 0 10 50 3 1 1 1 150 40 1 1 10 50 3 1 1 1 150 40 1 1 10 50 3

Side

Number of Inputs, V

Side

DD2

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse Width Distortion (ns)

Temperature Range

Package Description

Package Option

−40°C to +125°C 16-Lead SOIC_W RW-16

−40°C to +125°C 16-Lead SOIC_IC RI-16-1

−40°C to +125°C 16-Lead SOIC_W RW-16

−40°C to +125°C 16-Lead SOIC_IC RI-16-1

Rev. B | Page 20 of 20

Datasheet ADuM2210 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PCB LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE