Datasheet ADUM1410 Datasheet (ANALOG DEVICES)

Quad-Channel Digital Isolators

Data Sheet

FEATURES

Low power operation

5 V operation

1.3 mA per channel maximum @ 0 Mbps to 2 Mbps

4.0 mA per channel maximum @ 10 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

1.8 mA per channel maximum @ 10 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C Up to 10 Mbps data rate (NRZ) Programmable default output state High common-mode transient immunity: >25 kV/μs 16-lead, RoHS-compliant, SOIC wide body package

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 V

= 560 V peak

IORM

TÜV approval: IEC/EN 60950-1

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation

GENERAL DESCRIPTION

The ADuM141x1 are four-channel digital isolators based on

Analog Devices, Inc. iCoupler® technology. Combining high

s

peed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The usual concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects, are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler

1

Protected by U.S. Patents 5,952,849 6,873,065 and 7,075,329.

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuM1410/ADuM1411/ADuM1412

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

ADuM1410

2

GND

1

3

V

V V

DISABLE

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

ENCODE DECODE

ID

7 8

1

Figure 1. ADuM1410

1

V

DD1

ADuM1411

2

GND

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

7

1

8

1

V

CTRL

GND

V

OD

Figure 2. ADuM1411

1

V

DD1

ADuM1412

2

GND

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

6

DECODE ENCODE

7

1

8

1

V V

CTRL

GND

V

OC

OD

Figure 3. ADuM1412

devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM141x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide) up to 10 Mbps. All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have a default output control pin. This allows the user to define the logic state the outputs are to adopt in the absence of the input power. Unlike other optocoupler alternatives, the ADuM141x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

CTRL

2

9

GND

2

06580-001

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

CTRL

2

9

GND

2

06580-002

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

CTRL

2

9

GND

2

06580-003

ADuM1410/ADuM1411/ADuM1412 Data Sheet

REVISION HISTORY

3/12—Rev. H to Rev. I

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section................................................................. 1

Change to PC Board Layout Section............................................ 19

11/10—Rev. G to Rev. H

Added TÜV Approval to Features Section.................................... 1

Added TÜV Column, Table 5....................................................... 10

6/07—Rev. F to Rev. G

Updated VDE Certification Throughout...................................... 1

Changes to Features and Applications........................................... 1

Changes to DC Specifications in Table 1....................................... 3

Changes to DC Specifications in Table 2....................................... 5

Changes to DC Specifications in Table 3....................................... 7

Changes to Regulatory Information Section .............................. 10

Added Table 10 ...............................................................................12

Added Insulation Lifetime Section .............................................. 21

Absolute Maximum Ratings ......................................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions......................... 13

Typical Performance Characteristics........................................... 17

Applications Information.............................................................. 19

PC Board Layout ........................................................................ 19

Propagation Delay-Related Parameters................................... 19

DC Correctness and Magnetic Field Immunity........................... 19



Power Consumption.................................................................. 20

Insulation Lifetime..................................................................... 20

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22



2/07—Rev. E to Rev. F

Added ADuM1410ARWZ ...............................................Universal

Updated Pin Name CTRL to CTRL

Changes to Ordering Guide.......................................................... 21

10/06—Rev. D to Rev. E

Added ADuM1411 and ADuM1412 ...............................Universal

Deleted ADuM1310 ........................................................... Universal

Changes to Features ..........................................................................1

Changes to Specifications Section...................................................3

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide.......................................................... 20

3/06—Rev. C to Rev. D

Added Note 1 and Changes to Figure 2..........................................1

Changes to Absolute Maximum Ratings..................................... 11

11/05—Revision C: Initial Version

Throughout ........................1

2

Rev. I | Page 2 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel,

Output Supply Current per Channel,

ADuM1410, Total Supply Current,

ADuM1411, Total Supply Current,

ADuM1412, Total Supply Current,

All Models

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.73 mA

I

DDI (Q)

DD1

= V

= 5 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.38 0.53 mA

DDO (Q)

Quiescent

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.4 3.2 mA DC to 1 MHz logic signal frequency

DD1 (Q)

1.2 1.6 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Four Channels

1

8.8 12 mA 5 MHz logic signal frequency

DD1 (10)

2.8 4.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal frequency

DD1 (Q)

1.8 2.4 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

1

Four Channels

5.4 7.6 mA 5 MHz logic signal frequency

DD1 (10)

3.8 5.3 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

2.0 2.6 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

or V

DD1

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages

DD1 (10)

, IIB, IIC,

I

IA

, I

I

ID

I

CTRL2

V

IH

V

IL

V

OAH

V

OCH

V

OAL

V

OCL

CTRL1

, I

, V , V

, I

4.6 6.5 mA 5 MHz logic signal frequency

DD2 (10)

−10 +0.01 +10 µA

,

DISABLE

2.0 V

0.8 V (V

or V

OBH

ODH

OBL

ODL

,

DD1

(V

DD1

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

) − 0.1 5.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

0 V ≤ V 0 V ≤ V 0 V ≤ V

, VIB, VIC, VID ≤ V

IA

, V

CTRL1

CTRL2

≤ V

DISABLE

DD1

≤ V

IxH

IxL

or V

DD2

, ,

DD1

Logic High Output Voltages

IxH

IxL

Rev. I | Page 3 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM141xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM141xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

6

Channel-to-Channel Matching,

Opposing-Directional Channels

All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.2 Mbps Input Enable Time8 t Input Disable Time8 t Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current

per Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See Figure through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 15

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

8

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

DD1

9

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

, t

20 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 30 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

6

| 25 35 kV/µs

|CM

H

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

0.12

I

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V mA/

Mbps

0.04

I

DDO (D)

mA/ Mbps

ower Consumption

propagation delay is

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

Figure 10

Power Consumption

logic state (see Table 14).

2

Figure 8

DD1

11

is set high

Rev. I | Page 4 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel,

Output Supply Current per Channel,

ADuM1410, Total Supply Current,

ADuM1411, Total Supply Current,

ADuM1412, Total Supply Current,

All Models

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.25 0.38 mA

I

DDI (Q)

DD1

= V

= 3.0 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.19 0.33 mA

DDO (Q)

Quiescent

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.6 mA

DD1 (Q)

0.8 1.0 mA

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

1

Four Channels

4.5 6.5 mA 5 MHz logic signal frequency

DD1 (10)

1.4 1.8 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.9 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.9 1.7 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Four Channels

1

3.1 4.5 mA 5 MHz logic signal frequency

DD1 (10)

2.1 3.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.0 1.8 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

or V

DD1

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages

DD1 (10)

, IIB, IIC,

I

IA

, I

I

ID

CTRL1

I

CTRL2

V

IH

V

IL

V

OAH

V

OCH

V

OAL

V

OCL

, I

, V , V

, I

2.6 3.8 mA 5 MHz logic signal frequency

DD2 (10)

−10 +0.01 +10 µA

,

DISABLE

1.6 V

0.4 V (V

or V

OBH

ODH

OBL

ODL

,

DD1

(V

DD1

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

) − 0.1 3.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V I

DC to 1 MHz logic signal frequency

, VIB, VIC, VID ≤ V

0 V ≤ V

IA

0 V ≤ V

CTRL1

0 V ≤ V

DISABLE

= 4 mA, VIx = V

Ox

, V

CTRL2

≤ V

DD1

≤ V

IxH

IxL

DD1

Logic High Output Voltages

IxH

IxL

or V

DD2

, ,

Rev. I | Page 5 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM141xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM141xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.1 Mbps Input Enable Time8 t Input Disable Time8 t Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current

per Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See Figure through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 15

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

8

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

DD1

9

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DISABLE

, t

20 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 40 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 5 ns CL = 15 pF, CMOS signal levels

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

| 25 35 kV/µs

|CM

H

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

0.07

I

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V mA/

DD1

Mbps

0.02

I

DDO (D)

mA/ Mbps

ower Consumption

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

logic state (see Table 14).

2

Power Consumption

Figure 8

Figure 10

11

propagation delay is

PLH

is set high

DISABLE

Rev. I | Page 6 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

5 V/3 V operation: 4.5 V ≤ V minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel,

Quiescent 5 V/3 V Operation 0.50 0.73 mA 3 V/5 V Operation 0.25 0.38 mA

Output Supply Current per Channel,

Quiescent 5 V/3 V Operation 0.19 0.33 mA 3 V/5 V Operation 0.38 0.53 mA

ADuM1410, Total Supply Current,

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.4 3.2 mA

3 V/5 V Operation 1.2 1.6 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.8 1.0 mA

3 V/5 V Operation 1.2 1.6 mA

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 8.6 11 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.4 6.5 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 1.4 1.8 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.6 3.0 mA 5 MHz logic signal frequency

ADuM1411, Total Supply Current,

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA

3 V/5 V Operation 1.0 1.9 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.7 mA

3 V/5 V Operation 1.7 2.4 mA

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 5.4 7.6 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.1 4.5 mA 5 MHz logic signal frequency

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V; or V

DD2

I

DDI (Q)

I

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (Q)

DD2 (Q)

DD1 (10)

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

= 3.0 V. All voltages are relative to their respective ground.

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

DD2

DC to 1 MHz logic signal frequency

≤ 5.5 V; all

Rev. I | Page 7 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

V

Supply Current I

DD2

5 V/3 V Operation 2.1 3.0 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.8 5.3 mA 5 MHz logic signal frequency

ADuM1412, Total Supply Current,

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.0 2.6 mA

3 V/5 V Operation 1.0 1.8 mA

V

Supply Current I

DD2

5 V/3 V Operation 1.0 1.8 mA

3 V/5 V Operation 2.0 2.6 mA

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 4.6 6.5 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.6 3.8 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 2.6 3.8 mA 5 MHz logic signal frequency 3 V/5 V Operation 4.6 6.5 mA 5 MHz logic signal frequency

All Models

Input Currents

Logic High Input Threshold

5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V

Logic Low Output Voltages

SWITCHING SPECIFICATIONS

ADuM141xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t

Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t

Channel-to-Channel Matching6 t

ADuM141xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

DD2 (10)

DD1 (Q)

DC to 1 MHz logic signal frequency

DD2 (Q)

DC to 1 MHz logic signal frequency

DD1 (10)

DD2 (10)

, IIB, IIC, IID,

I

IA

, I

I

CTRL1

I

DISABLE

V

IH

V

IL

, V

V

OAH

, V

V

OCH

, V

V

OAL

, V

V

OCL

, t

PHL

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/OD

, t

PHL

30 ns CL = 15 pF, CMOS signal levels

PSK

−10 +0.01 +10 µA

,

CTRL2

0 V ≤ V 0 V ≤ V 0 V ≤ V

,V

IA

CTRL1

DISABLE

, V

,V

≤ V

IB

IC

ID

,V

≤ V

CTRL2

≤ V

DD1

(V

or V or V

) − 0.1 ( V

DD2

) − 0.4 ( V

DD2

,

OBH

ODH

OBL

ODL

DD1

(V

DD1

0.0 0.1 V IOx = 20 µA, VIx = V

,

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V I

25 70 100 ns CL = 15 pF, CMOS signal levels

PLH

DD1

or V

V IOx = −20 µA, VIx = V

DD2)

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

= 4 mA, VIx = V

Ox

IxH

IxL

50 ns CL = 15 pF, CMOS signal levels

25 35 60 ns CL = 15 pF, CMOS signal levels

PLH

DD1

Logic High Output Voltages

DD1

or V

DD2

,

Rev. I | Page 8 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

Parameter Symbol Min Typ Max Unit Test Conditions

5 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

6

Channel-to-Channel Matching,

Opposing-Directional Channels

All Models

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 2.5 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient

Immunity at Logic High Output

Common-Mode Transient

Immunity at Logic Low Output

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Enable Time8 t Input Disable Time8 t

Input Dynamic Supply Current

per Channel

9

5 V Operation 0.12

3 V Operation 0.07

Output Dynamic Supply Current

per Channel

9

5 V Operation 0.04

3 V Operation 0.02

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See Figure through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 15

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the V

5

t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

8

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

DD1

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

6

= 15 pF, CMOS signal levels

L

| 25 35 kV/µs

|CM

H

7

|CML| 25 35 kV/µs

7

ENABLE

DISABLE

I

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V

mA/

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

= 0 V, VCM = 1000 V, transient

V

Ix

magnitude = 800 V

DD1

Mbps mA/

Mbps

I

DDO (D)

mA/ Mbps

ower Consumption

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

Power Consumption

DD2

Figure 8

Figure 10

11

propagation delay is

PLH

is set high

DISABLE

Rev. I | Page 9 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output)1 R Capacitance (Input-to-Output)

1

Input Capacitance2 C

10

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

IC Junction-to-Case Thermal Resistance

Side 1 θ Side 2 θ

1

The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

33 °C/W

JCI

28 °C/W

JCO

REGULATORY INFORMATION

The ADuM141x have been approved by the organizations listed in Tab l e 5 . See Ta ble 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 5.

UL CSA VDE TÜV

Recognized Under 1577 Component Recognition Program1

Double/reinforced insulation, 2500 V rms isolation voltage

File E214100 File 205078 File 2471900-4880-0001 Certificate B 10 03 56232 006

1

In accordance with UL 1577, each ADuM141x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

2

In accordance with DIN V VDE V 0884-10, each ADuM141x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection

limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage.

Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage.

12

Ω

Thermocouple located at center of package underside

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Approved according to

2

IEC 60950-1:2005 and EN 60950-1:2006

Reinforced insulation, 560 V peak

3000 V rms reinforced isolation at a 400 V rms working voltage. 3000 V rms basic isolation at a 600 V rms working voltage.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 mm min

Minimum External Tracking (Creepage) L(I02) 8.1 mm min

Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. I | Page 10 of 24

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

Data Sheet ADuM1410/ADuM1411/ADuM1412

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

After Environmental Tests Subgroup 1 896 V peak

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

After Input and/or Safety Test Subgroup 2

V

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak Safety-Limiting Values

Maximum value allowed in the event of a failure;

see Figure 4 Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

350

300

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

250

SIDE #2

200

Operating Temperature TA −40 +105 °C Supply Voltages1 V Input Signal Rise and Fall Times 1.0 ms

150

SIDE #1

100

1

All voltages are relative to their respective ground. See the DC Correctness

and Magnetic Field Immunity section for information on immunity to external magnetic fields.

560 V peak

IORM

1050 V peak

V

PR

, V

2.7 5.5 V

DD1

DD2

SAFETY-L IMITING CURRENT (mA)

50

0

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

50 100 150 200

CASE TEMPERAT URE (°C)

06580-007

Rev. I | Page 11 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 9.

Parameter Rating

Storage Temperature (TST) Range −65°C to +150°C Ambient Operating Temperature

) Range

(T

A

Supply Voltages (V Input Voltages (VIA, VIB, VIC, VID, V

, V

V

CTRL2

DISABLE

, V

)1 −0.5 V to +7.0 V

DD1

DD2

1, 2

)

Output Voltages (VOA, VOB, VOC, VOD)

−40°C to +105°C

−0.5 V to V

,

CTRL1

1, 2

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current per Pin3

Side 1 (IO1) −18 mA to +18 mA Side 2 (IO2) −22 mA to +22 mA

Common-Mode Transients4 −100 kV/s to +100 kV/s

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

3

See Figure 4 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Table 10. Maximum Continuous Working Voltage

1

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the section for more details. Insulation Lifetime

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. I | Page 12 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

*

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 2 AND PIN 8 ARE I NTERNALLY CONNECTED. CONNE CTING BOT H

IS RECOMME NDE D. PIN 9 AND PIN 15 ARE INTERNALLY

TO GND

1

CONNECTED. CO NNECTING BOT H TO GND

Table 11. ADuM1410 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND

1

Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended.

3 V

IA

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V

ID

7 DISABLE

8 GND1

Logic Input D.

Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state

determined by CTRL

.

2

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND

recommended. 9 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 10 CTRL2

11 V

OD

Default Output Control. Controls the logic state the outputs assume when the input power is off. V

outputs are high when CTRL2 is high or disconnected and V

V

OD

CTRL

is low and V

2

is off. When V

DD1

Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 16 V

Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

DD2

1

V

DD1

GND1*

2

V

3

IA

ADuM1410

4

V

IB

TOP VIEW

(Not to Scale)

V

5

IC

V

6

ID

DISABLE

GND1*

7 8

Figure 5. ADuM1410 Pin Configuration

power is on, this pin has no effect.

DD1

16

V

DD2

GND2*

15

V

14

OA

13

V

OB

V

12

OC

V

11

OD

CTRL

10

2

9

GND2*

IS RECOMMENDED.

2

DD1

6580-004

is

1

is

2

, VOB, VOC, and

OA

is off. VOA, VOB, VOC, and VOD outputs are low when

is

2

Rev. I | Page 13 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

*PIN 2 AND PIN 8 ARE INTERNALLY CO NNE CTED. CONNECTING BOTH

IS RECOMME NDE D. PIN 9 AND PIN 15 ARE INTERNALLY

TO GND

1

CONNECTED. CO NNE CTING BOT H TO GND

Table 12. ADuM1411 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND

1

Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended.

3 V

IA

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V

OD

7 CTRL1

Logic Output D.

Default Output Control. Controls the logic state the outputs assume when the input power is off. V

when CTRL

is high or disconnected and V

1

power is on, this pin has no effect. 8 GND1

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND

recommended. 9 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 10 CTRL2

Default Output Control. Controls the logic state the outputs assume when the input power is off. V

outputs are high when CTRL

is off. When V

DD1

11 V

low and V

ID

Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 16 V

Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

DD2

1

V

DD1

2

GND1*

V

3

IA

ADuM1411

V

4

IB

TOP VIEW

(Not to Scale)

5

V

IC

V

6

OD

CTRL

7

1

8

GND1*

Figure 6. ADuM1411 Pin Configuration

DD2

is high or disconnected and V

2

power is on, this pin has no effect.

DD1

16

V

DD2

15

GND2* V

14

OA

V

13

OB

12

V

OC

V

11

ID

CTRL

10

2

9

GND2*

IS RECOMMENDED.

2

06580-005

is off. VOD output is low when CTRL1 is low and V

is off. VOA, VOB, and VOC outputs are low when CTRL2 is

DD1

output is high

OD

is off. When V

DD2

, VOB, and VOC

OA

DD2

is

1

is

2

is

2

Rev. I | Page 14 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

*PIN 2 AND PIN 8 ARE INT E RNALLY CONNECTE D. CONNECTING BOTH

IS RECOMM ENDE D. PIN 9 AND PIN 15 ARE INTERNALLY

TO GND

1

CONNECTED. CO NNE CTING BOT H TO GND

Table 13. ADuM1412 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND

1

Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended.

3 V

IA

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 V

OD

7 CTRL1

Logic Output D.

Default Output Control. Controls the logic state the outputs assume when the input power is off. V

outputs are high when CTRL

8 GND1

and V

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND

is off. When V

DD2

power is on, this pin has no effect.

DD2

recommended. 9 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 10 CTRL2

Default Output Control. Controls the logic state the outputs assume when the input power is off. V

outputs are high when CTRL

11 V

and V

ID

Logic Input D.

is off. When V

DD1

power is on, this pin has no effect.

DD1

12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 16 V

Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

DD2

1

V

DD1

GND1*

2

V

3

IA

ADuM1412

4

V

IB

TOP VIEW

(Not to S cale)

V

5

OC

V

6

OD

CTRL

7

1

8

GND1*

Figure 7. ADuM1412 Pin Configuration

is high or disconnected and V

1

is high or disconnected and V

2

16

V

DD2

GND2*

15

V

14

OA

13

V

OB

V

12

IC

V

11

ID

CTRL

10

2

9

GND2*

IS RECOMMENDE D.

2

is off. VOC and VOD outputs are low when CTRL1 is low

DD2

is off. VOA and VOB outputs are low when CTRL2 is low

DD1

6580-006

and VOD

OC

is

1

is

2

and VOB

OA

is

2

Rev. I | Page 15 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Table 14. Truth Table (Positive Logic)

VIx Input1

CTRL Input

H X L or NC Powered Powered H Normal operation, data is high. L X L or NC Powered Powered L Normal operation, data is low. X H or NC H X Powered H

X L H X Powered L

X H or NC X Unpowered Powered H

X L X Unpowered Powered L

X X X Powered Unpowered Z

1

VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).

2

CTRLX refers to the default output control signal on the input side of a given channel (A, B, C, or D).

3

Available only on the ADuM1410.

4

V

refers to the power supply on the input side of a given channel (A, B, C, or D).

DDI

5

V

refers to the power supply on the output side of a given channel (A, B, C, or D).

DDO

V

X

DISABLE

2

State

V

DDI

3

State

4

V

DDO

State

5

V

Ox

Output

1

Description

Inputs disabled. Outputs are in the default state as determined by CTRLX.

Inputs disabled. Outputs are in the default state as determined by CTRL

.

X

Input unpowered. Outputs are in the default state as determined by CTRL Outputs return to input state within 1 µs of V

.

X

power restoration.

DDI

See the pin function descriptions (Tabl e 11, Table 12, and Tabl e 13) for more details.

Input unpowered. Outputs are in the default state as determined by CTRL Outputs return to input state within 1 µs of V

.

X

power restoration.

DDI

See the pin function descriptions (Tabl e 11, Table 12, and Tabl e 13) for more details.

Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 µs of V

power restoration.

DDO

See the pin function descriptions (Tabl e 11, Table 12, and Tabl e 13) for more details.

Rev. I | Page 16 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

10

1.5

1.0

0.5

CURRENT/CHANNEL (mA)

0

268410

5V

3V

DATA RATE (Mb p s)

Figure 8. Typical Supply Current per Input Channel vs. Data Rate

for 5 V and 3 V Operation

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CURRENT/CHANNEL (mA)

0.2

0.1

0

268410

5V

3V

DATA RATE (Mb p s)

Figure 9. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

8

6

4

CURRENT (mA)

2

0

06580-008

26841

Figure 11. Typical ADuM1410 V

5V

3V

DATA RATE (Mb p s)

Supply Current vs. Data Rate

DD1

0

06580-011

for 5 V and 3 V Operation

10

8

6

4

CURRENT (mA)

2

0

06580-009

26841

Figure 12. Typical ADuM1410 V

5V

3V

DATA RATE (Mb p s)

Supply Current vs. Data Rate

DD2

0

06580-012

for 5 V and 3 V Operation

1.4

1.2

1.0

0.8

0.6

0.4

CURRENT/CHANNEL (mA)

0.2

0

26841

5V

3V

0

DATA RATE (Mb p s)

Figure 10. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

06580-010

Rev. I | Page 17 of 24

10

8

6

4

CURRENT (mA)

2

0

26841

DATA RATE (Mb p s)

Figure 13. Typical ADuM1411 V

for 5 V and 3 V Operation

5V

3V

Supply Current vs. Data Rate

DD1

0

06580-013

ADuM1410/ADuM1411/ADuM1412 Data Sheet

10

8

6

4

CURRENT (mA)

2

0

Figure 14. Typical ADuM1411 V

8

6

4

5V

3V

26841

DATA RATE (Mb p s)

Supply Current vs. Data Rate

DD2

0

06580-014

CURRENT (mA)

2

0

Figure 15. Typical ADuM1412 V

for 5 V and 3 V Operation

5V

3V

0

26841

DATA RATE (Mb p s)

or V

DD1

Supply Current vs. Data Rate

DD2

0

06580-015

for 5 V and 3 V Operation

Rev. I | Page 18 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

V

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM141x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V and Pin 16 for V

. The capacitor value should be between

DD2

, and between Pin 15

DD1

0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both ground pins on each package are connected together close to the package.

V

DD1

GND

1

V

IA

V V V

DISABLE

GND

IB IC ID

1

ADuM1410

Figure 16. Recommended Printed Circuit Board Layout

V

DD2

GND V

OA

V

OB

V

OC

V

OD

CTRL GND

2

6580-016

In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition.

INPUT (

)

Ix

OUTPUT (V

t

PLH

)

Ox

t

PHL

Figure 17. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM141x component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM141x components operating under the same conditions.

50%

Rev. I | Page 19 of 24

06580-017

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 14) by the watchdog timer circuit.

The magnetic field immunity of the ADuM141x is determined by the changing magnetic field, which induces a voltage in the transformer’s receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM141x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt) ∑ π r

where: β is magnetic flux density (gauss).

is the radius of the nth turn in the receiving coil (cm).

r

n

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM141x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18.

100

10

1

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FL UX

0.001 1k 10k 10M

Figure 18. Maximum Allowable External Magnetic Flux Density

2

; n = 1, 2, … , N

n

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

06580-018

ADuM1410/ADuM1411/ADuM1412 Data Sheet

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM141x transformers. Figure 19 shows these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM141x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted previously, a 0.5 kA current would have to be placed 5 mm away from the ADuM141x to affect the operation of the component.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALL OWABLE CURRENT ( kA)

0.01 1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 19. Maximum Allowable Current for Various

Current-to-ADuM141x Spacings

06580-019

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM141x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.

For each input channel, the supply current is given by

= I

I

DDI

DDI (Q)

I

DDI

= I

× (2f − fr) + I

DDI (D)

DDI (Q)

f ≤ 0.5 fr

f > 0.5 fr

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

DDO (Q)

f > 0.5 fr

where:

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz); it is half the input

data rate, expressed in units of Mbps.

f

is the input stage refresh rate (Mbps).

r

, I

I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

To calculate the total V

DD1

and V

supply current, the supply

DD2

currents for each input and output channel corresponding to V

DD1

and V

are calculated and totaled. Figure 8 and Figure 9

DD2

show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 shows the per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 show the total V V

supply current as a function of data rate for ADuM1410/

DD2

DD1

and

ADuM1411/ADuM1412 channel configurations.

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM141x.

Rev. I | Page 20 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Tabl e 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM141x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 1 0 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 21 or Figure 22 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 1 0.

Note that the voltage presented in Figure 21 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 20. Bipolar AC Waveform

06580-020

RATED PEAK VOL TAGE

0V

Figure 21. Unipolar AC Waveform

06580-021

RATED PEAK VOL TAGE

0V

Figure 22. DC Waveform

06580-022

Rev. I | Page 21 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

(

5

0

(

0

5

.

0

2

9

5

)

.

0

9

8

)

1.27 (0.0500)

0.40 (0.0157)

45°

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 23. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Inputs,

Model1

V

DD1

ADuM1410ARWZ 4 0 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1410ARWZ-RL 4 0 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1410BRWZ 4 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1410BRWZ-RL 4 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1411ARWZ 3 1 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1411ARWZ-RL 3 1 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1411BRWZ 3 1 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1411BRWZ-RL 3 1 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1412ARWZ 2 2 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1412ARWZ-RL 2 2 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1412BRWZ 2 2 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1412BRWZ-RL 2 2 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16

1

Z = RoHS Compliant Part.

Side

Number of Inputs, V

Side

DD2

Maximum Data Rate

Maximum Propagation Delay, 5 V

Maximum Pulse Width Distortion

Temperature Range

Package Description

Package Option

Rev. I | Page 22 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

NOTES

Rev. I | Page 23 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

NOTES

Rev. I | Page 24 of 24

Datasheet ADUM1410 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE