Datasheet ADUM1310 Datasheet (ANALOG DEVICES)

Triple-Channel Digital Isolators

Data Sheet

FEATURES

Low power operation

5 V operation

1.7 mA per channel maximum @ 0 Mbps to 2 Mbps

4.0 mA per channel maximum @ 2 Mbps to 10 Mbps

3 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps

2.1 mA per channel maximum @ 2 Mbps to 10 Mbps Bidirectional communication 3 V/5 V level translation Schmitt trigger inputs High temperature operation: 105°C Up to 10 Mbps data rate (NRZ) Programmable default output state High common-mode transient immunity: >25 kV/μs 16-lead, RoHS-compliant, SOIC wide body package

8.1 mm external creepage

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 V

= 560 V peak working voltage

IORM

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceiver Industrial field bus isolation

ADuM1310/ADuM1311

FUNCTIONAL BLOCK DIAGRAMS

1

V

GND

DISABLE

GND

DD1

V

NC

1

IA

IB

IC

1

ADuM1310

2

ENCODE DECODE

3

ENCODE DECODE

4

ENCODE DECODE

5

6

7

8

Figure 1. ADuM1310

1

V

GND

CTRL

GND

V

DD1

V

OC

NC

1

IA

IB

1

ADuM1311

2

ENCODE DECODE

3

ENCODE DECODE

4

DECODE ENCODE

5

6

7

8

Figure 2. ADuM1311

16

V

DD2

GND

15

2

14

V

OA

13

V

OB

12

V

OC

11

NC

10

CTRL

2

9

GND

2

04904-001

16

V

DD2

GND

15

2

14

V

OA

13

V

OB

12

V

IC

11

NC

10

CTRL

2

9

GND

2

04904-002

GENERAL DESCRIPTION

The ADuM131x1 are 3-channel digital isolators based on

Analog Devices, Inc. iCoupler® technology. Combining high

speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, maximum operating temperature, and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The iCoupler also offers higher channel densities and more options for channel directionality.

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The ADuM131x isolators provide three independent isolation channels in a variety of channel configurations and data rates up to 10 Mbps (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to

5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products allow the user to predetermine the default output state in the absence of input V

power with a simple

DD1

control pin. Unlike other optocoupler alternatives, the ADuM131x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/ power-down conditions.

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents

pending.

ADuM1310/ADuM1311 Data Sheet

REVISION HISTORY

3/12—Rev. G to Rev. H

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 18

Updated Outline Dimensions ....................................................... 21

6/07—Rev. F to Rev. G

Updated VDE Certification Throughout ...................................... 1

Changes to Features and Applications ........................................... 1

Changes to DC Specifications in Table 1 ....................................... 3

Changes to DC Specifications in Table 2 ....................................... 5

Changes to DC Specifications in Table 3 ....................................... 7

Changes to Regulatory Information Section .............................. 10

Added Table 10 ............................................................................... 12

Added Insulation Lifetime Section .............................................. 19

1/07—Rev. E to Rev. F

Added ADuM1311 ............................................................. Universal

Changes to Typical Performance Characteristics Section ......... 16

Changes to Ordering Guide .......................................................... 20

10/06—Rev. D to Rev. E

Removed ADuM1410 ........................................................ Universal

Updated Format .................................................................. Universal

Change to Figure 3 ......................................................................... 10

Changes to Table 10 ....................................................................... 10

Changes to Application Information Section ............................. 12

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 18

3/06—Rev. C to Rev. D

Added Note 1; Changes to Figure 2 ................................................ 1

Changes to Absolute Maximum Ratings ..................................... 11

11/05—Revision C: Initial Version

Rev. H | Page 2 of 24

Data Sheet ADuM1310/ADuM1311

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

ADuM1310, Total Supply Current,

ADuM1311, Total Supply Current,

For All Models

SWITCHING SPECIFICATIONS

ADuM131xARWZ

ADuM131xBRWZ

≤ 5.5 V, 4.5 V ≤ V

DD1

Three Channels

1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

DD1

= V

= 5 V. All voltages are relative to their respective grounds.

DD2

DC to 2 Mbps

V

Supply Current I

DD1

2.4 3.2 mA

DD1 (Q)

DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

1.2 1.6 mA

DD2 (Q)

DC to 1 MHz logic signal frequency

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

1

Three Channels

6.6 9.0 mA 5 MHz logic signal frequency

DD1 (10)

2.1 3.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

2.2 2.8 mA

DD1 (Q)

DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

1.8 2.4 mA

DD2 (Q)

DC to 1 MHz logic signal frequency

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold

4.5 5.7 mA 5 MHz logic signal frequency

DD1 (10)

3.5 4.3 mA 5 MHz logic signal frequency

DD2 (10)

, IIB, IIC, I

I

IA

I

CTRL2

V

IH

V

IL

OAH

OAL

, I

, V

CTRL1

DISABLE

OBH

, V

OBL

−10 +0.01 +10 μA

,

0 V ≤ V 0 V ≤ V 0 V ≤ V

2.0 V

0.8 V (V

or V

, V

OCL

DD1

OCH

(V

DD1

0.0 0.1 V IOx = 20 μA, VIx = V

) − 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

, VIB, VIC ≤ V

IA

, V

CTRL1

CTRL2

≤ V

DISABLE

0.2 0.4 V IOx = 4 mA, VIx = V

≤ V

DD1

or V

DD1

DD2

or V

DD1

DD2,

Logic High Output Voltages V

IxH

Logic Low Output Voltages V

IxL

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

, t

20 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

, t

20 30 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 5 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

30 ns CL = 15 pF, CMOS signal levels

PSK

,

Rev. H | Page 3 of 24

ADuM1310/ADuM1311 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

5 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

6

Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.2 Mbps Input Enable Time8 t Input Disable Time8 t Input Supply Current per Channel,

Quiescent

Output Supply Current per Channel,

Quiescent

Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current per

Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).

9

I

the same orientation as Channel A must be included to account for the total current consumed.

10

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in

DDx (Q)

9

10

and V

DD1

supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.

DD2

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

6

|CMH| 25 35 kV/μs

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/μs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

0.50 0.73 mA

I

DDI (Q)

I

0.38 0.53 mA

DDO (Q)

0.12

I

DDI (D)

2.0 μs VIA, VIB, VIC = 0 V or V

5.0 μs VIA, VIB, VIC = 0 V or V

mA/ Mbps

0.04

I

DDO (D)

mA/ Mbps

ower Consumption

Figure 9

propagation delay is

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

Power Consumption

Figure 6

Figure 8

DD1

is set high

Rev. H | Page 4 of 24

Data Sheet ADuM1310/ADuM1311

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

ADuM1310, Total Supply Current,

ADuM1311, Total Supply Current,

For All Models

SWITCHING SPECIFICATIONS

ADuM131xARWZ

ADuM131xBRWZ

≤ 3.6 V, 2.7 V ≤ V

DD1

Three Channels

1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

DD1

= V

= 3.0 V. All voltages are relative to their respective ground.

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.6 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.8 1.0 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Three Channels

1

3.4 4.9 mA 5 MHz logic signal frequency

DD1 (10)

1.1 1.3 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.9 1.4 DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold

2.5 3.5 mA 5 MHz logic signal frequency

DD1 (10)

1.9 2.6 5 MHz logic signal frequency

DD2 (10)

, IIB, IIC, I

I

IA

I

CTRL2

V

IH

V

IL

OAH

OAL

, I

, V

DISABLE

OBH

, V

OBL

−10 +0.01 +10 μA

CTRL1

,

0 V ≤ V 0 V ≤ V 0 V ≤ V

1.6 V

0.4 V (V

or V

, V

DD1

OCH

(V

DD1

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

0.2 0.4 V I

) − 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

Ox

, VIB, VIC ≤ V

IA

, V

CTRL1

CTRL2

≤ V

DISABLE

= 4 mA, VIx = V

DD1

≤ V

IxL

IxH

DD1

IxH

Logic Low Output Voltages V

or V

DD1

Logic High Output Voltages V

or V

DD2

DD2,

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

, t

20 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

, t

20 30 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

6

Channel-to-Channel Matching,

Opposing-Directional Channels

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

6

,

Rev. H | Page 5 of 24

ADuM1310/ADuM1311 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

|CMH| 25 35 kV/μs

|CML| 25 35 kV/μs

Refresh Rate fr 1.1 Mbps Input Enable Time8 t Input Disable Time8 t Input Supply Current per Channel,

Quiescent

Output Supply Current per Channel,

Quiescent

Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current

per Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).

9

I

the same orientation as Channel A must be included to account for the total current consumed.

10

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in

DDx (Q)

9

DD1

10

and V

supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.

DD2

ENABLE

DISABLE

0.25 0.38 mA

I

DDI (Q)

0.19 0.33 mA

I

DDO (Q)

0.07

I

DDI (D)

I

0.02

DDO (D)

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

2.0 μs VIA, VIB, VIC = 0 V or V

5.0 μs VIA, VIB, VIC = 0 V or V

mA/ Mbps

ower Consumption

Figure 9

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

Figure 8

DD1

DISABLE

is set high

Rev. H | Page 6 of 24

Data Sheet ADuM1310/ADuM1311

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

5 V/3 V operation: 4.5 V ≤ V minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

ADuM1310, Total Supply Current,

Three Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.4 3.2 mA

3 V/5 V Operation 1.2 1.6 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.8 1.0 mA

3 V/5 V Operation 1.2 1.6 mA

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 6.5 8.2 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 1.1 1.3 mA 5 MHz logic signal frequency 3 V/5 V Operation 1.9 2.2 mA 5 MHz logic signal frequency

ADuM1311, Total Supply Current,

Three Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA

3 V/5 V Operation 1.0 1.6 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.4 mA

3 V/5 V Operation 1.8 2.4 mA

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 4.5 5.7 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.5 3.5 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 1.9 2.6 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.5 4.3 mA 5 MHz logic signal frequency

For All Models

Input Currents

Logic High Input Threshold

V

= 5 V Operation 2.0 V

DDX

V

= 3 V Operation 1.6 V

DDX

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

, IIB, IIC, I

I

IA

I

CTRL2

V

IH

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

= 3.0 V. All voltages are relative to their respective ground.

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

DC to 1 MHz logic signal frequency

−10 +0.01 +10 μA

, I

DISABLE

CTRL1

,

0 V ≤ V 0 V ≤ V 0 V ≤ V

≤ 5.5 V; all

DD2

, VIB, VIC ≤ V

IA

, V

CTRL1

≤ V

DISABLE

CTRL2

DD1

≤ V

DD1

or V

DD1

or V

DD2

,

Rev. H | Page 7 of 24

ADuM1310/ADuM1311 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

Logic Low Input Threshold

V

= 5 V Operation 0.8 V

DDX

V

= 3 V Operation 0.4 V

DDX

Logic High Output Voltages V

Logic Low Output Voltages V

SWITCHING SPECIFICATIONS

ADuM131xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion |t Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM131xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 2.5 ns

3 V/5 V Operation 2.5 ns Common-Mode Transient

Immunity at Logic High Output

Common-Mode Transient

Immunity at Logic Low Output

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Enable Time8 t Input Disable Time8 t Input Supply Current per Channel,

Quiescent

V

DDX

V

DDX

9

= 5 V Operation I = 3 V Operation I

Output Supply Current per

Channel, Quiescent

V

= 5 V Operation I

DDX

V

= 3 V Operation I

DDX

Input Dynamic Supply Current per

Channel

V

10

= 5 V Operation 0.12

DDX

= 3 V Operation 0.07

DDX

PLH

− t

6

PHL

V

IL

, V

OAH

OBH

, V

OAL

OBL

, t

PHL

PLH

, V

(V

or V or V

) − 0.1 (V

DD2

) − 0.4 (V

DD2

OCH

DD1

(V

DD1

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

0.2 0.4 V IOx = 4 mA, VIx = V

DD1

or V

) V IOx = −20 μA, VIx = V

DD2

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

IxH

IxL

25 100 ns CL = 15 pF, CMOS signal levels

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

6

= 15 pF, CMOS signal levels

L

|CMH| 25 35 kV/μs

7

|CML| 25 35 kV/μs

7

ENABLE

DISABLE

2.0 μs VIA, VIB, VIC, VID = 0 V or V

5.0 μs VIA, VIB, VIC, VID = 0 V or V

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

DD1

0.50 0.73 mA

DDI (Q)

0.25 0.38 mA

DDI (Q)

9

0.38 0.53 mA

DDO (Q)

0.19 0.33 mA

DDO (Q)

I

DDI (D)

mA/ Mbps

Rev. H | Page 8 of 24

Data Sheet ADuM1310/ADuM1311

Parameter Symbol Min Typ Max Unit Test Conditions

Output Dynamic Supply Current

per Channel

V

= 5 V Operation 0.04

DDX

V

= 3 V Operation 0.02

DDX

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

10

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

DD1

and V

supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.

DD2

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).

9

I

is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in

DDx (Q)

the same orientation as Channel A must be included to account for the total current consumed.

10

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

I

DDI (D)

mA/ Mbps

ower Consumption

Figure 9

propagation delay is

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

Power Consumption

Figure 6

Figure 8

is set high

Rev. H | Page 9 of 24

ADuM1310/ADuM1311 Data Sheet

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output)1 R Capacitance (Input-to-Output)

1

Input Capacitance2 C IC Junction-to-Case Thermal Resistance

Side 1 θ Side 2 θ

1

The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM131x have been approved by the organizations listed in Tab l e 5 . See Ta ble 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 5.

UL CSA VDE

Recognized Under 1577 Component Recognition Program

Double/Reinforced Insulation, 2500 V rms Isolation Voltage

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM131x is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM131x is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection

limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.

1

1012 Ω

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

33 °C/W Thermocouple located at center of package underside

JCI

28 °C/W

JCO

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-03 and

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122

Reinforced insulation, 560 V peak IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. H | Page 10 of 24

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

Data Sheet ADuM1310/ADuM1311

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

The ADuM131x isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

After Environmental Tests Subgroup 1 896 V peak

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

After Input and/or Safety Test Subgroup 2

V

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 4000 V peak Safety-Limiting Values

Maximum value allowed in the event of a failure;

see Figure 3 Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

560 V peak

IORM

1050 V peak

V

PR

350

300

250

200

150

100

SAFETY-LIMITING CURRENT ( mA)

50

0

Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

SIDE 2

SIDE 1

50 100 150 200

CASE TEMPERATURE (°C)

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C Supply Voltages1 V Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground. See the

and Magnetic Field Immunity magnetic fiel ds.

section for information on immunity to external

04904-005

, V

2.7 5.5 V

DD1

DD2

DC Correctness

Rev. H | Page 11 of 24

ADuM1310/ADuM1311 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 9.

Parameter Rating

Storage Temperature (TST) Range −65°C to +150°C Ambient Operating Temperature

) Range

(T

A

Supply Voltages (V

, V

)1 −0.5 V to +7.0 V

DD1

DD2

Input Voltage

, VIB, VIC, V

(V

IA

Output Voltage (VOA, VOB, VOC)

DISABLE

, V

CTRL1

CTRL2

1, 2

−40°C to +105°C

−0.5 V to V

1, 2

)

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current per Pin3

Side 1 (IO1) −18 mA to +18 mA Side 2 (IO2) −22 mA to +22 mA

Common-Mode Transients4 −100 kV/μs to +100 kV/μs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

3

See Figure 3 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Table 10. Maximum Continuous Working Voltage

1

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the section for more details. Insulation Lifetime

Rev. H | Page 12 of 24

Data Sheet ADuM1310/ADuM1311

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

DD1

2

*GND

1

V

3

IA

ADuM1310

V

4

IB

TOP VIEW

5

V

IC

(Not to Scale)

NC 6 NC11

DISABLE 7 CTRL

8

*GND

1

NC = NO CONNECT

*PIN 2 AND PIN 8 ARE INT E RNALLY CONNECT ED. CONNECTING BOTH

IS RECOMM ENDE D. PIN 9 AND PIN 15 ARE INTERNALLY

TO GND

1

CONNECTED. CO NNE CTING BOT H TO GND

Figure 4. ADuM1310 Pin Configuration

Table 11. ADuM1310 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND 3 V

IA

1

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 NC 7 DISABLE

No Connection.

Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state

determined by CTRL

.

2

8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 CTRL2

11 NC

Default Output Control. Controls the logic state the outputs take on when the input power is off. V

V

outputs are high when CTRL2 is high or disconnected and V

OC

CTRL

is low and V

2

is off. When V

DD1

power is on, this pin has no effect.

DD1

No Connection. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

DD2

V

16

DD2

15

GND2* V

14

OA

V

13

OB

12

V

OC

10

2

9

GND2*

IS RECOMMENDE D.

2

04904-003

, VOB, and

is off. VOA, VOB, and VOC outputs are low when

DD1

OA

Rev. H | Page 13 of 24

ADuM1310/ADuM1311 Data Sheet

1

V

DD1

*GND

2

1

V

3

IA

ADuM1311

4

V

IB

V

CTRL *GND

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH

IS RECOMME NDE D. PIN 9 AND PIN 15 ARE INTERNALLY

TO GND

1

CONNECTED. CO NNECTING BOT H TO GND

TOP VIEW

5

OC

(Not to S cale)

6

NC

7

1

8

1

NC = NO CONNECT

Figure 5. ADuM1311 Pin Configuration

Table 12. ADuM1311 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND 3 V

IA

1

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 NC 7 CTRL1

No Connection.

Default Output Control. Controls the logic state the outputs take on when the input power is off. V

high when CTRL

When V

DD2

is high or disconnected and V

1

power is on, this pin has no effect. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 CTRL2

11 NC

Default Output Control. Controls the logic state the outputs take on when the input power is off. V outputs are high when CTRL is low and V

is off. When V

DD1

is high or disconnected and V

2

power is on, this pin has no effect.

DD1

No Connection. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

DD2

16

V

DD2

GND2*

15

V

14

OA

13

V

OB

V

12

IC

11

NC CTRL

10

2

GND2*

9

IS RECOMMENDED.

2

is off. VOC output is low when CTRL1 is low and V

DD2

DD1

04904-004

is off. VOA and VOB outputs are low when CTRL2

output is

OC

is off.

DD2

and VOB

OA

Rev. H | Page 14 of 24

Data Sheet ADuM1310/ADuM1311

Table 13. Truth Table (Positive Logic)

VIx Input1

CTRL Input

H X L or NC Powered Powered H Normal operation, data is high. L X L or NC Powered Powered L Normal operation, data is low. X

H or NC

X L H X Powered L

X

H or NC

X L X Unpowered Powered L

X X X Powered Unpowered Z

1

VIx and VOx refer to the input and output signals of a given channel (A, B, or C).

2

CTRLx refers to the default output control signal on the input side of a given channel (A, B, or C).

3

Available only on the ADuM1310.

4

V

refers to the power supply on the input side of a given channel (A, B, or C).

DDI

5

V

refers to the power supply on the output side of a given channel (A, B, or C).

DDO

V

x

DISABLE

2

State

V

DDI

3

State

4

V

DDO

State

5

H X Powered H

X Unpowered Powered H

V

Ox

Output Description

Inputs disabled. Outputs are in the default state determined by CTRLx.

Inputs disabled. Outputs are in the default state determined by

.

CTRL

x

Input unpowered. Outputs are in the default state determined by

. Outputs return to input state within 1 μs of V

CTRL

x

restoration. See the pin function descriptions (Table 11 and Table 12) for more details.

Input unpowered. Outputs are in the default state determined by

. Outputs return to input state within 1 μs of V

CTRL

x

restoration. See the pin function descriptions (Table 11 and Table 12) for more details.

Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 μs of V See the pin function descriptions (Table 11 and Table 12) for more details.

power

DDI

power

DDI

power restoration.

DDO

Rev. H | Page 15 of 24

ADuM1310/ADuM1311 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

6

1.5

1.0

0.5

CURRENT/CHANNEL (mA)

0

2468

DATA RATE (Mbps)

5V

3V

10

Figure 6. Typical Supply Current per Input Channel vs. Data Rate

for 5 V and 3 V Operation

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CURRENT/CHANNEL (mA)

0.2

0.1 0

0

2468

DATA RATE (Mbps)

5V

3V

10

Figure 7. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

5V

4

3V

2

CURRENT (mA)

04904-006

0

2468

DATA RATE (Mbps)

Figure 9. Typical ADuM1310 V

Supply Current vs. Data Rate

DD1

04904-009

10

for 5 V and 3 V Operation

6

4

5V

2

CURRENT (mA)

3V

04904-007

0

2468

DATA RATE (Mbps)

Figure 10. Typical ADuM1310 V

Supply Current vs. Data Rate

DD2

04904-010

10

for 5 V and 3 V Operation (No Output Load)

1.4

1.2

1.0

0.8

0.6

0.4

CURRENT/CHANNEL (mA)

0.2

0

2468

DATA RATE (Mbps)

5V

3V

10

Figure 8. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

04904-008

Rev. H | Page 16 of 24

6

4

2

CURRENT (mA)

0

2468

DATA RATE (Mbps)

Figure 11. Typical ADuM1311 V

for 5 V and 3 V Operation (No Output Load)

5V

3V

Supply Current vs. Data Rate

DD1

04904-011

10

Data Sheet ADuM1310/ADuM1311

6

4

2

CURRENT (mA)

0

Figure 12. Typical ADuM1311 V

for 5 V and 3 V Operation (No Output Load)

5V

3V

2468

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD2

04904-012

10

Rev. H | Page 17 of 24

ADuM1310/ADuM1311 Data Sheet

V

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM131x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 13). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V for V

. The capacitor value should be between 0.01 μF and

DD2

and between Pin 15 and Pin 16

DD1

0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should be considered, unless both ground pins on each package are connected together close to the package.

V

DD1

GND

1

V

IA

V

IB

VIC/V

OC

DISABLE/CTRL

NC

1

GND

1

Figure 13. Recommended Printed Circuit Board Layout

ADuM1310/

ADuM1311

V

DD2

GND V

OA

V

OB

VOC/V NC

CTRL GND

2

IC

2

04904-013

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the device’s absolute maximum ratings, thereby leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition.

INPUT (

)

Ix

OUTPUT (V

t

PLH

)

Ox

Figure 14. Propagation Delay Parameters

t

PHL

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

50%

04904-014

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM131x component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM131x components operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 13) by the watchdog timer circuit.

The magnetic field immunity of the ADuM131x is determined by the changing magnetic field, which induces a voltage in the transformer’s receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM131x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)

where:

β is magnetic flux density (gauss). r

is the radius of the nth turn in the receiving coil (cm).

n

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM131x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 15.

2

∑ π r

; n = 1, 2, … , N

n

Rev. H | Page 18 of 24

Data Sheet ADuM1310/ADuM1311

100

10

1

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k

Figure 15. Maximum Allowable External Magnetic Flux Density

10k 100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

100M

04904-015

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM131x transformers. Figure 16 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM131x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, a 0.5 kA current would have to be placed 5 mm away from the ADuM131x to affect the component’s operation.

1000

DISTANC E = 1m

100

10

DISTANC E = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALL OWABLE CURRENT (kA)

0.01 1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 16. Maximum Allowable Current

for Various Current-to-ADuM131x Spacings

04904-016

Note that, at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficient to trigger succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM131x isolator is a function of the supply voltage, the channel data rate, and the channel output load.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

= I

I

DDI

× (2f − fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

where:

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz); it is half the input

data rate, expressed in units of Mbps.

f

is the input stage refresh rate (Mbps).

r

, I

I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

To calculate the total V

DD1

and V

supply current, the supply

DD2

currents for each input and output channel corresponding to V

DD1

and V

are calculated and totaled. The ADuM131x

DD2

contains an internal data channel that is not available to the user. This channel is in the same orientation as Channel A and consumes quiescent current. The contribution of this channel must be included in the total quiescent current calculation for each supply. Figure 6 and Figure 7 show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 shows per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 12 show total V

DD1

and V

supply current as a

DD2

function of data rate for ADuM1310/ADuM1311 channel configurations.

f ≤ 0.5 fr

f > 0.5 fr

DDO (Q)

f > 0.5 fr

Rev. H | Page 19 of 24

ADuM1310/ADuM1311 Data Sheet

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM131x.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Ta b le 1 0 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM131x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 17, Figure 18, and Figure 19 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 1 0 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 18 or Figure 19 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 1 0.

Note that the voltage presented in Figure 18 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 17. Bipolar AC Waveform

04904-017

RATED PEAK VOL TAGE

0V

Figure 18. Unipolar AC Waveform

04904-018

RATED PEAK VOL TAGE

0V

Figure 19. DC Waveform

04904-019

Rev. H | Page 20 of 24

Data Sheet ADuM1310/ADuM1311

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0

.

0

.

7

5

2

5

(

0

.

0

2

9

(

0

.

0

9

1.27 (0.0500)

0.40 (0.0157)

5

)

45°

8

)

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

16

1

1.27 (0.0500) BSC

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 20. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Inputs,

Model1

V

DD1

ADuM1310ARWZ 3 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1310ARWZ-RL 3 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W, 13” Reel RW-16 ADuM1310BRWZ 3 0 10 50 5 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1310BRWZ-RL 3 0 10 50 5 −40°C to +105°C 16-Lead SOIC_W, 13” Reel RW-16 ADuM1311ARWZ 2 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1311ARWZ-RL 2 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W, 13” Reel RW-16 ADuM1311BRWZ 2 1 10 50 5 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1311BRWZ-RL 2 1 10 50 5 −40°C to +105°C 16-Lead SOIC_W, 13” Reel RW-16

1

Z = RoHS Compliant Part.

Side

Number of Inputs, V

Side

DD2

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse Width Distortion (ns)

Temperature Range

Package Description

Package Option

Rev. H | Page 21 of 24

ADuM1310/ADuM1311 Data Sheet

NOTES

Rev. H | Page 22 of 24

Data Sheet ADuM1310/ADuM1311

NOTES

Rev. H | Page 23 of 24

ADuM1310/ADuM1311 Data Sheet

NOTES

Rev. H | Page 24 of 24

Datasheet ADUM1310 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE