Datasheet ADUM1300 Datasheet (ANALOG DEVICES)

G

Triple-Channel Digital Isolators

Data Sheet

FEATURES

Qualified for automotive applications Low power operation

5 V operation

1.2 mA per channel maximum @ 0 Mbps to 2 Mbps

3.5 mA per channel maximum @ 10 Mbps 32 mA per channel maximum @ 90 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

2.2 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body package RoHS-compliant models available

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V

= 560 V peak

IORM

TÜV approval: IEC/EN/UL/CSA 61010-1

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Automotive systems

ADuM1300/ADuM1301

GENERAL DESCRIPTION

The ADuM130x1 are triple-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocouplers.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth of the power of optocouplers at comparable signal data rates.

The ADuM130x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM130x provide low pulse width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM130x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

ND

1

ENCODE DECODE

3

V

IA

4

V

NC

ND

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

7

8

1

Figure 1. ADuM1300 Functional Block Diagram

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

NC

10

V

E2

9

GND

2

03787-001

1

V

DD1

2

GND

1

ENCODE DECODE

3

V

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

6

7

E1

8

1

GND

V

OC

NC

V

Figure 2. ADuM1301 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

NC

10

V

E2

9

GND

2

03787-002

ADuM1300/ADuM1301 Data Sheet

REVISION HISTORY

3/12—Rev. H to Rev. I

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section .................................................................1

Change to PC Board Layout Section ............................................25

Updated Outline Dimensions........................................................28

Moved Automotive Products Section...........................................28

5/08—Rev. G to Rev. H

Added ADuM1300W and ADuM1301W Parts............. Universal

Changes to Features List...................................................................1

Added Table 4 ..................................................................................11

Added Table 5 ..................................................................................13

Added Table 6 ..................................................................................15

Added Table 7 ..................................................................................17

Changes to Table 12 ........................................................................20

Changes to Table 13 ........................................................................21

Added Automotive Products Section ...........................................27

Changes to Ordering Guide...........................................................28

11/07—Rev. F to Rev. G

Changes to Note 1 and Figure 2 ......................................................1

Added ADuM130xARW Change vs. Temperature Parameter ...3 Added ADuM130xARW Change vs. Temperature Parameter ...5 Added ADuM130xARW Change vs. Temperature Parameter ...8

Changes to Figure 14 ......................................................................16

6/07—Rev. E to Rev. F

Updated VDE Certification Throughout.......................................1

Changes to Features, Note 1, Figure 1, and Figure 2 ....................1

Changes to Regulatory Information Section...............................10

Added Table 10 ................................................................................12

Added Insulation Lifetime Section ...............................................17

Updated Outline Dimensions........................................................19

Changes to Ordering Guide...........................................................19

2/06—Rev. D to Rev. E

Updated Format ................................................................. Universal

Added TÜV Approval .......................................................Universal

Changes to Figure 2 ..........................................................................1

5/05—Rev. C to Rev. D

Changes to Format............................................................. Universal

Changes to Figure 2 ..........................................................................1

Changes to Table 6 ..........................................................................10

Changes to Ordering Guide...........................................................18

6/04—Rev. B to Rev. C

Changes to Format............................................................. Universal

Changes to Features.......................................................................... 1

Changes to Electrical Characteristics—5 V Operation................3

Changes to Electrical Characteristics—3 V Operation................5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation ............................................................................7

Changes to Ordering Guide...........................................................18

5/04—Rev. A to Rev. B

Changes to the Format...................................................... Universal

Changes to the Features....................................................................1

Changes to Table 7 and Table 8.....................................................14

Changes to Table 9 ..........................................................................15

Changes to the DC Correctness and Magnetic Field Immunity

Section ..............................................................................................19

Changes to the Power Consumption Section..............................20

Changes to the Ordering Guide....................................................21

9/03—Rev. 0 to Rev. A

Edits to Regulatory Information...................................................13

Edits to Absolute Maximum Ratings............................................15

Deleted the Package Branding Information ................................16

9/03—Revision 0: Initial Version

Rev. I | Page 3 of 32

ADuM1300/ADuM1301 Data Sheet

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1300 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM1301 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V (V Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM130xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

VIH, V VIL, V

OAH

, V

OAL

, t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 5 V. These

DD2

0.50 0.53 mA

0.19 0.24 mA

1.6 2.5 mA DC to 1 MHz logic signal freq.

0.7 1.0 mA DC to 1 MHz logic signal freq.

6.5 8.1 mA 5 MHz logic signal freq.

1.9 2.5 mA 5 MHz logic signal freq.

57 77 mA 45 MHz logic signal freq. 16 18 mA 45 MHz logic signal freq.

1.3 2.1 mA DC to 1 MHz logic signal freq.

1.0 1.4 mA DC to 1 MHz logic signal freq.

5.0 6.2 mA 5 MHz logic signal freq.

3.4 4.2 mA 5 MHz logic signal freq.

43 57 mA 45 MHz logic signal freq. 29 37 mA 45 MHz logic signal freq.

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

E2

EH

EL

, V

OBH

OBL

50 65 100 ns CL = 15 pF, CMOS signal levels

PLH

2.0 V

0.8 V

, V

(V

or V

OCH

DD1

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

) − 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0 V ≤ V

, VE2 ≤ V

E1

DD1

IxL

DD1

or V

IxH

IxL

or V

DD2

50 ns CL = 15 pF, CMOS signal levels

,

DD2

Rev. I | Page 4 of 32

Data Sheet ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 100 ns C 10 Mbps C

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

ADuM130xCRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 8.3 11.1 ns C 90 120 Mbps C

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

10 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

t

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

For All Models

Output Disable Propagation Delay (High/Low

t

PHZ

, t

PLH

6 8 ns CL = 15 pF, CMOS signal levels

to High Impedance)

Output Enable Propagation Delay (High

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic

High Output Common-Mode Transient Immunity at Logic

Low Output

7

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the V

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.19 mA/Mbps

DDI (D)

0.05 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Power Consumption

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

Power Consumption

Figure 9

propagation delay is

PLH

Figure 8

Rev. I | Page 5 of 32

ADuM1300/ADuM1301 Data Sheet

ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1300 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM1301 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V (V Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM130xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching6 t

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

VIH, V VIL, V

OAH

OAL

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.15 mA

0.9 1.7 mA DC to 1 MHz logic signal freq.

0.4 0.7 mA DC to 1 MHz logic signal freq.

3.4 4.9 mA 5 MHz logic signal freq.

1.1 1.6 mA 5 MHz logic signal freq.

31 48 mA 45 MHz logic signal freq. 8 13 mA 45 MHz logic signal freq.

0.7 1.4 mA DC to 1 MHz logic signal freq.

0.6 0.9 mA DC to 1 MHz logic signal freq.

2.6 3.7 mA 5 MHz logic signal freq.

1.8 2.5 mA 5 MHz logic signal freq.

24 36 mA 45 MHz logic signal freq. 16 23 mA 45 MHz logic signal freq.

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

E2

EH

EL

, V

OBH

, V

OBL

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PLH

1.6 V

0.4 V

, V

(V

or V

OCH

DD1

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

) − 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0 V ≤ V

, VE2 ≤ V

E1

DD1

IxL

DD1

or V

IxH

IxL

or V

DD2

50 ns CL = 15 pF, CMOS signal levels

,

Rev. I | Page 6 of 32

Data Sheet ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 100 ns C 10 Mbps C

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

26 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

ADuM130xCRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 8.3 11.1 ns C 90 120 Mbps C

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

For All Models

Output Disable Propagation Delay (High/Low to

t

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

High Impedance)

Output Enable Propagation Delay (High

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

Logic High Output Common-Mode Transient Immunity at

Logic Low Output

7

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the V

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.10 mA/Mbps

DDI (D)

0.03 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Power Consumption

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

Power Consumption

Figure 9

propagation delay is

PLH

Figure 8

Rev. I | Page 7 of 32

ADuM1300/ADuM1301 Data Sheet

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

2.7 V ≤ V

≤ 3.6 V, 4.5 V ≤ V

DD1

unless otherwise noted; all typical specifications are at T

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C; V

A

= 3.0 V, V

DD1

tions do not apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.11 0.15 mA 3 V/5 V Operation 0.19 0.24 mA

ADuM1300 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.6 2.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.7 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.4 0.7 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.0 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 6.5 8.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.1 1.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.9 2.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 57 77 mA 45 MHz logic signal freq. 3 V/5 V Operation 31 48 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 8 13 mA 45 MHz logic signal freq. 3 V/5 V Operation 16 18 mA 45 MHz logic signal freq.

ADuM1301 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.3 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.4 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.6 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 5.0 6.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.7 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.8 2.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.2 mA 5 MHz logic signal freq.

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

= 5 V, V

DD1

≤ 3.6 V; 3 V/5 V operation:

DD2

= 3.0 V. These specifica-

DD2

Rev. I | Page 8 of 32

Data Sheet ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 43 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 24 36 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 16 23 mA 45 MHz logic signal freq. 3 V/5 V Operation 29 37 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold

5 V/3 V Operation 2.0 V

3 V/5 V Operation 1.6 V Logic Low Input Threshold

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V Logic High Output Voltages V (V Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM130xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM130xBRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels Channel-to-Channel Matching, Opposing-

Directional Channels

6

ADuM130xCRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

DD1 (90)

DD2 (90)

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

E2

VIH, V

VIL, V

OAH

OAL

PHL

EH

EL

, V

OBH

, V

OBL

, t

PLH

, V

OCL

or V

OCH(VDD1

DD1

or V

) − 0.1 (V

DD2

) − 0.4 (V

DD2

DD1

or V

) V IOx = −20 μA, VIx = V

DD2

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

0.0 0.1 V IOx = 20 μA, VIx = V

50 70 100 ns CL = 15 pF, CMOS signal levels

0 V ≤ V

, VE2 ≤ V

E1

DD1

IxL

DD1

or V

IxH

IxL

or V

DD2

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

PW 100 ns C 10 Mbps C t

PHL

50 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

22 ns CL = 15 pF, CMOS signal levels

t

PSKOD

PW 8.3 11.1 ns C 90 120 Mbps C

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

14 ns CL = 15 pF, CMOS signal levels

t

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

,

Rev. I | Page 9 of 32

ADuM1300/ADuM1301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity at

Logic High Output

Common-Mode Transient Immunity at

Logic Low Output

7

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current per Channel8 I

5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current per Channel8

5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the P section. See through

for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Fi for total V

Figure 8 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See F through for information on

per-channel supply current for unloaded and loaded conditions. See the P section for guidance on calculating the per-channel supply current for a given data rate.

t

, t

PHZ

PLH

t

, t

PZH

PZL

|CM

| 25 35 kV/μs VIx = V

H

6 8 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

or V

DD1

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

DDI (D)

I

DDO (D)

ower Consumption

Figure 9 gure 12

propagation delay is measured

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load within the

PHL

PLH

. CML is the maximum common-mode voltage slew rate that can be

DD2

ower Consumption

igure 6

Figure 8

, VCM = 1000 V,

DD2

Figure 6

and V

DD1

DD2

Rev. I | Page 10 of 32

Data Sheet ADuM1300/ADuM1301

ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T specifications apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I

DDI (Q)

DDO (Q)

ADuM1300W, Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

ADuM1301W, Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages V

VIH, V VIL, V

OAH

OAL

SWITCHING SPECIFICATIONS

ADuM130xWSRWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

ADuM130xWTRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PHL

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching, Codirectional

Channels Channel-to-Channel Matching, Opposing-

Directional Channels

6

PSK

t

PSKCD

t

PSKOD

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 5 V. These

DD2

0.50 0.53 mA

0.19 0.24 mA

1.6 2.5 mA DC to 1 MHz logic signal freq.

0.7 1.0 mA DC to 1 MHz logic signal freq.

6.5 8.1 mA 5 MHz logic signal freq.

1.9 2.5 mA 5 MHz logic signal freq.

1.3 2.1 mA DC to 1 MHz logic signal freq.

1.0 1.4 mA DC to 1 MHz logic signal freq.

5.0 6.2 mA 5 MHz logic signal freq.

3.4 4.2 mA 5 MHz logic signal freq.

−10 +0.01 +10 μA

E2

0 V ≤ V 0 V ≤ V

2.0 V

0.8 V V

, V

OCH

V

0.0 0.1 V IOx = 20 μA, VIx = V

, V

OCL

− 0.1 5.0 V IOx = −20 μA, VIx = V

DD1

DD2

, V

− 0.4 4.8 V IOx = −4 mA, VIx = V

DD1

DD2

, V

EH

EL

OBH

OBL

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V I

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PLH

, VIB, VIC ≤ V

IA

, VE2 ≤ V

E1

= 4 mA, VIx = V

Ox

DD1

IxL

DD1

or V

IxH

IxL

or V

DD2

Logic High Output Voltages V

DD2

50 ns CL = 15 pF, CMOS signal levels

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PLH

15 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

,

Rev. I | Page 11 of 32

ADuM1300/ADuM1301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

, t

Output Disable Propagation Delay

t

PHZ

PLH

(High/Low to High Impedance)

t

, t

Output Enable Propagation Delay

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

| 25 35 kV/μs

Common-Mode Transient Immunity at Logic

High Output

Common-Mode Transient Immunity at Logic

Low Output

7

|CM

H

|CML| 25 35 kV/μs

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8 I

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.

DD2

or t

PHL

PLH

0.19 mA/Mbps

DDI (D)

0.05 mA/Mbps

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

6 8 ns CL = 15 pF, CMOS signal levels

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

Power Consumption

Figure 9

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

Figure 8

Rev. I | Page 12 of 32

Data Sheet ADuM1300/ADuM1301

ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 5.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1300W, Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM1301W, Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

SWITCHING SPECIFICATIONS

ADuM130xWSRWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM130xWTRWZ

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

VIH, V VIL, V

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

PW 100 ns C 10 Mbps C t

PHL

PWD 3 ns CL = 15 pF, CMOS signal levels

t

PSK

t

PSKCD

t

PSKOD

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.15 mA

0.9 1.7 mA DC to 1 MHz logic signal freq.

0.4 0.7 mA DC to 1 MHz logic signal freq.

3.4 4.9 mA 5 MHz logic signal freq.

1.1 1.6 mA 5 MHz logic signal freq.

0.7 1.4 mA DC to 1 MHz logic signal freq.

0.6 0.9 mA DC to 1 MHz logic signal freq.

2.6 3.7 mA 5 MHz logic signal freq.

1.8 2.5 mA 5 MHz logic signal freq.

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

OAH

OAL

, V

E2

EH

EL

OBH

OBL

1.6 V

0.4 V

, V

V

, V

OCH

V

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

− 0.1 3.0 V IOx = −20 μA, VIx = V

DD1

DD2

, V

− 0.4 2.8 V IOx = −4 mA, VIx = V

DD1

DD2

0 V ≤ V

, VE2 ≤ V

E1

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PLH

DD1

IxL

DD1

or V

IxH

IxL

or V

50 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PLH

26 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

DD2

,

DD2

Rev. I | Page 13 of 32

ADuM1300/ADuM1301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Disable Propagation Delay (High/Low to

t

, t

PHZ

PLH

High Impedance)

Output Enable Propagation Delay (High Impedance

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

Logic High Output

Common-Mode Transient Immunity at

Logic Low Output

7

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

for total V

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.

DD2

or t

PHL

PLH

0.10 mA/Mbps

DDI (D)

0.03 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

6 8 ns CL = 15 pF, CMOS signal levels

DD1/VDD2

transient magnitude = 800 V

Power Consumption

Figure 9

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

Figure 8

, VCM = 1000 V,

Rev. I | Page 14 of 32

Data Sheet ADuM1300/ADuM1301

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

≤ 5.5 V, 3.0 V ≤ V

DD1

1

≤ 3.6 V; all minimum/maximum specifications apply

DD2

= 25°C; V

A

= 5 V, V

DD1

= 3.0 V.

DD2

These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 6.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM1300W, Total Supply Current, Three Channels2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM1301W, Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages V

SWITCHING SPECIFICATIONS

ADuM130xWSRWZ

Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew6 t Channel-to-Channel Matching7

ADuM130xWTRWZ

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels Channel-to-Channel Matching, Opposing-

Directional Channels

6

0.50 0.53 mA

DDI (Q)

0.11 0.15 mA

DDO (Q)

1.6 2.5 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.4 0.7 mA DC to 1 MHz logic signal freq.

DD2 (Q)

6.5 8.1 mA 5 MHz logic signal freq.

DD1 (10)

1.1 1.6 mA 5 MHz logic signal freq.

DD2 (10)

1.3 2.1 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.6 0.9 mA DC to 1 MHz logic signal freq.

DD2 (Q)

5.0 6.2 mA 5 MHz logic signal freq.

DD1 (10)

1.8 2.5 mA 5 MHz logic signal freq.

DD2 (10)

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

VIH, V VIL, V

OAH

OAL

, V

E2

EH

EL

OBH

OBL

2.0 V

0.8 V

V

, V

OCH

V

0.0 0.1 V IOx = 20 μA, VIx = V

, V

OCL

DD1

, V

− 0.1 V

DD2

− 0.4 V

DD2

, V

V IOx = −20 μA, VIx = V

DD1

DD2

V I

,

DD1

− 0.2

V

DD2

, VE2 ≤ V

0 V ≤ V

E1

= −4 mA, VIx = V

Ox

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V I

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

= 4 mA, VIx = V

Ox

DD1

IxL

DD1

or V

IxH

IxL

or V

Logic High Output Voltages V

DD2

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

50 ns C

PW 100 ns C 10 Mbps C

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

PWD 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

22 ns CL = 15 pF, CMOS signal levels

t

PSKOD

,

Rev. I | Page 15 of 32

ADuM1300/ADuM1301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Disable Propagation Delay (High/Low

to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

Logic High Output Common-Mode Transient Immunity at

Logic Low Output

8

7

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel9 I Output Dynamic Supply Current per Channel8

1

All voltages are relative to their respective ground.

2

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through

for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total V

Figure 8 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See F through for information on

per-channel supply current for unloaded and loaded conditions. See the P section for guidance on calculating the per-channel supply current for a given data rate.

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

t

, t

PHZ

PLH

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

|CM

| 25 35 kV/μs VIx = V

H

6 8 ns CL = 15 pF, CMOS signal levels

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.19 mA/Mbps

DDI (D)

0.03 mA/Mbps

I

DDO (D)

Power Consumption

Figure 9 Figure 12

propagation delay is measured

PLH

that is measured between units at the same operating temperature, supply voltages, and output load within the

PLH

. CML is the maximum common-mode voltage slew rate that can be

DD2

igure 6

Figure 8

ower Consumption

Figure 6

DD1

and V

DD2

Rev. I | Page 16 of 32

Data Sheet ADuM1300/ADuM1301

ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T These apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 7.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1300W, Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM1301W, Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages V

SWITCHING SPECIFICATIONS

ADuM130xWSRWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6

ADuM130xWTRWZ

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels Channel-to-Channel Matching, Opposing-

Directional Channels

6

DDI (Q)

DDO (Q)

DD1 (Q)

DD2(Q)

DD1 (10)

DD2 (10)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

VIH, V VIL, V

, V

OAH

, V

OAL

, t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

PW 100 ns C 10 Mbps C

, t

t

PHL

PWD 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

t

PSK

t

PSKCD

t

PSKOD

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C; V

A

= 3.0 V, V

DD1

DD2

= 5 V.

0.26 0.31 mA

0.19 0.24 mA

0.9 1.7 mA DC to 1 MHz logic signal freq.

0.7 1.0 mA DC to 1 MHz logic signal freq.

3.4 4.9 mA 5 MHz logic signal freq.

1.9 2.5 mA 5 MHz logic signal freq.

0.7 1.4 mA DC to 1 MHz logic signal freq.

1.0 1.4 mA DC to 1 MHz logic signal freq.

2.6 3.7 mA 5 MHz logic signal freq.

3.4 4.2 mA 5 MHz logic signal freq.

−10 +0.01 +10 μA 0 7≤ VIA,V

E2

0 7≤ V

EH

EL

OBH

OBL

1.6 V

0.4 V

V

, V

OCH

V

0.0 0.1 V IOx = 20 μA, VIx = V

, V

OCL

DD1

, V

− 0.1 V

DD2

− 0.4 V

DD2

, V

V IOx = −20 μA, VIx = V

DD1

DD2

V I

,

DD1

− 0.2

V

DD2

= −4 mA, VIx = V

Ox

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V I

50 70 100 ns CL = 15 pF, CMOS signal levels

PLH

50 ns C

20 30 40 ns CL = 15 pF, CMOS signal levels

PLH

= 4 mA, VIx = V

Ox

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

E1

,V

, VIC ≤ V

IB

≤ V

E2

DD1

IxL

DD1

or V

IxH

IxL

or V

Logic High Output Voltages V

DD2

3 ns CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

,

Rev. I | Page 17 of 32

ADuM1300/ADuM1301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Disable Propagation Delay (High/Low

to High Impedance)

Output Enable Propagation Delay

(High Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity at Logic

High Output

Common-Mode Transient Immunity at Logic

Low Output

7

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through

for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total V

Figure 8 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See F through for information on

per-channel supply current for unloaded and loaded conditions. See the P section for guidance on calculating the per-channel supply current for a given data rate.

or t

PHL

t

, t

PHZ

PLH

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

|CM

| 25 35 kV/μs VIx = V

H

6 8 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.10 mA/Mbps

DDI (D)

0.05 mA/Mbps

I

DDO (D)

Power Consumption

Figure 9 Figure 12

propagation delay is measured

PLH

that is measured between units at the same operating temperature, supply voltages, and output load within the

PLH

. CML is the maximum common-mode voltage slew rate that can be

DD2

igure 6

Figure 8

ower Consumption

Figure 6

DD1

and V

DD2

Rev. I | Page 18 of 32

Data Sheet ADuM1300/ADuM1301

PACKAGE CHARACTERISTICS

Table 8.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output)1 R Capacitance (Input-to-Output)

1

Input Capacitance2 C IC Junction-to-Case Thermal Resistance, Side 1 θ

IC Junction-to-Case Thermal Resistance, Side 2 θ

1

Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,

Pin 15, and Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM130x are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.

Table 9.

UL CSA VDE TÜV

Recognized under 1577 Component Recognition Program1

Double/reinforced insulation, 2500 V rms isolation voltage

File E214100 File 205078 File 2471900-4880-0001 Certificate U8V 05 06 56232 002

1

In accordance with UL 1577, each ADuM130x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM130x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection

limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage

1012 Ω

I-O

C

1.7 pF f = 1 MHz

I-O

4.0 pF

I

33 °C/W

JCI

Thermocouple located at center of package underside

28 °C/W

JCO

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122

Approved according to IEC 61010-1:2001 (2 EN 61010-1:2001 (2 UL 61010-1:2004 CSA C22.2.61010.1:2005

Reinforced insulation, 560 V peak

Reinforced insulation, 400 V rms maximum working voltage

nd

Edition),

nd

Edition),

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 10.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. I | Page 19 of 32

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

ADuM1300/ADuM1301 Data Sheet

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.

Table 11.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

After Environmental Tests Subgroup 1 896 V peak

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

After Input and/or Safety Test Subgroup 2

V

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak Safety-Limiting Values

Maximum value allowed in the event of a failure

(see Figure 3) Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

350

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting

Values with Case Temperature per DIN V VDE V 0884-10

SIDE #2

SIDE #1

50 100 150 200

CASE TEMPERAT URE (°C)

03787-003

RECOMMENDED OPERATING CONDITIONS

Table 12.

Parameter Rating

Operating Temperature (TA)1 −40°C to +105°C Operating Temperature (TA)2 −40°C to +125°C Supply Voltages (V Supply Voltages (V Input Signal Rise and Fall Times 1.0 ms

1

Does not apply to ADuM1300W and ADuM1301W automotive grade versions.

2

Applies to ADuM1300W and ADuM1301W automotive grade versions.

3

All voltages are relative to their respective ground. See the

and Magnetic Field Immunity magnetic fields.

, V

DD1

DD2

, V

DD1

DD2

section for information on immunity to external

560 V peak

IORM

1050 V peak

V

PR

1, 3

)

2.7 V to 5.5 V

2, 3

)

3.0 V to 5.5 V

DC Correctness

Rev. I | Page 20 of 32

Data Sheet ADuM1300/ADuM1301

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 13.

Parameter Rating

Storage Temperature (TST) −65°C to +150°C Ambient Operating Temperature (TA)1 −40°C to +105°C Ambient Operating Temperature (TA)2 −40°C to +125°C Supply Voltages (V Input Voltage (VIA, VIB, VIC, VE1, VE2) Output Voltage (VOA, VOB, VOC)

, V

)3 −0.5 V to +7.0 V

DD1

DD2

3, 4

−0.5 V to V

+ 0.5 V

DDI

DDO

+ 0.5 V

Average Output Current per Pin5

Side 1 (IO1) −23 mA to +23 mA Side 2 (IO2) −30 mA to +30 mA

Common-Mode Transients6 −100 kV/μs to +100 kV/μs

1

Does not apply to ADuM1300W and ADuM1301W automotive grade

versions.

2

Applies to ADuM1300W and ADuM1301W automotive grade versions.

3

All voltages are relative to their respective ground.

4

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

5

See Figure 3 for maximum rated current values for various temperatures.

6

This refers to common-mode transients across the insulation barrier.

Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

1

Table 14. Maximum Continuous Working Voltage

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

DC Voltage

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Table 15. Truth Table (Positive Logic)

VIx Input1 VEx Input

1, 2

V

State1 V

DDI

State1 VOx Output1 Notes

DDO

H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H Outputs return to the input state within 1 μs of V

power restoration.

DDI

X L Unpowered Powered Z X X Powered Unpowered Indeterminate

1

VIx and VOx refer to the input and output signals of a given channel (A, B, or C). VEx refers to the output enable signal on the same side as the VOx outputs. V

refer to the supply voltages on the input and output sides of the given channel, respectively.

2

In noisy environments, connecting VEx to an external logic high or low is recommended.

Outputs return to the input state within 1 μs of V if the V within 8 ns of V

state is H or NC. Outputs return to a high impedance state

Ex

power restoration if the VEx state is L.

DDO

power restoration

DDO

Rev. I | Page 21 of 32

DDI

and V

DDO

ADuM1300/ADuM1301 Data Sheet

*

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

DD1

*GND

2

1

3

V

IA

ADuM1300

V

4

IB

TOP VIEW

(Not to S cale)

V

5

IC

6

NC NC

7

*GND

8

1

NC = NO CONNECT

PIN 2 AND PIN 8 ARE I NT ERNALLY CONNECTED, AND CONNECTING BOTH TO G ND CONNECTED, AND CO NNECTING BOT H TO GND

IS RECOMME NDED. PIN 9 AND PIN 15 ARE I NTERNALLY

1

Figure 4. ADuM1300 Pin Configuration Figure 5. ADuM1301 Pin Configuration

V

16

DD2

GND2*

15 14

V

OA

V

13

OB

V

12

OC

11

NC V

10

E2

GND2*

9

03787-004

IS RECOMMENDE D.

2

1

V

DD1

*GND

2

1

V

3

IA

ADuM1301

4

V

IB

TOP VIEW

(Not to Scale)

V

5

OC

NC

6 7

V

E1

*GND

8

1

NC = NO CONNECT

*PIN 2 AND PIN 8 ARE I NTERNALLY CO NNECTED, AND CONNECT ING BOTH TO GND CONNECTED, AND CO NNECTING BOT H TO GND

IS RECOMME NDE D. PIN 9 AND PIN 15 ARE INTERNALLY

1

16

V

DD2

GND2*

15

V

14

OA

13

V

OB

V

12

IC

NC

11 10

V

E2

GND2*

9

03787-005

IS RECOMMENDE D.

2

Table 16. ADuM1300 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND 3 V

IA

1

Supply Voltage for Isolator Side 1. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 NC No Connect. 7 NC No Connect. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA, VOB,

outputs are enabled when VE2 is high or

and V

OC

disconnected. V

when V

E2

to an external logic high or low is recommended.

V

E2

, VOB, and VOC outputs are disabled

OA

is low. In noisy environments, connecting

11 NC No Connect. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2.

DD2

Table 17. ADuM1301 Pin Function Descriptions

Mnemonic Description

No.

1 V

DD1

2 GND 3 V

IA

1

Supply Voltage for Isolator Side 1. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 NC No Connect. 7 VE1 Output Enable 1. Active high logic input. VOC output

is enabled when V

output is disabled when V

ments, connecting V

is high or disconnected. VOC

E1

is low. In noisy environ-

E1

to an external logic high

E1

or low is recommended. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA and

outputs are enabled when VE2 is high or discon-

V

OB

nected. V

low. In noisy environments, connecting V

and VOB outputs are disabled when VE2 is

OA

to an

E2

external logic high or low is recommended. 11 NC No Connect. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2.

DD2

Rev. I | Page 22 of 32

Data Sheet ADuM1300/ADuM1301

TYPICAL PERFORMANCE CHARACTERISTICS

20

18

16

14

12

10

8

6

CURRENT/CHANNEL (mA)

4

2

0

5V

3V

4020 60 80 100

DATA RATE (Mb ps)

Figure 6. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

03787-008

60

50

40

30

20

CURRENT (mA)

10

0

020

Figure 9. Typical ADuM1300 V

for 5 V and 3 V Operation

5V

3V

40 60 80 100

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD1

03787-011

6

5

4

3

2

CURRENT/CHANNEL (mA)

1

0

5V

3V

20 40 60 80 100

DATA RATE (Mb ps)

Figure 7. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

10

9

8

7

6

5

4

3

CURRENT/CHANNEL (mA)

2

1 0

0

5V

3V

20 40 8060 100

DATA RATE (Mb ps)

Figure 8. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

16

14

12

10

8

6

CURRENT (mA)

4

2

0

03787-009

Figure 10. Typical ADuM1300 V

5V

3V

4020 60 80 100

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD2

03787-012

for 5 V and 3 V Operation

50

45

40

35

30

25

20

CURRENT (mA)

15

10

5

0

03787-010

20 40 60 80 100

Figure 11. Typical ADuM1301 V

5V

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD1

3V

03787-013

for 5 V and 3 V Operation

Rev. I | Page 23 of 32

ADuM1300/ADuM1301 Data Sheet

30

25

20

15

5V

CURRENT (mA)

10

5

3V

40

35

30

PROPAGATI ON DELAY (n s)

3V

5V

0

Figure 12. Typical ADuM1301 V

20 40 60 80 100

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

25

–50 –25

03787-014

0507525 100

TEMPERATURE ( °C)

03787-019

Figure 13. Propagation Delay vs. Temperature, C Grade

Rev. I | Page 24 of 32

Data Sheet ADuM1300/ADuM1301

V

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM130x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 14). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V Pin 16 for V

. The capacitor value should be between 0.01 μF

DD2

and between Pin 15 and

DD1

and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.

V

DD1

GND

1

V

IA

V

IB

IC/VOC

NC

NC/V

E1

GND

1

Figure 14. Recommended Printed Circuit Board Layout

V

DD2

GND V

OA

V

OB

V

OC/VIC

NC V

E2

GND

2

3787-015

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high output.

INPUT (

OUTPUT (V

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM130x component.

Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM130x components operating under the same conditions.

)

Ix

t

PLH

)

Ox

Figure 15. Propagation Delay Parameters

50%

t

PHL

50%

Rev. I | Page 25 of 32

3787-016

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 15) by the watchdog timer circuit.

The ADuM130x is extremely immune to external magnetic fields. The limitation on the magnetic field immunity of the ADuM130x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM130x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)∑∏r

where:

β is magnetic flux density (gauss). N is the number of turns in the receiving coil. r

is the radius of the nth turn in the receiving coil (cm).

n

Given the geometry of the receiving coil in the ADuM130x and an imposed requirement that the induced voltage be 50% at most of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 16.

100

10

1

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k 10k 10M

Figure 16. Maximum Allowable External Magnetic Flux Density

2

; n = 1, 2, … , N

n

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

3787-017

ADuM1300/ADuM1301 Data Sheet

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM130x transformers. Figure 17 shows these allowable current magnitudes as a function of frequency for selected distances. The ADuM130x is extremely immune and can be affected only by extremely large currents operated at a high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM130x to affect the operation of the component.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALLOWABLE CURRENT (kA)

0.01 1k 10k 100M100k 1M 10M

MAGNETIC F I ELD FREQUENCY (Hz)

Figure 17. Maximum Allowable Current

for Various Current-to-ADuM130x Spacings

03787-018

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM130x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

I

DDI

= I

× (2f − fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

where:

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz); it is half of the input

data rate expressed in units of Mbps.

f

is the input stage refresh rate (Mbps).

r

, I

I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

To calculate the total V

DD1

and V

supply current, the supply

DD2

currents for each input and output channel corresponding to V

DD1

and V

are calculated and totaled. Figure 6 and Figure 7

DD2

provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 12 provide total V

supply current as a function of data rate for ADuM1300/

V

DD2

ADuM1301 channel configurations.

f ≤ 0.5 fr

f > 0.5 fr

DDO (Q)

f > 0.5 fr

and

DD1

Rev. I | Page 26 of 32

Data Sheet ADuM1300/ADuM1301

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM130x.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Tab le 1 4 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM130x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 18, Figure 19, and Figure 20 illustrate these different isolation voltage waveforms, respectively.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 1 4 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 19 or Figure 20 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 1 4.

Note that the voltage presented in Figure 19 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 18. Bipolar AC Waveform

03787-021

RATED PEAK VOL TAGE

0V

Figure 19. Unipolar AC Waveform

03787-022

RATED PEAK VOL TAGE

0V

Figure 20. DC Waveform

03787-023

Rev. I | Page 27 of 32

ADuM1300/ADuM1301 Data Sheet

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

5

.

2

5

(

0

.

0

2

9

(

0

.

0

9

1.27 (0.0500)

0.40 (0.0157)

)

5

45°

)

8

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters (and inches)

ORDERING GUIDE

Number of Inputs, V

DD1

Model

1, 2, 3, 4

ADuM1300ARW 3 0 1 100 40 −40°C to +105°C RW-16 ADuM1300CRW 3 0 90 32 2 −40°C to +105°C RW-16 ADuM1300ARWZ 3 0 1 100 40 −40°C to +105°C RW-16 ADuM1300BRWZ 3 0 10 50 3 −40°C to +105°C RW-16 ADuM1300CRWZ 3 0 90 32 2 −40°C to +105°C RW-16 ADuM1300WSRWZ 3 0 1 100 40 −40°C to +125°C RW-16 ADuM1300WTRWZ 3 0 10 32 3 −40°C to +125°C RW-16 ADuM1301ARW 2 1 1 100 40 −40°C to +105°C RW-16 ADuM1301BRW 2 1 10 50 3 −40°C to +105°C RW-16 ADuM1301CRW 2 1 90 32 2 −40°C to +105°C RW-16 ADuM1301ARWZ 2 1 1 100 40 −40°C to +105°C RW-16 ADuM1301BRWZ 2 1 10 50 3 −40°C to +105°C RW-16 ADuM1301CRWZ 2 1 90 32 2 −40°C to +105°C RW-16 ADuM1301WSRWZ 2 1 1 100 40 −40°C to +125°C RW-16 ADuM1301WTRWZ 2 1 10 32 3 −40°C to +125°C RW-16 EVAL-ADuMQSEBZ

1

Z = RoHS Compliant Part.

2

W = Qualified for Automotive Applications.

3

Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.

4

No tape-and-reel option is available for the ADuM1301CRW model.

5

RW-16 = 16-lead wide body SOIC.

Side

Number of Inputs, V

Side

DD2

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse Width Distortion (ns) Temperature Range

Package Option5

Rev. I | Page 28 of 32

Data Sheet ADuM1300/ADuM1301

AUTOMOTIVE PRODUCTS

The ADuM1300W/ADuM1301W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. I | Page 29 of 32

ADuM1300/ADuM1301 Data Sheet

NOTES

Rev. I | Page 30 of 32

Data Sheet ADuM1300/ADuM1301

NOTES

Rev. I | Page 31 of 32

ADuM1300/ADuM1301 Data Sheet

NOTES

Rev. I | Page 32 of 32

Datasheet ADUM1300 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION

ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION

ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION

ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE

AUTOMOTIVE PRODUCTS