Datasheet ADuM1300 Datasheet (Analog Devices)

G

Triple-Channel Digital Isolators

FEATURES

Low power operation

5 V operation

1.2 mA per channel max @ 0 Mbps to 2 Mbps

3.5 mA per channel max @ 10 Mbps 32 mA per channel max @ 90 Mbps

3 V operation

0.8 mA per channel max @ 0 Mbps to 2 Mbps

2.2 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns max pulse-width distortion

2 ns max channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function Wide body 16-lead SOIC package, Pb-free models available Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000 V

= 560 V peak

IORM

APPLICATIONS

General-purpose multichannel isolation SPI® interface/data converter isolation RS-232/RS-422/RS-485 transceiver Industrial field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

ADuM1300/ADuM1301

GENERAL DESCRIPTION

The ADuM130x are 3-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discretes is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM130x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM130x provides low pulse-width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM130x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

V

1

DD1

2

ND

1

V

NC

ND

ENCODE DECODE

3

IA

ENCODE DECODE

4

IB

ENCODE DECODE

5

IC

6

7

8

1

V

16

DD2

GND

15

V

14

OA

V

13

OB

V

12

OC

NC

11

V

10

E2

GND

9

Figure 1. ADuM1300 Functional Block Diagram

2

03789-0-001

V

1

DD1

2

GND

1

ENCODE DECODE

3

IA

ENCODE DECODE

4

IB

5

DECODE ENCODE

6

7

E1

8

1

GND

V

OC

NC

V

Figure 2. ADuM1301 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

NC

10

OR V

V

E2

9

GND

2

03789-0-002

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

ADuM1300/ADuM1301

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V wise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I Output Supply Current, per Channel, Quiescent I ADuM1300, Total Supply Current, Three Channels2

ADuM1301, Total Supply Current, Three Channels2

For All Models

SWITCHING SPECIFICATIONS

ADuM130xARW

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DD1

DDI (Q)

DDO (Q)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

Logic Low Output Voltages V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

4

5

– t

|

PLH

PHL

6

7

DD1 (90)

DD2 (90)

, IIB, IIC,

I

IA

I

E1

VIH, V VIL, V V

OAH

V

OCH

OAL

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels t

PSK

t

PSKCD/OD

1

= V

= 5 V.

DD2

0.50 0.53 mA

0.19 0.21 mA

1.6 2.5 mA DC to 1 MHz logic signal freq.

0.7 1.0 mA DC to 1 MHz logic signal freq.

6.5 8.1 mA 5 MHz logic signal freq.

1.9 2.5 mA 5 MHz logic signal freq.

57 77 mA 45 MHz logic signal freq. 16 18 mA 45 MHz logic signal freq.

1.3 2.1 mA DC to 1 MHz logic signal freq.

1.0 1.4 mA DC to 1 MHz logic signal freq.

5.0 6.2 mA 5 MHz logic signal freq.

3.4 4.2 mA 5 MHz logic signal freq.

43 57 mA 45 MHz logic signal freq. 29 37 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

, I

E2

2.0 V

0.8 V V

,

V

0.0 0.1 V IOx = 20 µA, VIx = V

, V

OCL

– 0.1 5.0 V IOx = –20 µA, VIx = V

DD1, VDD2

– 0.4 4.8 V IOx = –4 mA, VIx = V

DD1, VDD2

, V

EH

EL

OBH

OBL

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

, t

PLH

50 65 100 ns CL = 15 pF, CMOS signal levels

0 ≤ V 0 ≤ V

, VIB, VIC ≤ V

IA

, VE2 ≤ V

E1

DD1

or V

IxH

IxL

or V

DD2

,

50 ns CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels

Rev. C | Page 3 of 20

ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

ADuM130xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/t Common-Mode Transient Immunity at

Logic High Output

Common-Mode Transient Immunity at

Logic Low Output

8

Refresh Rate f Input Dynamic Supply Current, per Channel

9

Output Dynamic Supply Current, per Channel9 I

1

All voltages are relative to their respective ground.

2

The supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 17. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel supply current for a given data rate.

Figure 6

Figure 12

Figure 8 and I

DD1

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PHL

, t

PLH

20 32 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

15 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

18 27 32 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

, t

t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

10 ns CL = 15 pF, CMOS signal levels 2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

2.5 ns CL = 15 pF, CMOS signal levels = V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

I

DDI (D)

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

1.2 Mbps

0.19 mA/Mbps

0.05 mA/Mbps

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Figure 8

Figure 9

Rev. C | Page 4 of 20

ADuM1300/ADuM1301

= V

, IIB, I , I

E2

EH

EL

, V

OAH

OCH

, V

OAL

, t

PHL

PLH

PSK

PSKCD/OD

IC,

DD2

OBH

OBL

1

= 3.0 V.

0.26 0.31 mA

0.11 0.14 mA

0.9 1.7 mA DC to 1 MHz logic signal freq.

0.4 0.7 mA DC to 1 MHz logic signal freq.

3.4 4.9 mA 5 MHz logic signal freq.

1.1 1.6 mA 5 MHz logic signal freq.

31 48 mA 45 MHz logic signal freq. 8 13 mA 45 MHz logic signal freq.

0.7 1.4 mA DC to 1 MHz logic signal freq.

0.6 0.9 mA DC to 1 MHz logic signal freq.

2.6 3.7 mA 5 MHz logic signal freq.

1.8 2.5 mA 5 MHz logic signal freq.

24 36 mA 45 MHz logic signal freq. 16 23 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

0 ≤ V 0 ≤ V

, VIB, VIC ≤ V

IA

≤ V

E1,VE2

1.6 V

0.4 V V

,

V

0.0 0.1 V IOx = 20 µA, VIx = V

, V

OCL

– 0.1 3.0 V IOx = –20 µA, VIx = V

DD1, VDD2

– 0.4 2.8 V IOx = –4 mA, VIx = V

DD1, VDD2

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

50 75 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels

DD1

or V

IxH

IxL

or V

IxH

IxL

DD2

,

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V wise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I Output Supply Current, per Channel, Quiescent I ADuM1300, Total Supply Current, Three Channels2

ADuM1301, Total Supply Current, Three Channels2

For All Models

SWITCHING SPECIFICATIONS

ADuM130xARW

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DD1

DDI (Q)

DDO (Q)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

DD1 (90)

DD2 (90)

I

IA

I

E1

VIH, V VIL, V V

V

Logic Low Output Voltages V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

4

5

– t

|

PLH

PHL

6

7

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t PWD 40 ns CL = 15 pF, CMOS signal levels t t

Rev. C | Page 5 of 20

ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

ADuM130xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/t Common-Mode Transient Immunity at

Logic High Output Common-Mode Transient Immunity at

Logic Low Output

8

Refresh Rate f Input Dynamic Supply Current, per Channel

9

Output Dynamic Supply Current, per Channel9 I

1

All voltages are relative to their respective ground.

2

The supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 17. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel supply current for a given data rate.

Figure 6

Figure 12

DD1

and I

Figure 8

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

PLH

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PHL

, t

PLH

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

26 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

20 34 45 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

, t

t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

16 ns CL = 15 pF, CMOS signal levels 2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

I

DDI (D)

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

1.1 Mbps

0.10 mA/Mbps

0.03 mA/Mbps

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Figure 8

Figure 9

Rev. C | Page 6 of 20

ADuM1300/ADuM1301

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

1

5 V/3 V operation: 4.5 V ≤ V

≤ 5.5 V, 2.7 V ≤ V

DD1

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all min/max

DD2

specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at

= 25°C; V

T

A

= 3.0 V, V

DD1

= 5 V; or V

DD2

= 5 V, V

DD1

= 3.0 V.

DD2

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

DDI (Q)

5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA

Output Supply Current, per Channel, Quiescent I

DDO (Q)

5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM1300, Total Supply Current, Three Channels2

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 1.6 2.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.7 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

DD2(Q)

5 V/3 V Operation 0.4 0.7 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.0 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 6.5 8.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 1.1 1.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.9 2.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

DD1 (90)

5 V/3 V Operation 57 77 mA 45 MHz logic signal freq. 3 V/5 V Operation 31 48 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (90)

5 V/3 V Operation 8 13 mA 45 MHz logic signal freq. 3 V/5 V Operation 16 18 mA 45 MHz logic signal freq.

ADuM1301, Total Supply Current, Three Channels2

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 1.3 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.4 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.6 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 5.0 6.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.7 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 1.8 2.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.2 mA 5 MHz logic signal freq.

Rev. C | Page 7 of 20

ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

DD1 (90)

5 V/3 V Operation 43 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 24 36 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (90)

5 V/3 V Operation 16 23 mA 45 MHz logic signal freq. 3 V/5 V Operation 29 37 mA 45 MHz logic signal freq.

For All Models

Input Currents

Logic High Input Threshold

, IIB, IIC,

I

IA

, I

I

E1

VIH, V

E2

EH

5 V/3 V Operation 2.0 V

3 V/5 V Operation 1.6 V Logic Low Input Threshold

VIL, V

EL

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V Logic High Output Voltages

Logic Low Output Voltages V

, V

V

OAH

OBH

V

OCH

, V

OAL

OBL

SWITCHING SPECIFICATIONS

ADuM130xARW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

4

5

– t

|

PLH

PHL

6

7

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

, t

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels t

PSK

t

PSKCD/OD

ADuM130xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF,CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

, t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

PSK

t

PSKCD

t

PSKOD

ADuM130xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH-tPHL

5

|

, t

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

PSK

t

PSKCD

t

PSKOD

–10 +0.01 +10 µA

0 ≤ V 0 ≤ V

IA,VIB

E1,VE2

, VIC ≤ V

≤ V

V

,

DD1, VDD2

–

V

DD1/VDD2

V IOx = –20 µA, VIx = V

0.1 V

,

DD1

– 0.4

V

DD2

0.0 0.1 V IOx = 20 µA, VIx = V

, V

OCL

V

DD1

V

DD2

V I

/

– 0.2

= –4 mA, VIx = V

Ox

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

50 70 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels

15 35 50 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

20 30 40 ns CL = 15 pF, CMOS signal levels

14 ns CL = 15 pF, CMOS signal levels 2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

DD1

or V

IxH

IxL

or V

IxH

IxL

DD2

,

Rev. C | Page 8 of 20

ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

, t

Output Disable Propagation Delay

t

PHZ

PLH

(High/Low-to-High Impedance)

t

Output Enable Propagation Delay

PZH

, t

PZL

(High Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/t

f

5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity at

Logic High Output

Common-Mode Transient Immunity at

Logic Low Output

8

Refresh Rate f

|CMH| 25 35 kV/µs

|CML| 25 35 kV/µs

r

5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current, per Channel9I

DDI (D)

5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel9 I

DDI (D)

5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps

1

All voltages are relative to their respective ground.

2

Supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 17. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total I supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

recommended operating conditions.

7

Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load within the

PHL

PLH

barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

sustained while maintaining V range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through for information on per-

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the

O

channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel supply current for a given data rate.

6 8 ns CL = 15 pF, CMOS signal levels

C

= 15 pF, CMOS signal levels

L

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

and I

DD1

DD2

propagation delay is measured

PLH

. CML is the maximum common-mode voltage slew rate that can be

DD2

Figure 8

Rev. C | Page 9 of 20

ADuM1300/ADuM1301

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output) Capacitance (Input-Output) Input Capacitance IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

1

Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM130x have been approved by the organizations listed in Table 5.

Table 5.

UL CSA VDE

Recognized under 1577 component recognition program

Double insulation, 2500 V rms isolation voltage

File E214100

1

In accordance with UL1577, each ADuM130x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).

2

In accordance with DIN EN 60747-5-2, each ADuM130x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection

limit = 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.

1

2

Approved under CSA Component

1

Acceptance Notice #5A

R

I-O

C

I-O

C

I

JCI

JCO

10

1.7 pF f = 1 MHz

4.0 pF 33 °C/W 28 °C/W

Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms maximum working voltage

File 205078

12

Ω

Thermocouple located at center of package underside

Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

2

Basic insulation, 560 V peak

Complies with DIN EN 60747-5-2 (VDE 0884 Part 2):2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000

Reinforced insulation, 560 V peak

File 2471900-4880-0001

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 8.40 min mm

Minimum External Tracking (Creepage) L(I02) 8.10 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. C | Page 10 of 20

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

ADuM1300/ADuM1301

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage V Input to Output Test Voltage, Method b1

V

× 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC

IORM

Input to Output Test Voltage, Method a

After Environmental Tests Subgroup 1

V

× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

After Input and/or Safety Test Subgroup 2/3

V

× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) V Safety-Limiting Values (Maximum value allowed in the event of a failure; also see Thermal

Derating Curve, Figure 3)

Case Temperature

Side 1 Current

Side 2 Current Insulation Resistance at TS, VIO = 500 V R

This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.

I–IV I–III I–II

IORM

V

PR

V

PR

560 V peak 1050 V peak

896

672

TR

T

S

I

S1

I

S2

S

4000 V peak

150 265 335

9

>10

V peak

°C mA mA Ω

The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.

350

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

Figure 3. Thermal Derating Curve, Dependence of Safety Limiting

Values with Case Temperature per DIN EN 60747-5-2

SIDE #2

SIDE #1

50 100 150 200

CASE TEMPERATURE (°C)

03787-0-003

RECOMMENDED OPERATION CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature T Supply Voltages Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground.

See the DC Correctness and Magnetic Field Immunity section on Page 16

for information on immunity to external magnetic fields.

1

A

V

DD1

–40 +105 °C

, V

2.7 5.5 V

DD2

Rev. C | Page 11 of 20

ADuM1300/ADuM1301

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature T Ambient Operating Temperature T Supply Voltages Input Voltage Output Voltage Average Output Current, Per Pin

1

1, 2

3

Side 1 I Side 2 I

Common-Mode Transients

4

ST

A

V

, V

DD1

DD2

VIA, VIB, VIC, VE1, V VOA, VOB, V

E2

OC

O1

O2

–100 +100 kV/µs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

3

See for maximum rated current values for various temperatures. Figure 3

4

Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or

permanent damage.

refer to the supply voltages on the input and output sides of a given channel, respectively. See P section. C Board Layout

DDO

–65 +150 °C –40 +105 °C –0.5 +7.0 V –0.5 V –0.5 V

+ 0.5 V

DDI

+ 0.5 V

DDO

–23 +23 mA –30 +30 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Table 10. Truth Table (Positive Logic)

V

Input1VEX Input2V

IX

H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H

X L Unpowered Powered Z X X Powered Unpowered Indeterminate

1

VIX and VOX refer to the input and output signals of a given channel (A, B, or C). VEX refers to the output enable signal on the same side as the VOX outputs. V

refer to the supply voltages on the input and output sides of the given channel, respectively.

2

In noisy environments, connecting VEX to an external logic high or low is recommended.

State1 V

DDI

State1 VOX Output1 Notes

DDO

Outputs return to the input state within 1 µs of V tion.

Outputs return to the input state within 1 µs of V tion, if V within 8 ns of V

power restora-

DDI

power restora-

state is H or NC. Outputs returns to high impedance state

EX

power restoration, if VEX state is L.

DDO

and V

DDI

DDO

Rev. C | Page 12 of 20

ADuM1300/ADuM1301

*

PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS

V

1 16

DD1

GND

2 15

1

ADuM1300

TOP VIEW

V

3 14

IA

(Not to Scale)

V

4 13

IB

V

5 12

IC

NC

6 11

NC

7 10

GND

8 9

1

NC = NO CONNECT

Figure 4. ADuM1300 Pin Configuration

V

DD2

GND2* V

OA

V

OB

V

OC

NC V

E2

GND2*

03787-0-004

V

1 16

DD1

GND

2 15

1

V

3 14

IA

(Not to Scale)

V

4 13

IB

V

5 12

OC

NC

6 11

V

7 10

E1

GND

8 9

1

NC = NO CONNECT

ADuM1301

TOP VIEW

V

DD2

GND2* V

OA

V

OB

V

IC

NC V

E2

GND2*

03787-0-005

Figure 5. ADuM1301 Pin Configuration

* Pins 2 and 8 are internally connected. Connecting both to GND1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND2 is recommended.

Output enable Pin 10 on the ADuM1300 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM1301 may be left

disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM1301) and Pin 10 (for both models) to an external logic high or

low is recommended.

Table 11. ADuM1300 Pin Function Descriptions

Pin No. Mnemonic Function

1 V

DD1

Supply Voltage for Isolator Side 1, 2.7 V to

5.5 V. 2 GND 3 V

IA

4 V

IB

5 V

IC

1

Ground 1. Ground reference for isolator Side 1. Logic Input A. Logic Input B.

Logic Input C. 6 NC No Connect. 7 NC No Connect. 8 GND 9 GND 10 V

E2

1

2

Ground 1. Ground Reference for Isolator Side 1.

Ground 2. Ground Reference for Isolator Side 2.

Output Enable 2. Active high logic input. VOA, VOB,

outputs are enabled when VE2 is high or

and V

OC

disconnected. V

abled when V

connecting V

, VOB, and VOC outputs are dis-

OA

is low. In noisy environments,

E2

to an external logic high or low is

E2

recommended. 11 NC No Connect. 12 V

OC

13 V

OB

14 V

OA

15 GND 16 V

DD2

2

Logic Output C.

Logic Output B.

Logic Output A.

Ground 2. Ground Reference for Isolator Side 2.

Supply Voltage for Isolator Side 2, 2.7 V to

5.5 V.

Table 12. ADuM1301 Pin Function Descriptions

Pin No. Mnemonic Functio n

1 V

DD1

Supply Voltage for Isolator Side 1, 2.7 V to

5.5 V. 2 GND 3 V

IA

4 V

IB

5 V

OC

1

Ground 1. Ground Reference for Isolator Side 1. Logic Input A. Logic Input B.

Logic Output C. 6 NC No Connect. 7 V

E1

Output Enable 1. Active high logic input. V

put is enabled when V

V

is disabled when VE1 is low. In noisy environ-

OC

ments, connecting to V

is high or disconnected.

E1

to an external logic high

E1

or low is recommended. 8 GND 9 GND 10 V

E2

1

2

Ground 1. Ground Reference for Isolator Side 1.

Ground 2. Ground Reference for Isolator Side 2.

Output Enable 2. Active high logic input. VOA and

outputs are enabled when VE2 is high or dis-

V

OB

connected. V

when V

ing V

E2

and VOB outputs are disabled

OA

is low. In noisy environments, connect-

E2

to an external logic high or low is recom-

mended. 11 NC No Connect. 12 V

IC

13 V

OB

14 V

OA

15 GND 16 V

DD2

2

Logic Input C.

Logic Output B.

Logic Output A.

Ground 2. Ground Reference for Isolator Side 2.

Supply Voltage for Isolator Side 2, 2.7 V to

5.5 V.

out-

OC

Rev. C | Page 13 of 20

ADuM1300/ADuM1301

TYPICAL PERFORMANCE CHARACTERISTICS

20

18

16

14

12

10

8

6

CURRENT/CHANNEL (mA)

4

2

0

Figure 6. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

6

5V

3V

4020 60 80 100

DATA RATE (Mbps)

03787-0-008

60

50

40

30

20

CURRENT (mA)

10

0

020

Figure 9. Typical ADuM1300 V

for 5 V and 3 V Operation

16

5V

3V

40 60 80 100

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD1

03787-0-011

5

4

3

5V

3V

20 40 60 80 100

DATA RATE (Mbps)

CURRENT/CHANNEL (mA)

2

1

0

Figure 7. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

10

9

8

7

6

5

CURRENT/CHANNEL (mA)

4

3

2

1 0

0

5V

3V

20 40 8060 100

DATA RATE (Mbps)

Figure 8. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

03787-0-009

03787-0-010

14

12

10

8

6

CURRENT (mA)

4

2

0

5V

DATA RATE (Mbps)

Figure 10. Typical ADuM1300 V

for 5 V and 3 V Operation

50

45

40

35

30

25

20

CURRENT (mA)

15

10

5

0

20 40 60 80 100

DATA RATE (Mbps)

Figure 11. Typical ADuM1301 V

for 5 V and 3 V Operation

3V

4020 60 80 100

Supply Current vs. Data Rate

DD2

5V

3V

Supply Current vs. Data Rate

DD1

03787-0-012

03787-0-013

Rev. C | Page 14 of 20

ADuM1300/ADuM1301

30

25

20

15

CURRENT (mA)

10

5

5V

3V

40

35

30

PROPAGATION DELAY (ns)

3V

5V

0

20 40 60 80 100

Figure 12. Typical ADuM1301 V

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

03787-0-014

25

–50 –25

0507525 100

TEMPERATURE (°C)

Figure 13. Propagation Delay vs. Temperature, C Grade

03787-0-019

Rev. C | Page 15 of 20

ADuM1300/ADuM1301

V

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM130x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (Figure 14). Bypass capacitors are most conveniently connected between Pins 1 and 2 for V

. The capacitor value should be between 0.01 µF and 0.1 µF.

V

DD2

The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pins 1 and 8 and between Pins 9 and 16 should also be considered unless the ground pair on each package side is connected close to the package.

V

DD1

GND

1

V

IA

V

IB

IC/OC

NC

V

E1

GND

1

Figure 14. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage.

and between Pins 15 and 16 for

DD1

V

DD2

GND

2

V

OA

V

OB

V

OC/IC

NC V

E2

GND

2

03787-0-015

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than 2 µs at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit.

The ADuM130x is extremely immune to external magnetic fields. The limitation on the ADuM130x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM130x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

2

∑∏r

V = (–dβ/dt)

; n = 1, 2,…, N

n

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high.

INPUT (

)

IX

OUTPUT (

t

PLH

)

OX

Figure 15. Propagation Delay Parameters

t

PHL

Pulse-width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM130x component.

Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM130x components operating under the same conditions.

50%

Rev. C | Page 16 of 20

03787-0-016

where:

β is magnetic flux density (gauss). N is the number of turns in the receiving coil.

is the radius of the nth turn in the receiving coil (cm).

r

n

Given the geometry of the receiving coil in the ADuM130x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 16.

ADuM1300/ADuM1301

100.000

10.000

1.000

0.100

DENSITY (kgauss)

0.010

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k 10k 10M

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

Figure 16. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM130x transformers. Figure 17 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the ADuM130x is extremely immune and can be affected only by extremely large currents operated at high frequency, very close to the component. For the 1 MHz example, one would have to place a 0.5 kA current 5 mm away from the ADuM130x to affect the component’s operation.

1000.00 DISTANCE = 1m

100.00

10.00 DISTANCE = 100mm

1.00 DISTANCE = 5mm

0.10

MAXIMUM ALLOWABLE CURRENT (kA)

0.01

1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 17. Maximum Allowable Current

for Various Current-to-ADuM130x Spacings

03787-0-018

03787-0-017

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM130x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

= I

I

DDI

DDI (Q)

I

= I

DDI

For each output channel, the supply current is given by

I

DDO

I

DDO

where:

I

, I

DDI (D)

DDO (D)

per channel (mA/Mbps).

is output load capacitance (pF).

C

L

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

is the input stage refresh rate (Mbps).

f

r

, I

I

DDI (Q)

DDO (Q)

ply currents (mA).

To calculate the total I currents for each input and output channel corresponding to

and I

I

DD1

provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides perchannel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 12 provide total

and I

I

DD1

ADuM1300/ADuM1301 channel configurations.

× (2f – fr) + I

= I

= (I

DDI (D)

f ≤ 0.5f

DDO (Q)

+ (0.5 × 10−3) × CLV

DDO (D)

DDI (Q)

) × (2f – fr) + I

DDO

are the input and output dynamic supply currents

are the specified input and output quiescent sup-

and I

DD1

are calculated and totaled. Figure 6 and Figure 7

DD2

supply current as a function of data rate for

DD2

supply current, the supply

DD2

f ≤ 0.5f

f > 0.5f

DDO (Q)

f > 0.5f

r

Rev. C | Page 17 of 20

ADuM1300/ADuM1301

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500) BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AA

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8° 0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Figure 18. 16-Lead Standard Small Outline Package [SOIC]

Wide Body (RW-16)

Dimensions shown in millimeters (inches)

ORDERING GUIDE

Number of Inputs, V

Side

DD2

Model

ADuM1300ARW

2

Number of Inputs,

Side

V

DD1

3 0 1 100 40 –40 to +105 RW-16 ADuM1300BRW2 3 0 10 50 3 –40 to +105 RW-16 ADuM1300CRW2 3 0 90 32 2 –40 to +105 RW-16 ADuM1300ARWZ ADuM1300BRWZ ADuM1300CRWZ

2, 3

3 0 1 100 40 –40 to +105 RW-16

2, 3

3 0 10 50 3 –40 to +105 RW-16

2, 3

3 0 90 32 2 –40 to +105 RW-16 ADuM1301ARW2 2 1 1 100 40 –40 to +105 RW-16 ADuM1301BRW2 2 1 10 50 3 –40 to +105 RW-16 ADuM1301CRW2 2 1 90 32 2 –40 to +105 RW-16 ADuM1301ARWZ ADuM1301BRWZ ADuM1301CRWZ

2, 3

3 0 1 100 40 –40 to +105 RW-16

2, 3

3 0 10 50 3 –40 to +105 RW-16

2, 3

3 0 90 32 2 –40 to +105 RW-16

1

RW-16 = 16-lead wide body SOIC.

2

Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.

3

Z = Pb-free part.

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse-Width Distortion (ns)

Temperature Range (°C)

Package Option

1

Rev. C | Page 18 of 20

ADuM1300/ADuM1301

NOTES

Rev. C | Page 19 of 20

ADuM1300/ADuM1301

NOTES

C03787–0–6/04(C)

Rev. C | Page 20 of 20

Datasheet ADuM1300 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

RECOMMENDED OPERATION CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION INFORMATION

PC BOARD LAYOUT

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

PROPAGATION DELAY-RELATED PARAMETERS

POWER CONSUMPTION

OUTLINE DIMENSIONS

ORDERING GUIDE