High-side or low-side relative to input: ±700 V
High-side/low-side differential: 700 V
PEAK
0.1 A peak output current
High frequency operation: 5 MHz max
High common-mode transient immunity: >50 kV/μs
High temperature operation: 105°C
Wide body, 16-lead SOIC
UL1577 2500 V rms input-to-output withstand voltage
The ADuM12301 is an isolated half-bridge gate driver that
employs Analog Devices’ iCoupler® technology to provide
independent and isolated high-side and low-side outputs.
Combining high speed CMOS and monolithic transformer
technology, this isolation component provides outstanding
performance characteristics superior to optocoupler-based
solutions.
By avoiding the use of LEDs and photodiodes, this iCoupler
gate drive device is able to provide precision timing characteristics
not possible with optocouplers. Furthermore, the reliability and
performance stability problems associated with optocoupler
LEDs are avoided.
In comparison to gate drivers employing high voltage level
translation methodologies, the ADuM1230 offers the benefit of
true, galvanic isolation between the input and each output. Each
output may be operated up to ±700 V
thereby supporting low-side switching to negative voltages. The
differential voltage between the high-side and low-side can be
as high as 700 V
.
P
relative to the input,
P
As a result, the ADuM1230 provides reliable control over the
switching characteristics of IGBT/MOSFET configurations over
a wide range of positive or negative switching voltages.
1
Protected by U.S. Patents 5,952,849 and 6,291,907.
FUNCTIONAL BLOCK DIAGRAM
116
V
V
V
DD1
GND
DISABLE
NC
NC
V
DD1
IA
215
IB
314
413
1
5
6
7
8
ENCODEDECODE
ENCODEDECODE
Figure 1.
V
DDA
V
OA
GND
A
NC
12
NC
11
V
DDB
10
V
OB
9
GND
B
05460-001
Rev. PrI December 1, 2005
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
All voltages are relative to their respective ground. 4.5 V ≤ V
specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T
V
DD1
= 5 V, V
= 15 V, V
DDA
= 15 V.
DDB
Table 1.
Parameter SymbolMinTyp MaxUnitTest Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent I
Output Supply Current, A or B, Quiescent
Input Supply Current, 10 Mbps I
Output Supply Current, A or B, 10 Mbps
DDI (Q)
I
DDA (Q)
I
DDB (Q)
DDI (10)
I
DDA (10)
I
DDB (10)
Input Currents IIA, IIB, I
Logic High Input Threshold VIH 2.0 V
Logic Low Input Threshold VIL 0.8 V
Logic High Output Voltages V
Logic Low Output Voltages V
Output Short-Circuit Pulsed Current1 I
OA (SC)
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 100 ns CL = 200 pF
Maximum Switching Frequency3 10 Mbps CL = 200 pF
Propagation Delay4 t
Change vs. Temperature 100 ps/°C
Pulse Width Distortion, |t
Channel-to-Channel Matching,
Rising or Falling Edges
Channel-to-Channel Matching,
Rising vs. Falling Edges
PLH
5
− t
| PWD 8 ns CL = 200 pF
PHL
5 ns CL = 200 pF
6
13 ns C
Part-to-Part Matching, Rising or Falling Edges7 55 ns CL = 200 pF
Part-to-Part Matching, Rising vs. Falling Edges8 63 ns CL = 200 pF
Output Rise/Fall Time (10% to 90%) tR/tF 20 ns CL = 200 pF
1
Short-circuit duration less than 1 second. Average power must conform to the limit shown under the Absolute Maximum Ratings.
2
The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed.
3
The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
Channel-to-channel matching, rising vs. falling edges is the magnitude of the propagation delay difference between two channels of the same part when the inputs
are either both rising edges or falling edges. The supply voltages and the loads on each channel are equal.
6
Channel-to-channel matching, rising or falling edges is the magnitude of the propagation delay difference between two channels of the same part when one input is
a rising edge and the other input is a falling edge. The supply voltages and loads on each channel are equal.
7
Part-to-part matching, rising or falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when the inputs
are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal.
8
Part-to-part matching, rising vs. falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when one input
is a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal.
≤ 5.5 V, 12 V ≤ V
DD1
≤ 18 V, 12 V ≤ V
DDA
≤ 18 V. All min/max
DDB
4.0 mA
,
1.2 mA
8.0 mA
,
22 mA C
−10 +0.01 +10 μA 0 ≤ VIA, VIB, V
DISABLE
, V
OAH
OBH
, V
0.1 V IOA, IOB = 1 mA
OAL
OBL
, I
100 mA
OB (SC)
, t
97 124 160 ns CL = 200 pF
PHL
PLH
V
V
DDA
DDB
− 0.1,
− 0.1
V
, V
V IOA, IOB = −1 mA
DDA
DDB
A
= 200 pF
L
DISABLE
= 200 pF
L
propagation delay is
PLH
= 25°C,
≤ V
DD1
Rev. PrI | Page 3 of 12
Page 4
ADuM1230 Preliminary Technical Data
PACKAGE CHARACTERISTICS
Table 2.
Parameter SymbolMinTyp MaxUnitTest Conditions
Resistance (Input-to-Output)1 R
Capacitance (Input-to-Output)1 C
Input Capacitance CI 4.0 pF
IC Junction-to-Ambient Thermal Resistance θ
1
The device is considered a 2-terminal device: Pins 1 through 8 are shorted together, and Pins 9 through 16 are shorted together.
REGULATORY INFORMATION
The ADuM1230 is approved, as shown in Table 3.
Table 3.
UL1
Recognized under 1577 component recognition program
1
In accordance with UL1577, each ADuM1230 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).
1012 Ω
I-O
2.0 pF f = 1 MHz
I-O
76 °C/W
JCa
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Val ue Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.1 min mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
RECOMMENDED OPERATING CONDITIONS
Table 5.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Input Supply Voltage1 V
Output Supply Voltages1 V
Input Signal Rise and Fall Times 1 ms
Common-Mode Transient Immunity, Input-to-Output2 −50 +50 kV/μs
Common-Mode Transient Immunity, Between Outputs2 −50 +50 kV/μs
Transient Immunity, Supply Voltages2 −50 +50 kV/μs
1
All voltages are relative to their respective ground.
2
See the Common-Mode Transient Immunity section for transient diagrams and additional information.
4.5 5.5 V
DD1
, V
DDA
12 18 V
DDB
Rev. PrI | Page 4 of 12
Page 5
Preliminary Technical Data ADuM1230
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter SymbolMinMax Unit
Storage Temperature TST −55 +150 °C
−40 +105 °C
Ambient Operating
T
A
Temperature
Input Supply Voltage1 V
Output Supply Voltage1 V
Input Voltage1 V
Output Voltage1 V
Input-Output Voltage2 −700 +700 V
Output Differential
Voltage
3
Output DC Current IOA, I
Common-Mode
Transie nts
1
All voltages are relative to their respective ground.
2
Input-to-output voltage is defined as GNDA − GND1 or GNDB − GND1.
3
Output differential voltage is defined as GNDA − GNDB.
4
Refers to common-mode transients across any insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings can cause latchup or permanent damage.
4
−0.5 +7.0 V
DD1
, V
DDA
IA
OA
700 V
−0.5 +27 V
DDB
, VIB −0.5 V
, VOB −0.5
OB
−20 +20 mA
DDI
V
DDA
V
DDB
+ 0.5 V
+ 0.5,
V
+ 0.5
PEAK
PEAK
−100 +100 kV/μs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Ambient temperature = 25°C, unless otherwise noted.
Table 7. ADuM1230 Truth Table (Positive Logic)
VIA/VIB Input V
State DISABLE VOA/VOB Output Notes
DD1
H Powered L H
L Powered L L
X Unpowered X L Output returns to input state within 1 μs of V
X Powered H L
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
power restoration.
DDI
Rev. PrI | Page 5 of 12
Page 6
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